2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König <christian.koenig@amd.com>
25 #include <linux/firmware.h>
28 #include "radeon_asic.h"
32 * uvd_v2_2_fence_emit - emit an fence & trap command
34 * @rdev: radeon_device pointer
35 * @fence: fence to emit
37 * Write a fence and a trap command to the ring.
39 void uvd_v2_2_fence_emit(struct radeon_device
*rdev
,
40 struct radeon_fence
*fence
)
42 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
43 uint64_t addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
45 radeon_ring_write(ring
, PACKET0(UVD_CONTEXT_ID
, 0));
46 radeon_ring_write(ring
, fence
->seq
);
47 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA0
, 0));
48 radeon_ring_write(ring
, lower_32_bits(addr
));
49 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA1
, 0));
50 radeon_ring_write(ring
, upper_32_bits(addr
) & 0xff);
51 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_CMD
, 0));
52 radeon_ring_write(ring
, 0);
54 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA0
, 0));
55 radeon_ring_write(ring
, 0);
56 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA1
, 0));
57 radeon_ring_write(ring
, 0);
58 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_CMD
, 0));
59 radeon_ring_write(ring
, 2);
63 * uvd_v2_2_semaphore_emit - emit semaphore command
65 * @rdev: radeon_device pointer
66 * @ring: radeon_ring pointer
67 * @semaphore: semaphore to emit commands for
68 * @emit_wait: true if we should emit a wait command
70 * Emit a semaphore command (either wait or signal) to the UVD ring.
72 bool uvd_v2_2_semaphore_emit(struct radeon_device
*rdev
,
73 struct radeon_ring
*ring
,
74 struct radeon_semaphore
*semaphore
,
77 uint64_t addr
= semaphore
->gpu_addr
;
79 radeon_ring_write(ring
, PACKET0(UVD_SEMA_ADDR_LOW
, 0));
80 radeon_ring_write(ring
, (addr
>> 3) & 0x000FFFFF);
82 radeon_ring_write(ring
, PACKET0(UVD_SEMA_ADDR_HIGH
, 0));
83 radeon_ring_write(ring
, (addr
>> 23) & 0x000FFFFF);
85 radeon_ring_write(ring
, PACKET0(UVD_SEMA_CMD
, 0));
86 radeon_ring_write(ring
, emit_wait
? 1 : 0);
92 * uvd_v2_2_resume - memory controller programming
94 * @rdev: radeon_device pointer
96 * Let the UVD memory controller know it's offsets
98 int uvd_v2_2_resume(struct radeon_device
*rdev
)
101 uint32_t chip_id
, size
;
104 /* RV770 uses V1.0 MC */
105 if (rdev
->family
== CHIP_RV770
)
106 return uvd_v1_0_resume(rdev
);
108 r
= radeon_uvd_resume(rdev
);
112 /* program the VCPU memory controller bits 0-27 */
113 addr
= rdev
->uvd
.gpu_addr
>> 3;
114 size
= RADEON_GPU_PAGE_ALIGN(rdev
->uvd_fw
->size
+ 4) >> 3;
115 WREG32(UVD_VCPU_CACHE_OFFSET0
, addr
);
116 WREG32(UVD_VCPU_CACHE_SIZE0
, size
);
119 size
= RADEON_UVD_HEAP_SIZE
>> 3;
120 WREG32(UVD_VCPU_CACHE_OFFSET1
, addr
);
121 WREG32(UVD_VCPU_CACHE_SIZE1
, size
);
124 size
= (RADEON_UVD_STACK_SIZE
+
125 (RADEON_UVD_SESSION_SIZE
* rdev
->uvd
.max_handles
)) >> 3;
126 WREG32(UVD_VCPU_CACHE_OFFSET2
, addr
);
127 WREG32(UVD_VCPU_CACHE_SIZE2
, size
);
130 addr
= (rdev
->uvd
.gpu_addr
>> 28) & 0xF;
131 WREG32(UVD_LMI_ADDR_EXT
, (addr
<< 12) | (addr
<< 0));
134 addr
= (rdev
->uvd
.gpu_addr
>> 32) & 0xFF;
135 WREG32(UVD_LMI_EXT40_ADDR
, addr
| (0x9 << 16) | (0x1 << 31));
137 /* tell firmware which hardware it is running on */
138 switch (rdev
->family
) {
142 chip_id
= 0x01000005;
145 chip_id
= 0x01000006;
148 chip_id
= 0x01000007;
152 chip_id
= 0x01000008;
155 chip_id
= 0x01000009;
158 chip_id
= 0x0100000a;
161 chip_id
= 0x0100000b;
165 chip_id
= 0x0100000c;
168 chip_id
= 0x0100000e;
171 chip_id
= 0x0100000f;
174 chip_id
= 0x01000010;
177 chip_id
= 0x01000011;
180 chip_id
= 0x01000012;
183 chip_id
= 0x01000014;
186 chip_id
= 0x01000015;
190 chip_id
= 0x01000016;
193 chip_id
= 0x01000017;
196 WREG32(UVD_VCPU_CHIP_ID
, chip_id
);