WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / hda.c
blob94245a18a0435e1e019b59594e00a09df5494481
1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright (C) 2019 NVIDIA Corporation
4 */
6 #include <linux/bug.h>
8 #include <sound/hda_verbs.h>
10 #include "hda.h"
12 void tegra_hda_parse_format(unsigned int format, struct tegra_hda_format *fmt)
14 unsigned int mul, div, bits, channels;
16 if (format & AC_FMT_TYPE_NON_PCM)
17 fmt->pcm = false;
18 else
19 fmt->pcm = true;
21 if (format & AC_FMT_BASE_44K)
22 fmt->sample_rate = 44100;
23 else
24 fmt->sample_rate = 48000;
26 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
27 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
29 fmt->sample_rate *= (mul + 1) / (div + 1);
31 switch (format & AC_FMT_BITS_MASK) {
32 case AC_FMT_BITS_8:
33 fmt->bits = 8;
34 break;
36 case AC_FMT_BITS_16:
37 fmt->bits = 16;
38 break;
40 case AC_FMT_BITS_20:
41 fmt->bits = 20;
42 break;
44 case AC_FMT_BITS_24:
45 fmt->bits = 24;
46 break;
48 case AC_FMT_BITS_32:
49 fmt->bits = 32;
50 break;
52 default:
53 bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT;
54 WARN(1, "invalid number of bits: %#x\n", bits);
55 fmt->bits = 8;
56 break;
59 channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
61 /* channels are encoded as n - 1 */
62 fmt->channels = channels + 1;