1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
7 #include <linux/bitops.h>
9 #define V3D_MASK(high, low) ((u32)GENMASK(high, low))
10 /* Using the GNU statement expression extension */
11 #define V3D_SET_FIELD(value, field) \
13 u32 fieldval = (value) << field##_SHIFT; \
14 WARN_ON((fieldval & ~field##_MASK) != 0); \
15 fieldval & field##_MASK; \
18 #define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \
21 /* Hub registers for shared hardware between V3D cores. */
23 #define V3D_HUB_AXICFG 0x00000
24 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
25 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
26 #define V3D_HUB_UIFCFG 0x00004
27 #define V3D_HUB_IDENT0 0x00008
29 #define V3D_HUB_IDENT1 0x0000c
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
34 # define V3D_HUB_IDENT1_NHOSTS_MASK V3D_MASK(15, 12)
35 # define V3D_HUB_IDENT1_NHOSTS_SHIFT 12
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
38 # define V3D_HUB_IDENT1_REV_MASK V3D_MASK(7, 4)
39 # define V3D_HUB_IDENT1_REV_SHIFT 4
40 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
41 # define V3D_HUB_IDENT1_TVER_SHIFT 0
43 #define V3D_HUB_IDENT2 0x00010
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
45 # define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0)
46 # define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0
48 #define V3D_HUB_IDENT3 0x00014
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
51 # define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0)
52 # define V3D_HUB_IDENT3_IPIDX_SHIFT 0
54 #define V3D_HUB_INT_STS 0x00050
55 #define V3D_HUB_INT_SET 0x00054
56 #define V3D_HUB_INT_CLR 0x00058
57 #define V3D_HUB_INT_MSK_STS 0x0005c
58 #define V3D_HUB_INT_MSK_SET 0x00060
59 #define V3D_HUB_INT_MSK_CLR 0x00064
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
61 # define V3D_HUB_INT_MMU_PTI BIT(4)
62 # define V3D_HUB_INT_MMU_CAP BIT(3)
63 # define V3D_HUB_INT_MSO BIT(2)
64 # define V3D_HUB_INT_TFUC BIT(1)
65 # define V3D_HUB_INT_TFUF BIT(0)
67 #define V3D_GCA_CACHE_CTRL 0x0000c
68 # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0)
70 #define V3D_GCA_SAFE_SHUTDOWN 0x000b0
71 # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0)
73 #define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4
74 # define V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED 3
76 # define V3D_TOP_GR_BRIDGE_REVISION 0x00000
77 # define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8)
78 # define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8
79 # define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0)
80 # define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0
83 # define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008
84 # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0)
86 # define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c
87 # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
89 #define V3D_TFU_CS 0x00400
90 /* Stops current job, empties input fifo. */
91 # define V3D_TFU_CS_TFURST BIT(31)
92 # define V3D_TFU_CS_CVTCT_MASK V3D_MASK(23, 16)
93 # define V3D_TFU_CS_CVTCT_SHIFT 16
94 # define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8)
95 # define V3D_TFU_CS_NFREE_SHIFT 8
96 # define V3D_TFU_CS_BUSY BIT(0)
98 #define V3D_TFU_SU 0x00404
99 /* Interrupt when FINTTHR input slots are free (0 = disabled) */
100 # define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8)
101 # define V3D_TFU_SU_FINTTHR_SHIFT 8
102 /* Skips resetting the CRC at the start of CRC generation. */
103 # define V3D_TFU_SU_CRCCHAIN BIT(4)
104 /* skips writes, computes CRC of the image. miplevels must be 0. */
105 # define V3D_TFU_SU_CRC BIT(3)
106 # define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0)
107 # define V3D_TFU_SU_THROTTLE_SHIFT 0
109 #define V3D_TFU_ICFG 0x00408
110 /* Interrupt when the conversion is complete. */
111 # define V3D_TFU_ICFG_IOC BIT(0)
113 /* Input Image Address */
114 #define V3D_TFU_IIA 0x0040c
115 /* Input Chroma Address */
116 #define V3D_TFU_ICA 0x00410
117 /* Input Image Stride */
118 #define V3D_TFU_IIS 0x00414
119 /* Input Image U-Plane Address */
120 #define V3D_TFU_IUA 0x00418
121 /* Output Image Address */
122 #define V3D_TFU_IOA 0x0041c
123 /* Image Output Size */
124 #define V3D_TFU_IOS 0x00420
125 /* TFU YUV Coefficient 0 */
126 #define V3D_TFU_COEF0 0x00424
127 /* Use these regs instead of the defaults. */
128 # define V3D_TFU_COEF0_USECOEF BIT(31)
129 /* TFU YUV Coefficient 1 */
130 #define V3D_TFU_COEF1 0x00428
131 /* TFU YUV Coefficient 2 */
132 #define V3D_TFU_COEF2 0x0042c
133 /* TFU YUV Coefficient 3 */
134 #define V3D_TFU_COEF3 0x00430
136 #define V3D_TFU_CRC 0x00434
138 /* Per-MMU registers. */
140 #define V3D_MMUC_CONTROL 0x01000
141 # define V3D_MMUC_CONTROL_CLEAR BIT(3)
142 # define V3D_MMUC_CONTROL_FLUSHING BIT(2)
143 # define V3D_MMUC_CONTROL_FLUSH BIT(1)
144 # define V3D_MMUC_CONTROL_ENABLE BIT(0)
146 #define V3D_MMU_CTL 0x01200
147 # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27)
148 # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26)
149 # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25)
150 # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24)
151 # define V3D_MMU_CTL_PT_INVALID BIT(20)
152 # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19)
153 # define V3D_MMU_CTL_PT_INVALID_INT BIT(18)
154 # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17)
155 # define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16)
156 # define V3D_MMU_CTL_WRITE_VIOLATION BIT(12)
157 # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11)
158 # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10)
159 # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9)
160 # define V3D_MMU_CTL_TLB_CLEARING BIT(7)
161 # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3)
162 # define V3D_MMU_CTL_TLB_CLEAR BIT(2)
163 # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1)
164 # define V3D_MMU_CTL_ENABLE BIT(0)
166 #define V3D_MMU_PT_PA_BASE 0x01204
167 #define V3D_MMU_HIT 0x01208
168 #define V3D_MMU_MISSES 0x0120c
169 #define V3D_MMU_STALLS 0x01210
171 #define V3D_MMU_ADDR_CAP 0x01214
172 # define V3D_MMU_ADDR_CAP_ENABLE BIT(31)
173 # define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0)
174 # define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0
176 #define V3D_MMU_SHOOT_DOWN 0x01218
177 # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29)
178 # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28)
179 # define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0)
180 # define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0
182 #define V3D_MMU_BYPASS_START 0x0121c
183 #define V3D_MMU_BYPASS_END 0x01220
185 /* AXI ID of the access that faulted */
186 #define V3D_MMU_VIO_ID 0x0122c
188 /* Address for illegal PTEs to return */
189 #define V3D_MMU_ILLEGAL_ADDR 0x01230
190 # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31)
192 /* Address that faulted */
193 #define V3D_MMU_VIO_ADDR 0x01234
195 #define V3D_MMU_DEBUG_INFO 0x01238
196 # define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
197 # define V3D_MMU_PA_WIDTH_SHIFT 8
198 # define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4)
199 # define V3D_MMU_VA_WIDTH_SHIFT 4
200 # define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
201 # define V3D_MMU_VERSION_SHIFT 0
203 /* Per-V3D-core registers */
205 #define V3D_CTL_IDENT0 0x00000
206 # define V3D_IDENT0_VER_MASK V3D_MASK(31, 24)
207 # define V3D_IDENT0_VER_SHIFT 24
209 #define V3D_CTL_IDENT1 0x00004
210 /* Multiples of 1kb */
211 # define V3D_IDENT1_VPM_SIZE_MASK V3D_MASK(31, 28)
212 # define V3D_IDENT1_VPM_SIZE_SHIFT 28
213 # define V3D_IDENT1_NSEM_MASK V3D_MASK(23, 16)
214 # define V3D_IDENT1_NSEM_SHIFT 16
215 # define V3D_IDENT1_NTMU_MASK V3D_MASK(15, 12)
216 # define V3D_IDENT1_NTMU_SHIFT 12
217 # define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8)
218 # define V3D_IDENT1_QUPS_SHIFT 8
219 # define V3D_IDENT1_NSLC_MASK V3D_MASK(7, 4)
220 # define V3D_IDENT1_NSLC_SHIFT 4
221 # define V3D_IDENT1_REV_MASK V3D_MASK(3, 0)
222 # define V3D_IDENT1_REV_SHIFT 0
224 #define V3D_CTL_IDENT2 0x00008
225 # define V3D_IDENT2_BCG_INT BIT(28)
227 #define V3D_CTL_MISCCFG 0x00018
228 # define V3D_CTL_MISCCFG_QRMAXCNT_MASK V3D_MASK(3, 1)
229 # define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT 1
230 # define V3D_MISCCFG_OVRTMUOUT BIT(0)
232 #define V3D_CTL_L2CACTL 0x00020
233 # define V3D_L2CACTL_L2CCLR BIT(2)
234 # define V3D_L2CACTL_L2CDIS BIT(1)
235 # define V3D_L2CACTL_L2CENA BIT(0)
237 #define V3D_CTL_SLCACTL 0x00024
238 # define V3D_SLCACTL_TVCCS_MASK V3D_MASK(27, 24)
239 # define V3D_SLCACTL_TVCCS_SHIFT 24
240 # define V3D_SLCACTL_TDCCS_MASK V3D_MASK(19, 16)
241 # define V3D_SLCACTL_TDCCS_SHIFT 16
242 # define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8)
243 # define V3D_SLCACTL_UCC_SHIFT 8
244 # define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0)
245 # define V3D_SLCACTL_ICC_SHIFT 0
247 #define V3D_CTL_L2TCACTL 0x00030
248 # define V3D_L2TCACTL_TMUWCF BIT(8)
249 # define V3D_L2TCACTL_L2T_NO_WM BIT(4)
250 /* Invalidates cache lines. */
251 # define V3D_L2TCACTL_FLM_FLUSH 0
252 /* Removes cachelines without writing dirty lines back. */
253 # define V3D_L2TCACTL_FLM_CLEAR 1
254 /* Writes out dirty cachelines and marks them clean, but doesn't invalidate. */
255 # define V3D_L2TCACTL_FLM_CLEAN 2
256 # define V3D_L2TCACTL_FLM_MASK V3D_MASK(2, 1)
257 # define V3D_L2TCACTL_FLM_SHIFT 1
258 # define V3D_L2TCACTL_L2TFLS BIT(0)
259 #define V3D_CTL_L2TFLSTA 0x00034
260 #define V3D_CTL_L2TFLEND 0x00038
262 #define V3D_CTL_INT_STS 0x00050
263 #define V3D_CTL_INT_SET 0x00054
264 #define V3D_CTL_INT_CLR 0x00058
265 #define V3D_CTL_INT_MSK_STS 0x0005c
266 #define V3D_CTL_INT_MSK_SET 0x00060
267 #define V3D_CTL_INT_MSK_CLR 0x00064
268 # define V3D_INT_QPU_MASK V3D_MASK(27, 16)
269 # define V3D_INT_QPU_SHIFT 16
270 # define V3D_INT_CSDDONE BIT(7)
271 # define V3D_INT_PCTR BIT(6)
272 # define V3D_INT_GMPV BIT(5)
273 # define V3D_INT_TRFB BIT(4)
274 # define V3D_INT_SPILLUSE BIT(3)
275 # define V3D_INT_OUTOMEM BIT(2)
276 # define V3D_INT_FLDONE BIT(1)
277 # define V3D_INT_FRDONE BIT(0)
279 #define V3D_CLE_CT0CS 0x00100
280 #define V3D_CLE_CT1CS 0x00104
281 #define V3D_CLE_CTNCS(n) (V3D_CLE_CT0CS + 4 * n)
282 #define V3D_CLE_CT0EA 0x00108
283 #define V3D_CLE_CT1EA 0x0010c
284 #define V3D_CLE_CTNEA(n) (V3D_CLE_CT0EA + 4 * n)
285 #define V3D_CLE_CT0CA 0x00110
286 #define V3D_CLE_CT1CA 0x00114
287 #define V3D_CLE_CTNCA(n) (V3D_CLE_CT0CA + 4 * n)
288 #define V3D_CLE_CT0RA 0x00118
289 #define V3D_CLE_CT1RA 0x0011c
290 #define V3D_CLE_CTNRA(n) (V3D_CLE_CT0RA + 4 * n)
291 #define V3D_CLE_CT0LC 0x00120
292 #define V3D_CLE_CT1LC 0x00124
293 #define V3D_CLE_CT0PC 0x00128
294 #define V3D_CLE_CT1PC 0x0012c
295 #define V3D_CLE_PCS 0x00130
296 #define V3D_CLE_BFC 0x00134
297 #define V3D_CLE_RFC 0x00138
298 #define V3D_CLE_TFBC 0x0013c
299 #define V3D_CLE_TFIT 0x00140
300 #define V3D_CLE_CT1CFG 0x00144
301 #define V3D_CLE_CT1TILECT 0x00148
302 #define V3D_CLE_CT1TSKIP 0x0014c
303 #define V3D_CLE_CT1PTCT 0x00150
304 #define V3D_CLE_CT0SYNC 0x00154
305 #define V3D_CLE_CT1SYNC 0x00158
306 #define V3D_CLE_CT0QTS 0x0015c
307 # define V3D_CLE_CT0QTS_ENABLE BIT(1)
308 #define V3D_CLE_CT0QBA 0x00160
309 #define V3D_CLE_CT1QBA 0x00164
310 #define V3D_CLE_CTNQBA(n) (V3D_CLE_CT0QBA + 4 * n)
311 #define V3D_CLE_CT0QEA 0x00168
312 #define V3D_CLE_CT1QEA 0x0016c
313 #define V3D_CLE_CTNQEA(n) (V3D_CLE_CT0QEA + 4 * n)
314 #define V3D_CLE_CT0QMA 0x00170
315 #define V3D_CLE_CT0QMS 0x00174
316 #define V3D_CLE_CT1QCFG 0x00178
317 /* If set without ETPROC, entirely skip tiles with no primitives. */
318 # define V3D_CLE_QCFG_ETFILT BIT(7)
319 /* If set with ETFILT, just write the clear color to tiles with no
322 # define V3D_CLE_QCFG_ETPROC BIT(6)
323 # define V3D_CLE_QCFG_ETSFLUSH BIT(1)
324 # define V3D_CLE_QCFG_MCDIS BIT(0)
326 #define V3D_PTB_BPCA 0x00300
327 #define V3D_PTB_BPCS 0x00304
328 #define V3D_PTB_BPOA 0x00308
329 #define V3D_PTB_BPOS 0x0030c
331 #define V3D_PTB_BXCF 0x00310
332 # define V3D_PTB_BXCF_RWORDERDISA BIT(1)
333 # define V3D_PTB_BXCF_CLIPDISA BIT(0)
335 #define V3D_V3_PCTR_0_EN 0x00674
336 #define V3D_V3_PCTR_0_EN_ENABLE BIT(31)
337 #define V3D_V4_PCTR_0_EN 0x00650
338 /* When a bit is set, resets the counter to 0. */
339 #define V3D_V3_PCTR_0_CLR 0x00670
340 #define V3D_V4_PCTR_0_CLR 0x00654
341 #define V3D_PCTR_0_OVERFLOW 0x00658
343 #define V3D_V3_PCTR_0_PCTRS0 0x00684
344 #define V3D_V3_PCTR_0_PCTRS15 0x00660
345 #define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \
347 /* Each src reg muxes four counters each. */
348 #define V3D_V4_PCTR_0_SRC_0_3 0x00660
349 #define V3D_V4_PCTR_0_SRC_28_31 0x0067c
350 # define V3D_PCTR_S0_MASK V3D_MASK(6, 0)
351 # define V3D_PCTR_S0_SHIFT 0
352 # define V3D_PCTR_S1_MASK V3D_MASK(14, 8)
353 # define V3D_PCTR_S1_SHIFT 8
354 # define V3D_PCTR_S2_MASK V3D_MASK(22, 16)
355 # define V3D_PCTR_S2_SHIFT 16
356 # define V3D_PCTR_S3_MASK V3D_MASK(30, 24)
357 # define V3D_PCTR_S3_SHIFT 24
358 # define V3D_PCTR_CYCLE_COUNT 32
360 /* Output values of the counters. */
361 #define V3D_PCTR_0_PCTR0 0x00680
362 #define V3D_PCTR_0_PCTR31 0x006fc
363 #define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \
365 #define V3D_GMP_STATUS 0x00800
366 # define V3D_GMP_STATUS_GMPRST BIT(31)
367 # define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24)
368 # define V3D_GMP_STATUS_WR_COUNT_SHIFT 24
369 # define V3D_GMP_STATUS_RD_COUNT_MASK V3D_MASK(22, 16)
370 # define V3D_GMP_STATUS_RD_COUNT_SHIFT 16
371 # define V3D_GMP_STATUS_WR_ACTIVE BIT(5)
372 # define V3D_GMP_STATUS_RD_ACTIVE BIT(4)
373 # define V3D_GMP_STATUS_CFG_BUSY BIT(3)
374 # define V3D_GMP_STATUS_CNTOVF BIT(2)
375 # define V3D_GMP_STATUS_INVPROT BIT(1)
376 # define V3D_GMP_STATUS_VIO BIT(0)
378 #define V3D_GMP_CFG 0x00804
379 # define V3D_GMP_CFG_LBURSTEN BIT(3)
380 # define V3D_GMP_CFG_PGCRSEN BIT()
381 # define V3D_GMP_CFG_STOP_REQ BIT(1)
382 # define V3D_GMP_CFG_PROT_ENABLE BIT(0)
384 #define V3D_GMP_VIO_ADDR 0x00808
385 #define V3D_GMP_VIO_TYPE 0x0080c
386 #define V3D_GMP_TABLE_ADDR 0x00810
387 #define V3D_GMP_CLEAR_LOAD 0x00814
388 #define V3D_GMP_PRESERVE_LOAD 0x00818
389 #define V3D_GMP_VALID_LINES 0x00820
391 #define V3D_CSD_STATUS 0x00900
392 # define V3D_CSD_STATUS_NUM_COMPLETED_MASK V3D_MASK(11, 4)
393 # define V3D_CSD_STATUS_NUM_COMPLETED_SHIFT 4
394 # define V3D_CSD_STATUS_NUM_ACTIVE_MASK V3D_MASK(3, 2)
395 # define V3D_CSD_STATUS_NUM_ACTIVE_SHIFT 2
396 # define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1)
397 # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
399 #define V3D_CSD_QUEUED_CFG0 0x00904
400 # define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK V3D_MASK(31, 16)
401 # define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT 16
402 # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0)
403 # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0
405 #define V3D_CSD_QUEUED_CFG1 0x00908
406 # define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK V3D_MASK(31, 16)
407 # define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT 16
408 # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0)
409 # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0
411 #define V3D_CSD_QUEUED_CFG2 0x0090c
412 # define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK V3D_MASK(31, 16)
413 # define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT 16
414 # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0)
415 # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0
417 #define V3D_CSD_QUEUED_CFG3 0x00910
418 # define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26)
419 # define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK V3D_MASK(25, 20)
420 # define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT 20
421 # define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK V3D_MASK(19, 12)
422 # define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT 12
423 # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8)
424 # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8
425 # define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0)
426 # define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0
428 /* Number of batches, minus 1 */
429 #define V3D_CSD_QUEUED_CFG4 0x00914
431 /* Shader address, pnan, singleseg, threading, like a shader record. */
432 #define V3D_CSD_QUEUED_CFG5 0x00918
434 /* Uniforms address (4 byte aligned) */
435 #define V3D_CSD_QUEUED_CFG6 0x0091c
437 #define V3D_CSD_CURRENT_CFG0 0x00920
438 #define V3D_CSD_CURRENT_CFG1 0x00924
439 #define V3D_CSD_CURRENT_CFG2 0x00928
440 #define V3D_CSD_CURRENT_CFG3 0x0092c
441 #define V3D_CSD_CURRENT_CFG4 0x00930
442 #define V3D_CSD_CURRENT_CFG5 0x00934
443 #define V3D_CSD_CURRENT_CFG6 0x00938
445 #define V3D_CSD_CURRENT_ID0 0x0093c
446 # define V3D_CSD_CURRENT_ID0_WG_X_MASK V3D_MASK(31, 16)
447 # define V3D_CSD_CURRENT_ID0_WG_X_SHIFT 16
448 # define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8)
449 # define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8
450 # define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0)
451 # define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0
453 #define V3D_CSD_CURRENT_ID1 0x00940
454 # define V3D_CSD_CURRENT_ID0_WG_Z_MASK V3D_MASK(31, 16)
455 # define V3D_CSD_CURRENT_ID0_WG_Z_SHIFT 16
456 # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0)
457 # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0
459 #define V3D_ERR_FDBGO 0x00f04
460 #define V3D_ERR_FDBGB 0x00f08
461 #define V3D_ERR_FDBGR 0x00f0c
463 #define V3D_ERR_FDBGS 0x00f10
464 # define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17)
465 # define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16)
466 # define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14)
467 # define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13)
468 # define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12)
469 # define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11)
470 # define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7)
471 # define V3D_ERR_FDBGS_EZTEST_PASS BIT(6)
472 # define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5)
473 # define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4)
474 # define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3)
475 # define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2)
476 # define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1)
477 # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
479 #define V3D_ERR_STAT 0x00f20
480 # define V3D_ERR_L2CARE BIT(15)
481 # define V3D_ERR_VCMBE BIT(14)
482 # define V3D_ERR_VCMRE BIT(13)
483 # define V3D_ERR_VCDI BIT(12)
484 # define V3D_ERR_VCDE BIT(11)
485 # define V3D_ERR_VDWE BIT(10)
486 # define V3D_ERR_VPMEAS BIT(9)
487 # define V3D_ERR_VPMEFNA BIT(8)
488 # define V3D_ERR_VPMEWNA BIT(7)
489 # define V3D_ERR_VPMERNA BIT(6)
490 # define V3D_ERR_VPMERR BIT(5)
491 # define V3D_ERR_VPMEWR BIT(4)
492 # define V3D_ERR_VPAERRGL BIT(3)
493 # define V3D_ERR_VPAEBRGL BIT(2)
494 # define V3D_ERR_VPAERGS BIT(1)
495 # define V3D_ERR_VPAEABB BIT(0)
497 #endif /* V3D_REGS_H */