WIP FPC-III support
[linux/fpc-iii.git] / drivers / gpu / host1x / hw / hw_host1x04_channel.h
blob38d110645ee02322b2d0d3bfd3c3735d1bc16ce3
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2013 NVIDIA Corporation.
4 */
6 /*
7 * Function naming determines intended use:
9 * <x>_r(void) : Returns the offset for register <x>.
11 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
13 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
16 * and masked to place it at field <y> of register <x>. This value
17 * can be |'d with others to produce a full register value for
18 * register <x>.
20 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
21 * value can be ~'d and then &'d to clear the value of field <y> for
22 * register <x>.
24 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
25 * to place it at field <y> of register <x>. This value can be |'d
26 * with others to produce a full register value for <x>.
28 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
30 * This value is suitable for direct comparison with other unshifted
31 * values appropriate for use in field <y> of register <x>.
33 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
34 * field <y> of register <x>. This value is suitable for direct
35 * comparison with unshifted values appropriate for use in field <y>
36 * of register <x>.
39 #ifndef HOST1X_HW_HOST1X04_CHANNEL_H
40 #define HOST1X_HW_HOST1X04_CHANNEL_H
42 static inline u32 host1x_channel_fifostat_r(void)
44 return 0x0;
46 #define HOST1X_CHANNEL_FIFOSTAT \
47 host1x_channel_fifostat_r()
48 static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)
50 return (r >> 11) & 0x1;
52 #define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \
53 host1x_channel_fifostat_cfempty_v(r)
54 static inline u32 host1x_channel_dmastart_r(void)
56 return 0x14;
58 #define HOST1X_CHANNEL_DMASTART \
59 host1x_channel_dmastart_r()
60 static inline u32 host1x_channel_dmaput_r(void)
62 return 0x18;
64 #define HOST1X_CHANNEL_DMAPUT \
65 host1x_channel_dmaput_r()
66 static inline u32 host1x_channel_dmaget_r(void)
68 return 0x1c;
70 #define HOST1X_CHANNEL_DMAGET \
71 host1x_channel_dmaget_r()
72 static inline u32 host1x_channel_dmaend_r(void)
74 return 0x20;
76 #define HOST1X_CHANNEL_DMAEND \
77 host1x_channel_dmaend_r()
78 static inline u32 host1x_channel_dmactrl_r(void)
80 return 0x24;
82 #define HOST1X_CHANNEL_DMACTRL \
83 host1x_channel_dmactrl_r()
84 static inline u32 host1x_channel_dmactrl_dmastop(void)
86 return 1 << 0;
88 #define HOST1X_CHANNEL_DMACTRL_DMASTOP \
89 host1x_channel_dmactrl_dmastop()
90 static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)
92 return (r >> 0) & 0x1;
94 #define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \
95 host1x_channel_dmactrl_dmastop_v(r)
96 static inline u32 host1x_channel_dmactrl_dmagetrst(void)
98 return 1 << 1;
100 #define HOST1X_CHANNEL_DMACTRL_DMAGETRST \
101 host1x_channel_dmactrl_dmagetrst()
102 static inline u32 host1x_channel_dmactrl_dmainitget(void)
104 return 1 << 2;
106 #define HOST1X_CHANNEL_DMACTRL_DMAINITGET \
107 host1x_channel_dmactrl_dmainitget()
108 static inline u32 host1x_channel_channelctrl_r(void)
110 return 0x98;
112 #define HOST1X_CHANNEL_CHANNELCTRL \
113 host1x_channel_channelctrl_r()
114 static inline u32 host1x_channel_channelctrl_kernel_filter_gbuffer_f(u32 v)
116 return (v & 0x1) << 2;
118 #define HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(v) \
119 host1x_channel_channelctrl_kernel_filter_gbuffer_f(v)
121 #endif