drivers/i2c/busses/i2c-designware-core.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Synopsys DesignWare I2C adapter driver.
   4  *
   5  * Based on the TI DAVINCI I2C adapter driver.
   6  *
   7  * Copyright (C) 2006 Texas Instruments.
   8  * Copyright (C) 2007 MontaVista Software Inc.
   9  * Copyright (C) 2009 Provigent Ltd.
  10  */
  11
  12 #include <linux/bits.h>
  13 #include <linux/compiler_types.h>
  14 #include <linux/completion.h>
  15 #include <linux/dev_printk.h>
  16 #include <linux/errno.h>
  17 #include <linux/i2c.h>
  18 #include <linux/regmap.h>
  19 #include <linux/types.h>
  20
  21 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |                     \
  22                                         I2C_FUNC_SMBUS_BYTE |           \
  23                                         I2C_FUNC_SMBUS_BYTE_DATA |      \
  24                                         I2C_FUNC_SMBUS_WORD_DATA |      \
  25                                         I2C_FUNC_SMBUS_BLOCK_DATA |     \
  26                                         I2C_FUNC_SMBUS_I2C_BLOCK)
  27
  28 #define DW_IC_CON_MASTER                        BIT(0)
  29 #define DW_IC_CON_SPEED_STD                     (1 << 1)
  30 #define DW_IC_CON_SPEED_FAST                    (2 << 1)
  31 #define DW_IC_CON_SPEED_HIGH                    (3 << 1)
  32 #define DW_IC_CON_SPEED_MASK                    GENMASK(2, 1)
  33 #define DW_IC_CON_10BITADDR_SLAVE               BIT(3)
  34 #define DW_IC_CON_10BITADDR_MASTER              BIT(4)
  35 #define DW_IC_CON_RESTART_EN                    BIT(5)
  36 #define DW_IC_CON_SLAVE_DISABLE                 BIT(6)
  37 #define DW_IC_CON_STOP_DET_IFADDRESSED          BIT(7)
  38 #define DW_IC_CON_TX_EMPTY_CTRL                 BIT(8)
  39 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL         BIT(9)
  40
  41 /*
  42  * Registers offset
  43  */
  44 #define DW_IC_CON               0x00
  45 #define DW_IC_TAR               0x04
  46 #define DW_IC_SAR               0x08
  47 #define DW_IC_DATA_CMD          0x10
  48 #define DW_IC_SS_SCL_HCNT       0x14
  49 #define DW_IC_SS_SCL_LCNT       0x18
  50 #define DW_IC_FS_SCL_HCNT       0x1c
  51 #define DW_IC_FS_SCL_LCNT       0x20
  52 #define DW_IC_HS_SCL_HCNT       0x24
  53 #define DW_IC_HS_SCL_LCNT       0x28
  54 #define DW_IC_INTR_STAT         0x2c
  55 #define DW_IC_INTR_MASK         0x30
  56 #define DW_IC_RAW_INTR_STAT     0x34
  57 #define DW_IC_RX_TL             0x38
  58 #define DW_IC_TX_TL             0x3c
  59 #define DW_IC_CLR_INTR          0x40
  60 #define DW_IC_CLR_RX_UNDER      0x44
  61 #define DW_IC_CLR_RX_OVER       0x48
  62 #define DW_IC_CLR_TX_OVER       0x4c
  63 #define DW_IC_CLR_RD_REQ        0x50
  64 #define DW_IC_CLR_TX_ABRT       0x54
  65 #define DW_IC_CLR_RX_DONE       0x58
  66 #define DW_IC_CLR_ACTIVITY      0x5c
  67 #define DW_IC_CLR_STOP_DET      0x60
  68 #define DW_IC_CLR_START_DET     0x64
  69 #define DW_IC_CLR_GEN_CALL      0x68
  70 #define DW_IC_ENABLE            0x6c
  71 #define DW_IC_STATUS            0x70
  72 #define DW_IC_TXFLR             0x74
  73 #define DW_IC_RXFLR             0x78
  74 #define DW_IC_SDA_HOLD          0x7c
  75 #define DW_IC_TX_ABRT_SOURCE    0x80
  76 #define DW_IC_ENABLE_STATUS     0x9c
  77 #define DW_IC_CLR_RESTART_DET   0xa8
  78 #define DW_IC_COMP_PARAM_1      0xf4
  79 #define DW_IC_COMP_VERSION      0xf8
  80 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
  81 #define DW_IC_COMP_TYPE         0xfc
  82 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  83
  84 #define DW_IC_INTR_RX_UNDER     BIT(0)
  85 #define DW_IC_INTR_RX_OVER      BIT(1)
  86 #define DW_IC_INTR_RX_FULL      BIT(2)
  87 #define DW_IC_INTR_TX_OVER      BIT(3)
  88 #define DW_IC_INTR_TX_EMPTY     BIT(4)
  89 #define DW_IC_INTR_RD_REQ       BIT(5)
  90 #define DW_IC_INTR_TX_ABRT      BIT(6)
  91 #define DW_IC_INTR_RX_DONE      BIT(7)
  92 #define DW_IC_INTR_ACTIVITY     BIT(8)
  93 #define DW_IC_INTR_STOP_DET     BIT(9)
  94 #define DW_IC_INTR_START_DET    BIT(10)
  95 #define DW_IC_INTR_GEN_CALL     BIT(11)
  96 #define DW_IC_INTR_RESTART_DET  BIT(12)
  97
  98 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  99                                          DW_IC_INTR_TX_ABRT | \
 100                                          DW_IC_INTR_STOP_DET)
 101 #define DW_IC_INTR_MASTER_MASK          (DW_IC_INTR_DEFAULT_MASK | \
 102                                          DW_IC_INTR_TX_EMPTY)
 103 #define DW_IC_INTR_SLAVE_MASK           (DW_IC_INTR_DEFAULT_MASK | \
 104                                          DW_IC_INTR_RX_DONE | \
 105                                          DW_IC_INTR_RX_UNDER | \
 106                                          DW_IC_INTR_RD_REQ)
 107
 108 #define DW_IC_STATUS_ACTIVITY           BIT(0)
 109 #define DW_IC_STATUS_TFE                BIT(2)
 110 #define DW_IC_STATUS_MASTER_ACTIVITY    BIT(5)
 111 #define DW_IC_STATUS_SLAVE_ACTIVITY     BIT(6)
 112
 113 #define DW_IC_SDA_HOLD_RX_SHIFT         16
 114 #define DW_IC_SDA_HOLD_RX_MASK          GENMASK(23, 16)
 115
 116 #define DW_IC_ERR_TX_ABRT       0x1
 117
 118 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
 119
 120 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
 121 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      GENMASK(3, 2)
 122
 123 /*
 124  * status codes
 125  */
 126 #define STATUS_IDLE                     0x0
 127 #define STATUS_WRITE_IN_PROGRESS        0x1
 128 #define STATUS_READ_IN_PROGRESS         0x2
 129
 130 /*
 131  * operation modes
 132  */
 133 #define DW_IC_MASTER            0
 134 #define DW_IC_SLAVE             1
 135
 136 /*
 137  * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 138  *
 139  * Only expected abort codes are listed here
 140  * refer to the datasheet for the full list
 141  */
 142 #define ABRT_7B_ADDR_NOACK      0
 143 #define ABRT_10ADDR1_NOACK      1
 144 #define ABRT_10ADDR2_NOACK      2
 145 #define ABRT_TXDATA_NOACK       3
 146 #define ABRT_GCALL_NOACK        4
 147 #define ABRT_GCALL_READ         5
 148 #define ABRT_SBYTE_ACKDET       7
 149 #define ABRT_SBYTE_NORSTRT      9
 150 #define ABRT_10B_RD_NORSTRT     10
 151 #define ABRT_MASTER_DIS         11
 152 #define ARB_LOST                12
 153 #define ABRT_SLAVE_FLUSH_TXFIFO 13
 154 #define ABRT_SLAVE_ARBLOST      14
 155 #define ABRT_SLAVE_RD_INTX      15
 156
 157 #define DW_IC_TX_ABRT_7B_ADDR_NOACK             BIT(ABRT_7B_ADDR_NOACK)
 158 #define DW_IC_TX_ABRT_10ADDR1_NOACK             BIT(ABRT_10ADDR1_NOACK)
 159 #define DW_IC_TX_ABRT_10ADDR2_NOACK             BIT(ABRT_10ADDR2_NOACK)
 160 #define DW_IC_TX_ABRT_TXDATA_NOACK              BIT(ABRT_TXDATA_NOACK)
 161 #define DW_IC_TX_ABRT_GCALL_NOACK               BIT(ABRT_GCALL_NOACK)
 162 #define DW_IC_TX_ABRT_GCALL_READ                BIT(ABRT_GCALL_READ)
 163 #define DW_IC_TX_ABRT_SBYTE_ACKDET              BIT(ABRT_SBYTE_ACKDET)
 164 #define DW_IC_TX_ABRT_SBYTE_NORSTRT             BIT(ABRT_SBYTE_NORSTRT)
 165 #define DW_IC_TX_ABRT_10B_RD_NORSTRT            BIT(ABRT_10B_RD_NORSTRT)
 166 #define DW_IC_TX_ABRT_MASTER_DIS                BIT(ABRT_MASTER_DIS)
 167 #define DW_IC_TX_ARB_LOST                       BIT(ARB_LOST)
 168 #define DW_IC_RX_ABRT_SLAVE_RD_INTX             BIT(ABRT_SLAVE_RD_INTX)
 169 #define DW_IC_RX_ABRT_SLAVE_ARBLOST             BIT(ABRT_SLAVE_ARBLOST)
 170 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO        BIT(ABRT_SLAVE_FLUSH_TXFIFO)
 171
 172 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 173                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 174                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 175                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 176                                          DW_IC_TX_ABRT_GCALL_NOACK)
 177
 178 struct clk;
 179 struct device;
 180 struct reset_control;
 181
 182 /**
 183  * struct dw_i2c_dev - private i2c-designware data
 184  * @dev: driver model device node
 185  * @map: IO registers map
 186  * @sysmap: System controller registers map
 187  * @base: IO registers pointer
 188  * @ext: Extended IO registers pointer
 189  * @cmd_complete: tx completion indicator
 190  * @clk: input reference clock
 191  * @pclk: clock required to access the registers
 192  * @slave: represent an I2C slave device
 193  * @cmd_err: run time hadware error code
 194  * @msgs: points to an array of messages currently being transferred
 195  * @msgs_num: the number of elements in msgs
 196  * @msg_write_idx: the element index of the current tx message in the msgs
 197  *      array
 198  * @tx_buf_len: the length of the current tx buffer
 199  * @tx_buf: the current tx buffer
 200  * @msg_read_idx: the element index of the current rx message in the msgs
 201  *      array
 202  * @rx_buf_len: the length of the current rx buffer
 203  * @rx_buf: the current rx buffer
 204  * @msg_err: error status of the current transfer
 205  * @status: i2c master status, one of STATUS_*
 206  * @abort_source: copy of the TX_ABRT_SOURCE register
 207  * @irq: interrupt number for the i2c master
 208  * @adapter: i2c subsystem adapter node
 209  * @slave_cfg: configuration for the slave device
 210  * @tx_fifo_depth: depth of the hardware tx fifo
 211  * @rx_fifo_depth: depth of the hardware rx fifo
 212  * @rx_outstanding: current master-rx elements in tx fifo
 213  * @timings: bus clock frequency, SDA hold and other timings
 214  * @sda_hold_time: SDA hold value
 215  * @ss_hcnt: standard speed HCNT value
 216  * @ss_lcnt: standard speed LCNT value
 217  * @fs_hcnt: fast speed HCNT value
 218  * @fs_lcnt: fast speed LCNT value
 219  * @fp_hcnt: fast plus HCNT value
 220  * @fp_lcnt: fast plus LCNT value
 221  * @hs_hcnt: high speed HCNT value
 222  * @hs_lcnt: high speed LCNT value
 223  * @acquire_lock: function to acquire a hardware lock on the bus
 224  * @release_lock: function to release a hardware lock on the bus
 225  * @shared_with_punit: true if this bus is shared with the SoCs PUNIT
 226  * @disable: function to disable the controller
 227  * @disable_int: function to disable all interrupts
 228  * @init: function to initialize the I2C hardware
 229  * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
 230  * @suspended: set to true if the controller is suspended
 231  *
 232  * HCNT and LCNT parameters can be used if the platform knows more accurate
 233  * values than the one computed based only on the input clock frequency.
 234  * Leave them to be %0 if not used.
 235  */
 236 struct dw_i2c_dev {
 237         struct device           *dev;
 238         struct regmap           *map;
 239         struct regmap           *sysmap;
 240         void __iomem            *base;
 241         void __iomem            *ext;
 242         struct completion       cmd_complete;
 243         struct clk              *clk;
 244         struct clk              *pclk;
 245         struct reset_control    *rst;
 246         struct i2c_client               *slave;
 247         u32                     (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
 248         int                     cmd_err;
 249         struct i2c_msg          *msgs;
 250         int                     msgs_num;
 251         int                     msg_write_idx;
 252         u32                     tx_buf_len;
 253         u8                      *tx_buf;
 254         int                     msg_read_idx;
 255         u32                     rx_buf_len;
 256         u8                      *rx_buf;
 257         int                     msg_err;
 258         unsigned int            status;
 259         u32                     abort_source;
 260         int                     irq;
 261         u32                     flags;
 262         struct i2c_adapter      adapter;
 263         u32                     functionality;
 264         u32                     master_cfg;
 265         u32                     slave_cfg;
 266         unsigned int            tx_fifo_depth;
 267         unsigned int            rx_fifo_depth;
 268         int                     rx_outstanding;
 269         struct i2c_timings      timings;
 270         u32                     sda_hold_time;
 271         u16                     ss_hcnt;
 272         u16                     ss_lcnt;
 273         u16                     fs_hcnt;
 274         u16                     fs_lcnt;
 275         u16                     fp_hcnt;
 276         u16                     fp_lcnt;
 277         u16                     hs_hcnt;
 278         u16                     hs_lcnt;
 279         int                     (*acquire_lock)(void);
 280         void                    (*release_lock)(void);
 281         bool                    shared_with_punit;
 282         void                    (*disable)(struct dw_i2c_dev *dev);
 283         void                    (*disable_int)(struct dw_i2c_dev *dev);
 284         int                     (*init)(struct dw_i2c_dev *dev);
 285         int                     (*set_sda_hold_time)(struct dw_i2c_dev *dev);
 286         int                     mode;
 287         struct i2c_bus_recovery_info rinfo;
 288         bool                    suspended;
 289 };
 290
 291 #define ACCESS_INTR_MASK        BIT(0)
 292 #define ACCESS_NO_IRQ_SUSPEND   BIT(1)
 293
 294 #define MODEL_MSCC_OCELOT       BIT(8)
 295 #define MODEL_BAIKAL_BT1        BIT(9)
 296 #define MODEL_MASK              GENMASK(11, 8)
 297
 298 int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
 299 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
 300 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
 301 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
 302 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev);
 303 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
 304 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
 305 void i2c_dw_release_lock(struct dw_i2c_dev *dev);
 306 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
 307 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
 308 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
 309 u32 i2c_dw_func(struct i2c_adapter *adap);
 310 void i2c_dw_disable(struct dw_i2c_dev *dev);
 311 void i2c_dw_disable_int(struct dw_i2c_dev *dev);
 312
 313 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
 314 {
 315         regmap_write(dev->map, DW_IC_ENABLE, 1);
 316 }
 317
 318 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
 319 {
 320         regmap_write(dev->map, DW_IC_ENABLE, 0);
 321 }
 322
 323 void __i2c_dw_disable(struct dw_i2c_dev *dev);
 324
 325 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
 326 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
 327
 328 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
 329 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
 330 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
 331 #else
 332 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
 333 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
 334 #endif
 335
 336 static inline int i2c_dw_probe(struct dw_i2c_dev *dev)
 337 {
 338         switch (dev->mode) {
 339         case DW_IC_SLAVE:
 340                 return i2c_dw_probe_slave(dev);
 341         case DW_IC_MASTER:
 342                 return i2c_dw_probe_master(dev);
 343         default:
 344                 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);
 345                 return -EINVAL;
 346         }
 347 }
 348
 349 static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
 350 {
 351         if (i2c_detect_slave_mode(dev->dev))
 352                 i2c_dw_configure_slave(dev);
 353         else
 354                 i2c_dw_configure_master(dev);
 355 }
 356
 357 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
 358 extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev);
 359 #else
 360 static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; }
 361 #endif
 362
 363 int i2c_dw_validate_speed(struct dw_i2c_dev *dev);
 364 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev);
 365
 366 #if IS_ENABLED(CONFIG_ACPI)
 367 int i2c_dw_acpi_configure(struct device *device);
 368 #else
 369 static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; }
 370 #endif