1 // SPDX-License-Identifier: GPL-2.0+
3 * FSI-attached I2C master algorithm
5 * Copyright 2018 IBM Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/bitfield.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/errno.h>
18 #include <linux/fsi.h>
19 #include <linux/i2c.h>
20 #include <linux/jiffies.h>
21 #include <linux/kernel.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
26 #include <linux/slab.h>
28 #define FSI_ENGID_I2C 0x7
30 #define I2C_DEFAULT_CLK_DIV 6
33 #define I2C_FSI_FIFO 0x00
34 #define I2C_FSI_CMD 0x04
35 #define I2C_FSI_MODE 0x08
36 #define I2C_FSI_WATER_MARK 0x0C
37 #define I2C_FSI_INT_MASK 0x10
38 #define I2C_FSI_INT_COND 0x14
39 #define I2C_FSI_OR_INT_MASK 0x14
40 #define I2C_FSI_INTS 0x18
41 #define I2C_FSI_AND_INT_MASK 0x18
42 #define I2C_FSI_STAT 0x1C
43 #define I2C_FSI_RESET_I2C 0x1C
44 #define I2C_FSI_ESTAT 0x20
45 #define I2C_FSI_RESET_ERR 0x20
46 #define I2C_FSI_RESID_LEN 0x24
47 #define I2C_FSI_SET_SCL 0x24
48 #define I2C_FSI_PORT_BUSY 0x28
49 #define I2C_FSI_RESET_SCL 0x2C
50 #define I2C_FSI_SET_SDA 0x30
51 #define I2C_FSI_RESET_SDA 0x34
54 #define I2C_CMD_WITH_START BIT(31)
55 #define I2C_CMD_WITH_ADDR BIT(30)
56 #define I2C_CMD_RD_CONT BIT(29)
57 #define I2C_CMD_WITH_STOP BIT(28)
58 #define I2C_CMD_FORCELAUNCH BIT(27)
59 #define I2C_CMD_ADDR GENMASK(23, 17)
60 #define I2C_CMD_READ BIT(16)
61 #define I2C_CMD_LEN GENMASK(15, 0)
64 #define I2C_MODE_CLKDIV GENMASK(31, 16)
65 #define I2C_MODE_PORT GENMASK(15, 10)
66 #define I2C_MODE_ENHANCED BIT(3)
67 #define I2C_MODE_DIAG BIT(2)
68 #define I2C_MODE_PACE_ALLOW BIT(1)
69 #define I2C_MODE_WRAP BIT(0)
71 /* watermark register */
72 #define I2C_WATERMARK_HI GENMASK(15, 12)
73 #define I2C_WATERMARK_LO GENMASK(7, 4)
75 #define I2C_FIFO_HI_LVL 4
76 #define I2C_FIFO_LO_LVL 4
78 /* interrupt register */
79 #define I2C_INT_INV_CMD BIT(15)
80 #define I2C_INT_PARITY BIT(14)
81 #define I2C_INT_BE_OVERRUN BIT(13)
82 #define I2C_INT_BE_ACCESS BIT(12)
83 #define I2C_INT_LOST_ARB BIT(11)
84 #define I2C_INT_NACK BIT(10)
85 #define I2C_INT_DAT_REQ BIT(9)
86 #define I2C_INT_CMD_COMP BIT(8)
87 #define I2C_INT_STOP_ERR BIT(7)
88 #define I2C_INT_BUSY BIT(6)
89 #define I2C_INT_IDLE BIT(5)
92 #define I2C_STAT_INV_CMD BIT(31)
93 #define I2C_STAT_PARITY BIT(30)
94 #define I2C_STAT_BE_OVERRUN BIT(29)
95 #define I2C_STAT_BE_ACCESS BIT(28)
96 #define I2C_STAT_LOST_ARB BIT(27)
97 #define I2C_STAT_NACK BIT(26)
98 #define I2C_STAT_DAT_REQ BIT(25)
99 #define I2C_STAT_CMD_COMP BIT(24)
100 #define I2C_STAT_STOP_ERR BIT(23)
101 #define I2C_STAT_MAX_PORT GENMASK(22, 16)
102 #define I2C_STAT_ANY_INT BIT(15)
103 #define I2C_STAT_SCL_IN BIT(11)
104 #define I2C_STAT_SDA_IN BIT(10)
105 #define I2C_STAT_PORT_BUSY BIT(9)
106 #define I2C_STAT_SELF_BUSY BIT(8)
107 #define I2C_STAT_FIFO_COUNT GENMASK(7, 0)
109 #define I2C_STAT_ERR (I2C_STAT_INV_CMD | \
111 I2C_STAT_BE_OVERRUN | \
112 I2C_STAT_BE_ACCESS | \
113 I2C_STAT_LOST_ARB | \
116 #define I2C_STAT_ANY_RESP (I2C_STAT_ERR | \
120 /* extended status register */
121 #define I2C_ESTAT_FIFO_SZ GENMASK(31, 24)
122 #define I2C_ESTAT_SCL_IN_SY BIT(15)
123 #define I2C_ESTAT_SDA_IN_SY BIT(14)
124 #define I2C_ESTAT_S_SCL BIT(13)
125 #define I2C_ESTAT_S_SDA BIT(12)
126 #define I2C_ESTAT_M_SCL BIT(11)
127 #define I2C_ESTAT_M_SDA BIT(10)
128 #define I2C_ESTAT_HI_WATER BIT(9)
129 #define I2C_ESTAT_LO_WATER BIT(8)
130 #define I2C_ESTAT_PORT_BUSY BIT(7)
131 #define I2C_ESTAT_SELF_BUSY BIT(6)
132 #define I2C_ESTAT_VERSION GENMASK(4, 0)
134 /* port busy register */
135 #define I2C_PORT_BUSY_RESET BIT(31)
137 /* wait for command complete or data request */
138 #define I2C_CMD_SLEEP_MAX_US 500
139 #define I2C_CMD_SLEEP_MIN_US 50
141 /* wait after reset; choose time from legacy driver */
142 #define I2C_RESET_SLEEP_MAX_US 2000
143 #define I2C_RESET_SLEEP_MIN_US 1000
145 /* choose timeout length from legacy driver; it's well tested */
146 #define I2C_ABORT_TIMEOUT msecs_to_jiffies(100)
148 struct fsi_i2c_master
{
149 struct fsi_device
*fsi
;
151 struct list_head ports
;
155 struct fsi_i2c_port
{
156 struct list_head list
;
157 struct i2c_adapter adapter
;
158 struct fsi_i2c_master
*master
;
163 static int fsi_i2c_read_reg(struct fsi_device
*fsi
, unsigned int reg
,
169 rc
= fsi_device_read(fsi
, reg
, &data_be
, sizeof(data_be
));
173 *data
= be32_to_cpu(data_be
);
178 static int fsi_i2c_write_reg(struct fsi_device
*fsi
, unsigned int reg
,
181 __be32 data_be
= cpu_to_be32p(data
);
183 return fsi_device_write(fsi
, reg
, &data_be
, sizeof(data_be
));
186 static int fsi_i2c_dev_init(struct fsi_i2c_master
*i2c
)
189 u32 mode
= I2C_MODE_ENHANCED
, extended_status
, watermark
;
192 /* since we use polling, disable interrupts */
193 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_INT_MASK
, &interrupt
);
197 mode
|= FIELD_PREP(I2C_MODE_CLKDIV
, I2C_DEFAULT_CLK_DIV
);
198 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
202 rc
= fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_ESTAT
, &extended_status
);
206 i2c
->fifo_size
= FIELD_GET(I2C_ESTAT_FIFO_SZ
, extended_status
);
207 watermark
= FIELD_PREP(I2C_WATERMARK_HI
,
208 i2c
->fifo_size
- I2C_FIFO_HI_LVL
);
209 watermark
|= FIELD_PREP(I2C_WATERMARK_LO
, I2C_FIFO_LO_LVL
);
211 return fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_WATER_MARK
, &watermark
);
214 static int fsi_i2c_set_port(struct fsi_i2c_port
*port
)
217 struct fsi_device
*fsi
= port
->master
->fsi
;
220 rc
= fsi_i2c_read_reg(fsi
, I2C_FSI_MODE
, &mode
);
224 if (FIELD_GET(I2C_MODE_PORT
, mode
) == port
->port
)
227 mode
= (mode
& ~I2C_MODE_PORT
) | FIELD_PREP(I2C_MODE_PORT
, port
->port
);
228 rc
= fsi_i2c_write_reg(fsi
, I2C_FSI_MODE
, &mode
);
232 /* reset engine when port is changed */
233 return fsi_i2c_write_reg(fsi
, I2C_FSI_RESET_ERR
, &dummy
);
236 static int fsi_i2c_start(struct fsi_i2c_port
*port
, struct i2c_msg
*msg
,
239 struct fsi_i2c_master
*i2c
= port
->master
;
240 u32 cmd
= I2C_CMD_WITH_START
| I2C_CMD_WITH_ADDR
;
244 if (msg
->flags
& I2C_M_RD
)
247 if (stop
|| msg
->flags
& I2C_M_STOP
)
248 cmd
|= I2C_CMD_WITH_STOP
;
250 cmd
|= FIELD_PREP(I2C_CMD_ADDR
, msg
->addr
);
251 cmd
|= FIELD_PREP(I2C_CMD_LEN
, msg
->len
);
253 return fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_CMD
, &cmd
);
256 static int fsi_i2c_get_op_bytes(int op_bytes
)
258 /* fsi is limited to max 4 byte aligned ops */
261 else if (op_bytes
== 3)
266 static int fsi_i2c_write_fifo(struct fsi_i2c_port
*port
, struct i2c_msg
*msg
,
271 struct fsi_i2c_master
*i2c
= port
->master
;
272 int bytes_to_write
= i2c
->fifo_size
- fifo_count
;
273 int bytes_remaining
= msg
->len
- port
->xfrd
;
275 bytes_to_write
= min(bytes_to_write
, bytes_remaining
);
277 while (bytes_to_write
) {
278 write
= fsi_i2c_get_op_bytes(bytes_to_write
);
280 rc
= fsi_device_write(i2c
->fsi
, I2C_FSI_FIFO
,
281 &msg
->buf
[port
->xfrd
], write
);
286 bytes_to_write
-= write
;
292 static int fsi_i2c_read_fifo(struct fsi_i2c_port
*port
, struct i2c_msg
*msg
,
297 struct fsi_i2c_master
*i2c
= port
->master
;
299 int xfr_remaining
= msg
->len
- port
->xfrd
;
302 bytes_to_read
= min_t(int, fifo_count
, xfr_remaining
);
304 while (bytes_to_read
) {
305 read
= fsi_i2c_get_op_bytes(bytes_to_read
);
308 rc
= fsi_device_read(i2c
->fsi
, I2C_FSI_FIFO
,
309 &msg
->buf
[port
->xfrd
], read
);
314 xfr_remaining
-= read
;
316 /* no more buffer but data in fifo, need to clear it */
317 rc
= fsi_device_read(i2c
->fsi
, I2C_FSI_FIFO
, &dummy
,
323 bytes_to_read
-= read
;
329 static int fsi_i2c_get_scl(struct i2c_adapter
*adap
)
332 struct fsi_i2c_port
*port
= adap
->algo_data
;
333 struct fsi_i2c_master
*i2c
= port
->master
;
335 fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_STAT
, &stat
);
337 return !!(stat
& I2C_STAT_SCL_IN
);
340 static void fsi_i2c_set_scl(struct i2c_adapter
*adap
, int val
)
343 struct fsi_i2c_port
*port
= adap
->algo_data
;
344 struct fsi_i2c_master
*i2c
= port
->master
;
347 fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_SET_SCL
, &dummy
);
349 fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_RESET_SCL
, &dummy
);
352 static int fsi_i2c_get_sda(struct i2c_adapter
*adap
)
355 struct fsi_i2c_port
*port
= adap
->algo_data
;
356 struct fsi_i2c_master
*i2c
= port
->master
;
358 fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_STAT
, &stat
);
360 return !!(stat
& I2C_STAT_SDA_IN
);
363 static void fsi_i2c_set_sda(struct i2c_adapter
*adap
, int val
)
366 struct fsi_i2c_port
*port
= adap
->algo_data
;
367 struct fsi_i2c_master
*i2c
= port
->master
;
370 fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_SET_SDA
, &dummy
);
372 fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_RESET_SDA
, &dummy
);
375 static void fsi_i2c_prepare_recovery(struct i2c_adapter
*adap
)
379 struct fsi_i2c_port
*port
= adap
->algo_data
;
380 struct fsi_i2c_master
*i2c
= port
->master
;
382 rc
= fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
386 mode
|= I2C_MODE_DIAG
;
387 fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
390 static void fsi_i2c_unprepare_recovery(struct i2c_adapter
*adap
)
394 struct fsi_i2c_port
*port
= adap
->algo_data
;
395 struct fsi_i2c_master
*i2c
= port
->master
;
397 rc
= fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
401 mode
&= ~I2C_MODE_DIAG
;
402 fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
405 static int fsi_i2c_reset_bus(struct fsi_i2c_master
*i2c
,
406 struct fsi_i2c_port
*port
)
411 /* force bus reset, ignore errors */
412 i2c_recover_bus(&port
->adapter
);
415 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_RESET_ERR
, &dummy
);
419 /* wait for command complete */
420 usleep_range(I2C_RESET_SLEEP_MIN_US
, I2C_RESET_SLEEP_MAX_US
);
422 rc
= fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_STAT
, &stat
);
426 if (stat
& I2C_STAT_CMD_COMP
)
429 /* failed to get command complete; reset engine again */
430 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_RESET_I2C
, &dummy
);
434 /* re-init engine again */
435 return fsi_i2c_dev_init(i2c
);
438 static int fsi_i2c_reset_engine(struct fsi_i2c_master
*i2c
, u16 port
)
444 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_RESET_I2C
, &dummy
);
449 rc
= fsi_i2c_dev_init(i2c
);
453 rc
= fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
457 /* set port; default after reset is 0 */
459 mode
&= ~I2C_MODE_PORT
;
460 mode
|= FIELD_PREP(I2C_MODE_PORT
, port
);
461 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_MODE
, &mode
);
466 /* reset busy register; hw workaround */
467 dummy
= I2C_PORT_BUSY_RESET
;
468 rc
= fsi_i2c_write_reg(i2c
->fsi
, I2C_FSI_PORT_BUSY
, &dummy
);
475 static int fsi_i2c_abort(struct fsi_i2c_port
*port
, u32 status
)
479 u32 cmd
= I2C_CMD_WITH_STOP
;
481 struct fsi_i2c_master
*i2c
= port
->master
;
482 struct fsi_device
*fsi
= i2c
->fsi
;
484 rc
= fsi_i2c_reset_engine(i2c
, port
->port
);
488 rc
= fsi_i2c_read_reg(fsi
, I2C_FSI_STAT
, &stat
);
492 /* if sda is low, peform full bus reset */
493 if (!(stat
& I2C_STAT_SDA_IN
)) {
494 rc
= fsi_i2c_reset_bus(i2c
, port
);
499 /* skip final stop command for these errors */
500 if (status
& (I2C_STAT_PARITY
| I2C_STAT_LOST_ARB
| I2C_STAT_STOP_ERR
))
503 /* write stop command */
504 rc
= fsi_i2c_write_reg(fsi
, I2C_FSI_CMD
, &cmd
);
508 /* wait until we see command complete in the master */
512 rc
= fsi_i2c_read_reg(fsi
, I2C_FSI_STAT
, &status
);
516 if (status
& I2C_STAT_CMD_COMP
)
519 usleep_range(I2C_CMD_SLEEP_MIN_US
, I2C_CMD_SLEEP_MAX_US
);
520 } while (time_after(start
+ I2C_ABORT_TIMEOUT
, jiffies
));
525 static int fsi_i2c_handle_status(struct fsi_i2c_port
*port
,
526 struct i2c_msg
*msg
, u32 status
)
531 if (status
& I2C_STAT_ERR
) {
532 rc
= fsi_i2c_abort(port
, status
);
536 if (status
& I2C_STAT_INV_CMD
)
539 if (status
& (I2C_STAT_PARITY
| I2C_STAT_BE_OVERRUN
|
543 if (status
& I2C_STAT_NACK
)
546 if (status
& I2C_STAT_LOST_ARB
)
549 if (status
& I2C_STAT_STOP_ERR
)
555 if (status
& I2C_STAT_DAT_REQ
) {
556 fifo_count
= FIELD_GET(I2C_STAT_FIFO_COUNT
, status
);
558 if (msg
->flags
& I2C_M_RD
)
559 return fsi_i2c_read_fifo(port
, msg
, fifo_count
);
561 return fsi_i2c_write_fifo(port
, msg
, fifo_count
);
564 if (status
& I2C_STAT_CMD_COMP
) {
565 if (port
->xfrd
< msg
->len
)
574 static int fsi_i2c_wait(struct fsi_i2c_port
*port
, struct i2c_msg
*msg
,
575 unsigned long timeout
)
579 unsigned long start
= jiffies
;
582 rc
= fsi_i2c_read_reg(port
->master
->fsi
, I2C_FSI_STAT
,
587 if (status
& I2C_STAT_ANY_RESP
) {
588 rc
= fsi_i2c_handle_status(port
, msg
, status
);
592 /* cmd complete and all data xfrd */
596 /* need to xfr more data, but maybe don't need wait */
600 usleep_range(I2C_CMD_SLEEP_MIN_US
, I2C_CMD_SLEEP_MAX_US
);
601 } while (time_after(start
+ timeout
, jiffies
));
606 static int fsi_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
,
610 unsigned long start_time
;
611 struct fsi_i2c_port
*port
= adap
->algo_data
;
612 struct fsi_i2c_master
*master
= port
->master
;
615 mutex_lock(&master
->lock
);
617 rc
= fsi_i2c_set_port(port
);
621 for (i
= 0; i
< num
; i
++) {
623 start_time
= jiffies
;
625 rc
= fsi_i2c_start(port
, msg
, i
== num
- 1);
629 rc
= fsi_i2c_wait(port
, msg
,
630 adap
->timeout
- (jiffies
- start_time
));
636 mutex_unlock(&master
->lock
);
640 static u32
fsi_i2c_functionality(struct i2c_adapter
*adap
)
642 return I2C_FUNC_I2C
| I2C_FUNC_PROTOCOL_MANGLING
|
643 I2C_FUNC_SMBUS_EMUL
| I2C_FUNC_SMBUS_BLOCK_DATA
;
646 static struct i2c_bus_recovery_info fsi_i2c_bus_recovery_info
= {
647 .recover_bus
= i2c_generic_scl_recovery
,
648 .get_scl
= fsi_i2c_get_scl
,
649 .set_scl
= fsi_i2c_set_scl
,
650 .get_sda
= fsi_i2c_get_sda
,
651 .set_sda
= fsi_i2c_set_sda
,
652 .prepare_recovery
= fsi_i2c_prepare_recovery
,
653 .unprepare_recovery
= fsi_i2c_unprepare_recovery
,
656 static const struct i2c_algorithm fsi_i2c_algorithm
= {
657 .master_xfer
= fsi_i2c_xfer
,
658 .functionality
= fsi_i2c_functionality
,
661 static struct device_node
*fsi_i2c_find_port_of_node(struct device_node
*fsi
,
664 struct device_node
*np
;
668 for_each_child_of_node(fsi
, np
) {
669 rc
= of_property_read_u32(np
, "reg", &port_no
);
670 if (!rc
&& port_no
== port
)
677 static int fsi_i2c_probe(struct device
*dev
)
679 struct fsi_i2c_master
*i2c
;
680 struct fsi_i2c_port
*port
;
681 struct device_node
*np
;
682 u32 port_no
, ports
, stat
;
685 i2c
= devm_kzalloc(dev
, sizeof(*i2c
), GFP_KERNEL
);
689 mutex_init(&i2c
->lock
);
690 i2c
->fsi
= to_fsi_dev(dev
);
691 INIT_LIST_HEAD(&i2c
->ports
);
693 rc
= fsi_i2c_dev_init(i2c
);
697 rc
= fsi_i2c_read_reg(i2c
->fsi
, I2C_FSI_STAT
, &stat
);
701 ports
= FIELD_GET(I2C_STAT_MAX_PORT
, stat
) + 1;
702 dev_dbg(dev
, "I2C master has %d ports\n", ports
);
704 for (port_no
= 0; port_no
< ports
; port_no
++) {
705 np
= fsi_i2c_find_port_of_node(dev
->of_node
, port_no
);
706 if (!of_device_is_available(np
))
709 port
= kzalloc(sizeof(*port
), GFP_KERNEL
);
716 port
->port
= port_no
;
718 port
->adapter
.owner
= THIS_MODULE
;
719 port
->adapter
.dev
.of_node
= np
;
720 port
->adapter
.dev
.parent
= dev
;
721 port
->adapter
.algo
= &fsi_i2c_algorithm
;
722 port
->adapter
.bus_recovery_info
= &fsi_i2c_bus_recovery_info
;
723 port
->adapter
.algo_data
= port
;
725 snprintf(port
->adapter
.name
, sizeof(port
->adapter
.name
),
726 "i2c_bus-%u", port_no
);
728 rc
= i2c_add_adapter(&port
->adapter
);
730 dev_err(dev
, "Failed to register adapter: %d\n", rc
);
735 list_add(&port
->list
, &i2c
->ports
);
738 dev_set_drvdata(dev
, i2c
);
743 static int fsi_i2c_remove(struct device
*dev
)
745 struct fsi_i2c_master
*i2c
= dev_get_drvdata(dev
);
746 struct fsi_i2c_port
*port
, *tmp
;
748 list_for_each_entry_safe(port
, tmp
, &i2c
->ports
, list
) {
749 list_del(&port
->list
);
750 i2c_del_adapter(&port
->adapter
);
757 static const struct fsi_device_id fsi_i2c_ids
[] = {
758 { FSI_ENGID_I2C
, FSI_VERSION_ANY
},
762 static struct fsi_driver fsi_i2c_driver
= {
763 .id_table
= fsi_i2c_ids
,
766 .bus
= &fsi_bus_type
,
767 .probe
= fsi_i2c_probe
,
768 .remove
= fsi_i2c_remove
,
772 module_fsi_driver(fsi_i2c_driver
);
774 MODULE_AUTHOR("Eddie James <eajames@us.ibm.com>");
775 MODULE_DESCRIPTION("FSI attached I2C master");
776 MODULE_LICENSE("GPL");