1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014 Linaro Ltd.
4 * Copyright (c) 2014 Hisilicon Limited.
6 * Now only support 7 bit address.
10 #include <linux/delay.h>
11 #include <linux/i2c.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
20 #define HIX5I2C_CTRL 0x00
21 #define HIX5I2C_COM 0x04
22 #define HIX5I2C_ICR 0x08
23 #define HIX5I2C_SR 0x0c
24 #define HIX5I2C_SCL_H 0x10
25 #define HIX5I2C_SCL_L 0x14
26 #define HIX5I2C_TXR 0x18
27 #define HIX5I2C_RXR 0x1c
30 #define I2C_ENABLE BIT(8)
31 #define I2C_UNMASK_TOTAL BIT(7)
32 #define I2C_UNMASK_START BIT(6)
33 #define I2C_UNMASK_END BIT(5)
34 #define I2C_UNMASK_SEND BIT(4)
35 #define I2C_UNMASK_RECEIVE BIT(3)
36 #define I2C_UNMASK_ACK BIT(2)
37 #define I2C_UNMASK_ARBITRATE BIT(1)
38 #define I2C_UNMASK_OVER BIT(0)
39 #define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
42 #define I2C_NO_ACK BIT(4)
43 #define I2C_START BIT(3)
44 #define I2C_READ BIT(2)
45 #define I2C_WRITE BIT(1)
46 #define I2C_STOP BIT(0)
49 #define I2C_CLEAR_START BIT(6)
50 #define I2C_CLEAR_END BIT(5)
51 #define I2C_CLEAR_SEND BIT(4)
52 #define I2C_CLEAR_RECEIVE BIT(3)
53 #define I2C_CLEAR_ACK BIT(2)
54 #define I2C_CLEAR_ARBITRATE BIT(1)
55 #define I2C_CLEAR_OVER BIT(0)
56 #define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
57 I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
58 I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
62 #define I2C_BUSY BIT(7)
63 #define I2C_START_INTR BIT(6)
64 #define I2C_END_INTR BIT(5)
65 #define I2C_SEND_INTR BIT(4)
66 #define I2C_RECEIVE_INTR BIT(3)
67 #define I2C_ACK_INTR BIT(2)
68 #define I2C_ARBITRATE_INTR BIT(1)
69 #define I2C_OVER_INTR BIT(0)
71 enum hix5hd2_i2c_state
{
72 HIX5I2C_STAT_RW_ERR
= -1,
75 HIX5I2C_STAT_SND_STOP
,
76 HIX5I2C_STAT_RW_SUCCESS
,
79 struct hix5hd2_i2c_priv
{
80 struct i2c_adapter adap
;
82 struct completion msg_complete
;
89 spinlock_t lock
; /* IRQ synchronization */
92 enum hix5hd2_i2c_state state
;
95 static u32
hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv
*priv
)
97 u32 val
= readl_relaxed(priv
->regs
+ HIX5I2C_SR
);
99 writel_relaxed(val
, priv
->regs
+ HIX5I2C_ICR
);
104 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv
*priv
)
106 writel_relaxed(I2C_CLEAR_ALL
, priv
->regs
+ HIX5I2C_ICR
);
109 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv
*priv
)
111 writel_relaxed(0, priv
->regs
+ HIX5I2C_CTRL
);
114 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv
*priv
)
116 writel_relaxed(I2C_ENABLE
| I2C_UNMASK_TOTAL
| I2C_UNMASK_ALL
,
117 priv
->regs
+ HIX5I2C_CTRL
);
120 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv
*priv
)
125 /* close all i2c interrupt */
126 val
= readl_relaxed(priv
->regs
+ HIX5I2C_CTRL
);
127 writel_relaxed(val
& (~I2C_UNMASK_TOTAL
), priv
->regs
+ HIX5I2C_CTRL
);
130 sysclock
= clk_get_rate(priv
->clk
);
131 scl
= (sysclock
/ (rate
* 2)) / 2 - 1;
132 writel_relaxed(scl
, priv
->regs
+ HIX5I2C_SCL_H
);
133 writel_relaxed(scl
, priv
->regs
+ HIX5I2C_SCL_L
);
135 /* restore original interrupt*/
136 writel_relaxed(val
, priv
->regs
+ HIX5I2C_CTRL
);
138 dev_dbg(priv
->dev
, "%s: sysclock=%d, rate=%d, scl=%d\n",
139 __func__
, sysclock
, rate
, scl
);
142 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv
*priv
)
144 hix5hd2_i2c_disable_irq(priv
);
145 hix5hd2_i2c_drv_setrate(priv
);
146 hix5hd2_i2c_clr_all_irq(priv
);
147 hix5hd2_i2c_enable_irq(priv
);
150 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv
*priv
)
152 clk_disable_unprepare(priv
->clk
);
154 clk_prepare_enable(priv
->clk
);
155 hix5hd2_i2c_init(priv
);
158 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv
*priv
)
160 unsigned long stop_time
;
163 /* wait for 100 milli seconds for the bus to be idle */
164 stop_time
= jiffies
+ msecs_to_jiffies(100);
166 int_status
= hix5hd2_i2c_clr_pend_irq(priv
);
167 if (!(int_status
& I2C_BUSY
))
170 usleep_range(50, 200);
171 } while (time_before(jiffies
, stop_time
));
176 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv
*priv
)
178 if (priv
->state
== HIX5I2C_STAT_SND_STOP
)
179 dev_dbg(priv
->dev
, "%s: rw and send stop over\n", __func__
);
181 dev_dbg(priv
->dev
, "%s: have not data to send\n", __func__
);
183 priv
->state
= HIX5I2C_STAT_RW_SUCCESS
;
187 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv
*priv
)
190 priv
->state
= HIX5I2C_STAT_SND_STOP
;
191 writel_relaxed(I2C_STOP
, priv
->regs
+ HIX5I2C_COM
);
193 hix5hd2_rw_over(priv
);
197 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv
*priv
)
199 if (priv
->msg_len
== 1) {
200 /* the last byte don't need send ACK */
201 writel_relaxed(I2C_READ
| I2C_NO_ACK
, priv
->regs
+ HIX5I2C_COM
);
202 } else if (priv
->msg_len
> 1) {
203 /* if i2c master receive data will send ACK */
204 writel_relaxed(I2C_READ
, priv
->regs
+ HIX5I2C_COM
);
206 hix5hd2_rw_handle_stop(priv
);
210 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv
*priv
)
214 if (priv
->msg_len
> 0) {
215 data
= priv
->msg
->buf
[priv
->msg_idx
++];
216 writel_relaxed(data
, priv
->regs
+ HIX5I2C_TXR
);
217 writel_relaxed(I2C_WRITE
, priv
->regs
+ HIX5I2C_COM
);
219 hix5hd2_rw_handle_stop(priv
);
223 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv
*priv
)
227 if (priv
->state
== HIX5I2C_STAT_INIT
) {
228 priv
->state
= HIX5I2C_STAT_RW
;
229 } else if (priv
->state
== HIX5I2C_STAT_RW
) {
230 if (priv
->msg
->flags
& I2C_M_RD
) {
231 data
= readl_relaxed(priv
->regs
+ HIX5I2C_RXR
);
232 priv
->msg
->buf
[priv
->msg_idx
++] = data
;
236 dev_dbg(priv
->dev
, "%s: error: priv->state = %d, msg_len = %d\n",
237 __func__
, priv
->state
, priv
->msg_len
);
243 static irqreturn_t
hix5hd2_i2c_irq(int irqno
, void *dev_id
)
245 struct hix5hd2_i2c_priv
*priv
= dev_id
;
249 spin_lock(&priv
->lock
);
251 int_status
= hix5hd2_i2c_clr_pend_irq(priv
);
254 if (int_status
& I2C_ARBITRATE_INTR
) {
256 dev_dbg(priv
->dev
, "ARB bus loss\n");
258 priv
->state
= HIX5I2C_STAT_RW_ERR
;
260 } else if (int_status
& I2C_ACK_INTR
) {
262 dev_dbg(priv
->dev
, "No ACK from device\n");
264 priv
->state
= HIX5I2C_STAT_RW_ERR
;
268 if (int_status
& I2C_OVER_INTR
) {
269 if (priv
->msg_len
> 0) {
270 ret
= hix5hd2_rw_preprocess(priv
);
273 priv
->state
= HIX5I2C_STAT_RW_ERR
;
276 if (priv
->msg
->flags
& I2C_M_RD
)
277 hix5hd2_read_handle(priv
);
279 hix5hd2_write_handle(priv
);
281 hix5hd2_rw_over(priv
);
286 if ((priv
->state
== HIX5I2C_STAT_RW_SUCCESS
&&
287 priv
->msg
->len
== priv
->msg_idx
) ||
288 (priv
->state
== HIX5I2C_STAT_RW_ERR
)) {
289 hix5hd2_i2c_disable_irq(priv
);
290 hix5hd2_i2c_clr_pend_irq(priv
);
291 complete(&priv
->msg_complete
);
294 spin_unlock(&priv
->lock
);
299 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv
*priv
, int stop
)
303 spin_lock_irqsave(&priv
->lock
, flags
);
304 hix5hd2_i2c_clr_all_irq(priv
);
305 hix5hd2_i2c_enable_irq(priv
);
307 writel_relaxed(i2c_8bit_addr_from_msg(priv
->msg
),
308 priv
->regs
+ HIX5I2C_TXR
);
310 writel_relaxed(I2C_WRITE
| I2C_START
, priv
->regs
+ HIX5I2C_COM
);
311 spin_unlock_irqrestore(&priv
->lock
, flags
);
314 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv
*priv
,
315 struct i2c_msg
*msgs
, int stop
)
317 unsigned long timeout
;
322 priv
->msg_len
= priv
->msg
->len
;
325 priv
->state
= HIX5I2C_STAT_INIT
;
327 reinit_completion(&priv
->msg_complete
);
328 hix5hd2_i2c_message_start(priv
, stop
);
330 timeout
= wait_for_completion_timeout(&priv
->msg_complete
,
333 priv
->state
= HIX5I2C_STAT_RW_ERR
;
334 priv
->err
= -ETIMEDOUT
;
335 dev_warn(priv
->dev
, "%s timeout=%d\n",
336 msgs
->flags
& I2C_M_RD
? "rx" : "tx",
342 * If this is the last message to be transfered (stop == 1)
343 * Then check if the bus can be brought back to idle.
345 if (priv
->state
== HIX5I2C_STAT_RW_SUCCESS
&& stop
)
346 ret
= hix5hd2_i2c_wait_bus_idle(priv
);
349 hix5hd2_i2c_reset(priv
);
354 static int hix5hd2_i2c_xfer(struct i2c_adapter
*adap
,
355 struct i2c_msg
*msgs
, int num
)
357 struct hix5hd2_i2c_priv
*priv
= i2c_get_adapdata(adap
);
360 pm_runtime_get_sync(priv
->dev
);
362 for (i
= 0; i
< num
; i
++, msgs
++) {
363 stop
= (i
== num
- 1);
364 ret
= hix5hd2_i2c_xfer_msg(priv
, msgs
, stop
);
372 pm_runtime_mark_last_busy(priv
->dev
);
373 pm_runtime_put_autosuspend(priv
->dev
);
377 static u32
hix5hd2_i2c_func(struct i2c_adapter
*adap
)
379 return I2C_FUNC_I2C
| (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
);
382 static const struct i2c_algorithm hix5hd2_i2c_algorithm
= {
383 .master_xfer
= hix5hd2_i2c_xfer
,
384 .functionality
= hix5hd2_i2c_func
,
387 static int hix5hd2_i2c_probe(struct platform_device
*pdev
)
389 struct device_node
*np
= pdev
->dev
.of_node
;
390 struct hix5hd2_i2c_priv
*priv
;
394 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
398 if (of_property_read_u32(np
, "clock-frequency", &freq
)) {
399 /* use 100k as default value */
400 priv
->freq
= I2C_MAX_STANDARD_MODE_FREQ
;
402 if (freq
> I2C_MAX_FAST_MODE_FREQ
) {
403 priv
->freq
= I2C_MAX_FAST_MODE_FREQ
;
404 dev_warn(priv
->dev
, "use max freq %d instead\n",
405 I2C_MAX_FAST_MODE_FREQ
);
411 priv
->regs
= devm_platform_ioremap_resource(pdev
, 0);
412 if (IS_ERR(priv
->regs
))
413 return PTR_ERR(priv
->regs
);
415 irq
= platform_get_irq(pdev
, 0);
417 dev_err(&pdev
->dev
, "cannot find HS-I2C IRQ\n");
421 priv
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
422 if (IS_ERR(priv
->clk
)) {
423 dev_err(&pdev
->dev
, "cannot get clock\n");
424 return PTR_ERR(priv
->clk
);
426 clk_prepare_enable(priv
->clk
);
428 strlcpy(priv
->adap
.name
, "hix5hd2-i2c", sizeof(priv
->adap
.name
));
429 priv
->dev
= &pdev
->dev
;
430 priv
->adap
.owner
= THIS_MODULE
;
431 priv
->adap
.algo
= &hix5hd2_i2c_algorithm
;
432 priv
->adap
.retries
= 3;
433 priv
->adap
.dev
.of_node
= np
;
434 priv
->adap
.algo_data
= priv
;
435 priv
->adap
.dev
.parent
= &pdev
->dev
;
436 i2c_set_adapdata(&priv
->adap
, priv
);
437 platform_set_drvdata(pdev
, priv
);
438 spin_lock_init(&priv
->lock
);
439 init_completion(&priv
->msg_complete
);
441 hix5hd2_i2c_init(priv
);
443 ret
= devm_request_irq(&pdev
->dev
, irq
, hix5hd2_i2c_irq
,
444 IRQF_NO_SUSPEND
, dev_name(&pdev
->dev
), priv
);
446 dev_err(&pdev
->dev
, "cannot request HS-I2C IRQ %d\n", irq
);
450 pm_runtime_set_autosuspend_delay(priv
->dev
, MSEC_PER_SEC
);
451 pm_runtime_use_autosuspend(priv
->dev
);
452 pm_runtime_set_active(priv
->dev
);
453 pm_runtime_enable(priv
->dev
);
455 ret
= i2c_add_adapter(&priv
->adap
);
462 pm_runtime_disable(priv
->dev
);
463 pm_runtime_set_suspended(priv
->dev
);
465 clk_disable_unprepare(priv
->clk
);
469 static int hix5hd2_i2c_remove(struct platform_device
*pdev
)
471 struct hix5hd2_i2c_priv
*priv
= platform_get_drvdata(pdev
);
473 i2c_del_adapter(&priv
->adap
);
474 pm_runtime_disable(priv
->dev
);
475 pm_runtime_set_suspended(priv
->dev
);
476 clk_disable_unprepare(priv
->clk
);
482 static int hix5hd2_i2c_runtime_suspend(struct device
*dev
)
484 struct hix5hd2_i2c_priv
*priv
= dev_get_drvdata(dev
);
486 clk_disable_unprepare(priv
->clk
);
491 static int hix5hd2_i2c_runtime_resume(struct device
*dev
)
493 struct hix5hd2_i2c_priv
*priv
= dev_get_drvdata(dev
);
495 clk_prepare_enable(priv
->clk
);
496 hix5hd2_i2c_init(priv
);
502 static const struct dev_pm_ops hix5hd2_i2c_pm_ops
= {
503 SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend
,
504 hix5hd2_i2c_runtime_resume
,
508 static const struct of_device_id hix5hd2_i2c_match
[] = {
509 { .compatible
= "hisilicon,hix5hd2-i2c" },
512 MODULE_DEVICE_TABLE(of
, hix5hd2_i2c_match
);
514 static struct platform_driver hix5hd2_i2c_driver
= {
515 .probe
= hix5hd2_i2c_probe
,
516 .remove
= hix5hd2_i2c_remove
,
518 .name
= "hix5hd2-i2c",
519 .pm
= &hix5hd2_i2c_pm_ops
,
520 .of_match_table
= hix5hd2_i2c_match
,
524 module_platform_driver(hix5hd2_i2c_driver
);
526 MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
527 MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
528 MODULE_LICENSE("GPL");
529 MODULE_ALIAS("platform:hix5hd2-i2c");