1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
4 Philip Edelbrock <phil@netroedge.com>
11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
17 Note: we assume there can only be one device, with one or more
19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
20 For devices supporting multiple ports the i2c_adapter should provide
21 an i2c_algorithm to access them.
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/stddef.h>
30 #include <linux/ioport.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 #include <linux/dmi.h>
34 #include <linux/acpi.h>
38 /* PIIX4 SMBus address offsets */
39 #define SMBHSTSTS (0 + piix4_smba)
40 #define SMBHSLVSTS (1 + piix4_smba)
41 #define SMBHSTCNT (2 + piix4_smba)
42 #define SMBHSTCMD (3 + piix4_smba)
43 #define SMBHSTADD (4 + piix4_smba)
44 #define SMBHSTDAT0 (5 + piix4_smba)
45 #define SMBHSTDAT1 (6 + piix4_smba)
46 #define SMBBLKDAT (7 + piix4_smba)
47 #define SMBSLVCNT (8 + piix4_smba)
48 #define SMBSHDWCMD (9 + piix4_smba)
49 #define SMBSLVEVT (0xA + piix4_smba)
50 #define SMBSLVDAT (0xC + piix4_smba)
52 /* count for request_region */
55 /* PCI Address Constants */
57 #define SMBHSTCFG 0x0D2
59 #define SMBSHDW1 0x0D4
60 #define SMBSHDW2 0x0D5
64 #define MAX_TIMEOUT 500
68 #define PIIX4_QUICK 0x00
69 #define PIIX4_BYTE 0x04
70 #define PIIX4_BYTE_DATA 0x08
71 #define PIIX4_WORD_DATA 0x0C
72 #define PIIX4_BLOCK_DATA 0x14
74 /* Multi-port constants */
75 #define PIIX4_MAX_ADAPTERS 4
76 #define HUDSON2_MAIN_PORTS 2 /* HUDSON2, KERNCZ reserves ports 3, 4 */
79 #define SB800_PIIX4_SMB_IDX 0xcd6
81 #define KERNCZ_IMC_IDX 0x3e
82 #define KERNCZ_IMC_DATA 0x3f
85 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
86 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
87 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
89 #define SB800_PIIX4_PORT_IDX 0x2c
90 #define SB800_PIIX4_PORT_IDX_ALT 0x2e
91 #define SB800_PIIX4_PORT_IDX_SEL 0x2f
92 #define SB800_PIIX4_PORT_IDX_MASK 0x06
93 #define SB800_PIIX4_PORT_IDX_SHIFT 1
95 /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
96 #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
97 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
98 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
100 /* insmod parameters */
102 /* If force is set to anything different from 0, we forcibly enable the
105 module_param (force
, int, 0);
106 MODULE_PARM_DESC(force
, "Forcibly enable the PIIX4. DANGEROUS!");
108 /* If force_addr is set to anything different from 0, we forcibly enable
109 the PIIX4 at the given address. VERY DANGEROUS! */
110 static int force_addr
;
111 module_param_hw(force_addr
, int, ioport
, 0);
112 MODULE_PARM_DESC(force_addr
,
113 "Forcibly enable the PIIX4 at the given address. "
114 "EXTREMELY DANGEROUS!");
116 static int srvrworks_csb5_delay
;
117 static struct pci_driver piix4_driver
;
119 static const struct dmi_system_id piix4_dmi_blacklist
[] = {
121 .ident
= "Sapphire AM2RD790",
123 DMI_MATCH(DMI_BOARD_VENDOR
, "SAPPHIRE Inc."),
124 DMI_MATCH(DMI_BOARD_NAME
, "PC-AM2RD790"),
128 .ident
= "DFI Lanparty UT 790FX",
130 DMI_MATCH(DMI_BOARD_VENDOR
, "DFI Inc."),
131 DMI_MATCH(DMI_BOARD_NAME
, "LP UT 790FX"),
137 /* The IBM entry is in a separate table because we only check it
138 on Intel-based systems */
139 static const struct dmi_system_id piix4_dmi_ibm
[] = {
142 .matches
= { DMI_MATCH(DMI_SYS_VENDOR
, "IBM"), },
150 static u8 piix4_port_sel_sb800
;
151 static u8 piix4_port_mask_sb800
;
152 static u8 piix4_port_shift_sb800
;
153 static const char *piix4_main_port_names_sb800
[PIIX4_MAX_ADAPTERS
] = {
154 " port 0", " port 2", " port 3", " port 4"
156 static const char *piix4_aux_port_name_sb800
= " port 1";
158 struct i2c_piix4_adapdata
{
164 u8 port
; /* Port number, shifted */
167 static int piix4_setup(struct pci_dev
*PIIX4_dev
,
168 const struct pci_device_id
*id
)
171 unsigned short piix4_smba
;
173 if ((PIIX4_dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
) &&
174 (PIIX4_dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5
))
175 srvrworks_csb5_delay
= 1;
177 /* On some motherboards, it was reported that accessing the SMBus
178 caused severe hardware problems */
179 if (dmi_check_system(piix4_dmi_blacklist
)) {
180 dev_err(&PIIX4_dev
->dev
,
181 "Accessing the SMBus on this system is unsafe!\n");
185 /* Don't access SMBus on IBM systems which get corrupted eeproms */
186 if (dmi_check_system(piix4_dmi_ibm
) &&
187 PIIX4_dev
->vendor
== PCI_VENDOR_ID_INTEL
) {
188 dev_err(&PIIX4_dev
->dev
, "IBM system detected; this module "
189 "may corrupt your serial eeprom! Refusing to load "
194 /* Determine the address of the SMBus areas */
196 piix4_smba
= force_addr
& 0xfff0;
199 pci_read_config_word(PIIX4_dev
, SMBBA
, &piix4_smba
);
200 piix4_smba
&= 0xfff0;
201 if(piix4_smba
== 0) {
202 dev_err(&PIIX4_dev
->dev
, "SMBus base address "
203 "uninitialized - upgrade BIOS or use "
204 "force_addr=0xaddr\n");
209 if (acpi_check_region(piix4_smba
, SMBIOSIZE
, piix4_driver
.name
))
212 if (!request_region(piix4_smba
, SMBIOSIZE
, piix4_driver
.name
)) {
213 dev_err(&PIIX4_dev
->dev
, "SMBus region 0x%x already in use!\n",
218 pci_read_config_byte(PIIX4_dev
, SMBHSTCFG
, &temp
);
220 /* If force_addr is set, we program the new address here. Just to make
221 sure, we disable the PIIX4 first. */
223 pci_write_config_byte(PIIX4_dev
, SMBHSTCFG
, temp
& 0xfe);
224 pci_write_config_word(PIIX4_dev
, SMBBA
, piix4_smba
);
225 pci_write_config_byte(PIIX4_dev
, SMBHSTCFG
, temp
| 0x01);
226 dev_info(&PIIX4_dev
->dev
, "WARNING: SMBus interface set to "
227 "new address %04x!\n", piix4_smba
);
228 } else if ((temp
& 1) == 0) {
230 /* This should never need to be done, but has been
231 * noted that many Dell machines have the SMBus
232 * interface on the PIIX4 disabled!? NOTE: This assumes
233 * I/O space and other allocations WERE done by the
234 * Bios! Don't complain if your hardware does weird
235 * things after enabling this. :') Check for Bios
236 * updates before resorting to this.
238 pci_write_config_byte(PIIX4_dev
, SMBHSTCFG
,
240 dev_notice(&PIIX4_dev
->dev
,
241 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
243 dev_err(&PIIX4_dev
->dev
,
244 "SMBus Host Controller not enabled!\n");
245 release_region(piix4_smba
, SMBIOSIZE
);
250 if (((temp
& 0x0E) == 8) || ((temp
& 0x0E) == 2))
251 dev_dbg(&PIIX4_dev
->dev
, "Using IRQ for SMBus\n");
252 else if ((temp
& 0x0E) == 0)
253 dev_dbg(&PIIX4_dev
->dev
, "Using SMI# for SMBus\n");
255 dev_err(&PIIX4_dev
->dev
, "Illegal Interrupt configuration "
256 "(or code out of date)!\n");
258 pci_read_config_byte(PIIX4_dev
, SMBREV
, &temp
);
259 dev_info(&PIIX4_dev
->dev
,
260 "SMBus Host Controller at 0x%x, revision %d\n",
266 static int piix4_setup_sb800(struct pci_dev
*PIIX4_dev
,
267 const struct pci_device_id
*id
, u8 aux
)
269 unsigned short piix4_smba
;
270 u8 smba_en_lo
, smba_en_hi
, smb_en
, smb_en_status
, port_sel
;
271 u8 i2ccfg
, i2ccfg_offset
= 0x10;
273 /* SB800 and later SMBus does not support forcing address */
274 if (force
|| force_addr
) {
275 dev_err(&PIIX4_dev
->dev
, "SMBus does not support "
276 "forcing address!\n");
280 /* Determine the address of the SMBus areas */
281 if ((PIIX4_dev
->vendor
== PCI_VENDOR_ID_AMD
&&
282 PIIX4_dev
->device
== PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
&&
283 PIIX4_dev
->revision
>= 0x41) ||
284 (PIIX4_dev
->vendor
== PCI_VENDOR_ID_AMD
&&
285 PIIX4_dev
->device
== PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
&&
286 PIIX4_dev
->revision
>= 0x49) ||
287 (PIIX4_dev
->vendor
== PCI_VENDOR_ID_HYGON
&&
288 PIIX4_dev
->device
== PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
))
291 smb_en
= (aux
) ? 0x28 : 0x2c;
293 if (!request_muxed_region(SB800_PIIX4_SMB_IDX
, 2, "sb800_piix4_smb")) {
294 dev_err(&PIIX4_dev
->dev
,
295 "SMB base address index region 0x%x already in use.\n",
296 SB800_PIIX4_SMB_IDX
);
300 outb_p(smb_en
, SB800_PIIX4_SMB_IDX
);
301 smba_en_lo
= inb_p(SB800_PIIX4_SMB_IDX
+ 1);
302 outb_p(smb_en
+ 1, SB800_PIIX4_SMB_IDX
);
303 smba_en_hi
= inb_p(SB800_PIIX4_SMB_IDX
+ 1);
305 release_region(SB800_PIIX4_SMB_IDX
, 2);
308 smb_en_status
= smba_en_lo
& 0x10;
309 piix4_smba
= smba_en_hi
<< 8;
313 smb_en_status
= smba_en_lo
& 0x01;
314 piix4_smba
= ((smba_en_hi
<< 8) | smba_en_lo
) & 0xffe0;
317 if (!smb_en_status
) {
318 dev_err(&PIIX4_dev
->dev
,
319 "SMBus Host Controller not enabled!\n");
323 if (acpi_check_region(piix4_smba
, SMBIOSIZE
, piix4_driver
.name
))
326 if (!request_region(piix4_smba
, SMBIOSIZE
, piix4_driver
.name
)) {
327 dev_err(&PIIX4_dev
->dev
, "SMBus region 0x%x already in use!\n",
332 /* Aux SMBus does not support IRQ information */
334 dev_info(&PIIX4_dev
->dev
,
335 "Auxiliary SMBus Host Controller at 0x%x\n",
340 /* Request the SMBus I2C bus config region */
341 if (!request_region(piix4_smba
+ i2ccfg_offset
, 1, "i2ccfg")) {
342 dev_err(&PIIX4_dev
->dev
, "SMBus I2C bus config region "
343 "0x%x already in use!\n", piix4_smba
+ i2ccfg_offset
);
344 release_region(piix4_smba
, SMBIOSIZE
);
347 i2ccfg
= inb_p(piix4_smba
+ i2ccfg_offset
);
348 release_region(piix4_smba
+ i2ccfg_offset
, 1);
351 dev_dbg(&PIIX4_dev
->dev
, "Using IRQ for SMBus\n");
353 dev_dbg(&PIIX4_dev
->dev
, "Using SMI# for SMBus\n");
355 dev_info(&PIIX4_dev
->dev
,
356 "SMBus Host Controller at 0x%x, revision %d\n",
357 piix4_smba
, i2ccfg
>> 4);
359 /* Find which register is used for port selection */
360 if (PIIX4_dev
->vendor
== PCI_VENDOR_ID_AMD
||
361 PIIX4_dev
->vendor
== PCI_VENDOR_ID_HYGON
) {
362 if (PIIX4_dev
->device
== PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
||
363 (PIIX4_dev
->device
== PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
&&
364 PIIX4_dev
->revision
>= 0x1F)) {
365 piix4_port_sel_sb800
= SB800_PIIX4_PORT_IDX_KERNCZ
;
366 piix4_port_mask_sb800
= SB800_PIIX4_PORT_IDX_MASK_KERNCZ
;
367 piix4_port_shift_sb800
= SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ
;
369 piix4_port_sel_sb800
= SB800_PIIX4_PORT_IDX_ALT
;
370 piix4_port_mask_sb800
= SB800_PIIX4_PORT_IDX_MASK
;
371 piix4_port_shift_sb800
= SB800_PIIX4_PORT_IDX_SHIFT
;
374 if (!request_muxed_region(SB800_PIIX4_SMB_IDX
, 2,
375 "sb800_piix4_smb")) {
376 release_region(piix4_smba
, SMBIOSIZE
);
380 outb_p(SB800_PIIX4_PORT_IDX_SEL
, SB800_PIIX4_SMB_IDX
);
381 port_sel
= inb_p(SB800_PIIX4_SMB_IDX
+ 1);
382 piix4_port_sel_sb800
= (port_sel
& 0x01) ?
383 SB800_PIIX4_PORT_IDX_ALT
:
384 SB800_PIIX4_PORT_IDX
;
385 piix4_port_mask_sb800
= SB800_PIIX4_PORT_IDX_MASK
;
386 piix4_port_shift_sb800
= SB800_PIIX4_PORT_IDX_SHIFT
;
387 release_region(SB800_PIIX4_SMB_IDX
, 2);
390 dev_info(&PIIX4_dev
->dev
,
391 "Using register 0x%02x for SMBus port selection\n",
392 (unsigned int)piix4_port_sel_sb800
);
397 static int piix4_setup_aux(struct pci_dev
*PIIX4_dev
,
398 const struct pci_device_id
*id
,
399 unsigned short base_reg_addr
)
401 /* Set up auxiliary SMBus controllers found on some
402 * AMD chipsets e.g. SP5100 (SB700 derivative) */
404 unsigned short piix4_smba
;
406 /* Read address of auxiliary SMBus controller */
407 pci_read_config_word(PIIX4_dev
, base_reg_addr
, &piix4_smba
);
408 if ((piix4_smba
& 1) == 0) {
409 dev_dbg(&PIIX4_dev
->dev
,
410 "Auxiliary SMBus controller not enabled\n");
414 piix4_smba
&= 0xfff0;
415 if (piix4_smba
== 0) {
416 dev_dbg(&PIIX4_dev
->dev
,
417 "Auxiliary SMBus base address uninitialized\n");
421 if (acpi_check_region(piix4_smba
, SMBIOSIZE
, piix4_driver
.name
))
424 if (!request_region(piix4_smba
, SMBIOSIZE
, piix4_driver
.name
)) {
425 dev_err(&PIIX4_dev
->dev
, "Auxiliary SMBus region 0x%x "
426 "already in use!\n", piix4_smba
);
430 dev_info(&PIIX4_dev
->dev
,
431 "Auxiliary SMBus Host Controller at 0x%x\n",
437 static int piix4_transaction(struct i2c_adapter
*piix4_adapter
)
439 struct i2c_piix4_adapdata
*adapdata
= i2c_get_adapdata(piix4_adapter
);
440 unsigned short piix4_smba
= adapdata
->smba
;
445 dev_dbg(&piix4_adapter
->dev
, "Transaction (pre): CNT=%02x, CMD=%02x, "
446 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT
),
447 inb_p(SMBHSTCMD
), inb_p(SMBHSTADD
), inb_p(SMBHSTDAT0
),
450 /* Make sure the SMBus host is ready to start transmitting */
451 if ((temp
= inb_p(SMBHSTSTS
)) != 0x00) {
452 dev_dbg(&piix4_adapter
->dev
, "SMBus busy (%02x). "
453 "Resetting...\n", temp
);
454 outb_p(temp
, SMBHSTSTS
);
455 if ((temp
= inb_p(SMBHSTSTS
)) != 0x00) {
456 dev_err(&piix4_adapter
->dev
, "Failed! (%02x)\n", temp
);
459 dev_dbg(&piix4_adapter
->dev
, "Successful!\n");
463 /* start the transaction by setting bit 6 */
464 outb_p(inb(SMBHSTCNT
) | 0x040, SMBHSTCNT
);
466 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
467 if (srvrworks_csb5_delay
) /* Extra delay for SERVERWORKS_CSB5 */
468 usleep_range(2000, 2100);
470 usleep_range(250, 500);
472 while ((++timeout
< MAX_TIMEOUT
) &&
473 ((temp
= inb_p(SMBHSTSTS
)) & 0x01))
474 usleep_range(250, 500);
476 /* If the SMBus is still busy, we give up */
477 if (timeout
== MAX_TIMEOUT
) {
478 dev_err(&piix4_adapter
->dev
, "SMBus Timeout!\n");
484 dev_err(&piix4_adapter
->dev
, "Error: Failed bus transaction\n");
489 dev_dbg(&piix4_adapter
->dev
, "Bus collision! SMBus may be "
490 "locked until next hard reset. (sorry!)\n");
491 /* Clock stops and slave is stuck in mid-transmission */
496 dev_dbg(&piix4_adapter
->dev
, "Error: no response!\n");
499 if (inb_p(SMBHSTSTS
) != 0x00)
500 outb_p(inb(SMBHSTSTS
), SMBHSTSTS
);
502 if ((temp
= inb_p(SMBHSTSTS
)) != 0x00) {
503 dev_err(&piix4_adapter
->dev
, "Failed reset at end of "
504 "transaction (%02x)\n", temp
);
506 dev_dbg(&piix4_adapter
->dev
, "Transaction (post): CNT=%02x, CMD=%02x, "
507 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT
),
508 inb_p(SMBHSTCMD
), inb_p(SMBHSTADD
), inb_p(SMBHSTDAT0
),
513 /* Return negative errno on error. */
514 static s32
piix4_access(struct i2c_adapter
* adap
, u16 addr
,
515 unsigned short flags
, char read_write
,
516 u8 command
, int size
, union i2c_smbus_data
* data
)
518 struct i2c_piix4_adapdata
*adapdata
= i2c_get_adapdata(adap
);
519 unsigned short piix4_smba
= adapdata
->smba
;
524 case I2C_SMBUS_QUICK
:
525 outb_p((addr
<< 1) | read_write
,
530 outb_p((addr
<< 1) | read_write
,
532 if (read_write
== I2C_SMBUS_WRITE
)
533 outb_p(command
, SMBHSTCMD
);
536 case I2C_SMBUS_BYTE_DATA
:
537 outb_p((addr
<< 1) | read_write
,
539 outb_p(command
, SMBHSTCMD
);
540 if (read_write
== I2C_SMBUS_WRITE
)
541 outb_p(data
->byte
, SMBHSTDAT0
);
542 size
= PIIX4_BYTE_DATA
;
544 case I2C_SMBUS_WORD_DATA
:
545 outb_p((addr
<< 1) | read_write
,
547 outb_p(command
, SMBHSTCMD
);
548 if (read_write
== I2C_SMBUS_WRITE
) {
549 outb_p(data
->word
& 0xff, SMBHSTDAT0
);
550 outb_p((data
->word
& 0xff00) >> 8, SMBHSTDAT1
);
552 size
= PIIX4_WORD_DATA
;
554 case I2C_SMBUS_BLOCK_DATA
:
555 outb_p((addr
<< 1) | read_write
,
557 outb_p(command
, SMBHSTCMD
);
558 if (read_write
== I2C_SMBUS_WRITE
) {
559 len
= data
->block
[0];
560 if (len
== 0 || len
> I2C_SMBUS_BLOCK_MAX
)
562 outb_p(len
, SMBHSTDAT0
);
563 inb_p(SMBHSTCNT
); /* Reset SMBBLKDAT */
564 for (i
= 1; i
<= len
; i
++)
565 outb_p(data
->block
[i
], SMBBLKDAT
);
567 size
= PIIX4_BLOCK_DATA
;
570 dev_warn(&adap
->dev
, "Unsupported transaction %d\n", size
);
574 outb_p((size
& 0x1C) + (ENABLE_INT9
& 1), SMBHSTCNT
);
576 status
= piix4_transaction(adap
);
580 if ((read_write
== I2C_SMBUS_WRITE
) || (size
== PIIX4_QUICK
))
586 case PIIX4_BYTE_DATA
:
587 data
->byte
= inb_p(SMBHSTDAT0
);
589 case PIIX4_WORD_DATA
:
590 data
->word
= inb_p(SMBHSTDAT0
) + (inb_p(SMBHSTDAT1
) << 8);
592 case PIIX4_BLOCK_DATA
:
593 data
->block
[0] = inb_p(SMBHSTDAT0
);
594 if (data
->block
[0] == 0 || data
->block
[0] > I2C_SMBUS_BLOCK_MAX
)
596 inb_p(SMBHSTCNT
); /* Reset SMBBLKDAT */
597 for (i
= 1; i
<= data
->block
[0]; i
++)
598 data
->block
[i
] = inb_p(SMBBLKDAT
);
604 static uint8_t piix4_imc_read(uint8_t idx
)
606 outb_p(idx
, KERNCZ_IMC_IDX
);
607 return inb_p(KERNCZ_IMC_DATA
);
610 static void piix4_imc_write(uint8_t idx
, uint8_t value
)
612 outb_p(idx
, KERNCZ_IMC_IDX
);
613 outb_p(value
, KERNCZ_IMC_DATA
);
616 static int piix4_imc_sleep(void)
618 int timeout
= MAX_TIMEOUT
;
620 if (!request_muxed_region(KERNCZ_IMC_IDX
, 2, "smbus_kerncz_imc"))
623 /* clear response register */
624 piix4_imc_write(0x82, 0x00);
625 /* request ownership flag */
626 piix4_imc_write(0x83, 0xB4);
627 /* kick off IMC Mailbox command 96 */
628 piix4_imc_write(0x80, 0x96);
631 if (piix4_imc_read(0x82) == 0xfa) {
632 release_region(KERNCZ_IMC_IDX
, 2);
635 usleep_range(1000, 2000);
638 release_region(KERNCZ_IMC_IDX
, 2);
642 static void piix4_imc_wakeup(void)
644 int timeout
= MAX_TIMEOUT
;
646 if (!request_muxed_region(KERNCZ_IMC_IDX
, 2, "smbus_kerncz_imc"))
649 /* clear response register */
650 piix4_imc_write(0x82, 0x00);
651 /* release ownership flag */
652 piix4_imc_write(0x83, 0xB5);
653 /* kick off IMC Mailbox command 96 */
654 piix4_imc_write(0x80, 0x96);
657 if (piix4_imc_read(0x82) == 0xfa)
659 usleep_range(1000, 2000);
662 release_region(KERNCZ_IMC_IDX
, 2);
666 * Handles access to multiple SMBus ports on the SB800.
667 * The port is selected by bits 2:1 of the smb_en register (0x2c).
668 * Returns negative errno on error.
670 * Note: The selected port must be returned to the initial selection to avoid
671 * problems on certain systems.
673 static s32
piix4_access_sb800(struct i2c_adapter
*adap
, u16 addr
,
674 unsigned short flags
, char read_write
,
675 u8 command
, int size
, union i2c_smbus_data
*data
)
677 struct i2c_piix4_adapdata
*adapdata
= i2c_get_adapdata(adap
);
678 unsigned short piix4_smba
= adapdata
->smba
;
679 int retries
= MAX_TIMEOUT
;
685 if (!request_muxed_region(SB800_PIIX4_SMB_IDX
, 2, "sb800_piix4_smb"))
688 /* Request the SMBUS semaphore, avoid conflicts with the IMC */
689 smbslvcnt
= inb_p(SMBSLVCNT
);
691 outb_p(smbslvcnt
| 0x10, SMBSLVCNT
);
693 /* Check the semaphore status */
694 smbslvcnt
= inb_p(SMBSLVCNT
);
695 if (smbslvcnt
& 0x10)
698 usleep_range(1000, 2000);
700 /* SMBus is still owned by the IMC, we give up */
707 * Notify the IMC (Integrated Micro Controller) if required.
708 * Among other responsibilities, the IMC is in charge of monitoring
709 * the System fans and temperature sensors, and act accordingly.
710 * All this is done through SMBus and can/will collide
711 * with our transactions if they are long (BLOCK_DATA).
712 * Therefore we need to request the ownership flag during those
715 if ((size
== I2C_SMBUS_BLOCK_DATA
) && adapdata
->notify_imc
) {
718 ret
= piix4_imc_sleep();
722 "IMC base address index region 0x%x already in use.\n",
727 "Failed to communicate with the IMC.\n");
733 /* If IMC communication fails do not retry */
736 "Continuing without IMC notification.\n");
737 adapdata
->notify_imc
= false;
741 outb_p(piix4_port_sel_sb800
, SB800_PIIX4_SMB_IDX
);
742 smba_en_lo
= inb_p(SB800_PIIX4_SMB_IDX
+ 1);
744 port
= adapdata
->port
;
745 if ((smba_en_lo
& piix4_port_mask_sb800
) != port
)
746 outb_p((smba_en_lo
& ~piix4_port_mask_sb800
) | port
,
747 SB800_PIIX4_SMB_IDX
+ 1);
749 retval
= piix4_access(adap
, addr
, flags
, read_write
,
750 command
, size
, data
);
752 outb_p(smba_en_lo
, SB800_PIIX4_SMB_IDX
+ 1);
754 /* Release the semaphore */
755 outb_p(smbslvcnt
| 0x20, SMBSLVCNT
);
757 if ((size
== I2C_SMBUS_BLOCK_DATA
) && adapdata
->notify_imc
)
761 release_region(SB800_PIIX4_SMB_IDX
, 2);
765 static u32
piix4_func(struct i2c_adapter
*adapter
)
767 return I2C_FUNC_SMBUS_QUICK
| I2C_FUNC_SMBUS_BYTE
|
768 I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA
|
769 I2C_FUNC_SMBUS_BLOCK_DATA
;
772 static const struct i2c_algorithm smbus_algorithm
= {
773 .smbus_xfer
= piix4_access
,
774 .functionality
= piix4_func
,
777 static const struct i2c_algorithm piix4_smbus_algorithm_sb800
= {
778 .smbus_xfer
= piix4_access_sb800
,
779 .functionality
= piix4_func
,
782 static const struct pci_device_id piix4_ids
[] = {
783 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
) },
784 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
) },
785 { PCI_DEVICE(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_3
) },
786 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP200_SMBUS
) },
787 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP300_SMBUS
) },
788 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP400_SMBUS
) },
789 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
) },
790 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
) },
791 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
) },
792 { PCI_DEVICE(PCI_VENDOR_ID_HYGON
, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
) },
793 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS
,
794 PCI_DEVICE_ID_SERVERWORKS_OSB4
) },
795 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS
,
796 PCI_DEVICE_ID_SERVERWORKS_CSB5
) },
797 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS
,
798 PCI_DEVICE_ID_SERVERWORKS_CSB6
) },
799 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS
,
800 PCI_DEVICE_ID_SERVERWORKS_HT1000SB
) },
801 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS
,
802 PCI_DEVICE_ID_SERVERWORKS_HT1100LD
) },
806 MODULE_DEVICE_TABLE (pci
, piix4_ids
);
808 static struct i2c_adapter
*piix4_main_adapters
[PIIX4_MAX_ADAPTERS
];
809 static struct i2c_adapter
*piix4_aux_adapter
;
810 static int piix4_adapter_count
;
812 static int piix4_add_adapter(struct pci_dev
*dev
, unsigned short smba
,
813 bool sb800_main
, u8 port
, bool notify_imc
,
814 u8 hw_port_nr
, const char *name
,
815 struct i2c_adapter
**padap
)
817 struct i2c_adapter
*adap
;
818 struct i2c_piix4_adapdata
*adapdata
;
821 adap
= kzalloc(sizeof(*adap
), GFP_KERNEL
);
823 release_region(smba
, SMBIOSIZE
);
827 adap
->owner
= THIS_MODULE
;
828 adap
->class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
829 adap
->algo
= sb800_main
? &piix4_smbus_algorithm_sb800
832 adapdata
= kzalloc(sizeof(*adapdata
), GFP_KERNEL
);
833 if (adapdata
== NULL
) {
835 release_region(smba
, SMBIOSIZE
);
839 adapdata
->smba
= smba
;
840 adapdata
->sb800_main
= sb800_main
;
841 adapdata
->port
= port
<< piix4_port_shift_sb800
;
842 adapdata
->notify_imc
= notify_imc
;
844 /* set up the sysfs linkage to our parent device */
845 adap
->dev
.parent
= &dev
->dev
;
847 if (has_acpi_companion(&dev
->dev
)) {
848 acpi_preset_companion(&adap
->dev
,
849 ACPI_COMPANION(&dev
->dev
),
853 snprintf(adap
->name
, sizeof(adap
->name
),
854 "SMBus PIIX4 adapter%s at %04x", name
, smba
);
856 i2c_set_adapdata(adap
, adapdata
);
858 retval
= i2c_add_adapter(adap
);
862 release_region(smba
, SMBIOSIZE
);
870 static int piix4_add_adapters_sb800(struct pci_dev
*dev
, unsigned short smba
,
873 struct i2c_piix4_adapdata
*adapdata
;
877 if (dev
->device
== PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
||
878 (dev
->device
== PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
&&
879 dev
->revision
>= 0x1F)) {
880 piix4_adapter_count
= HUDSON2_MAIN_PORTS
;
882 piix4_adapter_count
= PIIX4_MAX_ADAPTERS
;
885 for (port
= 0; port
< piix4_adapter_count
; port
++) {
886 u8 hw_port_nr
= port
== 0 ? 0 : port
+ 1;
888 retval
= piix4_add_adapter(dev
, smba
, true, port
, notify_imc
,
890 piix4_main_port_names_sb800
[port
],
891 &piix4_main_adapters
[port
]);
900 "Error setting up SB800 adapters. Unregistering!\n");
901 while (--port
>= 0) {
902 adapdata
= i2c_get_adapdata(piix4_main_adapters
[port
]);
903 if (adapdata
->smba
) {
904 i2c_del_adapter(piix4_main_adapters
[port
]);
906 kfree(piix4_main_adapters
[port
]);
907 piix4_main_adapters
[port
] = NULL
;
914 static int piix4_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
917 bool is_sb800
= false;
919 if ((dev
->vendor
== PCI_VENDOR_ID_ATI
&&
920 dev
->device
== PCI_DEVICE_ID_ATI_SBX00_SMBUS
&&
921 dev
->revision
>= 0x40) ||
922 dev
->vendor
== PCI_VENDOR_ID_AMD
||
923 dev
->vendor
== PCI_VENDOR_ID_HYGON
) {
924 bool notify_imc
= false;
927 if ((dev
->vendor
== PCI_VENDOR_ID_AMD
||
928 dev
->vendor
== PCI_VENDOR_ID_HYGON
) &&
929 dev
->device
== PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
) {
933 * Detect if IMC is active or not, this method is
934 * described on coreboot's AMD IMC notes
936 pci_bus_read_config_byte(dev
->bus
, PCI_DEVFN(0x14, 3),
942 /* base address location etc changed in SB800 */
943 retval
= piix4_setup_sb800(dev
, id
, 0);
948 * Try to register multiplexed main SMBus adapter,
949 * give up if we can't
951 retval
= piix4_add_adapters_sb800(dev
, retval
, notify_imc
);
955 retval
= piix4_setup(dev
, id
);
959 /* Try to register main SMBus adapter, give up if we can't */
960 retval
= piix4_add_adapter(dev
, retval
, false, 0, false, 0,
961 "", &piix4_main_adapters
[0]);
966 /* Check for auxiliary SMBus on some AMD chipsets */
969 if (dev
->vendor
== PCI_VENDOR_ID_ATI
&&
970 dev
->device
== PCI_DEVICE_ID_ATI_SBX00_SMBUS
) {
971 if (dev
->revision
< 0x40) {
972 retval
= piix4_setup_aux(dev
, id
, 0x58);
974 /* SB800 added aux bus too */
975 retval
= piix4_setup_sb800(dev
, id
, 1);
979 if (dev
->vendor
== PCI_VENDOR_ID_AMD
&&
980 (dev
->device
== PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
||
981 dev
->device
== PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
)) {
982 retval
= piix4_setup_sb800(dev
, id
, 1);
986 /* Try to add the aux adapter if it exists,
987 * piix4_add_adapter will clean up if this fails */
988 piix4_add_adapter(dev
, retval
, false, 0, false, 1,
989 is_sb800
? piix4_aux_port_name_sb800
: "",
996 static void piix4_adap_remove(struct i2c_adapter
*adap
)
998 struct i2c_piix4_adapdata
*adapdata
= i2c_get_adapdata(adap
);
1000 if (adapdata
->smba
) {
1001 i2c_del_adapter(adap
);
1002 if (adapdata
->port
== (0 << piix4_port_shift_sb800
))
1003 release_region(adapdata
->smba
, SMBIOSIZE
);
1009 static void piix4_remove(struct pci_dev
*dev
)
1011 int port
= piix4_adapter_count
;
1013 while (--port
>= 0) {
1014 if (piix4_main_adapters
[port
]) {
1015 piix4_adap_remove(piix4_main_adapters
[port
]);
1016 piix4_main_adapters
[port
] = NULL
;
1020 if (piix4_aux_adapter
) {
1021 piix4_adap_remove(piix4_aux_adapter
);
1022 piix4_aux_adapter
= NULL
;
1026 static struct pci_driver piix4_driver
= {
1027 .name
= "piix4_smbus",
1028 .id_table
= piix4_ids
,
1029 .probe
= piix4_probe
,
1030 .remove
= piix4_remove
,
1033 module_pci_driver(piix4_driver
);
1035 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
1036 MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>");
1037 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1038 MODULE_LICENSE("GPL");