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WIP FPC-III support
[linux/fpc-iii.git] / drivers / iio / adc / max1027.c
blobca1dff3924ff9c8d93802297f299c280a38d922c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * iio/adc/max1027.c
4 * Copyright (C) 2014 Philippe Reynes
5 *
6 * based on linux/drivers/iio/ad7923.c
7 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
8 * Copyright 2012 CS Systemes d'Information
9 *
10 * max1027.c
11 *
12 * Partial support for max1027 and similar chips.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/spi/spi.h>
19 #include <linux/delay.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26
27 #define MAX1027_CONV_REG BIT(7)
28 #define MAX1027_SETUP_REG BIT(6)
29 #define MAX1027_AVG_REG BIT(5)
30 #define MAX1027_RST_REG BIT(4)
31
32 /* conversion register */
33 #define MAX1027_TEMP BIT(0)
34 #define MAX1027_SCAN_0_N (0x00 << 1)
35 #define MAX1027_SCAN_N_M (0x01 << 1)
36 #define MAX1027_SCAN_N (0x02 << 1)
37 #define MAX1027_NOSCAN (0x03 << 1)
38 #define MAX1027_CHAN(n) ((n) << 3)
39
40 /* setup register */
41 #define MAX1027_UNIPOLAR 0x02
42 #define MAX1027_BIPOLAR 0x03
43 #define MAX1027_REF_MODE0 (0x00 << 2)
44 #define MAX1027_REF_MODE1 (0x01 << 2)
45 #define MAX1027_REF_MODE2 (0x02 << 2)
46 #define MAX1027_REF_MODE3 (0x03 << 2)
47 #define MAX1027_CKS_MODE0 (0x00 << 4)
48 #define MAX1027_CKS_MODE1 (0x01 << 4)
49 #define MAX1027_CKS_MODE2 (0x02 << 4)
50 #define MAX1027_CKS_MODE3 (0x03 << 4)
51
52 /* averaging register */
53 #define MAX1027_NSCAN_4 0x00
54 #define MAX1027_NSCAN_8 0x01
55 #define MAX1027_NSCAN_12 0x02
56 #define MAX1027_NSCAN_16 0x03
57 #define MAX1027_NAVG_4 (0x00 << 2)
58 #define MAX1027_NAVG_8 (0x01 << 2)
59 #define MAX1027_NAVG_16 (0x02 << 2)
60 #define MAX1027_NAVG_32 (0x03 << 2)
61 #define MAX1027_AVG_EN BIT(4)
62
63 enum max1027_id {
64 max1027,
65 max1029,
66 max1031,
67 max1227,
68 max1229,
69 max1231,
70 };
71
72 static const struct spi_device_id max1027_id[] = {
73 {"max1027", max1027},
74 {"max1029", max1029},
75 {"max1031", max1031},
76 {"max1227", max1227},
77 {"max1229", max1229},
78 {"max1231", max1231},
79 {}
80 };
81 MODULE_DEVICE_TABLE(spi, max1027_id);
82
83 static const struct of_device_id max1027_adc_dt_ids[] = {
84 { .compatible = "maxim,max1027" },
85 { .compatible = "maxim,max1029" },
86 { .compatible = "maxim,max1031" },
87 { .compatible = "maxim,max1227" },
88 { .compatible = "maxim,max1229" },
89 { .compatible = "maxim,max1231" },
90 {},
91 };
92 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
93
94 #define MAX1027_V_CHAN(index, depth) \
95 { \
96 .type = IIO_VOLTAGE, \
97 .indexed = 1, \
98 .channel = index, \
99 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
100 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
101 .scan_index = index + 1, \
102 .scan_type = { \
103 .sign = 'u', \
104 .realbits = depth, \
105 .storagebits = 16, \
106 .shift = 2, \
107 .endianness = IIO_BE, \
108 }, \
109 }
110
111 #define MAX1027_T_CHAN \
112 { \
113 .type = IIO_TEMP, \
114 .channel = 0, \
115 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
116 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
117 .scan_index = 0, \
118 .scan_type = { \
119 .sign = 'u', \
120 .realbits = 12, \
121 .storagebits = 16, \
122 .endianness = IIO_BE, \
123 }, \
124 }
125
126 #define MAX1X27_CHANNELS(depth) \
127 MAX1027_T_CHAN, \
128 MAX1027_V_CHAN(0, depth), \
129 MAX1027_V_CHAN(1, depth), \
130 MAX1027_V_CHAN(2, depth), \
131 MAX1027_V_CHAN(3, depth), \
132 MAX1027_V_CHAN(4, depth), \
133 MAX1027_V_CHAN(5, depth), \
134 MAX1027_V_CHAN(6, depth), \
135 MAX1027_V_CHAN(7, depth)
136
137 #define MAX1X29_CHANNELS(depth) \
138 MAX1X27_CHANNELS(depth), \
139 MAX1027_V_CHAN(8, depth), \
140 MAX1027_V_CHAN(9, depth), \
141 MAX1027_V_CHAN(10, depth), \
142 MAX1027_V_CHAN(11, depth)
143
144 #define MAX1X31_CHANNELS(depth) \
145 MAX1X27_CHANNELS(depth), \
146 MAX1X29_CHANNELS(depth), \
147 MAX1027_V_CHAN(12, depth), \
148 MAX1027_V_CHAN(13, depth), \
149 MAX1027_V_CHAN(14, depth), \
150 MAX1027_V_CHAN(15, depth)
151
152 static const struct iio_chan_spec max1027_channels[] = {
153 MAX1X27_CHANNELS(10),
154 };
155
156 static const struct iio_chan_spec max1029_channels[] = {
157 MAX1X29_CHANNELS(10),
158 };
159
160 static const struct iio_chan_spec max1031_channels[] = {
161 MAX1X31_CHANNELS(10),
162 };
163
164 static const struct iio_chan_spec max1227_channels[] = {
165 MAX1X27_CHANNELS(12),
166 };
167
168 static const struct iio_chan_spec max1229_channels[] = {
169 MAX1X29_CHANNELS(12),
170 };
171
172 static const struct iio_chan_spec max1231_channels[] = {
173 MAX1X31_CHANNELS(12),
174 };
175
176 static const unsigned long max1027_available_scan_masks[] = {
177 0x000001ff,
178 0x00000000,
179 };
180
181 static const unsigned long max1029_available_scan_masks[] = {
182 0x00001fff,
183 0x00000000,
184 };
185
186 static const unsigned long max1031_available_scan_masks[] = {
187 0x0001ffff,
188 0x00000000,
189 };
190
191 struct max1027_chip_info {
192 const struct iio_chan_spec *channels;
193 unsigned int num_channels;
194 const unsigned long *available_scan_masks;
195 };
196
197 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
198 [max1027] = {
199 .channels = max1027_channels,
200 .num_channels = ARRAY_SIZE(max1027_channels),
201 .available_scan_masks = max1027_available_scan_masks,
202 },
203 [max1029] = {
204 .channels = max1029_channels,
205 .num_channels = ARRAY_SIZE(max1029_channels),
206 .available_scan_masks = max1029_available_scan_masks,
207 },
208 [max1031] = {
209 .channels = max1031_channels,
210 .num_channels = ARRAY_SIZE(max1031_channels),
211 .available_scan_masks = max1031_available_scan_masks,
212 },
213 [max1227] = {
214 .channels = max1227_channels,
215 .num_channels = ARRAY_SIZE(max1227_channels),
216 .available_scan_masks = max1027_available_scan_masks,
217 },
218 [max1229] = {
219 .channels = max1229_channels,
220 .num_channels = ARRAY_SIZE(max1229_channels),
221 .available_scan_masks = max1029_available_scan_masks,
222 },
223 [max1231] = {
224 .channels = max1231_channels,
225 .num_channels = ARRAY_SIZE(max1231_channels),
226 .available_scan_masks = max1031_available_scan_masks,
227 },
228 };
229
230 struct max1027_state {
231 const struct max1027_chip_info *info;
232 struct spi_device *spi;
233 struct iio_trigger *trig;
234 __be16 *buffer;
235 struct mutex lock;
236
237 u8 reg ____cacheline_aligned;
238 };
239
240 static int max1027_read_single_value(struct iio_dev *indio_dev,
241 struct iio_chan_spec const *chan,
242 int *val)
243 {
244 int ret;
245 struct max1027_state *st = iio_priv(indio_dev);
246
247 if (iio_buffer_enabled(indio_dev)) {
248 dev_warn(&indio_dev->dev, "trigger mode already enabled");
249 return -EBUSY;
250 }
251
252 /* Start acquisition on conversion register write */
253 st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
254 ret = spi_write(st->spi, &st->reg, 1);
255 if (ret < 0) {
256 dev_err(&indio_dev->dev,
257 "Failed to configure setup register\n");
258 return ret;
259 }
260
261 /* Configure conversion register with the requested chan */
262 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
263 MAX1027_NOSCAN;
264 if (chan->type == IIO_TEMP)
265 st->reg |= MAX1027_TEMP;
266 ret = spi_write(st->spi, &st->reg, 1);
267 if (ret < 0) {
268 dev_err(&indio_dev->dev,
269 "Failed to configure conversion register\n");
270 return ret;
271 }
272
273 /*
274 * For an unknown reason, when we use the mode "10" (write
275 * conversion register), the interrupt doesn't occur every time.
276 * So we just wait 1 ms.
277 */
278 mdelay(1);
279
280 /* Read result */
281 ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
282 if (ret < 0)
283 return ret;
284
285 *val = be16_to_cpu(st->buffer[0]);
286
287 return IIO_VAL_INT;
288 }
289
290 static int max1027_read_raw(struct iio_dev *indio_dev,
291 struct iio_chan_spec const *chan,
292 int *val, int *val2, long mask)
293 {
294 int ret = 0;
295 struct max1027_state *st = iio_priv(indio_dev);
296
297 mutex_lock(&st->lock);
298
299 switch (mask) {
300 case IIO_CHAN_INFO_RAW:
301 ret = max1027_read_single_value(indio_dev, chan, val);
302 break;
303 case IIO_CHAN_INFO_SCALE:
304 switch (chan->type) {
305 case IIO_TEMP:
306 *val = 1;
307 *val2 = 8;
308 ret = IIO_VAL_FRACTIONAL;
309 break;
310 case IIO_VOLTAGE:
311 *val = 2500;
312 *val2 = chan->scan_type.realbits;
313 ret = IIO_VAL_FRACTIONAL_LOG2;
314 break;
315 default:
316 ret = -EINVAL;
317 break;
318 }
319 break;
320 default:
321 ret = -EINVAL;
322 break;
323 }
324
325 mutex_unlock(&st->lock);
326
327 return ret;
328 }
329
330 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
331 unsigned reg, unsigned writeval,
332 unsigned *readval)
333 {
334 struct max1027_state *st = iio_priv(indio_dev);
335 u8 *val = (u8 *)st->buffer;
336
337 if (readval) {
338 int ret = spi_read(st->spi, val, 2);
339 *readval = be16_to_cpu(st->buffer[0]);
340 return ret;
341 }
342
343 *val = (u8)writeval;
344 return spi_write(st->spi, val, 1);
345 }
346
347 static int max1027_validate_trigger(struct iio_dev *indio_dev,
348 struct iio_trigger *trig)
349 {
350 struct max1027_state *st = iio_priv(indio_dev);
351
352 if (st->trig != trig)
353 return -EINVAL;
354
355 return 0;
356 }
357
358 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
359 {
360 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
361 struct max1027_state *st = iio_priv(indio_dev);
362 int ret;
363
364 if (state) {
365 /* Start acquisition on cnvst */
366 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
367 MAX1027_REF_MODE2;
368 ret = spi_write(st->spi, &st->reg, 1);
369 if (ret < 0)
370 return ret;
371
372 /* Scan from 0 to max */
373 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
374 MAX1027_SCAN_N_M | MAX1027_TEMP;
375 ret = spi_write(st->spi, &st->reg, 1);
376 if (ret < 0)
377 return ret;
378 } else {
379 /* Start acquisition on conversion register write */
380 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
381 MAX1027_REF_MODE2;
382 ret = spi_write(st->spi, &st->reg, 1);
383 if (ret < 0)
384 return ret;
385 }
386
387 return 0;
388 }
389
390 static irqreturn_t max1027_trigger_handler(int irq, void *private)
391 {
392 struct iio_poll_func *pf = private;
393 struct iio_dev *indio_dev = pf->indio_dev;
394 struct max1027_state *st = iio_priv(indio_dev);
395
396 pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
397
398 /* fill buffer with all channel */
399 spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
400
401 iio_push_to_buffers(indio_dev, st->buffer);
402
403 iio_trigger_notify_done(indio_dev->trig);
404
405 return IRQ_HANDLED;
406 }
407
408 static const struct iio_trigger_ops max1027_trigger_ops = {
409 .validate_device = &iio_trigger_validate_own_device,
410 .set_trigger_state = &max1027_set_trigger_state,
411 };
412
413 static const struct iio_info max1027_info = {
414 .read_raw = &max1027_read_raw,
415 .validate_trigger = &max1027_validate_trigger,
416 .debugfs_reg_access = &max1027_debugfs_reg_access,
417 };
418
419 static int max1027_probe(struct spi_device *spi)
420 {
421 int ret;
422 struct iio_dev *indio_dev;
423 struct max1027_state *st;
424
425 pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
426
427 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
428 if (indio_dev == NULL) {
429 pr_err("Can't allocate iio device\n");
430 return -ENOMEM;
431 }
432
433 spi_set_drvdata(spi, indio_dev);
434
435 st = iio_priv(indio_dev);
436 st->spi = spi;
437 st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
438
439 mutex_init(&st->lock);
440
441 indio_dev->name = spi_get_device_id(spi)->name;
442 indio_dev->info = &max1027_info;
443 indio_dev->modes = INDIO_DIRECT_MODE;
444 indio_dev->channels = st->info->channels;
445 indio_dev->num_channels = st->info->num_channels;
446 indio_dev->available_scan_masks = st->info->available_scan_masks;
447
448 st->buffer = devm_kmalloc_array(&indio_dev->dev,
449 indio_dev->num_channels, 2,
450 GFP_KERNEL);
451 if (st->buffer == NULL) {
452 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
453 return -ENOMEM;
454 }
455
456 if (spi->irq) {
457 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
458 &iio_pollfunc_store_time,
459 &max1027_trigger_handler,
460 NULL);
461 if (ret < 0) {
462 dev_err(&indio_dev->dev, "Failed to setup buffer\n");
463 return ret;
464 }
465
466 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
467 indio_dev->name);
468 if (st->trig == NULL) {
469 ret = -ENOMEM;
470 dev_err(&indio_dev->dev,
471 "Failed to allocate iio trigger\n");
472 return ret;
473 }
474
475 st->trig->ops = &max1027_trigger_ops;
476 st->trig->dev.parent = &spi->dev;
477 iio_trigger_set_drvdata(st->trig, indio_dev);
478 ret = devm_iio_trigger_register(&indio_dev->dev,
479 st->trig);
480 if (ret < 0) {
481 dev_err(&indio_dev->dev,
482 "Failed to register iio trigger\n");
483 return ret;
484 }
485
486 ret = devm_request_threaded_irq(&spi->dev, spi->irq,
487 iio_trigger_generic_data_rdy_poll,
488 NULL,
489 IRQF_TRIGGER_FALLING,
490 spi->dev.driver->name,
491 st->trig);
492 if (ret < 0) {
493 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
494 return ret;
495 }
496 }
497
498 /* Internal reset */
499 st->reg = MAX1027_RST_REG;
500 ret = spi_write(st->spi, &st->reg, 1);
501 if (ret < 0) {
502 dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
503 return ret;
504 }
505
506 /* Disable averaging */
507 st->reg = MAX1027_AVG_REG;
508 ret = spi_write(st->spi, &st->reg, 1);
509 if (ret < 0) {
510 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
511 return ret;
512 }
513
514 return devm_iio_device_register(&spi->dev, indio_dev);
515 }
516
517 static struct spi_driver max1027_driver = {
518 .driver = {
519 .name = "max1027",
520 .of_match_table = max1027_adc_dt_ids,
521 },
522 .probe = max1027_probe,
523 .id_table = max1027_id,
524 };
525 module_spi_driver(max1027_driver);
526
527 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
528 MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC");
529 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support