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WIP FPC-III support
[linux/fpc-iii.git] / drivers / iio / adc / ti-ads1015.c
blob9fef39bcf997b90be945c25942489aa6f2842333
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADS1015 - Texas Instruments Analog-to-Digital Converter
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 *
7 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
8 * * 0x48 - ADDR connected to Ground
9 * * 0x49 - ADDR connected to Vdd
10 * * 0x4A - ADDR connected to SDA
11 * * 0x4B - ADDR connected to SCL
12 */
13
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/i2c.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/mutex.h>
22 #include <linux/delay.h>
23
24 #include <linux/iio/iio.h>
25 #include <linux/iio/types.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/events.h>
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/triggered_buffer.h>
30 #include <linux/iio/trigger_consumer.h>
31
32 #define ADS1015_DRV_NAME "ads1015"
33
34 #define ADS1015_CHANNELS 8
35
36 #define ADS1015_CONV_REG 0x00
37 #define ADS1015_CFG_REG 0x01
38 #define ADS1015_LO_THRESH_REG 0x02
39 #define ADS1015_HI_THRESH_REG 0x03
40
41 #define ADS1015_CFG_COMP_QUE_SHIFT 0
42 #define ADS1015_CFG_COMP_LAT_SHIFT 2
43 #define ADS1015_CFG_COMP_POL_SHIFT 3
44 #define ADS1015_CFG_COMP_MODE_SHIFT 4
45 #define ADS1015_CFG_DR_SHIFT 5
46 #define ADS1015_CFG_MOD_SHIFT 8
47 #define ADS1015_CFG_PGA_SHIFT 9
48 #define ADS1015_CFG_MUX_SHIFT 12
49
50 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
51 #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
52 #define ADS1015_CFG_COMP_POL_MASK BIT(3)
53 #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
54 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
55 #define ADS1015_CFG_MOD_MASK BIT(8)
56 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
57 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
58
59 /* Comparator queue and disable field */
60 #define ADS1015_CFG_COMP_DISABLE 3
61
62 /* Comparator polarity field */
63 #define ADS1015_CFG_COMP_POL_LOW 0
64 #define ADS1015_CFG_COMP_POL_HIGH 1
65
66 /* Comparator mode field */
67 #define ADS1015_CFG_COMP_MODE_TRAD 0
68 #define ADS1015_CFG_COMP_MODE_WINDOW 1
69
70 /* device operating modes */
71 #define ADS1015_CONTINUOUS 0
72 #define ADS1015_SINGLESHOT 1
73
74 #define ADS1015_SLEEP_DELAY_MS 2000
75 #define ADS1015_DEFAULT_PGA 2
76 #define ADS1015_DEFAULT_DATA_RATE 4
77 #define ADS1015_DEFAULT_CHAN 0
78
79 enum chip_ids {
80 ADSXXXX = 0,
81 ADS1015,
82 ADS1115,
83 };
84
85 enum ads1015_channels {
86 ADS1015_AIN0_AIN1 = 0,
87 ADS1015_AIN0_AIN3,
88 ADS1015_AIN1_AIN3,
89 ADS1015_AIN2_AIN3,
90 ADS1015_AIN0,
91 ADS1015_AIN1,
92 ADS1015_AIN2,
93 ADS1015_AIN3,
94 ADS1015_TIMESTAMP,
95 };
96
97 static const unsigned int ads1015_data_rate[] = {
98 128, 250, 490, 920, 1600, 2400, 3300, 3300
99 };
100
101 static const unsigned int ads1115_data_rate[] = {
102 8, 16, 32, 64, 128, 250, 475, 860
103 };
104
105 /*
106 * Translation from PGA bits to full-scale positive and negative input voltage
107 * range in mV
108 */
109 static int ads1015_fullscale_range[] = {
110 6144, 4096, 2048, 1024, 512, 256, 256, 256
111 };
112
113 /*
114 * Translation from COMP_QUE field value to the number of successive readings
115 * exceed the threshold values before an interrupt is generated
116 */
117 static const int ads1015_comp_queue[] = { 1, 2, 4 };
118
119 static const struct iio_event_spec ads1015_events[] = {
120 {
121 .type = IIO_EV_TYPE_THRESH,
122 .dir = IIO_EV_DIR_RISING,
123 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
124 BIT(IIO_EV_INFO_ENABLE),
125 }, {
126 .type = IIO_EV_TYPE_THRESH,
127 .dir = IIO_EV_DIR_FALLING,
128 .mask_separate = BIT(IIO_EV_INFO_VALUE),
129 }, {
130 .type = IIO_EV_TYPE_THRESH,
131 .dir = IIO_EV_DIR_EITHER,
132 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
133 BIT(IIO_EV_INFO_PERIOD),
134 },
135 };
136
137 #define ADS1015_V_CHAN(_chan, _addr) { \
138 .type = IIO_VOLTAGE, \
139 .indexed = 1, \
140 .address = _addr, \
141 .channel = _chan, \
142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
143 BIT(IIO_CHAN_INFO_SCALE) | \
144 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
145 .scan_index = _addr, \
146 .scan_type = { \
147 .sign = 's', \
148 .realbits = 12, \
149 .storagebits = 16, \
150 .shift = 4, \
151 .endianness = IIO_CPU, \
152 }, \
153 .event_spec = ads1015_events, \
154 .num_event_specs = ARRAY_SIZE(ads1015_events), \
155 .datasheet_name = "AIN"#_chan, \
156 }
157
158 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
159 .type = IIO_VOLTAGE, \
160 .differential = 1, \
161 .indexed = 1, \
162 .address = _addr, \
163 .channel = _chan, \
164 .channel2 = _chan2, \
165 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
166 BIT(IIO_CHAN_INFO_SCALE) | \
167 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
168 .scan_index = _addr, \
169 .scan_type = { \
170 .sign = 's', \
171 .realbits = 12, \
172 .storagebits = 16, \
173 .shift = 4, \
174 .endianness = IIO_CPU, \
175 }, \
176 .event_spec = ads1015_events, \
177 .num_event_specs = ARRAY_SIZE(ads1015_events), \
178 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
179 }
180
181 #define ADS1115_V_CHAN(_chan, _addr) { \
182 .type = IIO_VOLTAGE, \
183 .indexed = 1, \
184 .address = _addr, \
185 .channel = _chan, \
186 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
187 BIT(IIO_CHAN_INFO_SCALE) | \
188 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
189 .scan_index = _addr, \
190 .scan_type = { \
191 .sign = 's', \
192 .realbits = 16, \
193 .storagebits = 16, \
194 .endianness = IIO_CPU, \
195 }, \
196 .event_spec = ads1015_events, \
197 .num_event_specs = ARRAY_SIZE(ads1015_events), \
198 .datasheet_name = "AIN"#_chan, \
199 }
200
201 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
202 .type = IIO_VOLTAGE, \
203 .differential = 1, \
204 .indexed = 1, \
205 .address = _addr, \
206 .channel = _chan, \
207 .channel2 = _chan2, \
208 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
209 BIT(IIO_CHAN_INFO_SCALE) | \
210 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
211 .scan_index = _addr, \
212 .scan_type = { \
213 .sign = 's', \
214 .realbits = 16, \
215 .storagebits = 16, \
216 .endianness = IIO_CPU, \
217 }, \
218 .event_spec = ads1015_events, \
219 .num_event_specs = ARRAY_SIZE(ads1015_events), \
220 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
221 }
222
223 struct ads1015_channel_data {
224 bool enabled;
225 unsigned int pga;
226 unsigned int data_rate;
227 };
228
229 struct ads1015_thresh_data {
230 unsigned int comp_queue;
231 int high_thresh;
232 int low_thresh;
233 };
234
235 struct ads1015_data {
236 struct regmap *regmap;
237 /*
238 * Protects ADC ops, e.g: concurrent sysfs/buffered
239 * data reads, configuration updates
240 */
241 struct mutex lock;
242 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
243
244 unsigned int event_channel;
245 unsigned int comp_mode;
246 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
247
248 unsigned int *data_rate;
249 /*
250 * Set to true when the ADC is switched to the continuous-conversion
251 * mode and exits from a power-down state. This flag is used to avoid
252 * getting the stale result from the conversion register.
253 */
254 bool conv_invalid;
255 };
256
257 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
258 {
259 return (data->event_channel != ADS1015_CHANNELS);
260 }
261
262 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
263 int comp_mode)
264 {
265 WARN_ON(ads1015_event_channel_enabled(data));
266
267 data->event_channel = chan;
268 data->comp_mode = comp_mode;
269 }
270
271 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
272 {
273 data->event_channel = ADS1015_CHANNELS;
274 }
275
276 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
277 {
278 switch (reg) {
279 case ADS1015_CFG_REG:
280 case ADS1015_LO_THRESH_REG:
281 case ADS1015_HI_THRESH_REG:
282 return true;
283 default:
284 return false;
285 }
286 }
287
288 static const struct regmap_config ads1015_regmap_config = {
289 .reg_bits = 8,
290 .val_bits = 16,
291 .max_register = ADS1015_HI_THRESH_REG,
292 .writeable_reg = ads1015_is_writeable_reg,
293 };
294
295 static const struct iio_chan_spec ads1015_channels[] = {
296 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
297 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
298 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
299 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
300 ADS1015_V_CHAN(0, ADS1015_AIN0),
301 ADS1015_V_CHAN(1, ADS1015_AIN1),
302 ADS1015_V_CHAN(2, ADS1015_AIN2),
303 ADS1015_V_CHAN(3, ADS1015_AIN3),
304 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
305 };
306
307 static const struct iio_chan_spec ads1115_channels[] = {
308 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
309 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
310 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
311 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
312 ADS1115_V_CHAN(0, ADS1015_AIN0),
313 ADS1115_V_CHAN(1, ADS1015_AIN1),
314 ADS1115_V_CHAN(2, ADS1015_AIN2),
315 ADS1115_V_CHAN(3, ADS1015_AIN3),
316 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
317 };
318
319 #ifdef CONFIG_PM
320 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
321 {
322 int ret;
323 struct device *dev = regmap_get_device(data->regmap);
324
325 if (on) {
326 ret = pm_runtime_get_sync(dev);
327 if (ret < 0)
328 pm_runtime_put_noidle(dev);
329 } else {
330 pm_runtime_mark_last_busy(dev);
331 ret = pm_runtime_put_autosuspend(dev);
332 }
333
334 return ret < 0 ? ret : 0;
335 }
336
337 #else /* !CONFIG_PM */
338
339 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
340 {
341 return 0;
342 }
343
344 #endif /* !CONFIG_PM */
345
346 static
347 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
348 {
349 int ret, pga, dr, dr_old, conv_time;
350 unsigned int old, mask, cfg;
351
352 if (chan < 0 || chan >= ADS1015_CHANNELS)
353 return -EINVAL;
354
355 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
356 if (ret)
357 return ret;
358
359 pga = data->channel_data[chan].pga;
360 dr = data->channel_data[chan].data_rate;
361 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
362 ADS1015_CFG_DR_MASK;
363 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
364 dr << ADS1015_CFG_DR_SHIFT;
365
366 if (ads1015_event_channel_enabled(data)) {
367 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
368 cfg |= data->thresh_data[chan].comp_queue <<
369 ADS1015_CFG_COMP_QUE_SHIFT |
370 data->comp_mode <<
371 ADS1015_CFG_COMP_MODE_SHIFT;
372 }
373
374 cfg = (old & ~mask) | (cfg & mask);
375 if (old != cfg) {
376 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
377 if (ret)
378 return ret;
379 data->conv_invalid = true;
380 }
381 if (data->conv_invalid) {
382 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
383 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
384 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
385 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
386 usleep_range(conv_time, conv_time + 1);
387 data->conv_invalid = false;
388 }
389
390 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
391 }
392
393 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
394 {
395 struct iio_poll_func *pf = p;
396 struct iio_dev *indio_dev = pf->indio_dev;
397 struct ads1015_data *data = iio_priv(indio_dev);
398 s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
399 int chan, ret, res;
400
401 memset(buf, 0, sizeof(buf));
402
403 mutex_lock(&data->lock);
404 chan = find_first_bit(indio_dev->active_scan_mask,
405 indio_dev->masklength);
406 ret = ads1015_get_adc_result(data, chan, &res);
407 if (ret < 0) {
408 mutex_unlock(&data->lock);
409 goto err;
410 }
411
412 buf[0] = res;
413 mutex_unlock(&data->lock);
414
415 iio_push_to_buffers_with_timestamp(indio_dev, buf,
416 iio_get_time_ns(indio_dev));
417
418 err:
419 iio_trigger_notify_done(indio_dev->trig);
420
421 return IRQ_HANDLED;
422 }
423
424 static int ads1015_set_scale(struct ads1015_data *data,
425 struct iio_chan_spec const *chan,
426 int scale, int uscale)
427 {
428 int i;
429 int fullscale = div_s64((scale * 1000000LL + uscale) <<
430 (chan->scan_type.realbits - 1), 1000000);
431
432 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
433 if (ads1015_fullscale_range[i] == fullscale) {
434 data->channel_data[chan->address].pga = i;
435 return 0;
436 }
437 }
438
439 return -EINVAL;
440 }
441
442 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
443 {
444 int i;
445
446 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
447 if (data->data_rate[i] == rate) {
448 data->channel_data[chan].data_rate = i;
449 return 0;
450 }
451 }
452
453 return -EINVAL;
454 }
455
456 static int ads1015_read_raw(struct iio_dev *indio_dev,
457 struct iio_chan_spec const *chan, int *val,
458 int *val2, long mask)
459 {
460 int ret, idx;
461 struct ads1015_data *data = iio_priv(indio_dev);
462
463 mutex_lock(&data->lock);
464 switch (mask) {
465 case IIO_CHAN_INFO_RAW: {
466 int shift = chan->scan_type.shift;
467
468 ret = iio_device_claim_direct_mode(indio_dev);
469 if (ret)
470 break;
471
472 if (ads1015_event_channel_enabled(data) &&
473 data->event_channel != chan->address) {
474 ret = -EBUSY;
475 goto release_direct;
476 }
477
478 ret = ads1015_set_power_state(data, true);
479 if (ret < 0)
480 goto release_direct;
481
482 ret = ads1015_get_adc_result(data, chan->address, val);
483 if (ret < 0) {
484 ads1015_set_power_state(data, false);
485 goto release_direct;
486 }
487
488 *val = sign_extend32(*val >> shift, 15 - shift);
489
490 ret = ads1015_set_power_state(data, false);
491 if (ret < 0)
492 goto release_direct;
493
494 ret = IIO_VAL_INT;
495 release_direct:
496 iio_device_release_direct_mode(indio_dev);
497 break;
498 }
499 case IIO_CHAN_INFO_SCALE:
500 idx = data->channel_data[chan->address].pga;
501 *val = ads1015_fullscale_range[idx];
502 *val2 = chan->scan_type.realbits - 1;
503 ret = IIO_VAL_FRACTIONAL_LOG2;
504 break;
505 case IIO_CHAN_INFO_SAMP_FREQ:
506 idx = data->channel_data[chan->address].data_rate;
507 *val = data->data_rate[idx];
508 ret = IIO_VAL_INT;
509 break;
510 default:
511 ret = -EINVAL;
512 break;
513 }
514 mutex_unlock(&data->lock);
515
516 return ret;
517 }
518
519 static int ads1015_write_raw(struct iio_dev *indio_dev,
520 struct iio_chan_spec const *chan, int val,
521 int val2, long mask)
522 {
523 struct ads1015_data *data = iio_priv(indio_dev);
524 int ret;
525
526 mutex_lock(&data->lock);
527 switch (mask) {
528 case IIO_CHAN_INFO_SCALE:
529 ret = ads1015_set_scale(data, chan, val, val2);
530 break;
531 case IIO_CHAN_INFO_SAMP_FREQ:
532 ret = ads1015_set_data_rate(data, chan->address, val);
533 break;
534 default:
535 ret = -EINVAL;
536 break;
537 }
538 mutex_unlock(&data->lock);
539
540 return ret;
541 }
542
543 static int ads1015_read_event(struct iio_dev *indio_dev,
544 const struct iio_chan_spec *chan, enum iio_event_type type,
545 enum iio_event_direction dir, enum iio_event_info info, int *val,
546 int *val2)
547 {
548 struct ads1015_data *data = iio_priv(indio_dev);
549 int ret;
550 unsigned int comp_queue;
551 int period;
552 int dr;
553
554 mutex_lock(&data->lock);
555
556 switch (info) {
557 case IIO_EV_INFO_VALUE:
558 *val = (dir == IIO_EV_DIR_RISING) ?
559 data->thresh_data[chan->address].high_thresh :
560 data->thresh_data[chan->address].low_thresh;
561 ret = IIO_VAL_INT;
562 break;
563 case IIO_EV_INFO_PERIOD:
564 dr = data->channel_data[chan->address].data_rate;
565 comp_queue = data->thresh_data[chan->address].comp_queue;
566 period = ads1015_comp_queue[comp_queue] *
567 USEC_PER_SEC / data->data_rate[dr];
568
569 *val = period / USEC_PER_SEC;
570 *val2 = period % USEC_PER_SEC;
571 ret = IIO_VAL_INT_PLUS_MICRO;
572 break;
573 default:
574 ret = -EINVAL;
575 break;
576 }
577
578 mutex_unlock(&data->lock);
579
580 return ret;
581 }
582
583 static int ads1015_write_event(struct iio_dev *indio_dev,
584 const struct iio_chan_spec *chan, enum iio_event_type type,
585 enum iio_event_direction dir, enum iio_event_info info, int val,
586 int val2)
587 {
588 struct ads1015_data *data = iio_priv(indio_dev);
589 int realbits = chan->scan_type.realbits;
590 int ret = 0;
591 long long period;
592 int i;
593 int dr;
594
595 mutex_lock(&data->lock);
596
597 switch (info) {
598 case IIO_EV_INFO_VALUE:
599 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
600 ret = -EINVAL;
601 break;
602 }
603 if (dir == IIO_EV_DIR_RISING)
604 data->thresh_data[chan->address].high_thresh = val;
605 else
606 data->thresh_data[chan->address].low_thresh = val;
607 break;
608 case IIO_EV_INFO_PERIOD:
609 dr = data->channel_data[chan->address].data_rate;
610 period = val * USEC_PER_SEC + val2;
611
612 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
613 if (period <= ads1015_comp_queue[i] *
614 USEC_PER_SEC / data->data_rate[dr])
615 break;
616 }
617 data->thresh_data[chan->address].comp_queue = i;
618 break;
619 default:
620 ret = -EINVAL;
621 break;
622 }
623
624 mutex_unlock(&data->lock);
625
626 return ret;
627 }
628
629 static int ads1015_read_event_config(struct iio_dev *indio_dev,
630 const struct iio_chan_spec *chan, enum iio_event_type type,
631 enum iio_event_direction dir)
632 {
633 struct ads1015_data *data = iio_priv(indio_dev);
634 int ret = 0;
635
636 mutex_lock(&data->lock);
637 if (data->event_channel == chan->address) {
638 switch (dir) {
639 case IIO_EV_DIR_RISING:
640 ret = 1;
641 break;
642 case IIO_EV_DIR_EITHER:
643 ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
644 break;
645 default:
646 ret = -EINVAL;
647 break;
648 }
649 }
650 mutex_unlock(&data->lock);
651
652 return ret;
653 }
654
655 static int ads1015_enable_event_config(struct ads1015_data *data,
656 const struct iio_chan_spec *chan, int comp_mode)
657 {
658 int low_thresh = data->thresh_data[chan->address].low_thresh;
659 int high_thresh = data->thresh_data[chan->address].high_thresh;
660 int ret;
661 unsigned int val;
662
663 if (ads1015_event_channel_enabled(data)) {
664 if (data->event_channel != chan->address ||
665 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
666 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
667 return -EBUSY;
668
669 return 0;
670 }
671
672 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
673 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
674 high_thresh - 1);
675 }
676 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
677 low_thresh << chan->scan_type.shift);
678 if (ret)
679 return ret;
680
681 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
682 high_thresh << chan->scan_type.shift);
683 if (ret)
684 return ret;
685
686 ret = ads1015_set_power_state(data, true);
687 if (ret < 0)
688 return ret;
689
690 ads1015_event_channel_enable(data, chan->address, comp_mode);
691
692 ret = ads1015_get_adc_result(data, chan->address, &val);
693 if (ret) {
694 ads1015_event_channel_disable(data, chan->address);
695 ads1015_set_power_state(data, false);
696 }
697
698 return ret;
699 }
700
701 static int ads1015_disable_event_config(struct ads1015_data *data,
702 const struct iio_chan_spec *chan, int comp_mode)
703 {
704 int ret;
705
706 if (!ads1015_event_channel_enabled(data))
707 return 0;
708
709 if (data->event_channel != chan->address)
710 return 0;
711
712 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
713 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
714 return 0;
715
716 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
717 ADS1015_CFG_COMP_QUE_MASK,
718 ADS1015_CFG_COMP_DISABLE <<
719 ADS1015_CFG_COMP_QUE_SHIFT);
720 if (ret)
721 return ret;
722
723 ads1015_event_channel_disable(data, chan->address);
724
725 return ads1015_set_power_state(data, false);
726 }
727
728 static int ads1015_write_event_config(struct iio_dev *indio_dev,
729 const struct iio_chan_spec *chan, enum iio_event_type type,
730 enum iio_event_direction dir, int state)
731 {
732 struct ads1015_data *data = iio_priv(indio_dev);
733 int ret;
734 int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
735 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
736
737 mutex_lock(&data->lock);
738
739 /* Prevent from enabling both buffer and event at a time */
740 ret = iio_device_claim_direct_mode(indio_dev);
741 if (ret) {
742 mutex_unlock(&data->lock);
743 return ret;
744 }
745
746 if (state)
747 ret = ads1015_enable_event_config(data, chan, comp_mode);
748 else
749 ret = ads1015_disable_event_config(data, chan, comp_mode);
750
751 iio_device_release_direct_mode(indio_dev);
752 mutex_unlock(&data->lock);
753
754 return ret;
755 }
756
757 static irqreturn_t ads1015_event_handler(int irq, void *priv)
758 {
759 struct iio_dev *indio_dev = priv;
760 struct ads1015_data *data = iio_priv(indio_dev);
761 int val;
762 int ret;
763
764 /* Clear the latched ALERT/RDY pin */
765 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
766 if (ret)
767 return IRQ_HANDLED;
768
769 if (ads1015_event_channel_enabled(data)) {
770 enum iio_event_direction dir;
771 u64 code;
772
773 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
774 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
775 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
776 IIO_EV_TYPE_THRESH, dir);
777 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
778 }
779
780 return IRQ_HANDLED;
781 }
782
783 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
784 {
785 struct ads1015_data *data = iio_priv(indio_dev);
786
787 /* Prevent from enabling both buffer and event at a time */
788 if (ads1015_event_channel_enabled(data))
789 return -EBUSY;
790
791 return ads1015_set_power_state(iio_priv(indio_dev), true);
792 }
793
794 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
795 {
796 return ads1015_set_power_state(iio_priv(indio_dev), false);
797 }
798
799 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
800 .preenable = ads1015_buffer_preenable,
801 .postdisable = ads1015_buffer_postdisable,
802 .validate_scan_mask = &iio_validate_scan_mask_onehot,
803 };
804
805 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
806 "3 2 1 0.5 0.25 0.125");
807 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
808 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
809
810 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
811 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
812 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
813 sampling_frequency_available, "8 16 32 64 128 250 475 860");
814
815 static struct attribute *ads1015_attributes[] = {
816 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
817 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
818 NULL,
819 };
820
821 static const struct attribute_group ads1015_attribute_group = {
822 .attrs = ads1015_attributes,
823 };
824
825 static struct attribute *ads1115_attributes[] = {
826 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
827 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
828 NULL,
829 };
830
831 static const struct attribute_group ads1115_attribute_group = {
832 .attrs = ads1115_attributes,
833 };
834
835 static const struct iio_info ads1015_info = {
836 .read_raw = ads1015_read_raw,
837 .write_raw = ads1015_write_raw,
838 .read_event_value = ads1015_read_event,
839 .write_event_value = ads1015_write_event,
840 .read_event_config = ads1015_read_event_config,
841 .write_event_config = ads1015_write_event_config,
842 .attrs = &ads1015_attribute_group,
843 };
844
845 static const struct iio_info ads1115_info = {
846 .read_raw = ads1015_read_raw,
847 .write_raw = ads1015_write_raw,
848 .read_event_value = ads1015_read_event,
849 .write_event_value = ads1015_write_event,
850 .read_event_config = ads1015_read_event_config,
851 .write_event_config = ads1015_write_event_config,
852 .attrs = &ads1115_attribute_group,
853 };
854
855 static int ads1015_client_get_channels_config(struct i2c_client *client)
856 {
857 struct iio_dev *indio_dev = i2c_get_clientdata(client);
858 struct ads1015_data *data = iio_priv(indio_dev);
859 struct device *dev = &client->dev;
860 struct fwnode_handle *node;
861 int i = -1;
862
863 device_for_each_child_node(dev, node) {
864 u32 pval;
865 unsigned int channel;
866 unsigned int pga = ADS1015_DEFAULT_PGA;
867 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
868
869 if (fwnode_property_read_u32(node, "reg", &pval)) {
870 dev_err(dev, "invalid reg on %pfw\n", node);
871 continue;
872 }
873
874 channel = pval;
875 if (channel >= ADS1015_CHANNELS) {
876 dev_err(dev, "invalid channel index %d on %pfw\n",
877 channel, node);
878 continue;
879 }
880
881 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
882 pga = pval;
883 if (pga > 6) {
884 dev_err(dev, "invalid gain on %pfw\n", node);
885 fwnode_handle_put(node);
886 return -EINVAL;
887 }
888 }
889
890 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
891 data_rate = pval;
892 if (data_rate > 7) {
893 dev_err(dev, "invalid data_rate on %pfw\n", node);
894 fwnode_handle_put(node);
895 return -EINVAL;
896 }
897 }
898
899 data->channel_data[channel].pga = pga;
900 data->channel_data[channel].data_rate = data_rate;
901
902 i++;
903 }
904
905 return i < 0 ? -EINVAL : 0;
906 }
907
908 static void ads1015_get_channels_config(struct i2c_client *client)
909 {
910 unsigned int k;
911
912 struct iio_dev *indio_dev = i2c_get_clientdata(client);
913 struct ads1015_data *data = iio_priv(indio_dev);
914
915 if (!ads1015_client_get_channels_config(client))
916 return;
917
918 /* fallback on default configuration */
919 for (k = 0; k < ADS1015_CHANNELS; ++k) {
920 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
921 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
922 }
923 }
924
925 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
926 {
927 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
928 ADS1015_CFG_MOD_MASK,
929 mode << ADS1015_CFG_MOD_SHIFT);
930 }
931
932 static int ads1015_probe(struct i2c_client *client,
933 const struct i2c_device_id *id)
934 {
935 struct iio_dev *indio_dev;
936 struct ads1015_data *data;
937 int ret;
938 enum chip_ids chip;
939 int i;
940
941 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
942 if (!indio_dev)
943 return -ENOMEM;
944
945 data = iio_priv(indio_dev);
946 i2c_set_clientdata(client, indio_dev);
947
948 mutex_init(&data->lock);
949
950 indio_dev->name = ADS1015_DRV_NAME;
951 indio_dev->modes = INDIO_DIRECT_MODE;
952
953 chip = (enum chip_ids)device_get_match_data(&client->dev);
954 if (chip == ADSXXXX)
955 chip = id->driver_data;
956 switch (chip) {
957 case ADS1015:
958 indio_dev->channels = ads1015_channels;
959 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
960 indio_dev->info = &ads1015_info;
961 data->data_rate = (unsigned int *) &ads1015_data_rate;
962 break;
963 case ADS1115:
964 indio_dev->channels = ads1115_channels;
965 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
966 indio_dev->info = &ads1115_info;
967 data->data_rate = (unsigned int *) &ads1115_data_rate;
968 break;
969 default:
970 dev_err(&client->dev, "Unknown chip %d\n", chip);
971 return -EINVAL;
972 }
973
974 data->event_channel = ADS1015_CHANNELS;
975 /*
976 * Set default lower and upper threshold to min and max value
977 * respectively.
978 */
979 for (i = 0; i < ADS1015_CHANNELS; i++) {
980 int realbits = indio_dev->channels[i].scan_type.realbits;
981
982 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
983 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
984 }
985
986 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
987 ads1015_get_channels_config(client);
988
989 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
990 if (IS_ERR(data->regmap)) {
991 dev_err(&client->dev, "Failed to allocate register map\n");
992 return PTR_ERR(data->regmap);
993 }
994
995 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
996 ads1015_trigger_handler,
997 &ads1015_buffer_setup_ops);
998 if (ret < 0) {
999 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1000 return ret;
1001 }
1002
1003 if (client->irq) {
1004 unsigned long irq_trig =
1005 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1006 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1007 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1008 unsigned int cfg_comp =
1009 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1010 1 << ADS1015_CFG_COMP_LAT_SHIFT;
1011
1012 switch (irq_trig) {
1013 case IRQF_TRIGGER_LOW:
1014 cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1015 ADS1015_CFG_COMP_POL_SHIFT;
1016 break;
1017 case IRQF_TRIGGER_HIGH:
1018 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1019 ADS1015_CFG_COMP_POL_SHIFT;
1020 break;
1021 default:
1022 return -EINVAL;
1023 }
1024
1025 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1026 cfg_comp_mask, cfg_comp);
1027 if (ret)
1028 return ret;
1029
1030 ret = devm_request_threaded_irq(&client->dev, client->irq,
1031 NULL, ads1015_event_handler,
1032 irq_trig | IRQF_ONESHOT,
1033 client->name, indio_dev);
1034 if (ret)
1035 return ret;
1036 }
1037
1038 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1039 if (ret)
1040 return ret;
1041
1042 data->conv_invalid = true;
1043
1044 ret = pm_runtime_set_active(&client->dev);
1045 if (ret)
1046 return ret;
1047 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1048 pm_runtime_use_autosuspend(&client->dev);
1049 pm_runtime_enable(&client->dev);
1050
1051 ret = iio_device_register(indio_dev);
1052 if (ret < 0) {
1053 dev_err(&client->dev, "Failed to register IIO device\n");
1054 return ret;
1055 }
1056
1057 return 0;
1058 }
1059
1060 static int ads1015_remove(struct i2c_client *client)
1061 {
1062 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1063 struct ads1015_data *data = iio_priv(indio_dev);
1064
1065 iio_device_unregister(indio_dev);
1066
1067 pm_runtime_disable(&client->dev);
1068 pm_runtime_set_suspended(&client->dev);
1069 pm_runtime_put_noidle(&client->dev);
1070
1071 /* power down single shot mode */
1072 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1073 }
1074
1075 #ifdef CONFIG_PM
1076 static int ads1015_runtime_suspend(struct device *dev)
1077 {
1078 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1079 struct ads1015_data *data = iio_priv(indio_dev);
1080
1081 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1082 }
1083
1084 static int ads1015_runtime_resume(struct device *dev)
1085 {
1086 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1087 struct ads1015_data *data = iio_priv(indio_dev);
1088 int ret;
1089
1090 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1091 if (!ret)
1092 data->conv_invalid = true;
1093
1094 return ret;
1095 }
1096 #endif
1097
1098 static const struct dev_pm_ops ads1015_pm_ops = {
1099 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1100 ads1015_runtime_resume, NULL)
1101 };
1102
1103 static const struct i2c_device_id ads1015_id[] = {
1104 {"ads1015", ADS1015},
1105 {"ads1115", ADS1115},
1106 {}
1107 };
1108 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1109
1110 static const struct of_device_id ads1015_of_match[] = {
1111 {
1112 .compatible = "ti,ads1015",
1113 .data = (void *)ADS1015
1114 },
1115 {
1116 .compatible = "ti,ads1115",
1117 .data = (void *)ADS1115
1118 },
1119 {}
1120 };
1121 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1122
1123 static struct i2c_driver ads1015_driver = {
1124 .driver = {
1125 .name = ADS1015_DRV_NAME,
1126 .of_match_table = ads1015_of_match,
1127 .pm = &ads1015_pm_ops,
1128 },
1129 .probe = ads1015_probe,
1130 .remove = ads1015_remove,
1131 .id_table = ads1015_id,
1132 };
1133
1134 module_i2c_driver(ads1015_driver);
1135
1136 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1137 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1138 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support