WIP FPC-III support
[linux/fpc-iii.git] / drivers / infiniband / hw / efa / efa_admin_defs.h
blob29d53ed63b3ed59823e93722605fc689e137509f
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2 /*
3 * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
6 #ifndef _EFA_ADMIN_H_
7 #define _EFA_ADMIN_H_
9 enum efa_admin_aq_completion_status {
10 EFA_ADMIN_SUCCESS = 0,
11 EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
12 EFA_ADMIN_BAD_OPCODE = 2,
13 EFA_ADMIN_UNSUPPORTED_OPCODE = 3,
14 EFA_ADMIN_MALFORMED_REQUEST = 4,
15 /* Additional status is provided in ACQ entry extended_status */
16 EFA_ADMIN_ILLEGAL_PARAMETER = 5,
17 EFA_ADMIN_UNKNOWN_ERROR = 6,
18 EFA_ADMIN_RESOURCE_BUSY = 7,
21 struct efa_admin_aq_common_desc {
23 * 11:0 : command_id
24 * 15:12 : reserved12
26 u16 command_id;
28 /* as appears in efa_admin_aq_opcode */
29 u8 opcode;
32 * 0 : phase
33 * 1 : ctrl_data - control buffer address valid
34 * 2 : ctrl_data_indirect - control buffer address
35 * points to list of pages with addresses of control
36 * buffers
37 * 7:3 : reserved3
39 u8 flags;
43 * used in efa_admin_aq_entry. Can point directly to control data, or to a
44 * page list chunk. Used also at the end of indirect mode page list chunks,
45 * for chaining.
47 struct efa_admin_ctrl_buff_info {
48 u32 length;
50 struct efa_common_mem_addr address;
53 struct efa_admin_aq_entry {
54 struct efa_admin_aq_common_desc aq_common_descriptor;
56 union {
57 u32 inline_data_w1[3];
59 struct efa_admin_ctrl_buff_info control_buffer;
60 } u;
62 u32 inline_data_w4[12];
65 struct efa_admin_acq_common_desc {
67 * command identifier to associate it with the aq descriptor
68 * 11:0 : command_id
69 * 15:12 : reserved12
71 u16 command;
73 u8 status;
76 * 0 : phase
77 * 7:1 : reserved1
79 u8 flags;
81 u16 extended_status;
84 * indicates to the driver which AQ entry has been consumed by the
85 * device and could be reused
87 u16 sq_head_indx;
90 struct efa_admin_acq_entry {
91 struct efa_admin_acq_common_desc acq_common_descriptor;
93 u32 response_specific_data[14];
96 struct efa_admin_aenq_common_desc {
97 u16 group;
99 u16 syndrom;
102 * 0 : phase
103 * 7:1 : reserved - MBZ
105 u8 flags;
107 u8 reserved1[3];
109 u32 timestamp_low;
111 u32 timestamp_high;
114 struct efa_admin_aenq_entry {
115 struct efa_admin_aenq_common_desc aenq_common_desc;
117 /* command specific inline data */
118 u32 inline_data_w4[12];
121 /* aq_common_desc */
122 #define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
123 #define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
124 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
125 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
127 /* acq_common_desc */
128 #define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
129 #define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
131 /* aenq_common_desc */
132 #define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
134 #endif /* _EFA_ADMIN_H_ */