| blob | c87b94ea2939743cd4dad351b0c787699b4b7f89 |
1 /*
2 * Copyright(c) 2015 - 2020 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
48 /*
49 * This file contains all of the code that is specific to the HFI chip
50 */
52 #include <linux/pci.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
75 /*
76 * Default time to aggregate two 10K packets from the idle state
77 * (timer not running). The timer starts at the end of the first packet,
78 * so only the time for one 10K packet and header plus a bit extra is needed.
79 * 10 * 1024 + 64 header byte = 10304 byte
80 * 10304 byte / 12.5 GB/s = 824.32ns
81 */
94 uint loopback;
98 /* Other driver tunables */
108 u16 unused0;
109 u32 unused1;
110 };
112 /* str must be a string constant */
113 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
114 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
116 /* Send Error Consequences */
117 #define SEC_WRITE_DROPPED 0x1
118 #define SEC_PACKET_DROPPED 0x2
122 #define DEFAULT_KRCVQS 2
123 #define MIN_KERNEL_KCTXTS 2
124 #define FIRST_KERNEL_KCTXT 1
126 /*
127 * RSM instance allocation
128 * 0 - User Fecn Handling
129 * 1 - Vnic
130 * 2 - AIP
131 * 3 - Verbs
132 */
133 #define RSM_INS_FECN 0
134 #define RSM_INS_VNIC 1
135 #define RSM_INS_AIP 2
136 #define RSM_INS_VERBS 3
138 /* Bit offset into the GUID which carries HFI id information */
139 #define GUID_HFI_INDEX_SHIFT 39
141 /* extract the emulation revision */
142 #define emulator_rev(dd) ((dd)->irev >> 8)
143 /* parallel and serial emulation versions are 3 and 4 respectively */
144 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
145 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
147 /* RSM fields for Verbs */
148 /* packet type */
149 #define IB_PACKET_TYPE 2ull
150 #define QW_SHIFT 6ull
151 /* QPN[7..1] */
152 #define QPN_WIDTH 7ull
154 /* LRH.BTH: QW 0, OFFSET 48 - for match */
155 #define LRH_BTH_QW 0ull
156 #define LRH_BTH_BIT_OFFSET 48ull
157 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
158 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
159 #define LRH_BTH_SELECT
160 #define LRH_BTH_MASK 3ull
161 #define LRH_BTH_VALUE 2ull
163 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
164 #define LRH_SC_QW 0ull
165 #define LRH_SC_BIT_OFFSET 56ull
166 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
167 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
168 #define LRH_SC_MASK 128ull
169 #define LRH_SC_VALUE 0ull
171 /* SC[n..0] QW 0, OFFSET 60 - for select */
172 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
174 /* QPN[m+n:1] QW 1, OFFSET 1 */
175 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
177 /* RSM fields for AIP */
178 /* LRH.BTH above is reused for this rule */
180 /* BTH.DESTQP: QW 1, OFFSET 16 for match */
181 #define BTH_DESTQP_QW 1ull
182 #define BTH_DESTQP_BIT_OFFSET 16ull
183 #define BTH_DESTQP_OFFSET(off) ((BTH_DESTQP_QW << QW_SHIFT) | (off))
184 #define BTH_DESTQP_MATCH_OFFSET BTH_DESTQP_OFFSET(BTH_DESTQP_BIT_OFFSET)
185 #define BTH_DESTQP_MASK 0xFFull
186 #define BTH_DESTQP_VALUE 0x81ull
188 /* DETH.SQPN: QW 1 Offset 56 for select */
189 /* We use 8 most significant Soure QPN bits as entropy fpr AIP */
190 #define DETH_AIP_SQPN_QW 3ull
191 #define DETH_AIP_SQPN_BIT_OFFSET 56ull
192 #define DETH_AIP_SQPN_OFFSET(off) ((DETH_AIP_SQPN_QW << QW_SHIFT) | (off))
193 #define DETH_AIP_SQPN_SELECT_OFFSET \
194 DETH_AIP_SQPN_OFFSET(DETH_AIP_SQPN_BIT_OFFSET)
196 /* RSM fields for Vnic */
197 /* L2_TYPE: QW 0, OFFSET 61 - for match */
198 #define L2_TYPE_QW 0ull
199 #define L2_TYPE_BIT_OFFSET 61ull
200 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
201 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
202 #define L2_TYPE_MASK 3ull
203 #define L2_16B_VALUE 2ull
205 /* L4_TYPE QW 1, OFFSET 0 - for match */
206 #define L4_TYPE_QW 1ull
207 #define L4_TYPE_BIT_OFFSET 0ull
208 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
209 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
210 #define L4_16B_TYPE_MASK 0xFFull
211 #define L4_16B_ETH_VALUE 0x78ull
213 /* 16B VESWID - for select */
214 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
215 /* 16B ENTROPY - for select */
216 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
218 /* defines to build power on SC2VL table */
219 #define SC2VL_VAL( \
220 num, \
221 sc0, sc0val, \
222 sc1, sc1val, \
223 sc2, sc2val, \
224 sc3, sc3val, \
225 sc4, sc4val, \
226 sc5, sc5val, \
227 sc6, sc6val, \
228 sc7, sc7val) \
229 ( \
230 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
231 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
232 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
233 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
234 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
235 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
236 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
237 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
238 )
240 #define DC_SC_VL_VAL( \
241 range, \
242 e0, e0val, \
243 e1, e1val, \
244 e2, e2val, \
245 e3, e3val, \
246 e4, e4val, \
247 e5, e5val, \
248 e6, e6val, \
249 e7, e7val, \
250 e8, e8val, \
251 e9, e9val, \
252 e10, e10val, \
253 e11, e11val, \
254 e12, e12val, \
255 e13, e13val, \
256 e14, e14val, \
257 e15, e15val) \
258 ( \
259 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
260 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
261 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
262 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
263 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
264 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
265 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
266 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
267 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
268 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
269 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
270 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
271 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
272 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
273 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
274 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
275 )
277 /* all CceStatus sub-block freeze bits */
278 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
279 | CCE_STATUS_RXE_FROZE_SMASK \
280 | CCE_STATUS_TXE_FROZE_SMASK \
281 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
282 /* all CceStatus sub-block TXE pause bits */
283 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
284 | CCE_STATUS_TXE_PAUSED_SMASK \
285 | CCE_STATUS_SDMA_PAUSED_SMASK)
286 /* all CceStatus sub-block RXE pause bits */
287 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
289 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
290 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
292 /*
293 * CCE Error flags.
294 */
297 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
299 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
301 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
303 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
305 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
307 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
309 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
311 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
313 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
315 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
317 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
319 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
321 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
323 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
325 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
327 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
329 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
331 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
333 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
335 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
337 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
339 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
341 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
343 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
345 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
347 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
349 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
351 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
353 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
355 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
357 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
359 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
361 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
363 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
365 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
367 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
369 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
371 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
373 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
375 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
377 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
378 /*41-63 reserved*/
379 };
381 /*
382 * Misc Error flags
383 */
384 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
399 };
401 /*
402 * TXE PIO Error flags and consequences
403 */
406 SEC_WRITE_DROPPED,
407 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
409 SEC_SPC_FREEZE,
410 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
412 SEC_SPC_FREEZE,
413 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
415 SEC_SPC_FREEZE,
416 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
418 SEC_SPC_FREEZE,
419 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
421 SEC_SPC_FREEZE,
422 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
424 SEC_SPC_FREEZE,
425 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
427 SEC_SPC_FREEZE,
428 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
430 SEC_SPC_FREEZE,
431 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
433 SEC_SPC_FREEZE,
434 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
436 SEC_SPC_FREEZE,
437 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
439 SEC_SPC_FREEZE,
440 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
442 SEC_SPC_FREEZE,
443 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
446 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
449 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
451 SEC_SPC_FREEZE,
452 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
454 SEC_SPC_FREEZE,
455 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
458 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
460 SEC_SPC_FREEZE,
461 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
463 SEC_SPC_FREEZE,
464 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
467 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
469 SEC_SPC_FREEZE,
470 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
472 SEC_SPC_FREEZE,
473 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
476 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
479 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
481 SEC_SPC_FREEZE,
482 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
484 SEC_SPC_FREEZE,
485 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
487 SEC_SPC_FREEZE,
488 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
490 SEC_SPC_FREEZE,
491 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
493 SEC_SPC_FREEZE,
494 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
495 /*30-31 reserved*/
497 SEC_SPC_FREEZE,
498 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
500 SEC_SPC_FREEZE,
501 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
503 SEC_SPC_FREEZE,
504 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
506 SEC_SPC_FREEZE,
507 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
508 /*36-63 reserved*/
509 };
511 /* TXE PIO errors that cause an SPC freeze */
512 #define ALL_PIO_FREEZE_ERR \
513 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
524 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
525 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
526 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
527 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
528 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
529 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
530 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
531 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
532 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
533 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
534 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
535 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
536 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
537 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
538 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
539 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
540 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
541 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
543 /*
544 * TXE SDMA Error flags
545 */
548 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
550 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
552 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
554 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
555 /*04-63 reserved*/
556 };
558 /* TXE SDMA errors that cause an SPC freeze */
559 #define ALL_SDMA_FREEZE_ERR \
560 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
561 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
562 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
564 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
565 #define PORT_DISCARD_EGRESS_ERRS \
566 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
567 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
568 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
570 /*
571 * TXE Egress Error flags
572 */
573 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
577 /* 2 reserved */
582 /* 6 reserved */
587 /* 9-10 reserved */
669 };
671 /*
672 * TXE Egress Error Info flags
673 */
674 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
698 };
700 /* TXE Egress errors that cause an SPC freeze */
701 #define ALL_TXE_EGRESS_FREEZE_ERR \
702 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
703 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
704 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
705 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
706 | SEES(TX_LAUNCH_CSR_PARITY) \
707 | SEES(TX_SBRD_CTL_CSR_PARITY) \
708 | SEES(TX_CONFIG_PARITY) \
709 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
710 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
711 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
712 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
713 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
714 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
715 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
716 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
717 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
718 | SEES(TX_CREDIT_RETURN_PARITY))
720 /*
721 * TXE Send error flags
722 */
723 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
728 };
730 /*
731 * TXE Send Context Error flags and consequences
732 */
736 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
739 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
742 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
745 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
748 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
749 /* 5-63 reserved*/
750 };
752 /*
753 * RXE Receive Error flags
754 */
755 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
833 };
835 /* RXE errors that will trigger an SPC freeze */
836 #define ALL_RXE_FREEZE_ERR \
837 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
863 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
864 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
865 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
866 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
867 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
868 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
869 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
870 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
871 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
872 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
873 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
874 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
875 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
876 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
877 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
878 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
879 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
880 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
882 #define RXE_FREEZE_ABORT_MASK \
883 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
884 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
885 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
887 /*
888 * DCC Error Flags
889 */
890 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
938 };
940 /*
941 * LCB error flags
942 */
943 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
981 };
983 /*
984 * DC8051 Error Flags
985 */
986 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
999 };
1001 /*
1002 * DC8051 Information Error flags
1003 *
1004 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
1005 */
1011 FAILED_SERDES_INTERNAL_LOOPBACK),
1022 EXTERNAL_DEVICE_REQ_TIMEOUT),
1023 };
1025 /*
1026 * DC8051 Information Host Information flags
1027 *
1028 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1029 */
1041 };
1078 u32 state);
1107 /*
1108 * Error interrupt table entry. This is used as input to the interrupt
1109 * "clear down" routine used for all second tier error interrupt register.
1110 * Second tier interrupt registers have a single bit representing them
1111 * in the top-level CceIntStatus.
1112 */
1119 };
1121 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START)
1122 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START)
1123 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START)
1125 /*
1126 * Helpers for building HFI and DC error interrupt table entries. Different
1127 * helpers are needed because of inconsistent register names.
1128 */
1129 #define EE(reg, handler, desc) \
1130 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1131 handler, desc }
1132 #define DC_EE1(reg, handler, desc) \
1133 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1134 #define DC_EE2(reg, handler, desc) \
1135 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1137 /*
1138 * Table of the "misc" grouping of error interrupts. Each entry refers to
1139 * another register containing more information.
1140 */
1150 /* the rest are reserved */
1151 };
1153 /*
1154 * Index into the Various section of the interrupt sources
1155 * corresponding to the Critical Temperature interrupt.
1156 */
1157 #define TCRIT_INT_SOURCE 4
1159 /*
1160 * SDMA error interrupt entry - refers to another register containing more
1161 * information.
1162 */
1172 /* rest are reserved */
1173 };
1175 /*
1176 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1177 * register can not be derived from the MTU value because 10K is not
1178 * a power of 2. Therefore, we need a constant. Everything else can
1179 * be calculated.
1180 */
1181 #define DCC_CFG_PORT_MTU_CAP_10240 7
1183 /*
1184 * Table of the DC grouping of error interrupts. Each entry refers to
1185 * another register containing more information.
1186 */
1192 /* the rest are reserved */
1193 };
1196 /*
1197 * counter name
1198 */
1201 /*
1202 * csr to read for name (if applicable)
1203 */
1204 u64 csr;
1206 /*
1207 * offset into dd or ppd to store the counter's value
1208 */
1211 /*
1212 * flags
1213 */
1214 u8 flags;
1216 /*
1217 * accessor for stat element, context either dd or ppd
1218 */
1221 };
1223 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1224 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1226 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1227 { \
1228 name, \
1229 csr, \
1230 offset, \
1231 flags, \
1232 accessor \
1233 }
1235 /* 32bit RXE */
1236 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1237 CNTR_ELEM(#name, \
1238 (counter * 8 + RCV_COUNTER_ARRAY32), \
1239 0, flags | CNTR_32BIT, \
1240 port_access_u32_csr)
1242 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1243 CNTR_ELEM(#name, \
1244 (counter * 8 + RCV_COUNTER_ARRAY32), \
1245 0, flags | CNTR_32BIT, \
1246 dev_access_u32_csr)
1248 /* 64bit RXE */
1249 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1250 CNTR_ELEM(#name, \
1251 (counter * 8 + RCV_COUNTER_ARRAY64), \
1252 0, flags, \
1253 port_access_u64_csr)
1255 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1256 CNTR_ELEM(#name, \
1257 (counter * 8 + RCV_COUNTER_ARRAY64), \
1258 0, flags, \
1259 dev_access_u64_csr)
1261 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1262 #define OVR_ELM(ctx) \
1264 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1265 0, CNTR_NORMAL, port_access_u64_csr)
1267 /* 32bit TXE */
1268 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1269 CNTR_ELEM(#name, \
1270 (counter * 8 + SEND_COUNTER_ARRAY32), \
1271 0, flags | CNTR_32BIT, \
1272 port_access_u32_csr)
1274 /* 64bit TXE */
1275 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1276 CNTR_ELEM(#name, \
1277 (counter * 8 + SEND_COUNTER_ARRAY64), \
1278 0, flags, \
1279 port_access_u64_csr)
1281 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1282 CNTR_ELEM(#name,\
1283 counter * 8 + SEND_COUNTER_ARRAY64, \
1284 0, \
1285 flags, \
1286 dev_access_u64_csr)
1288 /* CCE */
1289 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1290 CNTR_ELEM(#name, \
1291 (counter * 8 + CCE_COUNTER_ARRAY32), \
1292 0, flags | CNTR_32BIT, \
1293 dev_access_u32_csr)
1295 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1296 CNTR_ELEM(#name, \
1297 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1298 0, flags | CNTR_32BIT, \
1299 dev_access_u32_csr)
1301 /* DC */
1302 #define DC_PERF_CNTR(name, counter, flags) \
1303 CNTR_ELEM(#name, \
1304 counter, \
1305 0, \
1306 flags, \
1307 dev_access_u64_csr)
1309 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1310 CNTR_ELEM(#name, \
1311 counter, \
1312 0, \
1313 flags, \
1314 dc_access_lcb_cntr)
1316 /* ibp counters */
1317 #define SW_IBP_CNTR(name, cntr) \
1318 CNTR_ELEM(#name, \
1319 0, \
1320 0, \
1321 CNTR_SYNTH, \
1322 access_ibp_##cntr)
1324 /**
1325 * hfi_addr_from_offset - return addr for readq/writeq
1326 * @dd - the dd device
1327 * @offset - the offset of the CSR within bar0
1328 *
1329 * This routine selects the appropriate base address
1330 * based on the indicated offset.
1331 */
1334 u32 offset)
1335 {
1339 }
1341 /**
1342 * read_csr - read CSR at the indicated offset
1343 * @dd - the dd device
1344 * @offset - the offset of the CSR within bar0
1345 *
1346 * Return: the value read or all FF's if there
1347 * is no mapping
1348 */
1350 {
1354 }
1356 /**
1357 * write_csr - write CSR at the indicated offset
1358 * @dd - the dd device
1359 * @offset - the offset of the CSR within bar0
1360 * @value - value to write
1361 */
1363 {
1367 /* avoid write to RcvArray */
1371 }
1372 }
1374 /**
1375 * get_csr_addr - return te iomem address for offset
1376 * @dd - the dd device
1377 * @offset - the offset of the CSR within bar0
1378 *
1379 * Return: The iomem address to use in subsequent
1380 * writeq/readq operations.
1381 */
1384 u32 offset)
1385 {
1389 }
1393 {
1394 u64 ret;
1404 }
1408 }
1410 /* Dev Access */
1413 {
1424 }
1426 }
1430 {
1436 }
1440 {
1446 }
1450 {
1456 }
1460 u64 data)
1461 {
1467 }
1471 {
1484 }
1488 }
1492 {
1507 }
1511 }
1513 /* Port Access */
1516 {
1522 }
1526 {
1528 u64 val;
1538 }
1541 }
1543 /* Software defined */
1545 u64 data)
1546 {
1547 u64 ret;
1557 }
1562 }
1566 {
1572 }
1576 {
1582 }
1586 u64 data)
1587 {
1593 }
1597 {
1606 else
1610 }
1614 u64 data)
1615 {
1623 }
1627 {
1635 }
1638 {
1645 }
1650 {
1659 /* A write can only zero the counter */
1662 else
1667 }
1670 }
1674 {
1679 }
1683 {
1688 }
1692 {
1696 }
1700 {
1704 }
1708 {
1712 }
1716 {
1720 }
1724 {
1728 }
1732 {
1737 }
1739 /* Software counters for the error status bits within MISC_ERR_STATUS */
1742 u64 data)
1743 {
1747 }
1751 u64 data)
1752 {
1756 }
1760 u64 data)
1761 {
1765 }
1770 {
1774 }
1778 u64 data)
1779 {
1783 }
1788 {
1792 }
1797 {
1801 }
1805 u64 data)
1806 {
1810 }
1814 u64 data)
1815 {
1819 }
1824 {
1828 }
1833 {
1837 }
1842 {
1846 }
1850 u64 data)
1851 {
1855 }
1857 /*
1858 * Software counter for the aggregate of
1859 * individual CceErrStatus counters
1860 */
1864 {
1868 }
1870 /*
1871 * Software counters corresponding to each of the
1872 * error status bits within CceErrStatus
1873 */
1876 u64 data)
1877 {
1881 }
1885 u64 data)
1886 {
1890 }
1894 u64 data)
1895 {
1899 }
1903 u64 data)
1904 {
1908 }
1912 u64 data)
1913 {
1917 }
1922 {
1926 }
1931 {
1935 }
1940 {
1944 }
1948 u64 data)
1949 {
1953 }
1957 {
1961 }
1965 u64 data)
1966 {
1970 }
1974 u64 data)
1975 {
1979 }
1984 {
1988 }
1993 {
1997 }
2001 u64 data)
2002 {
2006 }
2010 u64 data)
2011 {
2015 }
2019 u64 data)
2020 {
2024 }
2028 u64 data)
2029 {
2033 }
2038 {
2042 }
2046 u64 data)
2047 {
2051 }
2056 {
2060 }
2065 {
2069 }
2073 u64 data)
2074 {
2078 }
2082 u64 data)
2083 {
2087 }
2091 u64 data)
2092 {
2096 }
2100 u64 data)
2101 {
2105 }
2110 {
2114 }
2118 u64 data)
2119 {
2123 }
2128 {
2132 }
2137 {
2141 }
2146 {
2150 }
2155 {
2159 }
2164 {
2168 }
2173 {
2177 }
2182 {
2186 }
2190 u64 data)
2191 {
2195 }
2199 u64 data)
2200 {
2204 }
2209 {
2213 }
2218 {
2222 }
2227 {
2231 }
2235 u64 data)
2236 {
2240 }
2242 /*
2243 * Software counters corresponding to each of the
2244 * error status bits within RcvErrStatus
2245 */
2248 u64 data)
2249 {
2253 }
2258 {
2262 }
2266 u64 data)
2267 {
2271 }
2275 u64 data)
2276 {
2280 }
2285 {
2289 }
2294 {
2298 }
2302 u64 data)
2303 {
2307 }
2311 u64 data)
2312 {
2316 }
2320 u64 data)
2321 {
2325 }
2330 {
2334 }
2339 {
2343 }
2348 {
2352 }
2357 {
2361 }
2366 {
2370 }
2375 {
2379 }
2384 {
2388 }
2393 {
2397 }
2401 u64 data)
2402 {
2406 }
2411 {
2415 }
2420 {
2424 }
2429 {
2433 }
2438 {
2442 }
2447 {
2451 }
2456 {
2460 }
2465 {
2469 }
2474 {
2478 }
2483 {
2487 }
2492 {
2496 }
2501 {
2505 }
2510 {
2514 }
2519 {
2523 }
2527 u64 data)
2528 {
2532 }
2536 u64 data)
2537 {
2541 }
2545 u64 data)
2546 {
2550 }
2554 u64 data)
2555 {
2559 }
2564 {
2568 }
2573 {
2577 }
2582 {
2586 }
2591 {
2595 }
2600 {
2604 }
2609 {
2613 }
2618 {
2622 }
2627 {
2631 }
2636 {
2640 }
2645 {
2649 }
2654 {
2658 }
2663 {
2667 }
2672 {
2676 }
2681 {
2685 }
2690 {
2694 }
2699 {
2703 }
2707 u64 data)
2708 {
2712 }
2716 u64 data)
2717 {
2721 }
2725 u64 data)
2726 {
2730 }
2734 u64 data)
2735 {
2739 }
2743 u64 data)
2744 {
2748 }
2753 {
2757 }
2762 {
2766 }
2770 u64 data)
2771 {
2775 }
2779 u64 data)
2780 {
2784 }
2788 u64 data)
2789 {
2793 }
2797 u64 data)
2798 {
2802 }
2806 u64 data)
2807 {
2811 }
2815 u64 data)
2816 {
2820 }
2822 /*
2823 * Software counters corresponding to each of the
2824 * error status bits within SendPioErrStatus
2825 */
2829 {
2833 }
2838 {
2842 }
2847 {
2851 }
2856 {
2860 }
2864 u64 data)
2865 {
2869 }
2873 u64 data)
2874 {
2878 }
2882 u64 data)
2883 {
2887 }
2892 {
2896 }
2900 u64 data)
2901 {
2905 }
2909 u64 data)
2910 {
2914 }
2919 {
2923 }
2928 {
2932 }
2937 {
2941 }
2945 u64 data)
2946 {
2950 }
2955 {
2959 }
2964 {
2968 }
2973 {
2977 }
2982 {
2986 }
2990 u64 data)
2991 {
2995 }
2999 u64 data)
3000 {
3004 }
3009 {
3013 }
3018 {
3022 }
3027 {
3031 }
3036 {
3040 }
3045 {
3049 }
3054 {
3058 }
3063 {
3067 }
3072 {
3076 }
3081 {
3085 }
3089 u64 data)
3090 {
3094 }
3098 u64 data)
3099 {
3103 }
3107 u64 data)
3108 {
3112 }
3116 u64 data)
3117 {
3121 }
3125 u64 data)
3126 {
3130 }
3135 {
3139 }
3143 u64 data)
3144 {
3148 }
3150 /*
3151 * Software counters corresponding to each of the
3152 * error status bits within SendDmaErrStatus
3153 */
3157 {
3161 }
3166 {
3170 }
3174 u64 data)
3175 {
3179 }
3183 u64 data)
3184 {
3188 }
3190 /*
3191 * Software counters corresponding to each of the
3192 * error status bits within SendEgressErrStatus
3193 */
3197 {
3201 }
3206 {
3210 }
3214 u64 data)
3215 {
3219 }
3224 {
3228 }
3233 {
3237 }
3241 u64 data)
3242 {
3246 }
3250 u64 data)
3251 {
3255 }
3259 u64 data)
3260 {
3264 }
3268 u64 data)
3269 {
3273 }
3277 u64 data)
3278 {
3282 }
3286 u64 data)
3287 {
3291 }
3295 u64 data)
3296 {
3300 }
3304 u64 data)
3305 {
3309 }
3313 u64 data)
3314 {
3318 }
3322 u64 data)
3323 {
3327 }
3331 u64 data)
3332 {
3336 }
3340 u64 data)
3341 {
3345 }
3349 u64 data)
3350 {
3354 }
3358 u64 data)
3359 {
3363 }
3368 {
3372 }
3377 {
3381 }
3385 u64 data)
3386 {
3390 }
3395 {
3399 }
3404 {
3408 }
3413 {
3417 }
3422 {
3426 }
3431 {
3435 }
3440 {
3444 }
3449 {
3453 }
3458 {
3462 }
3467 {
3471 }
3476 {
3480 }
3485 {
3489 }
3494 {
3498 }
3503 {
3507 }
3512 {
3516 }
3521 {
3525 }
3530 {
3534 }
3539 {
3543 }
3548 {
3552 }
3557 {
3561 }
3566 {
3570 }
3575 {
3579 }
3584 {
3588 }
3593 {
3597 }
3602 {
3606 }
3611 {
3615 }
3620 {
3624 }
3628 u64 data)
3629 {
3633 }
3638 {
3642 }
3646 u64 data)
3647 {
3651 }
3655 u64 data)
3656 {
3660 }
3665 {
3669 }
3673 u64 data)
3674 {
3678 }
3682 u64 data)
3683 {
3687 }
3692 {
3696 }
3701 {
3705 }
3709 u64 data)
3710 {
3714 }
3719 {
3723 }
3727 u64 data)
3728 {
3732 }
3737 {
3741 }
3745 u64 data)
3746 {
3750 }
3755 {
3759 }
3764 {
3768 }
3770 /*
3771 * Software counters corresponding to each of the
3772 * error status bits within SendErrStatus
3773 */
3777 {
3781 }
3786 {
3790 }
3794 u64 data)
3795 {
3799 }
3801 /*
3802 * Software counters corresponding to each of the
3803 * error status bits within SendCtxtErrStatus
3804 */
3808 {
3812 }
3816 u64 data)
3817 {
3821 }
3826 {
3830 }
3835 {
3839 }
3843 u64 data)
3844 {
3848 }
3850 /*
3851 * Software counters corresponding to each of the
3852 * error status bits within SendDmaEngErrStatus
3853 */
3857 {
3861 }
3866 {
3870 }
3875 {
3879 }
3883 u64 data)
3884 {
3888 }
3892 u64 data)
3893 {
3897 }
3902 {
3906 }
3911 {
3915 }
3920 {
3924 }
3928 u64 data)
3929 {
3933 }
3937 u64 data)
3938 {
3942 }
3946 u64 data)
3947 {
3951 }
3955 u64 data)
3956 {
3960 }
3964 u64 data)
3965 {
3969 }
3973 u64 data)
3974 {
3978 }
3982 u64 data)
3983 {
3987 }
3992 {
3996 }
4001 {
4005 }
4009 {
4013 }
4017 u64 data)
4018 {
4022 }
4026 u64 data)
4027 {
4031 }
4036 {
4040 }
4044 u64 data)
4045 {
4049 }
4053 u64 data)
4054 {
4058 }
4062 u64 data)
4063 {
4067 }
4071 u64 data)
4072 {
4087 }
4089 }
4091 #define def_access_sw_cpu(cntr) \
4092 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4093 void *context, int vl, int mode, u64 data) \
4094 { \
4095 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4096 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4097 ppd->ibport_data.rvp.cntr, vl, \
4098 mode, data); \
4099 }
4105 #define def_access_ibp_counter(cntr) \
4106 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4107 void *context, int vl, int mode, u64 data) \
4108 { \
4109 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4110 \
4111 if (vl != CNTR_INVALID_VL) \
4112 return 0; \
4113 \
4114 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
4115 mode, data); \
4116 }
4139 CNTR_NORMAL),
4141 CNTR_NORMAL),
4143 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4144 CNTR_NORMAL),
4146 CNTR_NORMAL),
4152 CNTR_NORMAL),
4154 CNTR_NORMAL),
4156 CNTR_NORMAL),
4158 CNTR_NORMAL),
4160 CNTR_NORMAL),
4162 CNTR_NORMAL),
4168 CNTR_SYNTH),
4170 access_dc_rcv_err_cnt),
4172 CNTR_SYNTH),
4174 CNTR_SYNTH),
4176 CNTR_SYNTH),
4180 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4181 CNTR_SYNTH),
4185 CNTR_SYNTH),
4187 CNTR_SYNTH),
4189 CNTR_SYNTH),
4191 CNTR_SYNTH),
4193 CNTR_SYNTH),
4195 CNTR_SYNTH),
4197 CNTR_SYNTH),
4209 CNTR_SYNTH),
4213 CNTR_SYNTH),
4218 CNTR_SYNTH),
4220 CNTR_SYNTH),
4222 CNTR_SYNTH),
4224 CNTR_SYNTH),
4226 CNTR_SYNTH),
4229 CNTR_SYNTH),
4231 CNTR_SYNTH),
4233 CNTR_SYNTH),
4236 CNTR_SYNTH),
4239 CNTR_SYNTH),
4242 CNTR_SYNTH),
4245 CNTR_SYNTH),
4248 CNTR_SYNTH),
4250 CNTR_SYNTH),
4253 CNTR_SYNTH),
4258 CNTR_SYNTH),
4269 CNTR_SYNTH),
4274 CNTR_SYNTH),
4276 access_sw_cpu_intr),
4278 access_sw_cpu_rcv_limit),
4280 access_sw_ctx0_seq_drop),
4282 access_sw_vtx_wait),
4284 access_sw_pio_wait),
4286 access_sw_pio_drain),
4288 access_sw_kmem_wait),
4290 hfi1_access_sw_tid_wait),
4292 access_sw_send_schedule),
4296 dev_access_u32_csr),
4299 access_sde_int_cnt),
4302 access_sde_err_cnt),
4305 access_sde_idle_int_cnt),
4308 access_sde_progress_int_cnt),
4309 /* MISC_ERR_STATUS */
4311 CNTR_NORMAL,
4312 access_misc_pll_lock_fail_err_cnt),
4314 CNTR_NORMAL,
4315 access_misc_mbist_fail_err_cnt),
4317 CNTR_NORMAL,
4318 access_misc_invalid_eep_cmd_err_cnt),
4320 CNTR_NORMAL,
4321 access_misc_efuse_done_parity_err_cnt),
4323 CNTR_NORMAL,
4324 access_misc_efuse_write_err_cnt),
4327 access_misc_efuse_read_bad_addr_err_cnt),
4329 CNTR_NORMAL,
4330 access_misc_efuse_csr_parity_err_cnt),
4332 CNTR_NORMAL,
4333 access_misc_fw_auth_failed_err_cnt),
4335 CNTR_NORMAL,
4336 access_misc_key_mismatch_err_cnt),
4338 CNTR_NORMAL,
4339 access_misc_sbus_write_failed_err_cnt),
4341 CNTR_NORMAL,
4342 access_misc_csr_write_bad_addr_err_cnt),
4344 CNTR_NORMAL,
4345 access_misc_csr_read_bad_addr_err_cnt),
4347 CNTR_NORMAL,
4348 access_misc_csr_parity_err_cnt),
4349 /* CceErrStatus */
4351 CNTR_NORMAL,
4352 access_sw_cce_err_status_aggregated_cnt),
4354 CNTR_NORMAL,
4355 access_cce_msix_csr_parity_err_cnt),
4357 CNTR_NORMAL,
4358 access_cce_int_map_unc_err_cnt),
4360 CNTR_NORMAL,
4361 access_cce_int_map_cor_err_cnt),
4363 CNTR_NORMAL,
4364 access_cce_msix_table_unc_err_cnt),
4366 CNTR_NORMAL,
4367 access_cce_msix_table_cor_err_cnt),
4370 access_cce_rxdma_conv_fifo_parity_err_cnt),
4373 access_cce_rcpl_async_fifo_parity_err_cnt),
4375 CNTR_NORMAL,
4376 access_cce_seg_write_bad_addr_err_cnt),
4378 CNTR_NORMAL,
4379 access_cce_seg_read_bad_addr_err_cnt),
4381 CNTR_NORMAL,
4382 access_la_triggered_cnt),
4384 CNTR_NORMAL,
4385 access_cce_trgt_cpl_timeout_err_cnt),
4387 CNTR_NORMAL,
4388 access_pcic_receive_parity_err_cnt),
4390 CNTR_NORMAL,
4391 access_pcic_transmit_back_parity_err_cnt),
4394 access_pcic_transmit_front_parity_err_cnt),
4396 CNTR_NORMAL,
4397 access_pcic_cpl_dat_q_unc_err_cnt),
4399 CNTR_NORMAL,
4400 access_pcic_cpl_hd_q_unc_err_cnt),
4402 CNTR_NORMAL,
4403 access_pcic_post_dat_q_unc_err_cnt),
4405 CNTR_NORMAL,
4406 access_pcic_post_hd_q_unc_err_cnt),
4408 CNTR_NORMAL,
4409 access_pcic_retry_sot_mem_unc_err_cnt),
4411 CNTR_NORMAL,
4412 access_pcic_retry_mem_unc_err),
4414 CNTR_NORMAL,
4415 access_pcic_n_post_dat_q_parity_err_cnt),
4417 CNTR_NORMAL,
4418 access_pcic_n_post_h_q_parity_err_cnt),
4420 CNTR_NORMAL,
4421 access_pcic_cpl_dat_q_cor_err_cnt),
4423 CNTR_NORMAL,
4424 access_pcic_cpl_hd_q_cor_err_cnt),
4426 CNTR_NORMAL,
4427 access_pcic_post_dat_q_cor_err_cnt),
4429 CNTR_NORMAL,
4430 access_pcic_post_hd_q_cor_err_cnt),
4432 CNTR_NORMAL,
4433 access_pcic_retry_sot_mem_cor_err_cnt),
4435 CNTR_NORMAL,
4436 access_pcic_retry_mem_cor_err_cnt),
4439 CNTR_NORMAL,
4440 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4443 CNTR_NORMAL,
4444 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4445 ),
4448 CNTR_NORMAL,
4449 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4452 CNTR_NORMAL,
4453 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4456 access_cce_cli2_async_fifo_parity_err_cnt),
4458 CNTR_NORMAL,
4459 access_cce_csr_cfg_bus_parity_err_cnt),
4462 access_cce_cli0_async_fifo_parity_err_cnt),
4464 CNTR_NORMAL,
4465 access_cce_rspd_data_parity_err_cnt),
4467 CNTR_NORMAL,
4468 access_cce_trgt_access_err_cnt),
4471 access_cce_trgt_async_fifo_parity_err_cnt),
4473 CNTR_NORMAL,
4474 access_cce_csr_write_bad_addr_err_cnt),
4476 CNTR_NORMAL,
4477 access_cce_csr_read_bad_addr_err_cnt),
4479 CNTR_NORMAL,
4480 access_ccs_csr_parity_err_cnt),
4482 /* RcvErrStatus */
4484 CNTR_NORMAL,
4485 access_rx_csr_parity_err_cnt),
4487 CNTR_NORMAL,
4488 access_rx_csr_write_bad_addr_err_cnt),
4490 CNTR_NORMAL,
4491 access_rx_csr_read_bad_addr_err_cnt),
4493 CNTR_NORMAL,
4494 access_rx_dma_csr_unc_err_cnt),
4496 CNTR_NORMAL,
4497 access_rx_dma_dq_fsm_encoding_err_cnt),
4499 CNTR_NORMAL,
4500 access_rx_dma_eq_fsm_encoding_err_cnt),
4502 CNTR_NORMAL,
4503 access_rx_dma_csr_parity_err_cnt),
4505 CNTR_NORMAL,
4506 access_rx_rbuf_data_cor_err_cnt),
4508 CNTR_NORMAL,
4509 access_rx_rbuf_data_unc_err_cnt),
4511 CNTR_NORMAL,
4512 access_rx_dma_data_fifo_rd_cor_err_cnt),
4514 CNTR_NORMAL,
4515 access_rx_dma_data_fifo_rd_unc_err_cnt),
4517 CNTR_NORMAL,
4518 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4520 CNTR_NORMAL,
4521 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4523 CNTR_NORMAL,
4524 access_rx_rbuf_desc_part2_cor_err_cnt),
4526 CNTR_NORMAL,
4527 access_rx_rbuf_desc_part2_unc_err_cnt),
4529 CNTR_NORMAL,
4530 access_rx_rbuf_desc_part1_cor_err_cnt),
4532 CNTR_NORMAL,
4533 access_rx_rbuf_desc_part1_unc_err_cnt),
4535 CNTR_NORMAL,
4536 access_rx_hq_intr_fsm_err_cnt),
4538 CNTR_NORMAL,
4539 access_rx_hq_intr_csr_parity_err_cnt),
4541 CNTR_NORMAL,
4542 access_rx_lookup_csr_parity_err_cnt),
4544 CNTR_NORMAL,
4545 access_rx_lookup_rcv_array_cor_err_cnt),
4547 CNTR_NORMAL,
4548 access_rx_lookup_rcv_array_unc_err_cnt),
4551 access_rx_lookup_des_part2_parity_err_cnt),
4554 access_rx_lookup_des_part1_unc_cor_err_cnt),
4556 CNTR_NORMAL,
4557 access_rx_lookup_des_part1_unc_err_cnt),
4559 CNTR_NORMAL,
4560 access_rx_rbuf_next_free_buf_cor_err_cnt),
4562 CNTR_NORMAL,
4563 access_rx_rbuf_next_free_buf_unc_err_cnt),
4566 CNTR_NORMAL,
4567 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4570 access_rx_rbuf_fl_initdone_parity_err_cnt),
4573 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4575 CNTR_NORMAL,
4576 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4578 CNTR_NORMAL,
4579 access_rx_rbuf_empty_err_cnt),
4581 CNTR_NORMAL,
4582 access_rx_rbuf_full_err_cnt),
4584 CNTR_NORMAL,
4585 access_rbuf_bad_lookup_err_cnt),
4587 CNTR_NORMAL,
4588 access_rbuf_ctx_id_parity_err_cnt),
4590 CNTR_NORMAL,
4591 access_rbuf_csr_qeopdw_parity_err_cnt),
4594 CNTR_NORMAL,
4595 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4598 CNTR_NORMAL,
4599 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4602 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4605 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4608 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4611 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4614 CNTR_NORMAL,
4615 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4618 access_rx_rbuf_block_list_read_cor_err_cnt),
4621 access_rx_rbuf_block_list_read_unc_err_cnt),
4623 CNTR_NORMAL,
4624 access_rx_rbuf_lookup_des_cor_err_cnt),
4626 CNTR_NORMAL,
4627 access_rx_rbuf_lookup_des_unc_err_cnt),
4630 CNTR_NORMAL,
4631 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4633 CNTR_NORMAL,
4634 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4636 CNTR_NORMAL,
4637 access_rx_rbuf_free_list_cor_err_cnt),
4639 CNTR_NORMAL,
4640 access_rx_rbuf_free_list_unc_err_cnt),
4642 CNTR_NORMAL,
4643 access_rx_rcv_fsm_encoding_err_cnt),
4645 CNTR_NORMAL,
4646 access_rx_dma_flag_cor_err_cnt),
4648 CNTR_NORMAL,
4649 access_rx_dma_flag_unc_err_cnt),
4651 CNTR_NORMAL,
4652 access_rx_dc_sop_eop_parity_err_cnt),
4654 CNTR_NORMAL,
4655 access_rx_rcv_csr_parity_err_cnt),
4657 CNTR_NORMAL,
4658 access_rx_rcv_qp_map_table_cor_err_cnt),
4660 CNTR_NORMAL,
4661 access_rx_rcv_qp_map_table_unc_err_cnt),
4663 CNTR_NORMAL,
4664 access_rx_rcv_data_cor_err_cnt),
4666 CNTR_NORMAL,
4667 access_rx_rcv_data_unc_err_cnt),
4669 CNTR_NORMAL,
4670 access_rx_rcv_hdr_cor_err_cnt),
4672 CNTR_NORMAL,
4673 access_rx_rcv_hdr_unc_err_cnt),
4675 CNTR_NORMAL,
4676 access_rx_dc_intf_parity_err_cnt),
4678 CNTR_NORMAL,
4679 access_rx_dma_csr_cor_err_cnt),
4680 /* SendPioErrStatus */
4682 CNTR_NORMAL,
4683 access_pio_pec_sop_head_parity_err_cnt),
4685 CNTR_NORMAL,
4686 access_pio_pcc_sop_head_parity_err_cnt),
4689 access_pio_last_returned_cnt_parity_err_cnt),
4692 access_pio_current_free_cnt_parity_err_cnt),
4694 CNTR_NORMAL,
4695 access_pio_reserved_31_err_cnt),
4697 CNTR_NORMAL,
4698 access_pio_reserved_30_err_cnt),
4700 CNTR_NORMAL,
4701 access_pio_ppmc_sop_len_err_cnt),
4703 CNTR_NORMAL,
4704 access_pio_ppmc_bqc_mem_parity_err_cnt),
4706 CNTR_NORMAL,
4707 access_pio_vl_fifo_parity_err_cnt),
4709 CNTR_NORMAL,
4710 access_pio_vlf_sop_parity_err_cnt),
4712 CNTR_NORMAL,
4713 access_pio_vlf_v1_len_parity_err_cnt),
4715 CNTR_NORMAL,
4716 access_pio_block_qw_count_parity_err_cnt),
4718 CNTR_NORMAL,
4719 access_pio_write_qw_valid_parity_err_cnt),
4721 CNTR_NORMAL,
4722 access_pio_state_machine_err_cnt),
4724 CNTR_NORMAL,
4725 access_pio_write_data_parity_err_cnt),
4727 CNTR_NORMAL,
4728 access_pio_host_addr_mem_cor_err_cnt),
4730 CNTR_NORMAL,
4731 access_pio_host_addr_mem_unc_err_cnt),
4733 CNTR_NORMAL,
4734 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4736 CNTR_NORMAL,
4737 access_pio_init_sm_in_err_cnt),
4739 CNTR_NORMAL,
4740 access_pio_ppmc_pbl_fifo_err_cnt),
4743 access_pio_credit_ret_fifo_parity_err_cnt),
4745 CNTR_NORMAL,
4746 access_pio_v1_len_mem_bank1_cor_err_cnt),
4748 CNTR_NORMAL,
4749 access_pio_v1_len_mem_bank0_cor_err_cnt),
4751 CNTR_NORMAL,
4752 access_pio_v1_len_mem_bank1_unc_err_cnt),
4754 CNTR_NORMAL,
4755 access_pio_v1_len_mem_bank0_unc_err_cnt),
4757 CNTR_NORMAL,
4758 access_pio_sm_pkt_reset_parity_err_cnt),
4760 CNTR_NORMAL,
4761 access_pio_pkt_evict_fifo_parity_err_cnt),
4764 CNTR_NORMAL,
4765 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4767 CNTR_NORMAL,
4768 access_pio_sbrdctl_crrel_parity_err_cnt),
4770 CNTR_NORMAL,
4771 access_pio_pec_fifo_parity_err_cnt),
4773 CNTR_NORMAL,
4774 access_pio_pcc_fifo_parity_err_cnt),
4776 CNTR_NORMAL,
4777 access_pio_sb_mem_fifo1_err_cnt),
4779 CNTR_NORMAL,
4780 access_pio_sb_mem_fifo0_err_cnt),
4782 CNTR_NORMAL,
4783 access_pio_csr_parity_err_cnt),
4785 CNTR_NORMAL,
4786 access_pio_write_addr_parity_err_cnt),
4788 CNTR_NORMAL,
4789 access_pio_write_bad_ctxt_err_cnt),
4790 /* SendDmaErrStatus */
4793 access_sdma_pcie_req_tracking_cor_err_cnt),
4796 access_sdma_pcie_req_tracking_unc_err_cnt),
4798 CNTR_NORMAL,
4799 access_sdma_csr_parity_err_cnt),
4801 CNTR_NORMAL,
4802 access_sdma_rpy_tag_err_cnt),
4803 /* SendEgressErrStatus */
4805 CNTR_NORMAL,
4806 access_tx_read_pio_memory_csr_unc_err_cnt),
4809 access_tx_read_sdma_memory_csr_err_cnt),
4811 CNTR_NORMAL,
4812 access_tx_egress_fifo_cor_err_cnt),
4814 CNTR_NORMAL,
4815 access_tx_read_pio_memory_cor_err_cnt),
4817 CNTR_NORMAL,
4818 access_tx_read_sdma_memory_cor_err_cnt),
4820 CNTR_NORMAL,
4821 access_tx_sb_hdr_cor_err_cnt),
4823 CNTR_NORMAL,
4824 access_tx_credit_overrun_err_cnt),
4826 CNTR_NORMAL,
4827 access_tx_launch_fifo8_cor_err_cnt),
4829 CNTR_NORMAL,
4830 access_tx_launch_fifo7_cor_err_cnt),
4832 CNTR_NORMAL,
4833 access_tx_launch_fifo6_cor_err_cnt),
4835 CNTR_NORMAL,
4836 access_tx_launch_fifo5_cor_err_cnt),
4838 CNTR_NORMAL,
4839 access_tx_launch_fifo4_cor_err_cnt),
4841 CNTR_NORMAL,
4842 access_tx_launch_fifo3_cor_err_cnt),
4844 CNTR_NORMAL,
4845 access_tx_launch_fifo2_cor_err_cnt),
4847 CNTR_NORMAL,
4848 access_tx_launch_fifo1_cor_err_cnt),
4850 CNTR_NORMAL,
4851 access_tx_launch_fifo0_cor_err_cnt),
4853 CNTR_NORMAL,
4854 access_tx_credit_return_vl_err_cnt),
4856 CNTR_NORMAL,
4857 access_tx_hcrc_insertion_err_cnt),
4859 CNTR_NORMAL,
4860 access_tx_egress_fifo_unc_err_cnt),
4862 CNTR_NORMAL,
4863 access_tx_read_pio_memory_unc_err_cnt),
4865 CNTR_NORMAL,
4866 access_tx_read_sdma_memory_unc_err_cnt),
4868 CNTR_NORMAL,
4869 access_tx_sb_hdr_unc_err_cnt),
4871 CNTR_NORMAL,
4872 access_tx_credit_return_partiy_err_cnt),
4875 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4878 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4881 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4884 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4887 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4890 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4893 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4896 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4899 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4902 access_tx_sdma15_disallowed_packet_err_cnt),
4905 access_tx_sdma14_disallowed_packet_err_cnt),
4908 access_tx_sdma13_disallowed_packet_err_cnt),
4911 access_tx_sdma12_disallowed_packet_err_cnt),
4914 access_tx_sdma11_disallowed_packet_err_cnt),
4917 access_tx_sdma10_disallowed_packet_err_cnt),
4920 access_tx_sdma9_disallowed_packet_err_cnt),
4923 access_tx_sdma8_disallowed_packet_err_cnt),
4926 access_tx_sdma7_disallowed_packet_err_cnt),
4929 access_tx_sdma6_disallowed_packet_err_cnt),
4932 access_tx_sdma5_disallowed_packet_err_cnt),
4935 access_tx_sdma4_disallowed_packet_err_cnt),
4938 access_tx_sdma3_disallowed_packet_err_cnt),
4941 access_tx_sdma2_disallowed_packet_err_cnt),
4944 access_tx_sdma1_disallowed_packet_err_cnt),
4947 access_tx_sdma0_disallowed_packet_err_cnt),
4949 CNTR_NORMAL,
4950 access_tx_config_parity_err_cnt),
4952 CNTR_NORMAL,
4953 access_tx_sbrd_ctl_csr_parity_err_cnt),
4955 CNTR_NORMAL,
4956 access_tx_launch_csr_parity_err_cnt),
4958 CNTR_NORMAL,
4959 access_tx_illegal_vl_err_cnt),
4962 CNTR_NORMAL,
4963 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4965 CNTR_NORMAL,
4966 access_egress_reserved_10_err_cnt),
4968 CNTR_NORMAL,
4969 access_egress_reserved_9_err_cnt),
4972 access_tx_sdma_launch_intf_parity_err_cnt),
4974 CNTR_NORMAL,
4975 access_tx_pio_launch_intf_parity_err_cnt),
4977 CNTR_NORMAL,
4978 access_egress_reserved_6_err_cnt),
4980 CNTR_NORMAL,
4981 access_tx_incorrect_link_state_err_cnt),
4983 CNTR_NORMAL,
4984 access_tx_linkdown_err_cnt),
4987 CNTR_NORMAL,
4988 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4990 CNTR_NORMAL,
4991 access_egress_reserved_2_err_cnt),
4993 CNTR_NORMAL,
4994 access_tx_pkt_integrity_mem_unc_err_cnt),
4996 CNTR_NORMAL,
4997 access_tx_pkt_integrity_mem_cor_err_cnt),
4998 /* SendErrStatus */
5000 CNTR_NORMAL,
5001 access_send_csr_write_bad_addr_err_cnt),
5003 CNTR_NORMAL,
5004 access_send_csr_read_bad_addr_err_cnt),
5006 CNTR_NORMAL,
5007 access_send_csr_parity_cnt),
5008 /* SendCtxtErrStatus */
5010 CNTR_NORMAL,
5011 access_pio_write_out_of_bounds_err_cnt),
5013 CNTR_NORMAL,
5014 access_pio_write_overflow_err_cnt),
5017 access_pio_write_crosses_boundary_err_cnt),
5019 CNTR_NORMAL,
5020 access_pio_disallowed_packet_err_cnt),
5022 CNTR_NORMAL,
5023 access_pio_inconsistent_sop_err_cnt),
5024 /* SendDmaEngErrStatus */
5027 access_sdma_header_request_fifo_cor_err_cnt),
5029 CNTR_NORMAL,
5030 access_sdma_header_storage_cor_err_cnt),
5032 CNTR_NORMAL,
5033 access_sdma_packet_tracking_cor_err_cnt),
5035 CNTR_NORMAL,
5036 access_sdma_assembly_cor_err_cnt),
5038 CNTR_NORMAL,
5039 access_sdma_desc_table_cor_err_cnt),
5042 access_sdma_header_request_fifo_unc_err_cnt),
5044 CNTR_NORMAL,
5045 access_sdma_header_storage_unc_err_cnt),
5047 CNTR_NORMAL,
5048 access_sdma_packet_tracking_unc_err_cnt),
5050 CNTR_NORMAL,
5051 access_sdma_assembly_unc_err_cnt),
5053 CNTR_NORMAL,
5054 access_sdma_desc_table_unc_err_cnt),
5056 CNTR_NORMAL,
5057 access_sdma_timeout_err_cnt),
5059 CNTR_NORMAL,
5060 access_sdma_header_length_err_cnt),
5062 CNTR_NORMAL,
5063 access_sdma_header_address_err_cnt),
5065 CNTR_NORMAL,
5066 access_sdma_header_select_err_cnt),
5068 CNTR_NORMAL,
5069 access_sdma_reserved_9_err_cnt),
5071 CNTR_NORMAL,
5072 access_sdma_packet_desc_overflow_err_cnt),
5074 CNTR_NORMAL,
5075 access_sdma_length_mismatch_err_cnt),
5077 CNTR_NORMAL,
5078 access_sdma_halt_err_cnt),
5080 CNTR_NORMAL,
5081 access_sdma_mem_read_err_cnt),
5083 CNTR_NORMAL,
5084 access_sdma_first_desc_err_cnt),
5086 CNTR_NORMAL,
5087 access_sdma_tail_out_of_bounds_err_cnt),
5089 CNTR_NORMAL,
5090 access_sdma_too_long_err_cnt),
5092 CNTR_NORMAL,
5093 access_sdma_gen_mismatch_err_cnt),
5095 CNTR_NORMAL,
5096 access_sdma_wrong_dw_err_cnt),
5097 };
5101 CNTR_NORMAL),
5103 CNTR_NORMAL),
5105 CNTR_NORMAL),
5107 CNTR_NORMAL),
5109 CNTR_NORMAL),
5111 CNTR_NORMAL),
5113 CNTR_NORMAL),
5126 access_sw_link_dn_cnt),
5128 access_sw_link_up_cnt),
5130 access_sw_unknown_frame_cnt),
5132 access_sw_xmit_discards),
5135 access_sw_xmit_discards),
5137 access_xmit_constraint_errs),
5139 access_rcv_constraint_errs),
5154 access_sw_cpu_rc_acks),
5156 access_sw_cpu_rc_qacks),
5158 access_sw_cpu_rc_delayed_comp),
5239 };
5241 /* ======================================================================== */
5243 /* return true if this is chip revision revision a */
5245 {
5246 u8 chip_rev_minor =
5250 }
5252 /* return true if this is chip revision revision b */
5254 {
5255 u8 chip_rev_minor =
5259 }
5261 /* return true is kernel urg disabled for rcd */
5263 {
5264 u64 mask;
5270 }
5272 /*
5273 * Append string s to buffer buf. Arguments curp and len are the current
5274 * position and remaining length, respectively.
5275 *
5276 * return 0 on success, 1 on out of room
5277 */
5279 {
5285 /* add a comma, if first in the buffer */
5290 }
5292 len--;
5293 }
5295 /* copy the string */
5300 }
5302 len--;
5303 }
5305 done:
5306 /* write return values */
5311 }
5313 /*
5314 * Using the given flag table, print a comma separated string into
5315 * the buffer. End in '*' if the buffer is too short.
5316 */
5319 {
5326 /* make sure there is at least 2 so we can form "*" */
5337 }
5338 }
5340 /* any undocumented bits left? */
5344 }
5346 /* add * if ran out of room */
5348 /* may need to back up to add space for a '*' */
5352 }
5354 /* add final nul - space already allocated above */
5357 }
5359 /* first 8 CCE error interrupt source names */
5369 };
5371 /*
5372 * Return the miscellaneous error interrupt name.
5373 */
5375 {
5378 else
5383 }
5385 /*
5386 * Return the SDMA engine error interrupt name.
5387 */
5389 {
5392 }
5394 /*
5395 * Return the send context error interrupt name.
5396 */
5398 {
5401 }
5408 "TCritInt"
5409 };
5411 /*
5412 * Return the various interrupt name.
5413 */
5415 {
5418 else
5421 }
5423 /*
5424 * Return the DC interrupt name.
5425 */
5427 {
5433 };
5437 else
5440 }
5446 };
5448 /*
5449 * Return the SDMA engine interrupt name.
5450 */
5452 {
5453 /* what interrupt */
5455 /* which engine */
5460 else
5463 }
5465 /*
5466 * Return the receive available interrupt name.
5467 */
5469 {
5472 }
5474 /*
5475 * Return the receive urgent interrupt name.
5476 */
5478 {
5481 }
5483 /*
5484 * Return the send credit interrupt name.
5485 */
5487 {
5490 }
5492 /*
5493 * Return the reserved interrupt name.
5494 */
5496 {
5499 }
5502 {
5504 cce_err_status_flags,
5506 }
5509 {
5511 rxe_err_status_flags,
5513 }
5516 {
5519 }
5522 {
5524 pio_err_status_flags,
5526 }
5529 {
5531 sdma_err_status_flags,
5533 }
5536 {
5538 egress_err_status_flags,
5540 }
5543 {
5545 egress_err_info_flags,
5547 }
5550 {
5552 send_err_status_flags,
5554 }
5557 {
5561 /*
5562 * For most these errors, there is nothing that can be done except
5563 * report or record it.
5564 */
5570 /* this error requires a manual drop into SPC freeze mode */
5571 /* then a fix up */
5573 }
5578 /* maintain a counter over all cce_err_status errors */
5580 }
5581 }
5582 }
5584 /*
5585 * Check counters for receive errors that do not have an interrupt
5586 * associated with them.
5587 */
5588 #define RCVERR_CHECK_TIME 10
5590 {
5600 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5602 }
5606 }
5609 {
5611 /* Assume the hardware counter has been reset */
5614 }
5617 {
5620 }
5623 {
5633 /*
5634 * Freeze mode recovery is disabled for the errors
5635 * in RXE_FREEZE_ABORT_MASK
5636 */
5641 }
5646 }
5647 }
5650 {
5659 }
5660 }
5663 {
5676 }
5677 }
5680 {
5693 }
5694 }
5697 {
5699 }
5702 {
5704 }
5706 /*
5707 * We have had a "disallowed packet" error during egress. Determine the
5708 * integrity check which failed, and update relevant error counter, etc.
5709 *
5710 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5711 * bit of state per integrity check, and so we can miss the reason for an
5712 * egress error if more than one packet fails the same integrity check
5713 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5714 */
5717 {
5723 /* clear down all observed info as quickly as possible after read */
5730 /* Eventually add other counters for each bit */
5734 /*
5735 * Count all applicable bits as individual errors and
5736 * attribute them to the packet that triggered this handler.
5737 * This may not be completely accurate due to limitations
5738 * on the available hardware error information. There is
5739 * a single information register and any number of error
5740 * packets may have occurred and contributed to it before
5741 * this routine is called. This means that:
5742 * a) If multiple packets with the same error occur before
5743 * this routine is called, earlier packets are missed.
5744 * There is only a single bit for each error type.
5745 * b) Errors may not be attributed to the correct VL.
5746 * The driver is attributing all bits in the info register
5747 * to the packet that triggered this call, but bits
5748 * could be an accumulation of different packets with
5749 * different VLs.
5750 * c) A single error packet may have multiple counts attached
5751 * to it. There is no way for the driver to know if
5752 * multiple bits set in the info register are due to a
5753 * single packet or multiple packets. The driver assumes
5754 * multiple packets.
5755 */
5764 }
5765 }
5766 }
5768 /*
5769 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5770 * register. Does it represent a 'port inactive' error?
5771 */
5773 {
5776 }
5778 /*
5779 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5780 * register. Does it represent a 'disallowed packet' error?
5781 */
5783 {
5786 }
5788 /*
5789 * Input value is a bit position of one of the SDMA engine disallowed
5790 * packet errors. Return which engine. Use of this must be guarded by
5791 * disallowed_pkt_err().
5792 */
5794 {
5796 }
5798 /*
5799 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5800 * be done.
5801 */
5803 {
5807 /* range check */
5817 }
5819 /*
5820 * Translate the send context (sofware index) into a VL. Return -1 if the
5821 * translation cannot be done.
5822 */
5824 {
5831 /* there is no information for user (PSM) and ack contexts */
5845 }
5848 {
5862 /* fls64() returns a 1-based offset, we want it zero based */
5874 }
5876 }
5887 }
5888 }
5891 {
5901 }
5902 }
5904 /*
5905 * The maximum number of times the error clear down will loop before
5906 * blocking a repeating error. This value is arbitrary.
5907 */
5908 #define MAX_CLEAR_COUNT 20
5910 /*
5911 * Clear and handle an error register. All error interrupts are funneled
5912 * through here to have a central location to correctly handle single-
5913 * or multi-shot errors.
5914 *
5915 * For non per-context registers, call this routine with a context value
5916 * of 0 so the per-context offset is zero.
5917 *
5918 * If the handler loops too many times, assume that something is wrong
5919 * and can't be fixed, so mask the error bits.
5920 */
5922 u32 context,
5924 {
5925 u64 reg;
5926 u32 count;
5928 /* read in a loop until no more errors are seen */
5937 count++;
5939 u64 mask;
5943 /*
5944 * Read-modify-write so any other masked bits
5945 * remain masked.
5946 */
5951 }
5952 }
5953 }
5955 /*
5956 * CCE block "misc" interrupt. Source is < 16.
5957 */
5959 {
5966 source);
5967 }
5968 }
5971 {
5973 sc_err_status_flags,
5975 }
5977 /*
5978 * Send context error interrupt. Source (hw_context) is < 160.
5979 *
5980 * All send context errors cause the send context to halt. The normal
5981 * clear-down mechanism cannot be used because we cannot clear the
5982 * error bits until several other long-running items are done first.
5983 * This is OK because with the context halted, nothing else is going
5984 * to happen on it anyway.
5985 */
5988 {
5992 u64 status;
5993 u32 sw_index;
6003 }
6012 }
6014 /* tell the software that a halt has begun */
6021 status));
6026 /*
6027 * Automatically restart halted kernel contexts out of interrupt
6028 * context. User contexts must ask the driver to restart the context.
6029 */
6034 /*
6035 * Update the counters for the corresponding status bits.
6036 * Note that these particular counters are aggregated over all
6037 * 160 contexts.
6038 */
6042 }
6043 }
6047 {
6052 #ifdef CONFIG_SDMA_VERBOSITY
6057 #endif
6061 /*
6062 * Update the counters for the corresponding status bits.
6063 * Note that these particular counters are aggregated over
6064 * all 16 DMA engines.
6065 */
6069 }
6070 }
6072 /*
6073 * CCE block SDMA error interrupt. Source is < 16.
6074 */
6076 {
6077 #ifdef CONFIG_SDMA_VERBOSITY
6083 source);
6085 #endif
6087 }
6089 /*
6090 * CCE block "various" interrupt. Source is < 8.
6091 */
6093 {
6096 /*
6097 * TCritInt cannot go through interrupt_clear_down()
6098 * because it is not a second tier interrupt. The handler
6099 * should be called directly.
6100 */
6105 else
6109 }
6112 {
6113 /* src_ctx is always zero */
6121 __func__);
6124 /*
6125 * Cable removed, reset all our information about the
6126 * cache and cable capabilities
6127 */
6130 /*
6131 * We don't set cache_refresh_required here as we expect
6132 * an interrupt when a cable is inserted
6133 */
6138 flags);
6139 /* Invert the ModPresent pin now to detect plug-in */
6145 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6150 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6153 /*
6154 * The link is still in POLL. This means
6155 * that the normal link down processing
6156 * will not happen. We have to do it here
6157 * before turning the DC off.
6158 */
6160 }
6163 __func__);
6169 flags);
6171 /*
6172 * Stop inversion of ModPresent pin to detect
6173 * removal of the cable
6174 */
6181 }
6182 }
6186 __func__);
6190 }
6192 /* Schedule the QSFP work only if there is a cable attached. */
6195 }
6198 {
6207 }
6209 }
6212 {
6221 }
6223 }
6225 /*
6226 * Set the LCB selector - allow host access. The DCC selector always
6227 * points to the host.
6228 */
6230 {
6232 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6233 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6234 }
6236 /*
6237 * Clear the LCB selector - allow 8051 access. The DCC selector always
6238 * points to the host.
6239 */
6241 {
6243 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6244 }
6246 /*
6247 * Acquire LCB access from the 8051. If the host already has access,
6248 * just increment a counter. Otherwise, inform the 8051 that the
6249 * host is taking access.
6250 *
6251 * Returns:
6252 * 0 on success
6253 * -EBUSY if the 8051 has control and cannot be disturbed
6254 * -errno if unable to acquire access from the 8051
6255 */
6257 {
6261 /*
6262 * Use the host link state lock so the operation of this routine
6263 * { link state check, selector change, count increment } can occur
6264 * as a unit against a link state change. Otherwise there is a
6265 * race between the state change and the count increment.
6266 */
6272 }
6274 /* this access is valid only when the link is up */
6280 }
6289 }
6291 }
6293 done:
6296 }
6298 /*
6299 * Release LCB access by decrementing the use count. If the count is moving
6300 * from 1 to 0, inform 8051 that it has control back.
6301 *
6302 * Returns:
6303 * 0 on success
6304 * -errno if unable to release access to the 8051
6305 */
6307 {
6310 /*
6311 * Use the host link state lock because the acquire needed it.
6312 * Here, we only need to keep { selector change, count decrement }
6313 * as a unit.
6314 */
6320 }
6324 __func__);
6326 }
6335 /* restore host access if the grant didn't work */
6338 }
6339 }
6341 done:
6344 }
6346 /*
6347 * Initialize LCB access variables and state. Called during driver load,
6348 * after most of the initialization is finished.
6349 *
6350 * The DC default is LCB access on for the host. The driver defaults to
6351 * leaving access to the 8051. Assign access now - this constrains the call
6352 * to this routine to be after all LCB set-up is done. In particular, after
6353 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6354 */
6356 {
6358 }
6360 /*
6361 * Write a response back to a 8051 request.
6362 */
6364 {
6366 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6368 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6370 }
6372 /*
6373 * Handle host requests from the 8051.
6374 */
6376 {
6378 u64 reg;
6380 u8 type;
6386 /* zero out COMPLETED so the response is seen */
6389 /* extract request details */
6403 type);
6407 /* Put the LCB, RX FPE and TX FPE into reset */
6409 /* Make sure the write completed */
6411 /* Hold the reset long enough to take effect */
6413 /* Take the LCB, RX FPE and TX FPE out of reset */
6429 }
6430 }
6432 /*
6433 * Set up allocation unit vaulue.
6434 */
6436 {
6439 /* do not modify other values in the register */
6443 }
6445 /*
6446 * Set up initial VL15 credits of the remote. Assumes the rest of
6447 * the CM credit registers are zero from a previous global or credit reset.
6448 * Shared limit for VL15 will always be 0.
6449 */
6451 {
6454 /* set initial values for total and shared credit limit */
6456 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6458 /*
6459 * Set total limit to be equal to VL15 credits.
6460 * Leave shared limit at 0.
6461 */
6467 }
6469 /*
6470 * Zero all credit details from the previous connection and
6471 * reset the CM manager's internal counters.
6472 */
6474 {
6477 /* remove all previous VL credit limits */
6482 /* reset the CM block */
6484 /* reset cached value */
6486 }
6488 /* convert a vCU to a CU */
6490 {
6492 }
6494 /* convert a CU to a vCU */
6496 {
6498 }
6500 /* convert a vAU to an AU */
6502 {
6504 }
6507 {
6510 }
6512 /*
6513 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6514 */
6516 {
6517 u64 reg;
6519 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6521 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6524 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6534 }
6535 }
6537 /*
6538 * This routine should be called after the link has been transitioned to
6539 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6540 * reset).
6541 *
6542 * The expectation is that the caller of this routine would have taken
6543 * care of properly transitioning the link into the correct state.
6544 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6545 * before calling this function.
6546 */
6548 {
6555 /* Shutdown the LCB */
6557 /*
6558 * Going to OFFLINE would have causes the 8051 to put the
6559 * SerDes into reset already. Just need to shut down the 8051,
6560 * itself.
6561 */
6563 }
6566 {
6570 }
6572 /*
6573 * Calling this after the DC has been brought out of reset should not
6574 * do any damage.
6575 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6576 * before calling this function.
6577 */
6579 {
6585 /* Take the 8051 out of reset */
6587 /* Wait until 8051 is ready */
6590 __func__);
6592 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6594 /* lcb_shutdown() with abort=1 does not restore these */
6597 }
6600 {
6604 }
6606 /*
6607 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6608 */
6610 {
6612 u32 version;
6617 /*
6618 * These LCB defaults on emulator _s are good, nothing to do here:
6619 * LCB_CFG_TX_FIFOS_RADR
6620 * LCB_CFG_RX_FIFOS_RADR
6621 * LCB_CFG_LN_DCLK
6622 * LCB_CFG_IGNORE_LOST_RCLK
6623 */
6626 /* else this is _p */
6633 /* release 0x12 and below */
6635 /*
6636 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6637 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6638 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6639 */
6640 rx_radr =
6644 /*
6645 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6646 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6647 */
6650 /* release 0x13 up to 0x18 */
6651 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6652 rx_radr =
6658 /* release 0x19 */
6659 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6660 rx_radr =
6666 /* release 0x1a */
6667 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6668 rx_radr =
6675 /* release 0x1b and higher */
6676 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6677 rx_radr =
6682 }
6685 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6687 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6689 }
6691 /*
6692 * Handle a SMA idle message
6693 *
6694 * This is a work-queue function outside of the interrupt.
6695 */
6697 {
6699 sma_message_work);
6701 u64 msg;
6704 /*
6705 * msg is bytes 1-4 of the 40-bit idle message - the command code
6706 * is stripped off
6707 */
6712 /*
6713 * React to the SMA message. Byte[1] (0 for us) is the command.
6714 */
6717 /*
6718 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6719 * State Transitions
6720 *
6721 * Only expected in INIT or ARMED, discard otherwise.
6722 */
6727 /*
6728 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6729 * State Transitions
6730 *
6731 * Can activate the node. Discard otherwise.
6732 */
6739 dd,
6741 __func__);
6742 }
6749 }
6750 }
6753 {
6754 u64 rcvctrl;
6763 }
6766 {
6768 }
6771 {
6773 }
6775 /*
6776 * Called from all interrupt handlers to start handling an SPC freeze.
6777 */
6779 {
6788 /* enter frozen mode */
6791 /* notify all SDMA engines that they are going into a freeze */
6796 /* do halt pre-handling on all enabled send contexts */
6801 }
6803 /* Send context are frozen. Notify user space */
6810 }
6811 /* queue non-interrupt handler */
6813 }
6815 /*
6816 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6817 * depending on the "freeze" parameter.
6818 *
6819 * No need to return an error if it times out, our only option
6820 * is to proceed anyway.
6821 */
6823 {
6825 u64 reg;
6831 /* waiting until all indicators are set */
6835 /* waiting until all indicators are clear */
6838 }
6846 }
6848 }
6849 }
6851 /*
6852 * Do all freeze handling for the RXE block.
6853 */
6855 {
6859 /* disable port */
6862 /* disable all receive contexts */
6867 }
6868 }
6870 /*
6871 * Unfreeze handling for the RXE block - kernel contexts only.
6872 * This will also enable the port. User contexts will do unfreeze
6873 * handling on a per-context basis as they call into the driver.
6874 *
6875 */
6877 {
6878 u32 rcvmask;
6879 u16 i;
6882 /* enable all kernel contexts */
6886 /* Ensure all non-user contexts(including vnic) are enabled */
6891 }
6893 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6898 }
6900 /* enable port */
6902 }
6904 /*
6905 * Non-interrupt SPC freeze handling.
6906 *
6907 * This is a work-queue function outside of the triggering interrupt.
6908 */
6910 {
6912 freeze_work);
6915 /* wait for freeze indicators on all affected blocks */
6918 /* SPC is now frozen */
6920 /* do send PIO freeze steps */
6923 /* do send DMA freeze steps */
6926 /* do send egress freeze steps - nothing to do */
6928 /* do receive freeze steps */
6931 /*
6932 * Unfreeze the hardware - clear the freeze, wait for each
6933 * block's frozen bit to clear, then clear the frozen flag.
6934 */
6943 }
6945 /* do send PIO unfreeze steps for kernel contexts */
6948 /* do send DMA unfreeze steps */
6951 /* do send egress unfreeze steps - nothing to do */
6953 /* do receive unfreeze steps for kernel contexts */
6956 /*
6957 * The unfreeze procedure touches global device registers when
6958 * it disables and re-enables RXE. Mark the device unfrozen
6959 * after all that is done so other parts of the driver waiting
6960 * for the device to unfreeze don't do things out of order.
6961 *
6962 * The above implies that the meaning of HFI1_FROZEN flag is
6963 * "Device has gone into freeze mode and freeze mode handling
6964 * is still in progress."
6965 *
6966 * The flag will be removed when freeze mode processing has
6967 * completed.
6968 */
6972 /* no longer frozen */
6973 }
6975 /**
6976 * update_xmit_counters - update PortXmitWait/PortVlXmitWait
6977 * counters.
6978 * @ppd: info of physical Hfi port
6979 * @link_width: new link width after link up or downgrade
6980 *
6981 * Update the PortXmitWait and PortVlXmitWait counters after
6982 * a link up or downgrade event to reflect a link width change.
6983 */
6985 {
6987 u16 tx_width;
6988 u16 link_speed;
6993 /*
6994 * There are C_VL_COUNT number of PortVLXmitWait counters.
6995 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
6996 */
6999 }
7001 /*
7002 * Handle a link up interrupt from the 8051.
7003 *
7004 * This is a work-queue function outside of the interrupt.
7005 */
7007 {
7009 link_up_work);
7014 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
7016 /*
7017 * OPA specifies that certain counters are cleared on a transition
7018 * to link up, so do that.
7019 */
7021 /*
7022 * And (re)set link up default values.
7023 */
7026 /*
7027 * Set VL15 credits. Use cached value from verify cap interrupt.
7028 * In case of quick linkup or simulator, vl15 value will be set by
7029 * handle_linkup_change. VerifyCap interrupt handler will not be
7030 * called in those scenarios.
7031 */
7035 /* enforce link speed enabled */
7037 /* oops - current speed is not enabled, bounce */
7042 OPA_LINKDOWN_REASON_SPEED_POLICY);
7045 }
7046 }
7048 /*
7049 * Several pieces of LNI information were cached for SMA in ppd.
7050 * Reset these on link down
7051 */
7053 {
7058 }
7114 };
7116 /* return the neighbor link down reason string */
7118 {
7127 }
7129 /*
7130 * Handle a link down interrupt from the 8051.
7131 *
7132 * This is a work-queue function outside of the interrupt.
7133 */
7135 {
7137 u8 link_down_reason;
7139 link_down_work);
7149 /* Go offline first, then deal with reading/writing through 8051 */
7156 /* link down reason is only valid if the link was up */
7160 /* the link went down, no idle message reason */
7162 ldr_str);
7165 /*
7166 * The neighbor reason is only valid if an idle message
7167 * was received for it.
7168 */
7178 ldr_str);
7184 }
7186 /*
7187 * If no reason, assume peer-initiated but missed
7188 * LinkGoingDown idle flits.
7189 */
7193 /* went down while polling or going up */
7195 }
7199 /* inform the SMA when the link transitions from up to down */
7206 }
7210 /* disable the port */
7213 /*
7214 * If there is no cable attached, turn the DC off. Otherwise,
7215 * start the link bring up.
7216 */
7219 else
7221 }
7224 {
7226 link_bounce_work);
7228 /*
7229 * Only do something if the link is currently up.
7230 */
7237 }
7238 }
7240 /*
7241 * Mask conversion: Capability exchange to Port LTP. The capability
7242 * exchange has an implicit 16b CRC that is mandatory.
7243 */
7245 {
7256 }
7258 /*
7259 * Convert an OPA Port LTP mask to capability mask
7260 */
7262 {
7273 }
7275 /*
7276 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7277 */
7279 {
7288 else
7292 }
7295 {
7300 }
7301 }
7303 /*
7304 * Convert the given link width to the OPA link width bitmask.
7305 */
7307 {
7310 /*
7311 * Simulator and quick linkup do not set the width.
7312 * Just set it to 4x without complaint.
7313 */
7325 }
7326 }
7328 /*
7329 * Do a population count on the bottom nibble.
7330 */
7333 };
7336 {
7338 }
7340 /*
7341 * Read the active lane information from the 8051 registers and return
7342 * their widths.
7343 *
7344 * Active lane information is found in these 8051 registers:
7345 * enable_lane_tx
7346 * enable_lane_rx
7347 */
7350 {
7352 u8 enable_lane_rx;
7353 u8 enable_lane_tx;
7354 u8 tx_polarity_inversion;
7355 u8 rx_polarity_inversion;
7356 u8 max_rate;
7358 /* read the active lanes */
7363 /* convert to counts */
7367 /*
7368 * Set link_speed_active here, overriding what was set in
7369 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7370 * set the max_rate field in handle_verify_cap until v0.19.
7371 */
7374 /* max_rate: 0 = 12.5G, 1 = 25G */
7388 }
7389 }
7396 }
7398 /*
7399 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7400 * Valid after the end of VerifyCap and during LinkUp. Does not change
7401 * after link up. I.e. look elsewhere for downgrade information.
7402 *
7403 * Bits are:
7404 * + bits [7:4] contain the number of active transmitters
7405 * + bits [3:0] contain the number of active receivers
7406 * These are numbers 1 through 4 and can be different values if the
7407 * link is asymmetric.
7408 *
7409 * verify_cap_local_fm_link_width[0] retains its original value.
7410 */
7413 {
7425 /* print the active widths */
7427 }
7429 /*
7430 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7431 * hardware information when the link first comes up.
7432 *
7433 * The link width is not available until after VerifyCap.AllFramesReceived
7434 * (the trigger for handle_verify_cap), so this is outside that routine
7435 * and should be called when the 8051 signals linkup.
7436 */
7438 {
7441 /* get end-of-LNI link widths */
7444 /* use tx_width as the link is supposed to be symmetric on link up */
7446 /* link width downgrade active (LWD.A) starts out matching LW.A */
7449 /* per OPA spec, on link up LWD.E resets to LWD.S */
7451 /* cache the active egress rate (units {10^6 bits/sec]) */
7453 }
7455 /*
7456 * Handle a verify capabilities interrupt from the 8051.
7457 *
7458 * This is a work-queue function outside of the interrupt.
7459 */
7461 {
7463 link_vc_work);
7465 u64 reg;
7466 u8 power_management;
7467 u8 continuous;
7468 u8 vcu;
7469 u8 vau;
7470 u8 z;
7471 u16 vl15buf;
7472 u16 link_widths;
7473 u16 crc_mask;
7474 u16 crc_val;
7475 u16 device_id;
7477 u8 partner_supported_crc;
7478 u8 remote_tx_rate;
7479 u8 device_rev;
7492 /* print the active widths */
7505 /*
7506 * The peer vAU value just read is the peer receiver value. HFI does
7507 * not support a transmit vAU of 0 (AU == 8). We advertised that
7508 * with Z=1 in the fabric capabilities sent to the peer. The peer
7509 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7510 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7511 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7512 * subject to the Z value exception.
7513 */
7518 /*
7519 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7520 * credits value and wait for link-up interrupt ot set it.
7521 */
7525 /* set up the LCB CRC mode */
7528 /* order is important: use the lowest bit in common */
7535 else
7542 /* set (14b only) or clear sideband credit */
7550 }
7554 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7562 }
7564 /* actual rate is highest bit of the ANDed rates */
7571 }
7576 }
7578 /*
7579 * Cache the values of the supported, enabled, and active
7580 * LTP CRC modes to return in 'portinfo' queries. But the bit
7581 * flags that are returned in the portinfo query differ from
7582 * what's in the link_crc_mask, crc_sizes, and crc_val
7583 * variables. Convert these here.
7584 */
7586 /* supported crc modes */
7589 /* enabled crc modes */
7591 /* active crc mode */
7593 /* set up the remote credit return table */
7596 /*
7597 * The LCB is reset on entry to handle_verify_cap(), so this must
7598 * be applied on every link up.
7599 *
7600 * Adjust LCB error kill enable to kill the link if
7601 * these RBUF errors are seen:
7602 * REPLAY_BUF_MBE_SMASK
7603 * FLIT_INPUT_BUF_MBE_SMASK
7604 */
7607 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7610 }
7612 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7615 /* give 8051 access to the LCB CSRs */
7619 /* tell the 8051 to go to LinkUp */
7621 }
7623 /**
7624 * apply_link_downgrade_policy - Apply the link width downgrade enabled
7625 * policy against the current active link widths.
7626 * @ppd: info of physical Hfi port
7627 * @refresh_widths: True indicates link downgrade event
7628 * @return: True indicates a successful link downgrade. False indicates
7629 * link downgrade event failed and the link will bounce back to
7630 * default link width.
7631 *
7632 * Called when the enabled policy changes or the active link widths
7633 * change.
7634 * Refresh_widths indicates that a link downgrade occurred. The
7635 * link_downgraded variable is set by refresh_widths and
7636 * determines the success/failure of the policy application.
7637 */
7640 {
7643 u16 lwde;
7647 /* use the hls lock to avoid a race with actual link up */
7649 retry:
7651 /* only apply if the link is up */
7653 /* still going up..wait and retry */
7659 }
7662 __func__);
7663 }
7665 }
7673 }
7677 /* the 8051 reported a dead link as a downgrade */
7681 /* downgrade is disabled */
7683 /* bounce if not at starting active width */
7697 }
7700 /* Tx or Rx is outside the enabled policy */
7709 }
7711 done:
7716 OPA_LINKDOWN_REASON_WIDTH_POLICY);
7719 }
7722 }
7724 /*
7725 * Handle a link downgrade interrupt from the 8051.
7726 *
7727 * This is a work-queue function outside of the interrupt.
7728 */
7730 {
7732 link_downgrade_work);
7737 }
7740 {
7743 }
7746 {
7749 }
7752 {
7755 }
7758 {
7761 }
7764 {
7767 }
7770 {
7776 /* look at the flags */
7778 /* 8051 information set by firmware */
7779 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7784 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7787 /*
7788 * Handle error flags.
7789 */
7791 /*
7792 * LNI error indications are cleared by the 8051
7793 * only when starting polling. Only pay attention
7794 * to them when in the states that occur during
7795 * LNI.
7796 */
7803 err &
7804 FAILED_LNI));
7805 }
7807 }
7808 /* unknown frames can happen durning LNI, just count */
7812 }
7814 /* report remaining errors, but do not do anything */
7817 err));
7818 }
7820 /*
7821 * Handle host message flags.
7822 */
7824 /*
7825 * Presently, the driver does a busy wait for
7826 * host requests to complete. This is only an
7827 * informational message.
7828 * NOTE: The 8051 clears the host message
7829 * information *on the next 8051 command*.
7830 * Therefore, when linkup is achieved,
7831 * this flag will still be set.
7832 */
7834 }
7838 }
7843 }
7847 }
7851 }
7854 /* no downgrade action needed if going down */
7858 }
7862 }
7866 }
7868 /* report remaining messages, but do not do anything */
7872 host_msg));
7873 }
7876 }
7878 /*
7879 * Lost the 8051 heartbeat. If this happens, we
7880 * receive constant interrupts about it. Disable
7881 * the interrupt after the first.
7882 */
7889 }
7891 /* report the error, but do not do anything */
7894 }
7897 /*
7898 * if the link is already going down or disabled, do not
7899 * queue another. If there's a link down entry already
7900 * queued, don't queue another one.
7901 */
7912 __func__);
7913 else
7915 }
7916 }
7917 }
7934 /* no 7 */
7937 };
7947 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7960 };
7962 #define OPA_LDR_FMCONFIG_OFFSET 16
7963 #define OPA_LDR_PORTRCV_OFFSET 0
7965 {
7977 /* set status bit */
7979 }
7981 }
7985 /* this counter saturates at (2^32) - 1 */
7989 }
7997 /* set status bit */
7999 }
8013 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
8015 /*
8016 * lcl_reason cannot be derived from info
8017 * for this error
8018 */
8019 lcl_reason =
8020 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
8021 }
8028 }
8034 }
8036 /* just report this */
8038 extra);
8040 }
8049 OPA_EI_STATUS_SMASK)) {
8052 /* set status bit */
8054 OPA_EI_STATUS_SMASK;
8055 /*
8056 * save first 2 flits in the packet that caused
8057 * the error
8058 */
8061 }
8080 }
8086 }
8088 /* just report this */
8094 }
8097 /* informative only */
8100 }
8102 /* informative only */
8105 }
8110 /* report any remaining errors */
8120 __func__);
8123 }
8124 }
8127 {
8132 }
8134 /*
8135 * CCE block DC interrupt. Source is < 8.
8136 */
8138 {
8144 /*
8145 * This indicates that a parity error has occurred on the
8146 * address/control lines presented to the LBM. The error
8147 * is a single pulse, there is no associated error flag,
8148 * and it is non-maskable. This is because if a parity
8149 * error occurs on the request the request is dropped.
8150 * This should never occur, but it is nice to know if it
8151 * ever does.
8152 */
8156 }
8157 }
8159 /*
8160 * TX block send credit interrupt. Source is < 160.
8161 */
8163 {
8165 }
8167 /*
8168 * TX block SDMA interrupt. Source is < 48.
8169 *
8170 * SDMA interrupts are grouped by type:
8171 *
8172 * 0 - N-1 = SDma
8173 * N - 2N-1 = SDmaProgress
8174 * 2N - 3N-1 = SDmaIdle
8175 */
8177 {
8178 /* what interrupt */
8180 /* which engine */
8183 #ifdef CONFIG_SDMA_VERBOSITY
8187 #endif
8192 /* should not happen */
8194 }
8195 }
8197 /**
8198 * is_rcv_avail_int() - User receive context available IRQ handler
8199 * @dd: valid dd
8200 * @source: logical IRQ source (offset from IS_RCVAVAIL_START)
8201 *
8202 * RX block receive available interrupt. Source is < 160.
8203 *
8204 * This is the general interrupt handler for user (PSM) receive contexts,
8205 * and can only be used for non-threaded IRQs.
8206 */
8208 {
8218 }
8219 /* received an interrupt, but no rcd */
8222 /* received an interrupt, but are not using that context */
8224 }
8227 }
8229 /**
8230 * is_rcv_urgent_int() - User receive context urgent IRQ handler
8231 * @dd: valid dd
8232 * @source: logical IRQ source (offset from IS_RCVURGENT_START)
8233 *
8234 * RX block receive urgent interrupt. Source is < 160.
8235 *
8236 * NOTE: kernel receive contexts specifically do NOT enable this IRQ.
8237 */
8239 {
8249 }
8250 /* received an interrupt, but no rcd */
8253 /* received an interrupt, but are not using that context */
8255 }
8258 }
8260 /*
8261 * Reserved range interrupt. Should not be called in normal operation.
8262 */
8264 {
8269 }
8272 /*
8273 * start end
8274 * name func interrupt func
8275 */
8296 };
8298 /*
8299 * Interrupt source interrupt - called when the given source has an interrupt.
8300 * Source is a bit index into an array of 64-bit integers.
8301 */
8303 {
8306 /* avoids a double compare by walking the table in-order */
8312 }
8313 }
8314 /* fell off the end */
8316 }
8318 /**
8319 * gerneral_interrupt() - General interrupt handler
8320 * @irq: MSIx IRQ vector
8321 * @data: hfi1 devdata
8322 *
8323 * This is able to correctly handle all non-threaded interrupts. Receive
8324 * context DATA IRQs are threaded and are not supported by this handler.
8325 *
8326 */
8328 {
8331 u32 bit;
8337 /* phase 1: scan and clear all handled interrupts */
8342 }
8345 /* only clear if anything is set */
8348 }
8350 /* phase 2: call the appropriate handler */
8355 }
8358 }
8361 {
8364 u64 status;
8366 #ifdef CONFIG_SDMA_VERBOSITY
8370 #endif
8374 /* This read_csr is really bad in the hot path */
8379 /* clear the interrupt(s) */
8382 status);
8384 /* handle the interrupt(s) */
8389 }
8391 }
8393 /*
8394 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8395 * to insure that the write completed. This does NOT guarantee that
8396 * queued DMA writes to memory from the chip are pushed.
8397 */
8399 {
8404 /* force the above write on the chip and get a value back */
8406 }
8408 /* force the receive interrupt */
8410 {
8412 }
8414 /*
8415 * Return non-zero if a packet is present.
8416 *
8417 * This routine is called when rechecking for packets after the RcvAvail
8418 * interrupt has been cleared down. First, do a quick check of memory for
8419 * a packet present. If not found, use an expensive CSR read of the context
8420 * tail to determine the actual tail. The CSR read is necessary because there
8421 * is no method to push pending DMAs to memory other than an interrupt and we
8422 * are trying to determine if we need to force an interrupt.
8423 */
8425 {
8426 u32 tail;
8431 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8434 }
8436 /**
8437 * Common code for receive contexts interrupt handlers.
8438 * Update traces, increment kernel IRQ counter and
8439 * setup ASPM when needed.
8440 */
8442 {
8448 }
8450 /**
8451 * __hfi1_rcd_eoi_intr() - Make HW issue receive interrupt
8452 * when there are packets present in the queue. When calling
8453 * with interrupts enabled please use hfi1_rcd_eoi_intr.
8454 *
8455 * @rcd: valid receive context
8456 */
8458 {
8462 }
8464 /**
8465 * hfi1_rcd_eoi_intr() - End of Interrupt processing action
8466 *
8467 * @rcd: Ptr to hfi1_ctxtdata of receive context
8468 *
8469 * Hold IRQs so we can safely clear the interrupt and
8470 * recheck for a packet that may have arrived after the previous
8471 * check and the interrupt clear. If a packet arrived, force another
8472 * interrupt. This routine can be called at the end of receive packet
8473 * processing in interrupt service routines, interrupt service thread
8474 * and softirqs
8475 */
8477 {
8483 }
8485 /**
8486 * hfi1_netdev_rx_napi - napi poll function to move eoi inline
8487 * @napi - pointer to napi object
8488 * @budget - netdev budget
8489 */
8491 {
8502 }
8505 }
8507 /* Receive packet napi handler for netdevs VNIC and AIP */
8509 {
8517 else
8523 }
8526 }
8528 /*
8529 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8530 * This routine will try to handle packets immediately (latency), but if
8531 * it finds too many, it will invoke the thread handler (bandwitdh). The
8532 * chip receive interrupt is *not* cleared down until this or the thread (if
8533 * invoked) is finished. The intent is to avoid extra interrupts while we
8534 * are processing packets anyway.
8535 */
8537 {
8543 /* receive interrupt remains blocked while processing packets */
8546 /*
8547 * Too many packets were seen while processing packets in this
8548 * IRQ handler. Invoke the handler thread. The receive interrupt
8549 * remains blocked.
8550 */
8556 }
8558 /*
8559 * Receive packet thread handler. This expects to be invoked with the
8560 * receive interrupt still blocked.
8561 */
8563 {
8566 /* receive interrupt is still blocked from the IRQ handler */
8572 }
8574 /* ========================================================================= */
8577 {
8578 u64 reg;
8583 }
8586 {
8587 u64 reg;
8592 }
8595 {
8596 u64 reg;
8599 /* clear current state, set new state */
8603 }
8605 /*
8606 * Use the 8051 to read a LCB CSR.
8607 */
8609 {
8610 u32 regno;
8618 }
8620 }
8622 /* register is an index of LCB registers: (offset - base) / 8 */
8628 }
8630 /*
8631 * Provide a cache for some of the LCB registers in case the LCB is
8632 * unavailable.
8633 * (The LCB is unavailable in certain link states, for example.)
8634 */
8636 u32 off;
8637 u64 val;
8638 };
8644 };
8647 {
8650 u64 val;
8655 /* Update if we get good data */
8658 }
8659 }
8662 {
8669 }
8670 }
8674 }
8676 /*
8677 * Read an LCB CSR. Access may not be in host control, so check.
8678 * Return 0 on success, -EBUSY on failure.
8679 */
8681 {
8684 /* if up, go through the 8051 for the value */
8687 /* if going up or down, check the cache, otherwise, no access */
8692 }
8694 /* otherwise, host has access */
8697 }
8699 /*
8700 * Use the 8051 to write a LCB CSR.
8701 */
8703 {
8704 u32 regno;
8713 }
8715 }
8717 /* register is an index of LCB registers: (offset - base) / 8 */
8723 }
8725 /*
8726 * Write an LCB CSR. Access may not be in host control, so check.
8727 * Return 0 on success, -EBUSY on failure.
8728 */
8730 {
8733 /* if up, go through the 8051 for the value */
8736 /* if going up or down, no access */
8739 /* otherwise, host has access */
8742 }
8744 /*
8745 * Returns:
8746 * < 0 = Linux error, not able to get access
8747 * > 0 = 8051 command RETURN_CODE
8748 */
8751 {
8760 /* We can't send any commands to the 8051 if it's in reset */
8764 }
8766 /*
8767 * If an 8051 host command timed out previously, then the 8051 is
8768 * stuck.
8769 *
8770 * On first timeout, attempt to reset and restart the entire DC
8771 * block (including 8051). (Is this too big of a hammer?)
8772 *
8773 * If the 8051 times out a second time, the reset did not bring it
8774 * back to healthy life. In that case, fail any subsequent commands.
8775 */
8780 type);
8783 }
8786 }
8788 /*
8789 * If there is no timeout, then the 8051 command interface is
8790 * waiting for a command.
8791 */
8793 /*
8794 * When writing a LCB CSR, out_data contains the full value to
8795 * to be written, while in_data contains the relative LCB
8796 * address in 7:0. Do the work here, rather than the caller,
8797 * of distrubting the write data to where it needs to go:
8798 *
8799 * Write data
8800 * 39:00 -> in_data[47:8]
8801 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8802 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8803 */
8806 /* must preserve COMPLETED - it is tied to hardware */
8810 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8812 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8814 }
8816 /*
8817 * Do two writes: the first to stabilize the type and req_data, the
8818 * second to activate.
8819 */
8821 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8828 /* wait for completion, alternate: interrupt */
8842 }
8844 }
8850 /* top 16 bits are in a different register */
8855 }
8856 }
8860 /*
8861 * Clear command for next user.
8862 */
8865 fail:
8868 }
8871 {
8873 }
8877 {
8878 u64 data;
8889 }
8891 }
8893 /*
8894 * Read the 8051 firmware "registers". Use the RAM directly. Always
8895 * set the result, even on error.
8896 * Return 0 on success, -errno on failure
8897 */
8900 {
8901 u64 big_data;
8902 u32 addr;
8905 /* address start depends on the lane_id */
8909 else
8913 /* read is in 8-byte chunks, hardware will truncate the address down */
8917 /* extract the 4 bytes we want */
8920 else
8926 }
8929 }
8932 u8 continuous)
8933 {
8934 u32 frame;
8940 }
8944 {
8945 u32 frame;
8954 }
8958 {
8959 u32 frame;
8966 }
8969 u8 misc_bits,
8970 u8 flag_bits,
8971 u16 link_widths)
8972 {
8973 u32 frame;
8979 frame);
8980 }
8983 u8 device_rev)
8984 {
8985 u32 frame;
8990 }
8994 {
8995 u32 frame;
9001 }
9004 {
9005 u32 frame;
9006 u32 mask;
9010 /* Clear, then set field */
9014 frame);
9015 }
9019 {
9020 u32 frame;
9024 STS_FM_VERSION_MAJOR_MASK;
9026 STS_FM_VERSION_MINOR_MASK;
9030 STS_FM_VERSION_PATCH_MASK;
9031 }
9035 {
9036 u32 frame;
9043 }
9047 {
9048 u32 frame;
9056 }
9061 {
9062 u32 frame;
9069 }
9072 {
9073 u32 frame;
9077 }
9080 {
9082 }
9085 {
9087 }
9090 {
9091 u32 frame;
9101 }
9102 }
9105 {
9106 u32 frame;
9110 }
9113 {
9114 u32 frame;
9118 }
9125 {
9126 u32 frame;
9138 }
9141 u8 enable_lane_tx,
9142 u8 tx_polarity_inversion,
9143 u8 rx_polarity_inversion,
9144 u8 max_rate)
9145 {
9146 u32 frame;
9148 /* no need to mask, all variable sizes match field widths */
9154 }
9156 /*
9157 * Read an idle LCB message.
9158 *
9159 * Returns 0 on success, -EINVAL on error
9160 */
9162 {
9170 }
9172 /* return only the payload as we already know the type */
9175 }
9177 /*
9178 * Read an idle SMA message. To be done in response to a notification from
9179 * the 8051.
9180 *
9181 * Returns 0 on success, -EINVAL on error
9182 */
9184 {
9186 data);
9187 }
9189 /*
9190 * Send an idle LCB message.
9191 *
9192 * Returns 0 on success, -EINVAL on error
9193 */
9195 {
9204 }
9206 }
9208 /*
9209 * Send an idle SMA message.
9210 *
9211 * Returns 0 on success, -EINVAL on error
9212 */
9214 {
9215 u64 data;
9220 }
9222 /*
9223 * Initialize the LCB then do a quick link up. This may or may not be
9224 * in loopback.
9225 *
9226 * return 0 on success, -errno on error
9227 */
9229 {
9235 /* LCB_CFG_LOOPBACK.VAL = 2 */
9236 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9240 }
9242 /* start the LCBs */
9243 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9246 /* simulator only loopback steps */
9248 /* LCB_CFG_RUN.EN = 1 */
9258 }
9261 /*
9262 * When doing quick linkup and not in loopback, both
9263 * sides must be done with LCB set-up before either
9264 * starts the quick linkup. Put a delay here so that
9265 * both sides can be started and have a chance to be
9266 * done with LCB set up before resuming.
9267 */
9272 }
9277 /*
9278 * State "quick" LinkUp request sets the physical link state to
9279 * LinkUp without a verify capability sequence.
9280 * This state is in simulator v37 and later.
9281 */
9294 }
9297 }
9299 /*
9300 * Do all special steps to set up loopback.
9301 */
9303 {
9306 /* all loopbacks should disable self GUID check */
9310 /*
9311 * The simulator has only one loopback option - LCB. Switch
9312 * to that option, which includes quick link up.
9313 *
9314 * Accept all valid loopback values.
9315 */
9322 }
9324 /*
9325 * SerDes loopback init sequence is handled in set_local_link_attributes
9326 */
9330 /* LCB loopback - handled at poll time */
9334 /* not supported in emulation due to emulation RTL changes */
9339 }
9341 }
9343 /* external cable loopback requires no extra steps */
9349 }
9351 /*
9352 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9353 * used in the Verify Capability link width attribute.
9354 */
9356 {
9361 u16 from;
9362 u16 to;
9368 };
9373 }
9375 }
9377 /*
9378 * Set link attributes before moving to polling.
9379 */
9381 {
9383 u8 enable_lane_tx;
9384 u8 tx_polarity_inversion;
9385 u8 rx_polarity_inversion;
9388 /* reset our fabric serdes to clear any lingering problems */
9391 /* set the local tx rate - need to read-modify-write */
9398 /* set the tx rate to the fastest enabled */
9401 else
9404 /* set the tx rate to all enabled */
9410 }
9422 ret);
9424 }
9426 /*
9427 * DC supports continuous updates.
9428 */
9435 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9441 /*
9442 * SerDes loopback init sequence requires
9443 * setting bit 0 of MISC_CONFIG_BITS
9444 */
9448 /*
9449 * An external device configuration request is used to reset the LCB
9450 * to retry to obtain operational lanes when the first attempt is
9451 * unsuccesful.
9452 */
9462 /* let peer know who we are */
9467 set_local_link_attributes_fail:
9470 ret);
9472 }
9474 /*
9475 * Call this to start the link.
9476 * Do not do anything if the link is disabled.
9477 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9478 */
9480 {
9481 /*
9482 * Tune the SerDes to a ballpark setting for optimal signal and bit
9483 * error rate. Needs to be done before starting the link.
9484 */
9490 __func__);
9492 }
9494 /*
9495 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9496 * pkey table can be configured properly if the HFI unit is connected
9497 * to switch port with MgmtAllowed=NO
9498 */
9502 }
9505 {
9507 u64 mask;
9510 /*
9511 * Some QSFP cables have a quirk that asserts the IntN line as a side
9512 * effect of power up on plug-in. We ignore this false positive
9513 * interrupt until the module has finished powering up by waiting for
9514 * a minimum timeout of the module inrush initialization time of
9515 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9516 * module have stabilized.
9517 */
9520 /*
9521 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9522 */
9531 __func__);
9533 }
9535 }
9536 }
9539 {
9541 u64 mask;
9545 /*
9546 * Clear the status register to avoid an immediate interrupt
9547 * when we re-enable the IntN pin
9548 */
9550 QSFP_HFI0_INT_N);
9554 }
9556 }
9559 {
9563 /* Disable INT_N from triggering QSFP interrupts */
9566 /* Reset the QSFP */
9583 /*
9584 * Allow INT_N to trigger the QSFP interrupt to watch
9585 * for alarms and warnings
9586 */
9589 /*
9590 * After the reset, AOC transmitters are enabled by default. They need
9591 * to be turned off to complete the QSFP setup before they can be
9592 * enabled again.
9593 */
9595 }
9599 {
9605 __func__);
9610 __func__);
9612 /*
9613 * The remaining alarms/warnings don't matter if the link is down.
9614 */
9621 __func__);
9626 __func__);
9628 /* Byte 2 is vendor specific */
9633 __func__);
9638 __func__);
9643 __func__);
9648 __func__);
9653 __func__);
9658 __func__);
9663 __func__);
9668 __func__);
9673 __func__);
9678 __func__);
9683 __func__);
9688 __func__);
9690 /* Bytes 9-10 and 11-12 are reserved */
9691 /* Bytes 13-15 are vendor specific */
9694 }
9696 /* This routine will only be scheduled if the QSFP module present is asserted */
9698 {
9707 /* Sanity check */
9714 __func__);
9716 }
9718 /*
9719 * Turn DC back on after cable has been re-inserted. Up until
9720 * now, the DC has been in reset to save power.
9721 */
9729 /*
9730 * Allow INT_N to trigger the QSFP interrupt to watch
9731 * for alarms and warnings
9732 */
9736 }
9745 __func__);
9754 flags);
9755 }
9756 }
9757 }
9760 {
9762 u64 qsfp_mask;
9765 /* Clear current status to avoid spurious interrupts */
9767 qsfp_mask);
9769 qsfp_mask);
9773 /* Handle active low nature of INT_N and MODPRST_N pins */
9778 qsfp_mask);
9780 /* Enable the appropriate QSFP IRQ source */
9783 else
9785 }
9787 /*
9788 * Do a one-time initialize of the LCB block.
9789 */
9791 {
9792 /* simulator does not correctly handle LCB cclk loopback, skip */
9796 /* the DC has been reset earlier in the driver load */
9798 /* set LCB for cclk loopback on the port */
9806 }
9808 /*
9809 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9810 * on error.
9811 */
9813 {
9815 u8 status;
9817 /*
9818 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9819 * not present
9820 */
9824 /* read byte 2, the status byte */
9832 }
9834 /*
9835 * Values for QSFP retry.
9836 *
9837 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9838 * arrived at from experience on a large cluster.
9839 */
9840 #define MAX_QSFP_RETRIES 20
9843 /*
9844 * Try a QSFP read. If it fails, schedule a retry for later.
9845 * Called on first link activation after driver load.
9846 */
9848 {
9850 /* read failed */
9854 }
9862 }
9866 }
9868 /*
9869 * Workqueue function to start the link after a delay.
9870 */
9872 {
9876 }
9879 {
9881 u64 guid;
9892 }
9894 /* Set linkinit_reason on power up per OPA spec */
9897 /* one-time init of the LCB */
9904 }
9911 }
9915 }
9918 {
9921 /*
9922 * Shut down the link and keep it down. First turn off that the
9923 * driver wants to allow the link to be up (driver_link_ready).
9924 * Then make sure the link is not automatically restarted
9925 * (link_enabled). Cancel any pending restart. And finally
9926 * go offline.
9927 */
9938 OPA_LINKDOWN_REASON_REBOOT);
9941 /* disable the port */
9944 }
9947 {
9962 }
9965 }
9967 /*
9968 * index is the index into the receive array
9969 */
9972 {
9973 u64 reg;
9986 }
9990 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9998 /*
9999 * Eager entries are written and flushed
10000 *
10001 * Expected entries are flushed every 4 writes
10002 */
10004 done:
10006 }
10009 {
10011 u32 i;
10013 /* this could be optimized */
10021 }
10045 "HFI1_IB_CFG_PORT"
10046 };
10049 {
10053 }
10056 {
10101 unimplemented:
10104 dd,
10106 __func__,
10109 }
10112 }
10114 /*
10115 * The largest MAD packet size.
10116 */
10117 #define MAX_MAD_PACKET 2048
10119 /*
10120 * Return the maximum header bytes that can go on the _wire_
10121 * for this device. This count includes the ICRC which is
10122 * not part of the packet held in memory but it is appended
10123 * by the HW.
10124 * This is dependent on the device's receive header entry size.
10125 * HFI allows this to be set per-receive context, but the
10126 * driver presently enforces a global value.
10127 */
10129 {
10130 /*
10131 * The maximum non-payload (MTU) bytes in LRH.PktLen are
10132 * the Receive Header Entry Size minus the PBC (or RHF) size
10133 * plus one DW for the ICRC appended by HW.
10134 *
10135 * dd->rcd[0].rcvhdrqentsize is in DW.
10136 * We use rcd[0] as all context will have the same value. Also,
10137 * the first kernel context would have been allocated by now so
10138 * we are guaranteed a valid value.
10139 */
10141 }
10143 /*
10144 * Set Send Length
10145 * @ppd - per port data
10146 *
10147 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
10148 * registers compare against LRH.PktLen, so use the max bytes included
10149 * in the LRH.
10150 *
10151 * This routine changes all VL values except VL15, which it maintains at
10152 * the same value.
10153 */
10155 {
10161 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
10163 u32 thres;
10172 else
10176 }
10179 /* adjust kernel credit return thresholds based on new MTUs */
10180 /* all kernel receive contexts have the same hdrqentsize */
10189 thres);
10190 }
10197 /* Adjust maximum MTU for the port in DC */
10203 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10205 }
10208 {
10214 u32 lid;
10216 /*
10217 * Program 0 in CSR if port lid is extended. This prevents
10218 * 9B packets being sent out for large lids.
10219 */
10221 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10229 /*
10230 * Iterate over all the send contexts and set their SLID check
10231 */
10233 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10235 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10241 }
10243 /* Now we have to do the same thing for the sdma engines */
10245 }
10248 {
10252 "VerifyCap"
10253 };
10259 }
10277 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10282 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10289 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10296 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10302 };
10305 u32 code)
10306 {
10315 }
10317 /* describe the given last state complete frame */
10320 {
10322 u32 success;
10323 u32 state;
10324 u32 reason;
10325 u32 lanes;
10327 /*
10328 * Decode frame:
10329 * [ 0: 0] - success
10330 * [ 3: 1] - state
10331 * [ 7: 4] - next state timeout
10332 * [15: 8] - reason code
10333 * [31:16] - lanes
10334 */
10349 }
10351 /*
10352 * Read the last state complete frames and explain them. This routine
10353 * expects to be called if the link went down during link negotiation
10354 * and initialization (LNI). That is, anywhere between polling and link up.
10355 */
10357 {
10358 u32 last_local_state;
10359 u32 last_remote_state;
10364 /*
10365 * Don't report anything if there is nothing to report. A value of
10366 * 0 means the link was taken down while polling and there was no
10367 * training in-process.
10368 */
10374 }
10376 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10378 {
10379 u64 reg;
10382 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10392 }
10394 }
10396 }
10398 /* called when the logical link state is not down as it should be */
10400 {
10403 /*
10404 * Bring link up in LCB loopback
10405 */
10408 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10423 /*
10424 * Bring the link down again.
10425 */
10431 }
10433 /*
10434 * Helper for set_link_state(). Do not call except from that routine.
10435 * Expects ppd->hls_mutex to be held.
10436 *
10437 * @rem_reason value to be sent to the neighbor
10438 *
10439 * LinkDownReasons only set if transition succeeds.
10440 */
10442 {
10444 u32 previous_state;
10453 /* start offline transition */
10459 ret);
10461 }
10471 /* Disabling AOC transmitters */
10482 /* not fatal, but should warn */
10485 }
10486 }
10488 /*
10489 * Wait for the offline.Quiet transition if it hasn't happened yet. It
10490 * can take a while for the link to go down.
10491 */
10496 }
10498 /*
10499 * Now in charge of LCB - must be after the physical state is
10500 * offline.quiet and before host_link_state is changed.
10501 */
10505 /* make sure the logical state is also down */
10513 /*
10514 * The LNI has a mandatory wait time after the physical state
10515 * moves to Offline.Quiet. The wait time may be different
10516 * depending on how the link went down. The 8051 firmware
10517 * will observe the needed wait time and only move to ready
10518 * when that is completed. The largest of the quiet timeouts
10519 * is 6s, so wait that long and then at least 0.5s more for
10520 * other transitions, and another 0.5s for a buffer.
10521 */
10525 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10526 /* state is really offline, so make it so */
10529 }
10531 /*
10532 * The state is now offline and the 8051 is ready to accept host
10533 * requests.
10534 * - change our state
10535 * - notify others if we were previously in a linkup state
10536 */
10539 /* went down while link was up */
10543 /* went down while attempting link up */
10546 /* The QSFP doesn't need to be reset on LNI failure */
10548 }
10550 /* the active link width (downgrade) is 0 on link down */
10556 }
10558 /* return the link state name */
10560 {
10575 };
10579 }
10581 /* return the link state reason name */
10583 {
10598 }
10599 }
10601 }
10603 /*
10604 * driver_pstate - convert the driver's notion of a port's
10605 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10606 * Return -1 (converted to a u32) to indicate error.
10607 */
10609 {
10634 }
10635 }
10637 /*
10638 * driver_lstate - convert the driver's notion of a port's
10639 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10640 * (converted to a u32) to indicate error.
10641 */
10643 {
10658 }
10659 }
10663 {
10669 }
10670 }
10672 /**
10673 * data_vls_operational() - Verify if data VL BCT credits and MTU
10674 * are both set.
10675 * @ppd: pointer to hfi1_pportdata structure
10676 *
10677 * Return: true - Ok, false -otherwise.
10678 */
10680 {
10682 u64 reg;
10692 }
10695 }
10697 /*
10698 * Change the physical and/or logical link state.
10699 *
10700 * Do not call this routine while inside an interrupt. It contains
10701 * calls to routines that can take multiple seconds to finish.
10702 *
10703 * Returns 0 on success, -errno on failure.
10704 */
10706 {
10718 /* interpret poll -> poll as a link bounce */
10728 /*
10729 * If we're going to a (HLS_*) link state that implies the logical
10730 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10731 * reset is_sm_config_started to 0.
10732 */
10736 /*
10737 * Do nothing if the states match. Let a poll to poll link bounce
10738 * go through.
10739 */
10747 /*
10748 * Quick link up jumps from polling to here.
10749 *
10750 * Whether in normal or loopback mode, the
10751 * simulator jumps from polling to link up.
10752 * Accept that here.
10753 */
10754 /* OK */
10757 }
10759 /*
10760 * Wait for Link_Up physical state.
10761 * Physical and Logical states should already be
10762 * be transitioned to LinkUp and LinkInit respectively.
10763 */
10768 __func__);
10770 }
10776 __func__);
10778 }
10780 /* clear old transient LINKINIT_REASON code */
10783 OPA_LINKINIT_REASON_LINKUP;
10785 /* enable the port */
10791 /*
10792 * After link up, a new link width will have been set.
10793 * Update the xmit counters with regards to the new
10794 * link width.
10795 */
10808 __func__);
10811 }
10818 __func__);
10820 }
10823 /*
10824 * The simulator does not currently implement SMA messages,
10825 * so neighbor_normal is not set. Set it here when we first
10826 * move to Armed.
10827 */
10840 __func__);
10842 /* tell all engines to go running */
10847 /* Signal the IB layer that the port has went active */
10851 }
10858 /* Hand LED control to the DC */
10868 }
10873 }
10883 /* quick linkup does not go into polling */
10893 ret1);
10895 }
10896 }
10898 /*
10899 * Change the host link state after requesting DC8051 to
10900 * change its physical state so that we can ignore any
10901 * interrupt with stale LNI(XX) error, which will not be
10902 * cleared until DC8051 transitions to Polling state.
10903 */
10907 /*
10908 * If an error occurred above, go back to offline. The
10909 * caller may reschedule another attempt.
10910 */
10913 else
10917 /* link is disabled */
10920 /* allow any state to transition to disabled */
10922 /* must transition to offline first */
10928 }
10935 ret1);
10938 }
10943 __func__);
10945 }
10947 }
10954 /* allow any state to transition to offline */
10973 ret1);
10976 }
10987 }
10991 unexpected:
10997 done:
11004 }
11007 {
11008 u64 reg;
11016 /*
11017 * The VL Arbitrator high limit is sent in units of 4k
11018 * bytes, while HFI stores it in units of 64 bytes.
11019 */
11026 /* HFI only supports POLL as the default link down state */
11035 }
11037 /*
11038 * For link width, link width downgrade, and speed enable, always AND
11039 * the setting with what is actually supported. This has two benefits.
11040 * First, enabled can't have unsupported values, no matter what the
11041 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
11042 * "fill in with your supported value" have all the bits in the
11043 * field set, so simply ANDing with supported has the desired result.
11044 */
11056 /*
11057 * HFI does not follow IB specs, save this value
11058 * so we can report it, if asked.
11059 */
11063 /*
11064 * HFI does not follow IB specs, save this value
11065 * so we can report it, if asked.
11066 */
11085 }
11087 }
11089 /* begin functions related to vl arbitration table caching */
11091 {
11095 VL_ARB_LOW_PRIO_TABLE_SIZE);
11097 VL_ARB_HIGH_PRIO_TABLE_SIZE);
11099 /*
11100 * Note that we always return values directly from the
11101 * 'vl_arb_cache' (and do no CSR reads) in response to a
11102 * 'Get(VLArbTable)'. This is obviously correct after a
11103 * 'Set(VLArbTable)', since the cache will then be up to
11104 * date. But it's also correct prior to any 'Set(VLArbTable)'
11105 * since then both the cache, and the relevant h/w registers
11106 * will be zeroed.
11107 */
11111 }
11113 /*
11114 * vl_arb_lock_cache
11115 *
11116 * All other vl_arb_* functions should be called only after locking
11117 * the cache.
11118 */
11121 {
11126 }
11129 {
11131 }
11135 {
11137 }
11141 {
11143 }
11147 {
11149 }
11151 /* end functions related to vl arbitration table caching */
11155 {
11157 u64 reg;
11169 /*
11170 * Before adjusting VL arbitration weights, empty per-VL
11171 * FIFOs, otherwise a packet whose VL weight is being
11172 * set to 0 could get stuck in a FIFO with no chance to
11173 * egress.
11174 */
11179 dd,
11181 __func__);
11183 }
11186 /*
11187 * NOTE: The low priority shift and mask are used here, but
11188 * they are the same for both the low and high registers.
11189 */
11196 }
11202 err:
11206 }
11208 /*
11209 * Read one credit merge VL register.
11210 */
11213 {
11222 }
11224 /*
11225 * Read the current credit merge limits.
11226 */
11229 {
11230 u64 reg;
11233 /* not all entries are filled in */
11236 /* OPA and HFI have a 1-1 mapping */
11240 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
11252 }
11255 {
11256 u64 reg;
11259 /* each register contains 16 SC->VLnt mappings, 4 bits each */
11266 }
11274 }
11276 }
11280 {
11286 }
11287 }
11290 {
11327 }
11330 u16 limit)
11331 {
11335 }
11337 /* change only the shared limit portion of SendCmGLobalCredit */
11339 {
11340 u64 reg;
11346 }
11348 /* change only the total credit limit portion of SendCmGLobalCredit */
11350 {
11351 u64 reg;
11357 }
11359 /* set the given per-VL shared limit */
11361 {
11362 u64 reg;
11363 u32 addr;
11367 else
11374 }
11376 /* set the given per-VL dedicated limit */
11378 {
11379 u64 reg;
11380 u32 addr;
11384 else
11391 }
11393 /* spin until the given per-VL status mask bits clear */
11396 {
11398 u64 reg;
11409 }
11414 /*
11415 * If this occurs, it is likely there was a credit loss on the link.
11416 * The only recovery from that is a link bounce.
11417 */
11420 }
11422 /*
11423 * The number of credits on the VLs may be changed while everything
11424 * is "live", but the following algorithm must be followed due to
11425 * how the hardware is actually implemented. In particular,
11426 * Return_Credit_Status[] is the only correct status check.
11427 *
11428 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11429 * set Global_Shared_Credit_Limit = 0
11430 * use_all_vl = 1
11431 * mask0 = all VLs that are changing either dedicated or shared limits
11432 * set Shared_Limit[mask0] = 0
11433 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11434 * if (changing any dedicated limit)
11435 * mask1 = all VLs that are lowering dedicated limits
11436 * lower Dedicated_Limit[mask1]
11437 * spin until Return_Credit_Status[mask1] == 0
11438 * raise Dedicated_Limits
11439 * raise Shared_Limits
11440 * raise Global_Shared_Credit_Limit
11441 *
11442 * lower = if the new limit is lower, set the limit to the new value
11443 * raise = if the new limit is higher than the current value (may be changed
11444 * earlier in the algorithm), set the new limit to the new value
11445 */
11448 {
11455 /*
11456 * A0: add the variable any_shared_limit_changing below and in the
11457 * algorithm above. If removing A0 support, it can be removed.
11458 */
11463 u16 cur_total;
11466 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11467 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11468 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11469 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11470 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11471 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11472 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11473 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11476 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11479 /* find the new total credits, do sanity check on unused VLs */
11484 }
11491 }
11494 /* fetch the current values */
11497 /*
11498 * Create the masks we will use.
11499 */
11502 /*
11503 * NOTE: Assumes that the individual VL bits are adjacent and in
11504 * increasing order
11505 */
11506 stat_mask =
11507 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11520 this_shared_changing) {
11523 change_count++;
11524 }
11529 }
11530 }
11532 /* bracket the credit change with a total adjustment */
11536 /*
11537 * Start the credit change algorithm.
11538 */
11546 }
11555 }
11556 }
11572 }
11573 }
11577 /* now raise all dedicated that are going up */
11587 }
11588 }
11590 /* next raise all shared that are going up */
11598 }
11600 /* finally raise the global shared */
11606 /* bracket the credit change with a total adjustment */
11610 /*
11611 * Determine the actual number of operational VLS using the number of
11612 * dedicated and shared credits for each VL.
11613 */
11618 vl_count++;
11623 NULL);
11630 }
11632 }
11634 /*
11635 * Read the given fabric manager table. Return the size of the
11636 * table (in bytes) on success, and a negative error code on
11637 * failure.
11638 */
11641 {
11648 /*
11649 * OPA specifies 128 elements (of 2 bytes each), though
11650 * HFI supports only 16 elements in h/w.
11651 */
11658 /*
11659 * OPA specifies 128 elements (of 2 bytes each), though
11660 * HFI supports only 16 elements in h/w.
11661 */
11674 /* OPA specifies 128 elements, of 2 bytes each */
11679 /*
11680 * OPA specifies that this is the same size as the VL
11681 * arbitration tables (i.e., 256 bytes).
11682 */
11686 }
11688 }
11690 /*
11691 * Write the given fabric manager table.
11692 */
11694 {
11704 }
11715 }
11729 }
11731 }
11733 /*
11734 * Disable all data VLs.
11735 *
11736 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11737 */
11739 {
11746 }
11748 /*
11749 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11750 * Just re-enables all data VLs (the "fill" part happens
11751 * automatically - the name was chosen for symmetry with
11752 * stop_drain_data_vls()).
11753 *
11754 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11755 */
11757 {
11764 }
11766 /*
11767 * drain_data_vls() - assumes that disable_data_vls() has been called,
11768 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11769 * engines to drop to 0.
11770 */
11772 {
11776 }
11778 /*
11779 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11780 *
11781 * Use open_fill_data_vls() to resume using data VLs. This pair is
11782 * meant to be used like this:
11783 *
11784 * stop_drain_data_vls(dd);
11785 * // do things with per-VL resources
11786 * open_fill_data_vls(dd);
11787 */
11789 {
11797 }
11799 /*
11800 * Convert a nanosecond time to a cclock count. No matter how slow
11801 * the cclock, a non-zero ns will always have a non-zero result.
11802 */
11804 {
11805 u32 cclocks;
11814 }
11816 /*
11817 * Convert a cclock count to nanoseconds. Not matter how slow
11818 * the cclock, a non-zero cclocks will always have a non-zero result.
11819 */
11821 {
11822 u32 ns;
11831 }
11833 /*
11834 * Dynamically adjust the receive interrupt timeout for a context based on
11835 * incoming packet rate.
11836 *
11837 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11838 */
11840 {
11844 /*
11845 * This algorithm doubles or halves the timeout depending on whether
11846 * the number of packets received in this interrupt were less than or
11847 * greater equal the interrupt count.
11848 *
11849 * The calculations below do not allow a steady state to be achieved.
11850 * Only at the endpoints it is possible to have an unchanging
11851 * timeout.
11852 */
11854 /*
11855 * Not enough packets arrived before the timeout, adjust
11856 * timeout downward.
11857 */
11862 /*
11863 * More than enough packets arrived before the timeout, adjust
11864 * timeout upward.
11865 */
11869 }
11872 /*
11873 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11874 * been verified to be in range
11875 */
11878 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11879 }
11883 {
11885 u64 reg;
11888 /*
11889 * Need to write timeout register before updating RcvHdrHead to ensure
11890 * that a new value is used when the HW decides to restart counting.
11891 */
11898 }
11903 }
11906 {
11914 else
11918 }
11920 /*
11921 * Context Control and Receive Array encoding for buffer size:
11922 * 0x0 invalid
11923 * 0x1 4 KB
11924 * 0x2 8 KB
11925 * 0x3 16 KB
11926 * 0x4 32 KB
11927 * 0x5 64 KB
11928 * 0x6 128 KB
11929 * 0x7 256 KB
11930 * 0x8 512 KB (Receive Array only)
11931 * 0x9 1 MB (Receive Array only)
11932 * 0xa 2 MB (Receive Array only)
11933 *
11934 * 0xB-0xF - reserved (Receive Array only)
11935 *
11936 *
11937 * This routine assumes that the value has already been sanity checked.
11938 */
11940 {
11952 }
11954 }
11956 /**
11957 * encode_rcv_header_entry_size - return chip specific encoding for size
11958 * @size: size in dwords
11959 *
11960 * Convert a receive header entry size that to the encoding used in the CSR.
11961 *
11962 * Return a zero if the given size is invalid, otherwise the encoding.
11963 */
11965 {
11966 /* there are only 3 valid receive header entry sizes */
11974 }
11976 /**
11977 * hfi1_validate_rcvhdrcnt - validate hdrcnt
11978 * @dd: the device data
11979 * @thecnt: the header count
11980 */
11982 {
11986 }
11991 HFI1_MAX_HDRQ_EGRBUF_CNT);
11993 }
11999 }
12002 }
12004 /**
12005 * set_hdrq_regs - set header queue registers for context
12006 * @dd: the device data
12007 * @ctxt: the context
12008 * @entsize: the dword entry size
12009 * @hdrcnt: the number of header entries
12010 */
12012 {
12013 u64 reg;
12016 RCV_HDR_CNT_CNT_SHIFT;
12019 RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) <<
12020 RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
12023 RCV_HDR_SIZE_HDR_SIZE_SHIFT;
12026 /*
12027 * Program dummy tail address for every receive context
12028 * before enabling any receive context
12029 */
12032 }
12036 {
12039 u16 ctxt;
12049 /* if the context already enabled, don't do the extra steps */
12052 /* reset the tail and hdr addresses, and sequence count */
12060 /* reset the cached receive header queue head value */
12063 /*
12064 * Zero the receive header queue so we don't get false
12065 * positives when checking the sequence number. The
12066 * sequence numbers could land exactly on the same spot.
12067 * E.g. a rcd restart before the receive header wrapped.
12068 */
12071 /* starting timeout */
12074 /* enable the context */
12077 /* clean the egr buffer size first */
12083 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
12087 /* zero RcvEgrIndexHead */
12090 /* set eager count and base index */
12099 /*
12100 * Set TID (expected) count and base index.
12101 * rcd->expected_count is set to individual RcvArray entries,
12102 * not pairs, and the CSR takes a pair-count in groups of
12103 * four, so divide by 8.
12104 */
12114 }
12117 /*
12118 * When receive context is being disabled turn on tail
12119 * update with a dummy tail address and then disable
12120 * receive context.
12121 */
12125 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
12127 }
12130 }
12135 }
12140 }
12144 /* See comment on RcvCtxtCtrl.TailUpd above */
12147 }
12153 /*
12154 * In one-packet-per-eager mode, the size comes from
12155 * the RcvArray entry.
12156 */
12159 }
12180 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
12194 }
12195 }
12198 /*
12199 * The interrupt timeout and count must be set after
12200 * the context is enabled to take effect.
12201 */
12202 /* set interrupt timeout */
12205 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
12207 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
12210 }
12213 /*
12214 * If the context has been disabled and the Tail Update has
12215 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
12216 * so it doesn't contain an address that is invalid.
12217 */
12220 }
12223 {
12236 /* Get the start of the block of counters */
12239 /*
12240 * Now go and fill in each counter in the block.
12241 */
12246 /* Nothing */
12254 CNTR_MODE_R,
12257 CNTR,
12261 val;
12262 }
12267 j++) {
12268 val =
12275 val;
12276 }
12279 CNTR_INVALID_VL,
12283 }
12284 }
12285 }
12286 }
12288 }
12290 /*
12291 * Used by sysfs to create files for hfi stats to read
12292 */
12294 {
12312 /* Nothing */
12315 }
12321 CNTR_MODE_R,
12324 CNTR,
12328 }
12331 CNTR_INVALID_VL,
12332 CNTR_MODE_R,
12336 }
12337 }
12338 }
12340 }
12343 {
12361 }
12373 }
12374 }
12378 {
12379 u64 val;
12385 }
12391 /* If its a synthetic counter there is more work we need to do */
12394 /* No need to read already saturated */
12396 }
12399 /* 32bit counters can wrap multiple times */
12406 else
12407 upper++;
12408 }
12414 /* If we rolled we are saturated */
12417 }
12418 }
12425 }
12430 {
12431 u64 val;
12436 }
12448 data);
12449 }
12452 }
12459 }
12462 {
12473 }
12476 {
12487 }
12490 {
12502 /* We do not want to bother for disabled contexts */
12504 }
12507 }
12510 {
12522 /* We do not want to bother for disabled contexts */
12524 }
12527 }
12530 {
12531 u64 cur_tx;
12532 u64 cur_rx;
12533 u64 total_flits;
12539 update_cntr_work);
12541 /*
12542 * Rather than keep beating on the CSRs pick a minimal set that we can
12543 * check to watch for potential roll over. We can do this by looking at
12544 * the number of flits sent/recv. If the total flits exceeds 32bits then
12545 * we have to iterate all the counters and update.
12546 */
12554 CNTR,
12559 /*
12560 * May not be strictly necessary to update but it won't hurt and
12561 * simplifies the logic here.
12562 */
12575 }
12576 }
12587 }
12588 }
12598 }
12599 }
12600 }
12602 /*
12603 * We want the value in the register. The goal is to keep track
12604 * of the number of "ticks" not the counter value. In other
12605 * words if the register rolls we want to notice it and go ahead
12606 * and force an update.
12607 */
12621 }
12622 }
12625 {
12630 }
12634 {
12644 /* set up the stats timer; the add_timer is done at the end */
12647 /***********************/
12648 /* per device counters */
12649 /***********************/
12651 /* size names and determine how many we have*/
12659 }
12667 /* Add ",32" for 32-bit counters */
12670 sz++;
12672 }
12679 /* Add ",32" for 32-bit counters */
12682 sz++;
12684 }
12686 /* +1 for newline. */
12688 /* Add ",32" for 32-bit counters */
12693 }
12694 }
12696 /* allocate space for the counter values */
12698 GFP_KERNEL);
12706 /* allocate space for the counter names */
12712 /* fill in the names */
12715 /* Nothing */
12724 /* Counter is 32 bits */
12728 }
12731 }
12739 /* Counter is 32 bits */
12743 }
12746 }
12751 /* Counter is 32 bits */
12755 }
12758 }
12759 }
12761 /*********************/
12762 /* per port counters */
12763 /*********************/
12765 /*
12766 * Go through the counters for the overflows and disable the ones we
12767 * don't need. This varies based on platform so we need to do it
12768 * dynamically here.
12769 */
12774 }
12776 /* size port counter names and determine how many we have*/
12783 }
12791 /* Add ",32" for 32-bit counters */
12794 sz++;
12796 }
12798 /* +1 for newline */
12800 /* Add ",32" for 32-bit counters */
12805 }
12806 }
12808 /* allocate space for the counter names */
12814 /* fill in port cntr names */
12826 /* Counter is 32 bits */
12830 }
12833 }
12839 /* Counter is 32 bits */
12843 }
12846 }
12847 }
12849 /* allocate per port storage for counter values */
12859 }
12861 /* CPU counters need to be allocated and zeroed */
12874 bail:
12877 }
12880 {
12893 chip_lstate);
12895 }
12896 }
12899 {
12900 /* look at the HFI meta-states only */
12916 chip_pstate);
12918 }
12919 }
12921 /* return the OPA port logical state name */
12923 {
12931 };
12935 }
12937 /* return the OPA port physical state name */
12939 {
12953 };
12957 }
12959 /**
12960 * update_statusp - Update userspace status flag
12961 * @ppd: Port data structure
12962 * @state: port state information
12963 *
12964 * Actual port status is determined by the host_link_state value
12965 * in the ppd.
12966 *
12967 * host_link_state MUST be updated before updating the user space
12968 * statusp.
12969 */
12971 {
12972 /*
12973 * Set port status flags in the page mapped into userspace
12974 * memory. Do it here to ensure a reliable state - this is
12975 * the only function called by all state handling code.
12976 * Always set the flags due to the fact that the cache value
12977 * might have been changed explicitly outside of this
12978 * function.
12979 */
12985 HFI1_STATUS_IB_READY);
12993 }
12994 }
12997 }
12999 /**
13000 * wait_logical_linkstate - wait for an IB link state change to occur
13001 * @ppd: port device
13002 * @state: the state to wait for
13003 * @msecs: the number of milliseconds to wait
13004 *
13005 * Wait up to msecs milliseconds for IB link state change to occur.
13006 * For now, take the easy polling route.
13007 * Returns 0 if state reached, otherwise -ETIMEDOUT.
13008 */
13011 {
13013 u32 new_state;
13024 state);
13026 }
13028 }
13031 }
13034 {
13040 }
13042 /*
13043 * Read the physical hardware link state and check if it matches host
13044 * drivers anticipated state.
13045 */
13047 {
13056 }
13057 }
13059 /*
13060 * wait_physical_linkstate - wait for an physical link state change to occur
13061 * @ppd: port device
13062 * @state: the state to wait for
13063 * @msecs: the number of milliseconds to wait
13064 *
13065 * Wait up to msecs milliseconds for physical link state change to occur.
13066 * Returns 0 if state reached, otherwise -ETIMEDOUT.
13067 */
13070 {
13071 u32 read_state;
13082 state);
13084 }
13086 }
13090 }
13092 /*
13093 * wait_phys_link_offline_quiet_substates - wait for any offline substate
13094 * @ppd: port device
13095 * @msecs: the number of milliseconds to wait
13096 *
13097 * Wait up to msecs milliseconds for any offline physical link
13098 * state change to occur.
13099 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
13100 */
13103 {
13104 u32 read_state;
13117 }
13119 }
13123 }
13125 /*
13126 * wait_phys_link_out_of_offline - wait for any out of offline state
13127 * @ppd: port device
13128 * @msecs: the number of milliseconds to wait
13129 *
13130 * Wait up to msecs milliseconds for any out of offline physical link
13131 * state change to occur.
13132 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
13133 */
13136 {
13137 u32 read_state;
13150 }
13152 }
13156 }
13158 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
13159 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
13161 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
13162 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
13165 {
13168 u64 reg;
13173 SEND_CTXT_CHECK_ENABLE);
13176 else
13180 }
13181 }
13184 {
13186 u64 reg;
13191 __func__);
13193 }
13196 ASIC_STS_THERM_CURR_TEMP_MASK);
13198 ASIC_STS_THERM_LO_TEMP_MASK);
13200 ASIC_STS_THERM_HI_TEMP_MASK);
13202 ASIC_STS_THERM_CRIT_TEMP_MASK);
13203 /* triggers is a 3-bit value - 1 bit per trigger. */
13207 }
13209 /* ========================================================================= */
13211 /**
13212 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13213 * @dd: valid devdata
13214 * @src: IRQ source to determine register index from
13215 * @bits: the bits to set or clear
13216 * @set: true == set the bits, false == clear the bits
13217 *
13218 */
13221 {
13222 u64 reg;
13229 else
13233 }
13235 /**
13236 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources
13237 * @dd: valid devdata
13238 * @first: first IRQ source to set/clear
13239 * @last: last IRQ source (inclusive) to set/clear
13240 * @set: true == set the bits, false == clear the bits
13241 *
13242 * If first == last, set the exact source.
13243 */
13245 {
13247 u64 bit;
13248 u16 src;
13258 /* wrapped to next register? */
13262 }
13264 }
13268 }
13270 /*
13271 * Clear all interrupt sources on the chip.
13272 */
13274 {
13295 }
13297 /*
13298 * Remap the interrupt source from the general handler to the given MSI-X
13299 * interrupt.
13300 */
13302 {
13303 u64 reg;
13306 /* clear from the handled mask of the general interrupt */
13314 }
13316 /* direct the chip source to the given MSI-X interrupt */
13323 }
13326 {
13327 /*
13328 * SDMA engine interrupt sources grouped by type, rather than
13329 * engine. Per-engine interrupts are as follows:
13330 * SDMA
13331 * SDMAProgress
13332 * SDMAIdle
13333 */
13337 }
13339 /*
13340 * Set the general handler to accept all interrupts, remap all
13341 * chip interrupts back to MSI-X 0.
13342 */
13344 {
13347 /* all interrupts handled by the general handler */
13351 /* all chip interrupts map to MSI-X 0 */
13354 }
13356 /**
13357 * set_up_interrupts() - Initialize the IRQ resources and state
13358 * @dd: valid devdata
13359 *
13360 */
13362 {
13365 /* mask all interrupts */
13368 /* clear all pending interrupts */
13371 /* reset general handler mask, chip MSI-X mappings */
13374 /* ask for MSI-X interrupts */
13384 }
13386 /*
13387 * Set up context values in dd. Sets:
13388 *
13389 * num_rcv_contexts - number of contexts being used
13390 * n_krcv_queues - number of kernel contexts
13391 * first_dyn_alloc_ctxt - first dynamically allocated context
13392 * in array of contexts
13393 * freectxts - number of free user contexts
13394 * num_send_contexts - number of PIO send contexts being used
13395 * num_netdev_contexts - number of contexts reserved for netdev
13396 */
13398 {
13400 u16 num_netdev_contexts;
13405 u32 n_usr_ctxts;
13409 /*
13410 * Kernel receive contexts:
13411 * - Context 0 - control context (VL15/multicast/error)
13412 * - Context 1 - first kernel context
13413 * - Context 2 - second kernel context
13414 * ...
13415 */
13417 /*
13418 * n_krcvqs is the sum of module parameter kernel receive
13419 * contexts, krcvqs[]. It does not include the control
13420 * context, so add that.
13421 */
13423 else
13425 /*
13426 * Every kernel receive context needs an ACK send context.
13427 * one send context is allocated for each VL{0-7} and VL15
13428 */
13433 num_kernel_contexts);
13435 }
13437 /*
13438 * User contexts:
13439 * - default to 1 user context per real (non-HT) CPU core if
13440 * num_user_contexts is negative
13441 */
13444 else
13446 /*
13447 * Adjust the counts given a global max.
13448 */
13453 n_usr_ctxts);
13454 /* recalculate */
13456 }
13458 num_netdev_contexts =
13462 /*
13463 * The RMT entries are currently allocated as shown below:
13464 * 1. QOS (0 to 128 entries);
13465 * 2. FECN (num_kernel_context - 1 + num_user_contexts +
13466 * num_netdev_contexts);
13467 * 3. netdev (num_netdev_contexts).
13468 * It should be noted that FECN oversubscribe num_netdev_contexts
13469 * entries of RMT because both netdev and PSM could allocate any receive
13470 * context between dd->first_dyn_alloc_text and dd->num_rcv_contexts,
13471 * and PSM FECN must reserve an RMT entry for each possible PSM receive
13472 * context.
13473 */
13481 n_usr_ctxts,
13482 user_rmt_reduced);
13483 /* recalculate */
13485 }
13487 /* the first N are kernel contexts, the rest are user/netdev contexts */
13497 rcv_contexts,
13503 /*
13504 * Receive array allocation:
13505 * All RcvArray entries are divided into groups of 8. This
13506 * is required by the hardware and will speed up writes to
13507 * consecutive entries by using write-combining of the entire
13508 * cacheline.
13509 *
13510 * The number of groups are evenly divided among all contexts.
13511 * any left over groups will be given to the first N user
13512 * contexts.
13513 */
13530 }
13531 /*
13532 * PIO send contexts
13533 */
13538 dd,
13540 send_contexts,
13547 }
13550 }
13552 /*
13553 * Set the device/port partition key table. The MAD code
13554 * will ensure that, at least, the partial management
13555 * partition key is present in the table.
13556 */
13558 {
13566 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13568 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13569 /* Each register holds 4 PKey values. */
13574 }
13575 }
13577 /* Always enable HW pkeys check when pkeys table is set */
13579 }
13581 /*
13582 * These CSRs and memories are uninitialized on reset and must be
13583 * written before reading to set the ECC/parity bits.
13584 *
13585 * NOTE: All user context CSRs that are not mmaped write-only
13586 * (e.g. the TID flows) must be initialized even if the driver never
13587 * reads them.
13588 */
13590 {
13593 /* CceIntMap */
13597 /* SendCtxtCreditReturnAddr */
13601 /* PIO Send buffers */
13602 /* SDMA Send buffers */
13603 /*
13604 * These are not normally read, and (presently) have no method
13605 * to be read, so are not pre-initialized
13606 */
13608 /* RcvHdrAddr */
13609 /* RcvHdrTailAddr */
13610 /* RcvTidFlowTable */
13616 }
13618 /* RcvArray */
13622 /* RcvQPMapTable */
13625 }
13627 /*
13628 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13629 */
13631 u64 ctrl_bits)
13632 {
13634 u64 reg;
13636 /* is the condition present? */
13641 /* clear the condition */
13644 /* wait for the condition to clear */
13655 }
13657 }
13658 }
13660 /* set CCE CSRs to chip reset defaults */
13662 {
13665 /* CCE_REVISION read-only */
13666 /* CCE_REVISION2 read-only */
13667 /* CCE_CTRL - bits clear automatically */
13668 /* CCE_STATUS read-only, use CceCtrl to clear */
13674 /* CCE_ERR_STATUS read-only */
13677 /* CCE_ERR_FORCE leave alone */
13681 /* CCE_PCIE_CTRL leave alone */
13685 CCE_MSIX_TABLE_UPPER_RESETCSR);
13686 }
13688 /* CCE_MSIX_PBA read-only */
13691 }
13695 /* CCE_INT_STATUS read-only */
13698 /* CCE_INT_FORCE leave alone */
13699 /* CCE_INT_BLOCKED read-only */
13700 }
13703 }
13705 /* set MISC CSRs to chip reset defaults */
13707 {
13714 }
13715 /*
13716 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13717 * only be written 128-byte chunks
13718 */
13719 /* init RSA engine to clear lingering errors */
13723 /* MISC_STS_8051_DIGEST read-only */
13724 /* MISC_STS_SBM_DIGEST read-only */
13725 /* MISC_STS_PCIE_DIGEST read-only */
13726 /* MISC_STS_FAB_DIGEST read-only */
13727 /* MISC_ERR_STATUS read-only */
13730 /* MISC_ERR_FORCE leave alone */
13731 }
13733 /* set TXE CSRs to chip reset defaults */
13735 {
13738 /*
13739 * TXE Kernel CSRs
13740 */
13743 /* SEND_CONTEXTS read-only */
13744 /* SEND_DMA_ENGINES read-only */
13745 /* SEND_PIO_MEM_SIZE read-only */
13746 /* SEND_DMA_MEM_SIZE read-only */
13749 /* SEND_PIO_ERR_STATUS read-only */
13752 /* SEND_PIO_ERR_FORCE leave alone */
13753 /* SEND_DMA_ERR_STATUS read-only */
13756 /* SEND_DMA_ERR_FORCE leave alone */
13757 /* SEND_EGRESS_ERR_STATUS read-only */
13760 /* SEND_EGRESS_ERR_FORCE leave alone */
13769 /* SEND_ERR_STATUS read-only */
13772 /* SEND_ERR_FORCE read-only */
13785 /* SEND_CM_CREDIT_USED_STATUS read-only */
13794 /* SEND_CM_CREDIT_USED_VL read-only */
13795 /* SEND_CM_CREDIT_USED_VL15 read-only */
13796 /* SEND_EGRESS_CTXT_STATUS read-only */
13797 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13799 /* SEND_EGRESS_ERR_INFO read-only */
13800 /* SEND_EGRESS_ERR_SOURCE read-only */
13802 /*
13803 * TXE Per-Context CSRs
13804 */
13818 }
13820 /*
13821 * TXE Per-SDMA CSRs
13822 */
13825 /* SEND_DMA_STATUS read-only */
13829 /* SEND_DMA_HEAD read-only */
13832 /* SEND_DMA_IDLE_CNT read-only */
13835 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13836 /* SEND_DMA_ENG_ERR_STATUS read-only */
13839 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13847 }
13848 }
13850 /*
13851 * Expect on entry:
13852 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13853 */
13855 {
13856 u64 reg;
13859 /*
13860 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13861 * clear.
13862 */
13869 /*
13870 * Give up after 1ms - maximum wait time.
13871 *
13872 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
13873 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13874 * 136 KB / (66% * 250MB/s) = 844us
13875 */
13881 }
13883 }
13885 /* start the init - expect RcvCtrl to be 0 */
13888 /*
13889 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13890 * period after the write before RcvStatus.RxRbufInitDone is valid.
13891 * The delay in the first run through the loop below is sufficient and
13892 * required before the first read of RcvStatus.RxRbufInintDone.
13893 */
13896 /* wait for the init to finish */
13899 /* delay is required first time through - see above */
13905 /* give up after 100us - slowest possible at 33MHz is 73us */
13909 __func__);
13911 }
13912 }
13913 }
13915 /* set RXE CSRs to chip reset defaults */
13917 {
13920 /*
13921 * RXE Kernel CSRs
13922 */
13925 /* RCV_STATUS read-only */
13926 /* RCV_CONTEXTS read-only */
13927 /* RCV_ARRAY_CNT read-only */
13928 /* RCV_BUF_SIZE read-only */
13933 /* this is a clear-down */
13935 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13936 /* RCV_ERR_STATUS read-only */
13939 /* RCV_ERR_FORCE leave alone */
13953 /*
13954 * RXE Kernel and User Per-Context CSRs
13955 */
13957 /* kernel */
13959 /* RCV_CTXT_STATUS read-only */
13971 /* user */
13972 /* RCV_HDR_TAIL read-only */
13974 /* RCV_EGR_INDEX_TAIL read-only */
13976 /* RCV_EGR_OFFSET_TAIL read-only */
13980 }
13981 }
13982 }
13984 /*
13985 * Set sc2vl tables.
13986 *
13987 * They power on to zeros, so to avoid send context errors
13988 * they need to be set:
13989 *
13990 * SC 0-7 -> VL 0-7 (respectively)
13991 * SC 15 -> VL 15
13992 * otherwise
13993 * -> VL 0
13994 */
13996 {
13998 /* init per architecture spec, constrained by hardware capability */
14000 /* HFI maps sent packets */
14026 /* DC maps received packets */
14036 /* initialize the cached sc2vl values consistently with h/w */
14040 else
14042 }
14043 }
14045 /*
14046 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
14047 * depend on the chip going through a power-on reset - a driver may be loaded
14048 * and unloaded many times.
14049 *
14050 * Do not write any CSR values to the chip in this routine - there may be
14051 * a reset following the (possible) FLR in this routine.
14052 *
14053 */
14055 {
14059 /*
14060 * Put the HFI CSRs in a known state.
14061 * Combine this with a DC reset.
14062 *
14063 * Stop the device from doing anything while we do a
14064 * reset. We know there are no other active users of
14065 * the device since we are now in charge. Turn off
14066 * off all outbound and inbound traffic and make sure
14067 * the device does not generate any interrupts.
14068 */
14070 /* disable send contexts and SDMA engines */
14076 /* disable port (turn off RXE inbound traffic) and contexts */
14080 /* mask all interrupt sources */
14084 /*
14085 * DC Reset: do a full DC reset before the register clear.
14086 * A recommended length of time to hold is one CSR read,
14087 * so reread the CceDcCtrl. Then, hold the DC in reset
14088 * across the clear.
14089 */
14094 /*
14095 * A FLR will reset the SPC core and part of the PCIe.
14096 * The parts that need to be restored have already been
14097 * saved.
14098 */
14101 /* do the FLR, the DC reset will remain */
14104 /* restore command and BARs */
14108 __func__);
14110 }
14118 __func__);
14120 }
14121 }
14128 }
14129 /* clear the DC reset */
14132 /* Set the LED off */
14135 /*
14136 * Clear the QSFP reset.
14137 * An FLR enforces a 0 on all out pins. The driver does not touch
14138 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
14139 * anything plugged constantly in reset, if it pays attention
14140 * to RESET_N.
14141 * Prime examples of this are optical cables. Set all pins high.
14142 * I2CCLK and I2CDAT will change per direction, and INT_N and
14143 * MODPRS_N are input only and their value is ignored.
14144 */
14149 }
14152 {
14155 /* assign link credit variables */
14161 /* enough room for 8 MAD packets plus header - 17K */
14173 }
14175 }
14178 {
14181 SEND_BTH_QP_KDETH_QP_SHIFT);
14185 RCV_BTH_QP_KDETH_QP_SHIFT);
14186 }
14188 /**
14189 * hfi1_get_qp_map
14190 * @dd: device data
14191 * @idx: index to read
14192 */
14194 {
14199 }
14201 /**
14202 * init_qpmap_table
14203 * @dd - device data
14204 * @first_ctxt - first context
14205 * @last_ctxt - first context
14206 *
14207 * This return sets the qpn mapping table that
14208 * is indexed by qpn[8:1].
14209 *
14210 * The routine will round robin the 256 settings
14211 * from first_ctxt to last_ctxt.
14212 *
14213 * The first/last looks ahead to having specialized
14214 * receive contexts for mgmt and bypass. Normal
14215 * verbs traffic will assumed to be on a range
14216 * of receive contexts.
14217 */
14219 u32 first_ctxt,
14220 u32 last_ctxt)
14221 {
14229 ctxt++;
14236 }
14237 }
14241 }
14246 };
14249 u8 offset;
14250 u8 pkt_type;
14251 u32 field1_off;
14252 u32 field2_off;
14253 u32 index1_off;
14254 u32 index1_width;
14255 u32 index2_off;
14256 u32 index2_width;
14257 u32 mask1;
14258 u32 value1;
14259 u32 mask2;
14260 u32 value2;
14261 };
14263 /*
14264 * Return an initialized RMT map table for users to fill in. OK if it
14265 * returns NULL, indicating no table.
14266 */
14268 {
14276 }
14279 }
14281 /*
14282 * Write the final RMT map table to the chip and free the table. OK if
14283 * table is NULL.
14284 */
14287 {
14291 /* write table to chip */
14295 /* enable RSM */
14297 }
14298 }
14300 /* Is a receive side mapping rule */
14302 {
14304 }
14306 /*
14307 * Add a receive side mapping rule.
14308 */
14311 {
14328 }
14330 /*
14331 * Clear a receive side mapping rule.
14332 */
14334 {
14338 }
14340 /* return the number of RSM map table entries that will be used for QOS */
14343 {
14348 /* is QOS active at all? */
14354 /* determine bits for qpn */
14362 /* determine bits for vl */
14365 /* reject if too much is used */
14376 no_qos:
14382 }
14384 /**
14385 * init_qos - init RX qos
14386 * @dd - device data
14387 * @rmt - RSM map table
14388 *
14389 * This routine initializes Rule 0 and the RSM map table to implement
14390 * quality of service (qos).
14391 *
14392 * If all of the limit tests succeed, qos is applied based on the array
14393 * interpretation of krcvqs where entry 0 is VL0.
14394 *
14395 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14396 * feed both the RSM map table and the single rule.
14397 */
14399 {
14403 u64 reg;
14412 /* enough room in the map table? */
14417 /* add qos entries to the the RSM map table */
14425 /* generate the index the hardware will produce */
14429 /* replace default with context number */
14431 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14437 }
14439 }
14454 /* add rule 0 */
14457 /* mark RSM map entries as used */
14459 /* map everything else to the mcast/err/vl15 context */
14463 bail:
14466 }
14470 {
14472 u64 reg;
14474 u8 offset;
14475 u32 total_cnt;
14478 /* Exclude context 0 */
14480 else
14485 /* there needs to be enough room in the map table */
14489 }
14491 /*
14492 * RSM will extract the destination context as an index into the
14493 * map table. The destination contexts are a sequential block
14494 * in the range start...num_rcv_contexts-1 (inclusive).
14495 * Map entries are accessed as offset + extracted value. Adjust
14496 * the added offset so this sequence can be placed anywhere in
14497 * the table - as long as the entries themselves do not wrap.
14498 * There are only enough bits in offset for the table size, so
14499 * start with that to allow for a "negative" offset.
14500 */
14505 /* replace with identity mapping */
14512 }
14514 /*
14515 * For RSM intercept of Expected FECN packets:
14516 * o packet type 0 - expected
14517 * o match on F (bit 95), using select/match 1, and
14518 * o match on SH (bit 133), using select/match 2.
14519 *
14520 * Use index 1 to extract the 8-bit receive context from DestQP
14521 * (start at bit 64). Use that as the RSM map table index.
14522 */
14536 /* add rule 1 */
14540 }
14543 {
14545 }
14548 {
14551 u64 reg;
14552 u32 regoff;
14556 /* We already have contexts mapped in RMT */
14560 }
14564 rmt_start);
14566 }
14569 rmt_start,
14572 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14576 /* Update map register with netdev context */
14580 /* Wrap up netdev ctx index */
14582 /* Write back map register */
14592 }
14593 }
14596 }
14600 {
14604 }
14608 }
14611 {
14612 /*
14613 * go through with the initialisation only if this rule actually doesn't
14614 * exist yet
14615 */
14632 };
14635 }
14636 }
14638 /* Initialize RSM for VNIC */
14640 {
14643 /* Add rule for vnic */
14646 /* Match 16B packets */
14650 /* Match ETH L4 packets */
14654 /* Calc context from veswid and entropy */
14659 };
14662 }
14665 {
14667 }
14670 {
14671 /* only actually clear the rule if it's the last user asking to do so */
14674 }
14677 {
14679 u64 val;
14681 /* enable all receive errors */
14688 /* set up QOS, including the QPN map table */
14692 /* record number of used rsm map entries for netdev */
14696 /*
14697 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14698 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14699 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14700 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14701 * Max_PayLoad_Size set to its minimum of 128.
14702 *
14703 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14704 * (64 bytes). Max_Payload_Size is possibly modified upward in
14705 * tune_pcie_caps() which is called after this routine.
14706 */
14708 /* Have 16 bytes (4DW) of bypass header available in header queue */
14712 RCV_BYPASS_HDR_SIZE_SHIFT);
14715 }
14718 {
14719 /* enable all CCE errors */
14721 /* enable *some* Misc errors */
14723 /* enable all DC errors, except LCB */
14726 }
14728 /*
14729 * Fill out the given AU table using the given CU. A CU is defined in terms
14730 * AUs. The table is a an encoding: given the index, how many AUs does that
14731 * represent?
14732 *
14733 * NOTE: Assumes that the register layout is the same for the
14734 * local and remote tables.
14735 */
14738 {
14743 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14745 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14748 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14750 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14752 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14754 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14755 }
14758 {
14760 SEND_CM_LOCAL_AU_TABLE4_TO7);
14761 }
14764 {
14766 SEND_CM_REMOTE_AU_TABLE4_TO7);
14767 }
14770 {
14773 /* enable all PIO, SDMA, general, and Egress errors */
14779 /* enable all per-context and per-SDMA engine errors */
14785 /* set the local CU to AU mapping */
14788 /*
14789 * Set reasonable default for Credit Return Timer
14790 * Don't set on Simulator - causes it to choke.
14791 */
14794 }
14797 u16 jkey)
14798 {
14799 u8 hw_ctxt;
14800 u64 reg;
14808 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14809 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14813 /*
14814 * Enable send-side J_KEY integrity check, unless this is A0 h/w
14815 */
14820 }
14822 /* Enable J_KEY check on receive context. */
14825 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14829 }
14832 {
14833 u8 hw_ctxt;
14834 u64 reg;
14841 /*
14842 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14843 * This check would not have been enabled for A0 h/w, see
14844 * set_ctxt_jkey().
14845 */
14850 }
14851 /* Turn off the J_KEY on the receive side */
14855 }
14858 u16 pkey)
14859 {
14860 u8 hw_ctxt;
14861 u64 reg;
14868 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14876 }
14879 {
14880 u8 hw_ctxt;
14881 u64 reg;
14893 }
14895 /*
14896 * Start doing the clean up the the chip. Our clean up happens in multiple
14897 * stages and this is just the first.
14898 */
14900 {
14905 }
14907 #define HFI_BASE_GUID(dev) \
14908 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14910 /*
14911 * Information can be shared between the two HFIs on the same ASIC
14912 * in the same OS. This function finds the peer device and sets
14913 * up a shared structure.
14914 */
14916 {
14922 /* pre-allocate the asic structure in case we are the first device */
14928 /* Find our peer device */
14933 }
14936 /* use already allocated structure */
14942 }
14946 /* first one through - set up i2c devices */
14951 }
14953 /*
14954 * Set dd->boardname. Use a generic name if a name is not returned from
14955 * EFI variable space.
14956 *
14957 * Return 0 on success, -ENOMEM if space could not be allocated.
14958 */
14960 {
14961 /* generic board description */
14971 /* use generic description */
14975 }
14977 }
14979 /*
14980 * Check the interrupt registers to make sure that they are mapped correctly.
14981 * It is intended to help user identify any mismapping by VMM when the driver
14982 * is running in a VM. This function should only be called before interrupt
14983 * is set up properly.
14984 *
14985 * Return 0 on success, -EINVAL on failure.
14986 */
14988 {
14989 u64 reg;
14991 u64 mask;
14993 /* Clear CceIntMask[0] to avoid raising any interrupts */
15000 /* Clear all interrupt status bits */
15006 /* Set all interrupt status bits */
15012 /* Restore the interrupt mask */
15017 err_exit:
15021 }
15023 /**
15024 * hfi1_init_dd() - Initialize most of the dd structure.
15025 * @dev: the pci_dev for hfi1_ib device
15026 * @ent: pci_device_id struct for this dev
15027 *
15028 * This is global, and is called directly at init to set up the
15029 * chip-specific function pointers for later use.
15030 */
15032 {
15035 u64 reg;
15041 "Functional simulator"
15042 };
15049 /* init common fields */
15051 /* DC supports 4 link widths */
15057 /* start out enabling only 4X */
15061 /* link width active is 0 when link is down */
15062 /* link width downgrade active is 0 when link is down */
15069 }
15072 /* Set the default MTU. */
15076 /*
15077 * Set the initial values to reasonable default, will be set
15078 * for real when link is up.
15079 */
15083 /* initialize supported LTP CRC mode */
15085 /* initialize enabled LTP CRC mode */
15087 /* start in offline */
15090 }
15092 /*
15093 * Do remaining PCIe setup and save PCIe values in dd.
15094 * Any error printing is already done by the init code.
15095 * On return, we have the chip mapped.
15096 */
15101 /* Save PCI space registers to rewrite after device reset */
15111 /*
15112 * Check interrupt registers mapping if the driver has no access to
15113 * the upstream component. In this case, it is likely that the driver
15114 * is running in a VM.
15115 */
15120 }
15122 /*
15123 * obtain the hardware ID - NOT related to unit, which is a
15124 * software enumeration
15125 */
15129 /* the variable size will remove unwanted bits */
15136 /* speeds the hardware can support */
15138 /* speeds allowed to run at */
15140 /* give a reasonable active value, will be set on link up */
15143 /* fix up link widths for emulation _p */
15150 OPA_LINK_WIDTH_1X;
15151 }
15152 /* insure num_vls isn't larger than number of sdma engines */
15159 }
15161 /*
15162 * Convert the ns parameter to the 64 * cclocks used in the CSR.
15163 * Limit the max if larger than the field holds. If timeout is
15164 * non-zero, then the calculated field will be at least 1.
15165 *
15166 * Must be after icode is set up - the cclock rate depends
15167 * on knowing the hardware being used.
15168 */
15171 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
15173 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
15177 /* needs to be done before we look for the peer device */
15180 /* set up shared ASIC data with peer device */
15185 /* obtain chip sizes, reset chip CSRs */
15190 /* read in the PCIe link speed information */
15195 /* call before get_platform_config(), after init_chip_resources() */
15200 /* Needs to be called before hfi1_firmware_init */
15203 /* read in firmware */
15208 /*
15209 * In general, the PCIe Gen3 transition must occur after the
15210 * chip has been idled (so it won't initiate any PCIe transactions
15211 * e.g. an interrupt) and before the driver changes any registers
15212 * (the transition will reset the registers).
15213 *
15214 * In particular, place this call after:
15215 * - init_chip() - the chip will not initiate any PCIe transactions
15216 * - pcie_speeds() - reads the current link speed
15217 * - hfi1_firmware_init() - the needed firmware is ready to be
15218 * downloaded
15219 */
15224 /*
15225 * This should probably occur in hfi1_pcie_init(), but historically
15226 * occurs after the do_pcie_gen3_transition() code.
15227 */
15230 /* start setting dd values and adjusting CSRs */
15247 /* alloc netdev data */
15256 /* set initial RXE CSRs */
15261 /* set initial TXE CSRs */
15263 /* set initial non-RXE, non-TXE CSRs */
15265 /* set up KDETH QP prefix in both RX and TX CSRs */
15272 /* send contexts must be set up before receive contexts */
15281 /*
15282 * Initialize aspm, to be done after gen3 transition and setting up
15283 * contexts and before enabling interrupts
15284 */
15291 /* sdma init */
15296 }
15298 /* use contexts created by hfi1_create_kctxts */
15307 /* set up LCB access - must be after set_up_interrupts() */
15310 /*
15311 * Serial number is created from the base guid:
15312 * [27:24] = base guid [38:35]
15313 * [23: 0] = base guid [23: 0]
15314 */
15339 /* The user refcount starts with one to inidicate an active device */
15344 bail_free_rcverr:
15346 bail_free_cntrs:
15348 bail_clear_intr:
15351 bail_cleanup:
15354 bail_free:
15356 bail:
15358 }
15361 u32 dw_len)
15362 {
15363 u32 delta_cycles;
15365 /* rates here are in units of 10^6 bits/sec */
15377 }
15379 /**
15380 * create_pbc - build a pbc for transmission
15381 * @flags: special case flags or-ed in built pbc
15382 * @srate: static rate
15383 * @vl: vl
15384 * @dwlen: dword length (header words + data words + pbc words)
15385 *
15386 * Create a PBC with the given flags, rate, VL, and length.
15387 *
15388 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15389 * for verbs, which does not use this PSM feature. The lone other caller
15390 * is for the diagnostic interface which calls this if the user does not
15391 * supply their own PBC.
15392 */
15394 u32 dw_len)
15395 {
15401 pbc = flags
15409 }
15411 #define SBUS_THERMAL 0x4f
15412 #define SBUS_THERM_MONITOR_MODE 0x1
15414 #define THERM_FAILURE(dev, ret, reason) \
15415 dd_dev_err((dd), \
15417 (reason), (ret))
15419 /*
15420 * Initialize the thermal sensor.
15421 *
15422 * After initialization, enable polling of thermal sensor through
15423 * SBus interface. In order for this to work, the SBus Master
15424 * firmware has to be loaded due to the fact that the HW polling
15425 * logic uses SBus interrupts, which are not supported with
15426 * default firmware. Otherwise, no data will be returned through
15427 * the ASIC_STS_THERM CSR.
15428 */
15430 {
15441 }
15444 /* Disable polling of thermal readings */
15447 /* Thermal Sensor Initialization */
15448 /* Step 1: Reset the Thermal SBus Receiver */
15454 }
15455 /* Step 2: Set Reset bit in Thermal block */
15461 }
15462 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15468 }
15469 /* Step 4: Select temperature mode */
15471 WRITE_SBUS_RECEIVER,
15472 SBUS_THERM_MONITOR_MODE);
15476 }
15477 /* Step 5: De-assert block reset and start conversion */
15483 }
15484 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15487 /* Enable polling of thermal readings */
15490 /* Set initialized flag */
15495 done:
15498 }
15501 {
15503 /*
15504 * Thermal Critical Interrupt
15505 * Put the device into forced freeze mode, take link down to
15506 * offline, and put DC into reset.
15507 */
15512 /*
15513 * Shut DC down as much and as quickly as possible.
15514 *
15515 * Step 1: Take the link down to OFFLINE. This will cause the
15516 * 8051 to put the Serdes in reset. However, we don't want to
15517 * go through the entire link state machine since we want to
15518 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15519 * but rather an attempt to save the chip.
15520 * Code below is almost the same as quiet_serdes() but avoids
15521 * all the extra work and the sleeps.
15522 */
15526 PLS_OFFLINE);
15527 /*
15528 * Step 2: Shutdown LCB and 8051
15529 * After shutdown, do not restore DC_CFG_RESET value.
15530 */
15532 }