drivers/infiniband/sw/rxe/rxe_opcode.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
   2 /*
   3  * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
   4  * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
   5  */
   6
   7 #ifndef RXE_OPCODE_H
   8 #define RXE_OPCODE_H
   9
  10 /*
  11  * contains header bit mask definitions and header lengths
  12  * declaration of the rxe_opcode_info struct and
  13  * rxe_wr_opcode_info struct
  14  */
  15
  16 enum rxe_wr_mask {
  17         WR_INLINE_MASK                  = BIT(0),
  18         WR_ATOMIC_MASK                  = BIT(1),
  19         WR_SEND_MASK                    = BIT(2),
  20         WR_READ_MASK                    = BIT(3),
  21         WR_WRITE_MASK                   = BIT(4),
  22         WR_LOCAL_MASK                   = BIT(5),
  23         WR_REG_MASK                     = BIT(6),
  24
  25         WR_READ_OR_WRITE_MASK           = WR_READ_MASK | WR_WRITE_MASK,
  26         WR_READ_WRITE_OR_SEND_MASK      = WR_READ_OR_WRITE_MASK | WR_SEND_MASK,
  27         WR_WRITE_OR_SEND_MASK           = WR_WRITE_MASK | WR_SEND_MASK,
  28         WR_ATOMIC_OR_READ_MASK          = WR_ATOMIC_MASK | WR_READ_MASK,
  29 };
  30
  31 #define WR_MAX_QPT              (8)
  32
  33 struct rxe_wr_opcode_info {
  34         char                    *name;
  35         enum rxe_wr_mask        mask[WR_MAX_QPT];
  36 };
  37
  38 extern struct rxe_wr_opcode_info rxe_wr_opcode_info[];
  39
  40 enum rxe_hdr_type {
  41         RXE_LRH,
  42         RXE_GRH,
  43         RXE_BTH,
  44         RXE_RETH,
  45         RXE_AETH,
  46         RXE_ATMETH,
  47         RXE_ATMACK,
  48         RXE_IETH,
  49         RXE_RDETH,
  50         RXE_DETH,
  51         RXE_IMMDT,
  52         RXE_PAYLOAD,
  53         NUM_HDR_TYPES
  54 };
  55
  56 enum rxe_hdr_mask {
  57         RXE_LRH_MASK            = BIT(RXE_LRH),
  58         RXE_GRH_MASK            = BIT(RXE_GRH),
  59         RXE_BTH_MASK            = BIT(RXE_BTH),
  60         RXE_IMMDT_MASK          = BIT(RXE_IMMDT),
  61         RXE_RETH_MASK           = BIT(RXE_RETH),
  62         RXE_AETH_MASK           = BIT(RXE_AETH),
  63         RXE_ATMETH_MASK         = BIT(RXE_ATMETH),
  64         RXE_ATMACK_MASK         = BIT(RXE_ATMACK),
  65         RXE_IETH_MASK           = BIT(RXE_IETH),
  66         RXE_RDETH_MASK          = BIT(RXE_RDETH),
  67         RXE_DETH_MASK           = BIT(RXE_DETH),
  68         RXE_PAYLOAD_MASK        = BIT(RXE_PAYLOAD),
  69
  70         RXE_REQ_MASK            = BIT(NUM_HDR_TYPES + 0),
  71         RXE_ACK_MASK            = BIT(NUM_HDR_TYPES + 1),
  72         RXE_SEND_MASK           = BIT(NUM_HDR_TYPES + 2),
  73         RXE_WRITE_MASK          = BIT(NUM_HDR_TYPES + 3),
  74         RXE_READ_MASK           = BIT(NUM_HDR_TYPES + 4),
  75         RXE_ATOMIC_MASK         = BIT(NUM_HDR_TYPES + 5),
  76
  77         RXE_RWR_MASK            = BIT(NUM_HDR_TYPES + 6),
  78         RXE_COMP_MASK           = BIT(NUM_HDR_TYPES + 7),
  79
  80         RXE_START_MASK          = BIT(NUM_HDR_TYPES + 8),
  81         RXE_MIDDLE_MASK         = BIT(NUM_HDR_TYPES + 9),
  82         RXE_END_MASK            = BIT(NUM_HDR_TYPES + 10),
  83
  84         RXE_LOOPBACK_MASK       = BIT(NUM_HDR_TYPES + 12),
  85
  86         RXE_READ_OR_ATOMIC      = (RXE_READ_MASK | RXE_ATOMIC_MASK),
  87         RXE_WRITE_OR_SEND       = (RXE_WRITE_MASK | RXE_SEND_MASK),
  88 };
  89
  90 #define OPCODE_NONE             (-1)
  91 #define RXE_NUM_OPCODE          256
  92
  93 struct rxe_opcode_info {
  94         char                    *name;
  95         enum rxe_hdr_mask       mask;
  96         int                     length;
  97         int                     offset[NUM_HDR_TYPES];
  98 };
  99
 100 extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE];
 101
 102 #endif /* RXE_OPCODE_H */