drivers/media/i2c/imx290.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Sony IMX290 CMOS Image Sensor Driver
   4  *
   5  * Copyright (C) 2019 FRAMOS GmbH.
   6  *
   7  * Copyright (C) 2019 Linaro Ltd.
   8  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/i2c.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <media/media-entity.h>
  20 #include <media/v4l2-ctrls.h>
  21 #include <media/v4l2-device.h>
  22 #include <media/v4l2-fwnode.h>
  23 #include <media/v4l2-subdev.h>
  24
  25 #define IMX290_STANDBY 0x3000
  26 #define IMX290_REGHOLD 0x3001
  27 #define IMX290_XMSTA 0x3002
  28 #define IMX290_FR_FDG_SEL 0x3009
  29 #define IMX290_BLKLEVEL_LOW 0x300a
  30 #define IMX290_BLKLEVEL_HIGH 0x300b
  31 #define IMX290_GAIN 0x3014
  32 #define IMX290_HMAX_LOW 0x301c
  33 #define IMX290_HMAX_HIGH 0x301d
  34 #define IMX290_PGCTRL 0x308c
  35 #define IMX290_PHY_LANE_NUM 0x3407
  36 #define IMX290_CSI_LANE_MODE 0x3443
  37
  38 #define IMX290_PGCTRL_REGEN BIT(0)
  39 #define IMX290_PGCTRL_THRU BIT(1)
  40 #define IMX290_PGCTRL_MODE(n) ((n) << 4)
  41
  42 static const char * const imx290_supply_name[] = {
  43         "vdda",
  44         "vddd",
  45         "vdddo",
  46 };
  47
  48 #define IMX290_NUM_SUPPLIES ARRAY_SIZE(imx290_supply_name)
  49
  50 struct imx290_regval {
  51         u16 reg;
  52         u8 val;
  53 };
  54
  55 struct imx290_mode {
  56         u32 width;
  57         u32 height;
  58         u32 hmax;
  59         u8 link_freq_index;
  60
  61         const struct imx290_regval *data;
  62         u32 data_size;
  63 };
  64
  65 struct imx290 {
  66         struct device *dev;
  67         struct clk *xclk;
  68         struct regmap *regmap;
  69         u8 nlanes;
  70         u8 bpp;
  71
  72         struct v4l2_subdev sd;
  73         struct media_pad pad;
  74         struct v4l2_mbus_framefmt current_format;
  75         const struct imx290_mode *current_mode;
  76
  77         struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
  78         struct gpio_desc *rst_gpio;
  79
  80         struct v4l2_ctrl_handler ctrls;
  81         struct v4l2_ctrl *link_freq;
  82         struct v4l2_ctrl *pixel_rate;
  83
  84         struct mutex lock;
  85 };
  86
  87 struct imx290_pixfmt {
  88         u32 code;
  89         u8 bpp;
  90 };
  91
  92 static const struct imx290_pixfmt imx290_formats[] = {
  93         { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
  94         { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
  95 };
  96
  97 static const struct regmap_config imx290_regmap_config = {
  98         .reg_bits = 16,
  99         .val_bits = 8,
 100         .cache_type = REGCACHE_RBTREE,
 101 };
 102
 103 static const char * const imx290_test_pattern_menu[] = {
 104         "Disabled",
 105         "Sequence Pattern 1",
 106         "Horizontal Color-bar Chart",
 107         "Vertical Color-bar Chart",
 108         "Sequence Pattern 2",
 109         "Gradation Pattern 1",
 110         "Gradation Pattern 2",
 111         "000/555h Toggle Pattern",
 112 };
 113
 114 static const struct imx290_regval imx290_global_init_settings[] = {
 115         { 0x3007, 0x00 },
 116         { 0x3018, 0x65 },
 117         { 0x3019, 0x04 },
 118         { 0x301a, 0x00 },
 119         { 0x3444, 0x20 },
 120         { 0x3445, 0x25 },
 121         { 0x303a, 0x0c },
 122         { 0x3040, 0x00 },
 123         { 0x3041, 0x00 },
 124         { 0x303c, 0x00 },
 125         { 0x303d, 0x00 },
 126         { 0x3042, 0x9c },
 127         { 0x3043, 0x07 },
 128         { 0x303e, 0x49 },
 129         { 0x303f, 0x04 },
 130         { 0x304b, 0x0a },
 131         { 0x300f, 0x00 },
 132         { 0x3010, 0x21 },
 133         { 0x3012, 0x64 },
 134         { 0x3016, 0x09 },
 135         { 0x3070, 0x02 },
 136         { 0x3071, 0x11 },
 137         { 0x309b, 0x10 },
 138         { 0x309c, 0x22 },
 139         { 0x30a2, 0x02 },
 140         { 0x30a6, 0x20 },
 141         { 0x30a8, 0x20 },
 142         { 0x30aa, 0x20 },
 143         { 0x30ac, 0x20 },
 144         { 0x30b0, 0x43 },
 145         { 0x3119, 0x9e },
 146         { 0x311c, 0x1e },
 147         { 0x311e, 0x08 },
 148         { 0x3128, 0x05 },
 149         { 0x313d, 0x83 },
 150         { 0x3150, 0x03 },
 151         { 0x317e, 0x00 },
 152         { 0x32b8, 0x50 },
 153         { 0x32b9, 0x10 },
 154         { 0x32ba, 0x00 },
 155         { 0x32bb, 0x04 },
 156         { 0x32c8, 0x50 },
 157         { 0x32c9, 0x10 },
 158         { 0x32ca, 0x00 },
 159         { 0x32cb, 0x04 },
 160         { 0x332c, 0xd3 },
 161         { 0x332d, 0x10 },
 162         { 0x332e, 0x0d },
 163         { 0x3358, 0x06 },
 164         { 0x3359, 0xe1 },
 165         { 0x335a, 0x11 },
 166         { 0x3360, 0x1e },
 167         { 0x3361, 0x61 },
 168         { 0x3362, 0x10 },
 169         { 0x33b0, 0x50 },
 170         { 0x33b2, 0x1a },
 171         { 0x33b3, 0x04 },
 172 };
 173
 174 static const struct imx290_regval imx290_1080p_settings[] = {
 175         /* mode settings */
 176         { 0x3007, 0x00 },
 177         { 0x303a, 0x0c },
 178         { 0x3414, 0x0a },
 179         { 0x3472, 0x80 },
 180         { 0x3473, 0x07 },
 181         { 0x3418, 0x38 },
 182         { 0x3419, 0x04 },
 183         { 0x3012, 0x64 },
 184         { 0x3013, 0x00 },
 185         { 0x305c, 0x18 },
 186         { 0x305d, 0x03 },
 187         { 0x305e, 0x20 },
 188         { 0x305f, 0x01 },
 189         { 0x315e, 0x1a },
 190         { 0x3164, 0x1a },
 191         { 0x3480, 0x49 },
 192         /* data rate settings */
 193         { 0x3405, 0x10 },
 194         { 0x3446, 0x57 },
 195         { 0x3447, 0x00 },
 196         { 0x3448, 0x37 },
 197         { 0x3449, 0x00 },
 198         { 0x344a, 0x1f },
 199         { 0x344b, 0x00 },
 200         { 0x344c, 0x1f },
 201         { 0x344d, 0x00 },
 202         { 0x344e, 0x1f },
 203         { 0x344f, 0x00 },
 204         { 0x3450, 0x77 },
 205         { 0x3451, 0x00 },
 206         { 0x3452, 0x1f },
 207         { 0x3453, 0x00 },
 208         { 0x3454, 0x17 },
 209         { 0x3455, 0x00 },
 210 };
 211
 212 static const struct imx290_regval imx290_720p_settings[] = {
 213         /* mode settings */
 214         { 0x3007, 0x10 },
 215         { 0x303a, 0x06 },
 216         { 0x3414, 0x04 },
 217         { 0x3472, 0x00 },
 218         { 0x3473, 0x05 },
 219         { 0x3418, 0xd0 },
 220         { 0x3419, 0x02 },
 221         { 0x3012, 0x64 },
 222         { 0x3013, 0x00 },
 223         { 0x305c, 0x20 },
 224         { 0x305d, 0x00 },
 225         { 0x305e, 0x20 },
 226         { 0x305f, 0x01 },
 227         { 0x315e, 0x1a },
 228         { 0x3164, 0x1a },
 229         { 0x3480, 0x49 },
 230         /* data rate settings */
 231         { 0x3405, 0x10 },
 232         { 0x3446, 0x4f },
 233         { 0x3447, 0x00 },
 234         { 0x3448, 0x2f },
 235         { 0x3449, 0x00 },
 236         { 0x344a, 0x17 },
 237         { 0x344b, 0x00 },
 238         { 0x344c, 0x17 },
 239         { 0x344d, 0x00 },
 240         { 0x344e, 0x17 },
 241         { 0x344f, 0x00 },
 242         { 0x3450, 0x57 },
 243         { 0x3451, 0x00 },
 244         { 0x3452, 0x17 },
 245         { 0x3453, 0x00 },
 246         { 0x3454, 0x17 },
 247         { 0x3455, 0x00 },
 248 };
 249
 250 static const struct imx290_regval imx290_10bit_settings[] = {
 251         { 0x3005, 0x00},
 252         { 0x3046, 0x00},
 253         { 0x3129, 0x1d},
 254         { 0x317c, 0x12},
 255         { 0x31ec, 0x37},
 256         { 0x3441, 0x0a},
 257         { 0x3442, 0x0a},
 258         { 0x300a, 0x3c},
 259         { 0x300b, 0x00},
 260 };
 261
 262 static const struct imx290_regval imx290_12bit_settings[] = {
 263         { 0x3005, 0x01 },
 264         { 0x3046, 0x01 },
 265         { 0x3129, 0x00 },
 266         { 0x317c, 0x00 },
 267         { 0x31ec, 0x0e },
 268         { 0x3441, 0x0c },
 269         { 0x3442, 0x0c },
 270         { 0x300a, 0xf0 },
 271         { 0x300b, 0x00 },
 272 };
 273
 274 /* supported link frequencies */
 275 #define FREQ_INDEX_1080P        0
 276 #define FREQ_INDEX_720P         1
 277 static const s64 imx290_link_freq_2lanes[] = {
 278         [FREQ_INDEX_1080P] = 445500000,
 279         [FREQ_INDEX_720P] = 297000000,
 280 };
 281 static const s64 imx290_link_freq_4lanes[] = {
 282         [FREQ_INDEX_1080P] = 222750000,
 283         [FREQ_INDEX_720P] = 148500000,
 284 };
 285
 286 /*
 287  * In this function and in the similar ones below We rely on imx290_probe()
 288  * to ensure that nlanes is either 2 or 4.
 289  */
 290 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
 291 {
 292         if (imx290->nlanes == 2)
 293                 return imx290_link_freq_2lanes;
 294         else
 295                 return imx290_link_freq_4lanes;
 296 }
 297
 298 static inline int imx290_link_freqs_num(const struct imx290 *imx290)
 299 {
 300         if (imx290->nlanes == 2)
 301                 return ARRAY_SIZE(imx290_link_freq_2lanes);
 302         else
 303                 return ARRAY_SIZE(imx290_link_freq_4lanes);
 304 }
 305
 306 /* Mode configs */
 307 static const struct imx290_mode imx290_modes_2lanes[] = {
 308         {
 309                 .width = 1920,
 310                 .height = 1080,
 311                 .hmax = 0x1130,
 312                 .link_freq_index = FREQ_INDEX_1080P,
 313                 .data = imx290_1080p_settings,
 314                 .data_size = ARRAY_SIZE(imx290_1080p_settings),
 315         },
 316         {
 317                 .width = 1280,
 318                 .height = 720,
 319                 .hmax = 0x19c8,
 320                 .link_freq_index = FREQ_INDEX_720P,
 321                 .data = imx290_720p_settings,
 322                 .data_size = ARRAY_SIZE(imx290_720p_settings),
 323         },
 324 };
 325
 326 static const struct imx290_mode imx290_modes_4lanes[] = {
 327         {
 328                 .width = 1920,
 329                 .height = 1080,
 330                 .hmax = 0x0898,
 331                 .link_freq_index = FREQ_INDEX_1080P,
 332                 .data = imx290_1080p_settings,
 333                 .data_size = ARRAY_SIZE(imx290_1080p_settings),
 334         },
 335         {
 336                 .width = 1280,
 337                 .height = 720,
 338                 .hmax = 0x0ce4,
 339                 .link_freq_index = FREQ_INDEX_720P,
 340                 .data = imx290_720p_settings,
 341                 .data_size = ARRAY_SIZE(imx290_720p_settings),
 342         },
 343 };
 344
 345 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
 346 {
 347         if (imx290->nlanes == 2)
 348                 return imx290_modes_2lanes;
 349         else
 350                 return imx290_modes_4lanes;
 351 }
 352
 353 static inline int imx290_modes_num(const struct imx290 *imx290)
 354 {
 355         if (imx290->nlanes == 2)
 356                 return ARRAY_SIZE(imx290_modes_2lanes);
 357         else
 358                 return ARRAY_SIZE(imx290_modes_4lanes);
 359 }
 360
 361 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
 362 {
 363         return container_of(_sd, struct imx290, sd);
 364 }
 365
 366 static inline int imx290_read_reg(struct imx290 *imx290, u16 addr, u8 *value)
 367 {
 368         unsigned int regval;
 369         int ret;
 370
 371         ret = regmap_read(imx290->regmap, addr, &regval);
 372         if (ret) {
 373                 dev_err(imx290->dev, "I2C read failed for addr: %x\n", addr);
 374                 return ret;
 375         }
 376
 377         *value = regval & 0xff;
 378
 379         return 0;
 380 }
 381
 382 static int imx290_write_reg(struct imx290 *imx290, u16 addr, u8 value)
 383 {
 384         int ret;
 385
 386         ret = regmap_write(imx290->regmap, addr, value);
 387         if (ret) {
 388                 dev_err(imx290->dev, "I2C write failed for addr: %x\n", addr);
 389                 return ret;
 390         }
 391
 392         return ret;
 393 }
 394
 395 static int imx290_set_register_array(struct imx290 *imx290,
 396                                      const struct imx290_regval *settings,
 397                                      unsigned int num_settings)
 398 {
 399         unsigned int i;
 400         int ret;
 401
 402         for (i = 0; i < num_settings; ++i, ++settings) {
 403                 ret = imx290_write_reg(imx290, settings->reg, settings->val);
 404                 if (ret < 0)
 405                         return ret;
 406         }
 407
 408         /* Provide 10ms settle time */
 409         usleep_range(10000, 11000);
 410
 411         return 0;
 412 }
 413
 414 static int imx290_write_buffered_reg(struct imx290 *imx290, u16 address_low,
 415                                      u8 nr_regs, u32 value)
 416 {
 417         unsigned int i;
 418         int ret;
 419
 420         ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x01);
 421         if (ret) {
 422                 dev_err(imx290->dev, "Error setting hold register\n");
 423                 return ret;
 424         }
 425
 426         for (i = 0; i < nr_regs; i++) {
 427                 ret = imx290_write_reg(imx290, address_low + i,
 428                                        (u8)(value >> (i * 8)));
 429                 if (ret) {
 430                         dev_err(imx290->dev, "Error writing buffered registers\n");
 431                         return ret;
 432                 }
 433         }
 434
 435         ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x00);
 436         if (ret) {
 437                 dev_err(imx290->dev, "Error setting hold register\n");
 438                 return ret;
 439         }
 440
 441         return ret;
 442 }
 443
 444 static int imx290_set_gain(struct imx290 *imx290, u32 value)
 445 {
 446         int ret;
 447
 448         ret = imx290_write_buffered_reg(imx290, IMX290_GAIN, 1, value);
 449         if (ret)
 450                 dev_err(imx290->dev, "Unable to write gain\n");
 451
 452         return ret;
 453 }
 454
 455 /* Stop streaming */
 456 static int imx290_stop_streaming(struct imx290 *imx290)
 457 {
 458         int ret;
 459
 460         ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);
 461         if (ret < 0)
 462                 return ret;
 463
 464         msleep(30);
 465
 466         return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);
 467 }
 468
 469 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
 470 {
 471         struct imx290 *imx290 = container_of(ctrl->handler,
 472                                              struct imx290, ctrls);
 473         int ret = 0;
 474
 475         /* V4L2 controls values will be applied only when power is already up */
 476         if (!pm_runtime_get_if_in_use(imx290->dev))
 477                 return 0;
 478
 479         switch (ctrl->id) {
 480         case V4L2_CID_GAIN:
 481                 ret = imx290_set_gain(imx290, ctrl->val);
 482                 break;
 483         case V4L2_CID_TEST_PATTERN:
 484                 if (ctrl->val) {
 485                         imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);
 486                         imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
 487                         usleep_range(10000, 11000);
 488                         imx290_write_reg(imx290, IMX290_PGCTRL,
 489                                          (u8)(IMX290_PGCTRL_REGEN |
 490                                          IMX290_PGCTRL_THRU |
 491                                          IMX290_PGCTRL_MODE(ctrl->val)));
 492                 } else {
 493                         imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
 494                         usleep_range(10000, 11000);
 495                         if (imx290->bpp == 10)
 496                                 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
 497                                                  0x3c);
 498                         else /* 12 bits per pixel */
 499                                 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
 500                                                  0xf0);
 501                         imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
 502                 }
 503                 break;
 504         default:
 505                 ret = -EINVAL;
 506                 break;
 507         }
 508
 509         pm_runtime_put(imx290->dev);
 510
 511         return ret;
 512 }
 513
 514 static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
 515         .s_ctrl = imx290_set_ctrl,
 516 };
 517
 518 static int imx290_enum_mbus_code(struct v4l2_subdev *sd,
 519                                  struct v4l2_subdev_pad_config *cfg,
 520                                  struct v4l2_subdev_mbus_code_enum *code)
 521 {
 522         if (code->index >= ARRAY_SIZE(imx290_formats))
 523                 return -EINVAL;
 524
 525         code->code = imx290_formats[code->index].code;
 526
 527         return 0;
 528 }
 529
 530 static int imx290_enum_frame_size(struct v4l2_subdev *sd,
 531                                   struct v4l2_subdev_pad_config *cfg,
 532                                   struct v4l2_subdev_frame_size_enum *fse)
 533 {
 534         const struct imx290 *imx290 = to_imx290(sd);
 535         const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);
 536
 537         if ((fse->code != imx290_formats[0].code) &&
 538             (fse->code != imx290_formats[1].code))
 539                 return -EINVAL;
 540
 541         if (fse->index >= imx290_modes_num(imx290))
 542                 return -EINVAL;
 543
 544         fse->min_width = imx290_modes[fse->index].width;
 545         fse->max_width = imx290_modes[fse->index].width;
 546         fse->min_height = imx290_modes[fse->index].height;
 547         fse->max_height = imx290_modes[fse->index].height;
 548
 549         return 0;
 550 }
 551
 552 static int imx290_get_fmt(struct v4l2_subdev *sd,
 553                           struct v4l2_subdev_pad_config *cfg,
 554                           struct v4l2_subdev_format *fmt)
 555 {
 556         struct imx290 *imx290 = to_imx290(sd);
 557         struct v4l2_mbus_framefmt *framefmt;
 558
 559         mutex_lock(&imx290->lock);
 560
 561         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
 562                 framefmt = v4l2_subdev_get_try_format(&imx290->sd, cfg,
 563                                                       fmt->pad);
 564         else
 565                 framefmt = &imx290->current_format;
 566
 567         fmt->format = *framefmt;
 568
 569         mutex_unlock(&imx290->lock);
 570
 571         return 0;
 572 }
 573
 574 static inline u8 imx290_get_link_freq_index(struct imx290 *imx290)
 575 {
 576         return imx290->current_mode->link_freq_index;
 577 }
 578
 579 static s64 imx290_get_link_freq(struct imx290 *imx290)
 580 {
 581         u8 index = imx290_get_link_freq_index(imx290);
 582
 583         return *(imx290_link_freqs_ptr(imx290) + index);
 584 }
 585
 586 static u64 imx290_calc_pixel_rate(struct imx290 *imx290)
 587 {
 588         s64 link_freq = imx290_get_link_freq(imx290);
 589         u8 nlanes = imx290->nlanes;
 590         u64 pixel_rate;
 591
 592         /* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
 593         pixel_rate = link_freq * 2 * nlanes;
 594         do_div(pixel_rate, imx290->bpp);
 595         return pixel_rate;
 596 }
 597
 598 static int imx290_set_fmt(struct v4l2_subdev *sd,
 599                           struct v4l2_subdev_pad_config *cfg,
 600                       struct v4l2_subdev_format *fmt)
 601 {
 602         struct imx290 *imx290 = to_imx290(sd);
 603         const struct imx290_mode *mode;
 604         struct v4l2_mbus_framefmt *format;
 605         unsigned int i;
 606
 607         mutex_lock(&imx290->lock);
 608
 609         mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
 610                                       imx290_modes_num(imx290), width, height,
 611                                       fmt->format.width, fmt->format.height);
 612
 613         fmt->format.width = mode->width;
 614         fmt->format.height = mode->height;
 615
 616         for (i = 0; i < ARRAY_SIZE(imx290_formats); i++)
 617                 if (imx290_formats[i].code == fmt->format.code)
 618                         break;
 619
 620         if (i >= ARRAY_SIZE(imx290_formats))
 621                 i = 0;
 622
 623         fmt->format.code = imx290_formats[i].code;
 624         fmt->format.field = V4L2_FIELD_NONE;
 625
 626         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 627                 format = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
 628         } else {
 629                 format = &imx290->current_format;
 630                 imx290->current_mode = mode;
 631                 imx290->bpp = imx290_formats[i].bpp;
 632
 633                 if (imx290->link_freq)
 634                         __v4l2_ctrl_s_ctrl(imx290->link_freq,
 635                                            imx290_get_link_freq_index(imx290));
 636                 if (imx290->pixel_rate)
 637                         __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,
 638                                                  imx290_calc_pixel_rate(imx290));
 639         }
 640
 641         *format = fmt->format;
 642
 643         mutex_unlock(&imx290->lock);
 644
 645         return 0;
 646 }
 647
 648 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev,
 649                                   struct v4l2_subdev_pad_config *cfg)
 650 {
 651         struct v4l2_subdev_format fmt = { 0 };
 652
 653         fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
 654         fmt.format.width = 1920;
 655         fmt.format.height = 1080;
 656
 657         imx290_set_fmt(subdev, cfg, &fmt);
 658
 659         return 0;
 660 }
 661
 662 static int imx290_write_current_format(struct imx290 *imx290)
 663 {
 664         int ret;
 665
 666         switch (imx290->current_format.code) {
 667         case MEDIA_BUS_FMT_SRGGB10_1X10:
 668                 ret = imx290_set_register_array(imx290, imx290_10bit_settings,
 669                                                 ARRAY_SIZE(
 670                                                         imx290_10bit_settings));
 671                 if (ret < 0) {
 672                         dev_err(imx290->dev, "Could not set format registers\n");
 673                         return ret;
 674                 }
 675                 break;
 676         case MEDIA_BUS_FMT_SRGGB12_1X12:
 677                 ret = imx290_set_register_array(imx290, imx290_12bit_settings,
 678                                                 ARRAY_SIZE(
 679                                                         imx290_12bit_settings));
 680                 if (ret < 0) {
 681                         dev_err(imx290->dev, "Could not set format registers\n");
 682                         return ret;
 683                 }
 684                 break;
 685         default:
 686                 dev_err(imx290->dev, "Unknown pixel format\n");
 687                 return -EINVAL;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int imx290_set_hmax(struct imx290 *imx290, u32 val)
 694 {
 695         int ret;
 696
 697         ret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (val & 0xff));
 698         if (ret) {
 699                 dev_err(imx290->dev, "Error setting HMAX register\n");
 700                 return ret;
 701         }
 702
 703         ret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((val >> 8) & 0xff));
 704         if (ret) {
 705                 dev_err(imx290->dev, "Error setting HMAX register\n");
 706                 return ret;
 707         }
 708
 709         return 0;
 710 }
 711
 712 /* Start streaming */
 713 static int imx290_start_streaming(struct imx290 *imx290)
 714 {
 715         int ret;
 716
 717         /* Set init register settings */
 718         ret = imx290_set_register_array(imx290, imx290_global_init_settings,
 719                                         ARRAY_SIZE(
 720                                                 imx290_global_init_settings));
 721         if (ret < 0) {
 722                 dev_err(imx290->dev, "Could not set init registers\n");
 723                 return ret;
 724         }
 725
 726         /* Apply the register values related to current frame format */
 727         ret = imx290_write_current_format(imx290);
 728         if (ret < 0) {
 729                 dev_err(imx290->dev, "Could not set frame format\n");
 730                 return ret;
 731         }
 732
 733         /* Apply default values of current mode */
 734         ret = imx290_set_register_array(imx290, imx290->current_mode->data,
 735                                         imx290->current_mode->data_size);
 736         if (ret < 0) {
 737                 dev_err(imx290->dev, "Could not set current mode\n");
 738                 return ret;
 739         }
 740         ret = imx290_set_hmax(imx290, imx290->current_mode->hmax);
 741         if (ret < 0)
 742                 return ret;
 743
 744         /* Apply customized values from user */
 745         ret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
 746         if (ret) {
 747                 dev_err(imx290->dev, "Could not sync v4l2 controls\n");
 748                 return ret;
 749         }
 750
 751         ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);
 752         if (ret < 0)
 753                 return ret;
 754
 755         msleep(30);
 756
 757         /* Start streaming */
 758         return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);
 759 }
 760
 761 static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
 762 {
 763         struct imx290 *imx290 = to_imx290(sd);
 764         int ret = 0;
 765
 766         if (enable) {
 767                 ret = pm_runtime_get_sync(imx290->dev);
 768                 if (ret < 0) {
 769                         pm_runtime_put_noidle(imx290->dev);
 770                         goto unlock_and_return;
 771                 }
 772
 773                 ret = imx290_start_streaming(imx290);
 774                 if (ret) {
 775                         dev_err(imx290->dev, "Start stream failed\n");
 776                         pm_runtime_put(imx290->dev);
 777                         goto unlock_and_return;
 778                 }
 779         } else {
 780                 imx290_stop_streaming(imx290);
 781                 pm_runtime_put(imx290->dev);
 782         }
 783
 784 unlock_and_return:
 785
 786         return ret;
 787 }
 788
 789 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
 790 {
 791         unsigned int i;
 792
 793         for (i = 0; i < IMX290_NUM_SUPPLIES; i++)
 794                 imx290->supplies[i].supply = imx290_supply_name[i];
 795
 796         return devm_regulator_bulk_get(dev, IMX290_NUM_SUPPLIES,
 797                                        imx290->supplies);
 798 }
 799
 800 static int imx290_set_data_lanes(struct imx290 *imx290)
 801 {
 802         int ret = 0, laneval, frsel;
 803
 804         switch (imx290->nlanes) {
 805         case 2:
 806                 laneval = 0x01;
 807                 frsel = 0x02;
 808                 break;
 809         case 4:
 810                 laneval = 0x03;
 811                 frsel = 0x01;
 812                 break;
 813         default:
 814                 /*
 815                  * We should never hit this since the data lane count is
 816                  * validated in probe itself
 817                  */
 818                 dev_err(imx290->dev, "Lane configuration not supported\n");
 819                 ret = -EINVAL;
 820                 goto exit;
 821         }
 822
 823         ret = imx290_write_reg(imx290, IMX290_PHY_LANE_NUM, laneval);
 824         if (ret) {
 825                 dev_err(imx290->dev, "Error setting Physical Lane number register\n");
 826                 goto exit;
 827         }
 828
 829         ret = imx290_write_reg(imx290, IMX290_CSI_LANE_MODE, laneval);
 830         if (ret) {
 831                 dev_err(imx290->dev, "Error setting CSI Lane mode register\n");
 832                 goto exit;
 833         }
 834
 835         ret = imx290_write_reg(imx290, IMX290_FR_FDG_SEL, frsel);
 836         if (ret)
 837                 dev_err(imx290->dev, "Error setting FR/FDG SEL register\n");
 838
 839 exit:
 840         return ret;
 841 }
 842
 843 static int imx290_power_on(struct device *dev)
 844 {
 845         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 846         struct imx290 *imx290 = to_imx290(sd);
 847         int ret;
 848
 849         ret = clk_prepare_enable(imx290->xclk);
 850         if (ret) {
 851                 dev_err(dev, "Failed to enable clock\n");
 852                 return ret;
 853         }
 854
 855         ret = regulator_bulk_enable(IMX290_NUM_SUPPLIES, imx290->supplies);
 856         if (ret) {
 857                 dev_err(dev, "Failed to enable regulators\n");
 858                 clk_disable_unprepare(imx290->xclk);
 859                 return ret;
 860         }
 861
 862         usleep_range(1, 2);
 863         gpiod_set_value_cansleep(imx290->rst_gpio, 0);
 864         usleep_range(30000, 31000);
 865
 866         /* Set data lane count */
 867         imx290_set_data_lanes(imx290);
 868
 869         return 0;
 870 }
 871
 872 static int imx290_power_off(struct device *dev)
 873 {
 874         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 875         struct imx290 *imx290 = to_imx290(sd);
 876
 877         clk_disable_unprepare(imx290->xclk);
 878         gpiod_set_value_cansleep(imx290->rst_gpio, 1);
 879         regulator_bulk_disable(IMX290_NUM_SUPPLIES, imx290->supplies);
 880
 881         return 0;
 882 }
 883
 884 static const struct dev_pm_ops imx290_pm_ops = {
 885         SET_RUNTIME_PM_OPS(imx290_power_off, imx290_power_on, NULL)
 886 };
 887
 888 static const struct v4l2_subdev_video_ops imx290_video_ops = {
 889         .s_stream = imx290_set_stream,
 890 };
 891
 892 static const struct v4l2_subdev_pad_ops imx290_pad_ops = {
 893         .init_cfg = imx290_entity_init_cfg,
 894         .enum_mbus_code = imx290_enum_mbus_code,
 895         .enum_frame_size = imx290_enum_frame_size,
 896         .get_fmt = imx290_get_fmt,
 897         .set_fmt = imx290_set_fmt,
 898 };
 899
 900 static const struct v4l2_subdev_ops imx290_subdev_ops = {
 901         .video = &imx290_video_ops,
 902         .pad = &imx290_pad_ops,
 903 };
 904
 905 static const struct media_entity_operations imx290_subdev_entity_ops = {
 906         .link_validate = v4l2_subdev_link_validate,
 907 };
 908
 909 /*
 910  * Returns 0 if all link frequencies used by the driver for the given number
 911  * of MIPI data lanes are mentioned in the device tree, or the value of the
 912  * first missing frequency otherwise.
 913  */
 914 static s64 imx290_check_link_freqs(const struct imx290 *imx290,
 915                                    const struct v4l2_fwnode_endpoint *ep)
 916 {
 917         int i, j;
 918         const s64 *freqs = imx290_link_freqs_ptr(imx290);
 919         int freqs_count = imx290_link_freqs_num(imx290);
 920
 921         for (i = 0; i < freqs_count; i++) {
 922                 for (j = 0; j < ep->nr_of_link_frequencies; j++)
 923                         if (freqs[i] == ep->link_frequencies[j])
 924                                 break;
 925                 if (j == ep->nr_of_link_frequencies)
 926                         return freqs[i];
 927         }
 928         return 0;
 929 }
 930
 931 static int imx290_probe(struct i2c_client *client)
 932 {
 933         struct device *dev = &client->dev;
 934         struct fwnode_handle *endpoint;
 935         /* Only CSI2 is supported for now: */
 936         struct v4l2_fwnode_endpoint ep = {
 937                 .bus_type = V4L2_MBUS_CSI2_DPHY
 938         };
 939         struct imx290 *imx290;
 940         u32 xclk_freq;
 941         s64 fq;
 942         int ret;
 943
 944         imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
 945         if (!imx290)
 946                 return -ENOMEM;
 947
 948         imx290->dev = dev;
 949         imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config);
 950         if (IS_ERR(imx290->regmap)) {
 951                 dev_err(dev, "Unable to initialize I2C\n");
 952                 return -ENODEV;
 953         }
 954
 955         endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
 956         if (!endpoint) {
 957                 dev_err(dev, "Endpoint node not found\n");
 958                 return -EINVAL;
 959         }
 960
 961         ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
 962         fwnode_handle_put(endpoint);
 963         if (ret == -ENXIO) {
 964                 dev_err(dev, "Unsupported bus type, should be CSI2\n");
 965                 goto free_err;
 966         } else if (ret) {
 967                 dev_err(dev, "Parsing endpoint node failed\n");
 968                 goto free_err;
 969         }
 970
 971         /* Get number of data lanes */
 972         imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
 973         if (imx290->nlanes != 2 && imx290->nlanes != 4) {
 974                 dev_err(dev, "Invalid data lanes: %d\n", imx290->nlanes);
 975                 ret = -EINVAL;
 976                 goto free_err;
 977         }
 978
 979         dev_dbg(dev, "Using %u data lanes\n", imx290->nlanes);
 980
 981         if (!ep.nr_of_link_frequencies) {
 982                 dev_err(dev, "link-frequency property not found in DT\n");
 983                 ret = -EINVAL;
 984                 goto free_err;
 985         }
 986
 987         /* Check that link frequences for all the modes are in device tree */
 988         fq = imx290_check_link_freqs(imx290, &ep);
 989         if (fq) {
 990                 dev_err(dev, "Link frequency of %lld is not supported\n", fq);
 991                 ret = -EINVAL;
 992                 goto free_err;
 993         }
 994
 995         /* get system clock (xclk) */
 996         imx290->xclk = devm_clk_get(dev, "xclk");
 997         if (IS_ERR(imx290->xclk)) {
 998                 dev_err(dev, "Could not get xclk");
 999                 ret = PTR_ERR(imx290->xclk);
1000                 goto free_err;
1001         }
1002
1003         ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1004                                        &xclk_freq);
1005         if (ret) {
1006                 dev_err(dev, "Could not get xclk frequency\n");
1007                 goto free_err;
1008         }
1009
1010         /* external clock must be 37.125 MHz */
1011         if (xclk_freq != 37125000) {
1012                 dev_err(dev, "External clock frequency %u is not supported\n",
1013                         xclk_freq);
1014                 ret = -EINVAL;
1015                 goto free_err;
1016         }
1017
1018         ret = clk_set_rate(imx290->xclk, xclk_freq);
1019         if (ret) {
1020                 dev_err(dev, "Could not set xclk frequency\n");
1021                 goto free_err;
1022         }
1023
1024         ret = imx290_get_regulators(dev, imx290);
1025         if (ret < 0) {
1026                 dev_err(dev, "Cannot get regulators\n");
1027                 goto free_err;
1028         }
1029
1030         imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
1031                                                    GPIOD_OUT_HIGH);
1032         if (IS_ERR(imx290->rst_gpio)) {
1033                 dev_err(dev, "Cannot get reset gpio\n");
1034                 ret = PTR_ERR(imx290->rst_gpio);
1035                 goto free_err;
1036         }
1037
1038         mutex_init(&imx290->lock);
1039
1040         /*
1041          * Initialize the frame format. In particular, imx290->current_mode
1042          * and imx290->bpp are set to defaults: imx290_calc_pixel_rate() call
1043          * below relies on these fields.
1044          */
1045         imx290_entity_init_cfg(&imx290->sd, NULL);
1046
1047         v4l2_ctrl_handler_init(&imx290->ctrls, 4);
1048
1049         v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1050                           V4L2_CID_GAIN, 0, 72, 1, 0);
1051
1052         imx290->link_freq =
1053                 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
1054                                        V4L2_CID_LINK_FREQ,
1055                                        imx290_link_freqs_num(imx290) - 1, 0,
1056                                        imx290_link_freqs_ptr(imx290));
1057         if (imx290->link_freq)
1058                 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1059
1060         imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1061                                                V4L2_CID_PIXEL_RATE,
1062                                                1, INT_MAX, 1,
1063                                                imx290_calc_pixel_rate(imx290));
1064
1065         v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
1066                                      V4L2_CID_TEST_PATTERN,
1067                                      ARRAY_SIZE(imx290_test_pattern_menu) - 1,
1068                                      0, 0, imx290_test_pattern_menu);
1069
1070         imx290->sd.ctrl_handler = &imx290->ctrls;
1071
1072         if (imx290->ctrls.error) {
1073                 dev_err(dev, "Control initialization error %d\n",
1074                         imx290->ctrls.error);
1075                 ret = imx290->ctrls.error;
1076                 goto free_ctrl;
1077         }
1078
1079         v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
1080         imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1081         imx290->sd.dev = &client->dev;
1082         imx290->sd.entity.ops = &imx290_subdev_entity_ops;
1083         imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1084
1085         imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
1086         ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
1087         if (ret < 0) {
1088                 dev_err(dev, "Could not register media entity\n");
1089                 goto free_ctrl;
1090         }
1091
1092         ret = v4l2_async_register_subdev(&imx290->sd);
1093         if (ret < 0) {
1094                 dev_err(dev, "Could not register v4l2 device\n");
1095                 goto free_entity;
1096         }
1097
1098         /* Power on the device to match runtime PM state below */
1099         ret = imx290_power_on(dev);
1100         if (ret < 0) {
1101                 dev_err(dev, "Could not power on the device\n");
1102                 goto free_entity;
1103         }
1104
1105         pm_runtime_set_active(dev);
1106         pm_runtime_enable(dev);
1107         pm_runtime_idle(dev);
1108
1109         v4l2_fwnode_endpoint_free(&ep);
1110
1111         return 0;
1112
1113 free_entity:
1114         media_entity_cleanup(&imx290->sd.entity);
1115 free_ctrl:
1116         v4l2_ctrl_handler_free(&imx290->ctrls);
1117         mutex_destroy(&imx290->lock);
1118 free_err:
1119         v4l2_fwnode_endpoint_free(&ep);
1120
1121         return ret;
1122 }
1123
1124 static int imx290_remove(struct i2c_client *client)
1125 {
1126         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1127         struct imx290 *imx290 = to_imx290(sd);
1128
1129         v4l2_async_unregister_subdev(sd);
1130         media_entity_cleanup(&sd->entity);
1131         v4l2_ctrl_handler_free(sd->ctrl_handler);
1132
1133         mutex_destroy(&imx290->lock);
1134
1135         pm_runtime_disable(imx290->dev);
1136         if (!pm_runtime_status_suspended(imx290->dev))
1137                 imx290_power_off(imx290->dev);
1138         pm_runtime_set_suspended(imx290->dev);
1139
1140         return 0;
1141 }
1142
1143 static const struct of_device_id imx290_of_match[] = {
1144         { .compatible = "sony,imx290" },
1145         { /* sentinel */ }
1146 };
1147 MODULE_DEVICE_TABLE(of, imx290_of_match);
1148
1149 static struct i2c_driver imx290_i2c_driver = {
1150         .probe_new  = imx290_probe,
1151         .remove = imx290_remove,
1152         .driver = {
1153                 .name  = "imx290",
1154                 .pm = &imx290_pm_ops,
1155                 .of_match_table = of_match_ptr(imx290_of_match),
1156         },
1157 };
1158
1159 module_i2c_driver(imx290_i2c_driver);
1160
1161 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver");
1162 MODULE_AUTHOR("FRAMOS GmbH");
1163 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
1164 MODULE_LICENSE("GPL v2");