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WIP FPC-III support
[linux/fpc-iii.git] / drivers / media / i2c / ov13858.c
blob2f3be7a80cef4c8db9e358b3e42a64674b43abfa
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/i2c.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <media/v4l2-ctrls.h>
9 #include <media/v4l2-device.h>
10 #include <media/v4l2-fwnode.h>
11
12 #define OV13858_REG_VALUE_08BIT 1
13 #define OV13858_REG_VALUE_16BIT 2
14 #define OV13858_REG_VALUE_24BIT 3
15
16 #define OV13858_REG_MODE_SELECT 0x0100
17 #define OV13858_MODE_STANDBY 0x00
18 #define OV13858_MODE_STREAMING 0x01
19
20 #define OV13858_REG_SOFTWARE_RST 0x0103
21 #define OV13858_SOFTWARE_RST 0x01
22
23 /* PLL1 generates PCLK and MIPI_PHY_CLK */
24 #define OV13858_REG_PLL1_CTRL_0 0x0300
25 #define OV13858_REG_PLL1_CTRL_1 0x0301
26 #define OV13858_REG_PLL1_CTRL_2 0x0302
27 #define OV13858_REG_PLL1_CTRL_3 0x0303
28 #define OV13858_REG_PLL1_CTRL_4 0x0304
29 #define OV13858_REG_PLL1_CTRL_5 0x0305
30
31 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
32 #define OV13858_REG_PLL2_CTRL_B 0x030b
33 #define OV13858_REG_PLL2_CTRL_C 0x030c
34 #define OV13858_REG_PLL2_CTRL_D 0x030d
35 #define OV13858_REG_PLL2_CTRL_E 0x030e
36 #define OV13858_REG_PLL2_CTRL_F 0x030f
37 #define OV13858_REG_PLL2_CTRL_12 0x0312
38 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
39 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
40
41 /* Chip ID */
42 #define OV13858_REG_CHIP_ID 0x300a
43 #define OV13858_CHIP_ID 0x00d855
44
45 /* V_TIMING internal */
46 #define OV13858_REG_VTS 0x380e
47 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
48 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
49 #define OV13858_VTS_MAX 0x7fff
50
51 /* HBLANK control - read only */
52 #define OV13858_PPL_270MHZ 2244
53 #define OV13858_PPL_540MHZ 4488
54
55 /* Exposure control */
56 #define OV13858_REG_EXPOSURE 0x3500
57 #define OV13858_EXPOSURE_MIN 4
58 #define OV13858_EXPOSURE_STEP 1
59 #define OV13858_EXPOSURE_DEFAULT 0x640
60
61 /* Analog gain control */
62 #define OV13858_REG_ANALOG_GAIN 0x3508
63 #define OV13858_ANA_GAIN_MIN 0
64 #define OV13858_ANA_GAIN_MAX 0x1fff
65 #define OV13858_ANA_GAIN_STEP 1
66 #define OV13858_ANA_GAIN_DEFAULT 0x80
67
68 /* Digital gain control */
69 #define OV13858_REG_B_MWB_GAIN 0x5100
70 #define OV13858_REG_G_MWB_GAIN 0x5102
71 #define OV13858_REG_R_MWB_GAIN 0x5104
72 #define OV13858_DGTL_GAIN_MIN 0
73 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
74 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
75 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
76
77 /* Test Pattern Control */
78 #define OV13858_REG_TEST_PATTERN 0x4503
79 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
80 #define OV13858_TEST_PATTERN_MASK 0xfc
81
82 /* Number of frames to skip */
83 #define OV13858_NUM_OF_SKIP_FRAMES 2
84
85 struct ov13858_reg {
86 u16 address;
87 u8 val;
88 };
89
90 struct ov13858_reg_list {
91 u32 num_of_regs;
92 const struct ov13858_reg *regs;
93 };
94
95 /* Link frequency config */
96 struct ov13858_link_freq_config {
97 u32 pixels_per_line;
98
99 /* PLL registers for this link frequency */
100 struct ov13858_reg_list reg_list;
101 };
102
103 /* Mode : resolution and related config&values */
104 struct ov13858_mode {
105 /* Frame width */
106 u32 width;
107 /* Frame height */
108 u32 height;
109
110 /* V-timing */
111 u32 vts_def;
112 u32 vts_min;
113
114 /* Index of Link frequency config to be used */
115 u32 link_freq_index;
116 /* Default register values */
117 struct ov13858_reg_list reg_list;
118 };
119
120 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
121 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
122 /* PLL1 registers */
123 {OV13858_REG_PLL1_CTRL_0, 0x07},
124 {OV13858_REG_PLL1_CTRL_1, 0x01},
125 {OV13858_REG_PLL1_CTRL_2, 0xc2},
126 {OV13858_REG_PLL1_CTRL_3, 0x00},
127 {OV13858_REG_PLL1_CTRL_4, 0x00},
128 {OV13858_REG_PLL1_CTRL_5, 0x01},
129
130 /* PLL2 registers */
131 {OV13858_REG_PLL2_CTRL_B, 0x05},
132 {OV13858_REG_PLL2_CTRL_C, 0x01},
133 {OV13858_REG_PLL2_CTRL_D, 0x0e},
134 {OV13858_REG_PLL2_CTRL_E, 0x05},
135 {OV13858_REG_PLL2_CTRL_F, 0x01},
136 {OV13858_REG_PLL2_CTRL_12, 0x01},
137 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
138 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
139 };
140
141 /*
142 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
143 * 4 lanes
144 */
145 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
146 /* PLL1 registers */
147 {OV13858_REG_PLL1_CTRL_0, 0x07},
148 {OV13858_REG_PLL1_CTRL_1, 0x01},
149 {OV13858_REG_PLL1_CTRL_2, 0xc2},
150 {OV13858_REG_PLL1_CTRL_3, 0x01},
151 {OV13858_REG_PLL1_CTRL_4, 0x00},
152 {OV13858_REG_PLL1_CTRL_5, 0x01},
153
154 /* PLL2 registers */
155 {OV13858_REG_PLL2_CTRL_B, 0x05},
156 {OV13858_REG_PLL2_CTRL_C, 0x01},
157 {OV13858_REG_PLL2_CTRL_D, 0x0e},
158 {OV13858_REG_PLL2_CTRL_E, 0x05},
159 {OV13858_REG_PLL2_CTRL_F, 0x01},
160 {OV13858_REG_PLL2_CTRL_12, 0x01},
161 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
162 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
163 };
164
165 static const struct ov13858_reg mode_4224x3136_regs[] = {
166 {0x3013, 0x32},
167 {0x301b, 0xf0},
168 {0x301f, 0xd0},
169 {0x3106, 0x15},
170 {0x3107, 0x23},
171 {0x350a, 0x00},
172 {0x350e, 0x00},
173 {0x3510, 0x00},
174 {0x3511, 0x02},
175 {0x3512, 0x00},
176 {0x3600, 0x2b},
177 {0x3601, 0x52},
178 {0x3602, 0x60},
179 {0x3612, 0x05},
180 {0x3613, 0xa4},
181 {0x3620, 0x80},
182 {0x3621, 0x10},
183 {0x3622, 0x30},
184 {0x3624, 0x1c},
185 {0x3640, 0x10},
186 {0x3641, 0x70},
187 {0x3660, 0x04},
188 {0x3661, 0x80},
189 {0x3662, 0x12},
190 {0x3664, 0x73},
191 {0x3665, 0xa7},
192 {0x366e, 0xff},
193 {0x366f, 0xf4},
194 {0x3674, 0x00},
195 {0x3679, 0x0c},
196 {0x367f, 0x01},
197 {0x3680, 0x0c},
198 {0x3681, 0x50},
199 {0x3682, 0x50},
200 {0x3683, 0xa9},
201 {0x3684, 0xa9},
202 {0x3709, 0x5f},
203 {0x3714, 0x24},
204 {0x371a, 0x3e},
205 {0x3737, 0x04},
206 {0x3738, 0xcc},
207 {0x3739, 0x12},
208 {0x373d, 0x26},
209 {0x3764, 0x20},
210 {0x3765, 0x20},
211 {0x37a1, 0x36},
212 {0x37a8, 0x3b},
213 {0x37ab, 0x31},
214 {0x37c2, 0x04},
215 {0x37c3, 0xf1},
216 {0x37c5, 0x00},
217 {0x37d8, 0x03},
218 {0x37d9, 0x0c},
219 {0x37da, 0xc2},
220 {0x37dc, 0x02},
221 {0x37e0, 0x00},
222 {0x37e1, 0x0a},
223 {0x37e2, 0x14},
224 {0x37e3, 0x04},
225 {0x37e4, 0x2a},
226 {0x37e5, 0x03},
227 {0x37e6, 0x04},
228 {0x3800, 0x00},
229 {0x3801, 0x00},
230 {0x3802, 0x00},
231 {0x3803, 0x08},
232 {0x3804, 0x10},
233 {0x3805, 0x9f},
234 {0x3806, 0x0c},
235 {0x3807, 0x57},
236 {0x3808, 0x10},
237 {0x3809, 0x80},
238 {0x380a, 0x0c},
239 {0x380b, 0x40},
240 {0x380c, 0x04},
241 {0x380d, 0x62},
242 {0x380e, 0x0c},
243 {0x380f, 0x8e},
244 {0x3811, 0x04},
245 {0x3813, 0x05},
246 {0x3814, 0x01},
247 {0x3815, 0x01},
248 {0x3816, 0x01},
249 {0x3817, 0x01},
250 {0x3820, 0xa8},
251 {0x3821, 0x00},
252 {0x3822, 0xc2},
253 {0x3823, 0x18},
254 {0x3826, 0x11},
255 {0x3827, 0x1c},
256 {0x3829, 0x03},
257 {0x3832, 0x00},
258 {0x3c80, 0x00},
259 {0x3c87, 0x01},
260 {0x3c8c, 0x19},
261 {0x3c8d, 0x1c},
262 {0x3c90, 0x00},
263 {0x3c91, 0x00},
264 {0x3c92, 0x00},
265 {0x3c93, 0x00},
266 {0x3c94, 0x40},
267 {0x3c95, 0x54},
268 {0x3c96, 0x34},
269 {0x3c97, 0x04},
270 {0x3c98, 0x00},
271 {0x3d8c, 0x73},
272 {0x3d8d, 0xc0},
273 {0x3f00, 0x0b},
274 {0x3f03, 0x00},
275 {0x4001, 0xe0},
276 {0x4008, 0x00},
277 {0x4009, 0x0f},
278 {0x4011, 0xf0},
279 {0x4017, 0x08},
280 {0x4050, 0x04},
281 {0x4051, 0x0b},
282 {0x4052, 0x00},
283 {0x4053, 0x80},
284 {0x4054, 0x00},
285 {0x4055, 0x80},
286 {0x4056, 0x00},
287 {0x4057, 0x80},
288 {0x4058, 0x00},
289 {0x4059, 0x80},
290 {0x405e, 0x20},
291 {0x4500, 0x07},
292 {0x4503, 0x00},
293 {0x450a, 0x04},
294 {0x4809, 0x04},
295 {0x480c, 0x12},
296 {0x481f, 0x30},
297 {0x4833, 0x10},
298 {0x4837, 0x0e},
299 {0x4902, 0x01},
300 {0x4d00, 0x03},
301 {0x4d01, 0xc9},
302 {0x4d02, 0xbc},
303 {0x4d03, 0xd7},
304 {0x4d04, 0xf0},
305 {0x4d05, 0xa2},
306 {0x5000, 0xfd},
307 {0x5001, 0x01},
308 {0x5040, 0x39},
309 {0x5041, 0x10},
310 {0x5042, 0x10},
311 {0x5043, 0x84},
312 {0x5044, 0x62},
313 {0x5180, 0x00},
314 {0x5181, 0x10},
315 {0x5182, 0x02},
316 {0x5183, 0x0f},
317 {0x5200, 0x1b},
318 {0x520b, 0x07},
319 {0x520c, 0x0f},
320 {0x5300, 0x04},
321 {0x5301, 0x0c},
322 {0x5302, 0x0c},
323 {0x5303, 0x0f},
324 {0x5304, 0x00},
325 {0x5305, 0x70},
326 {0x5306, 0x00},
327 {0x5307, 0x80},
328 {0x5308, 0x00},
329 {0x5309, 0xa5},
330 {0x530a, 0x00},
331 {0x530b, 0xd3},
332 {0x530c, 0x00},
333 {0x530d, 0xf0},
334 {0x530e, 0x01},
335 {0x530f, 0x10},
336 {0x5310, 0x01},
337 {0x5311, 0x20},
338 {0x5312, 0x01},
339 {0x5313, 0x20},
340 {0x5314, 0x01},
341 {0x5315, 0x20},
342 {0x5316, 0x08},
343 {0x5317, 0x08},
344 {0x5318, 0x10},
345 {0x5319, 0x88},
346 {0x531a, 0x88},
347 {0x531b, 0xa9},
348 {0x531c, 0xaa},
349 {0x531d, 0x0a},
350 {0x5405, 0x02},
351 {0x5406, 0x67},
352 {0x5407, 0x01},
353 {0x5408, 0x4a},
354 };
355
356 static const struct ov13858_reg mode_2112x1568_regs[] = {
357 {0x3013, 0x32},
358 {0x301b, 0xf0},
359 {0x301f, 0xd0},
360 {0x3106, 0x15},
361 {0x3107, 0x23},
362 {0x350a, 0x00},
363 {0x350e, 0x00},
364 {0x3510, 0x00},
365 {0x3511, 0x02},
366 {0x3512, 0x00},
367 {0x3600, 0x2b},
368 {0x3601, 0x52},
369 {0x3602, 0x60},
370 {0x3612, 0x05},
371 {0x3613, 0xa4},
372 {0x3620, 0x80},
373 {0x3621, 0x10},
374 {0x3622, 0x30},
375 {0x3624, 0x1c},
376 {0x3640, 0x10},
377 {0x3641, 0x70},
378 {0x3660, 0x04},
379 {0x3661, 0x80},
380 {0x3662, 0x10},
381 {0x3664, 0x73},
382 {0x3665, 0xa7},
383 {0x366e, 0xff},
384 {0x366f, 0xf4},
385 {0x3674, 0x00},
386 {0x3679, 0x0c},
387 {0x367f, 0x01},
388 {0x3680, 0x0c},
389 {0x3681, 0x50},
390 {0x3682, 0x50},
391 {0x3683, 0xa9},
392 {0x3684, 0xa9},
393 {0x3709, 0x5f},
394 {0x3714, 0x28},
395 {0x371a, 0x3e},
396 {0x3737, 0x08},
397 {0x3738, 0xcc},
398 {0x3739, 0x20},
399 {0x373d, 0x26},
400 {0x3764, 0x20},
401 {0x3765, 0x20},
402 {0x37a1, 0x36},
403 {0x37a8, 0x3b},
404 {0x37ab, 0x31},
405 {0x37c2, 0x14},
406 {0x37c3, 0xf1},
407 {0x37c5, 0x00},
408 {0x37d8, 0x03},
409 {0x37d9, 0x0c},
410 {0x37da, 0xc2},
411 {0x37dc, 0x02},
412 {0x37e0, 0x00},
413 {0x37e1, 0x0a},
414 {0x37e2, 0x14},
415 {0x37e3, 0x08},
416 {0x37e4, 0x38},
417 {0x37e5, 0x03},
418 {0x37e6, 0x08},
419 {0x3800, 0x00},
420 {0x3801, 0x00},
421 {0x3802, 0x00},
422 {0x3803, 0x00},
423 {0x3804, 0x10},
424 {0x3805, 0x9f},
425 {0x3806, 0x0c},
426 {0x3807, 0x5f},
427 {0x3808, 0x08},
428 {0x3809, 0x40},
429 {0x380a, 0x06},
430 {0x380b, 0x20},
431 {0x380c, 0x04},
432 {0x380d, 0x62},
433 {0x380e, 0x0c},
434 {0x380f, 0x8e},
435 {0x3811, 0x04},
436 {0x3813, 0x05},
437 {0x3814, 0x03},
438 {0x3815, 0x01},
439 {0x3816, 0x03},
440 {0x3817, 0x01},
441 {0x3820, 0xab},
442 {0x3821, 0x00},
443 {0x3822, 0xc2},
444 {0x3823, 0x18},
445 {0x3826, 0x04},
446 {0x3827, 0x90},
447 {0x3829, 0x07},
448 {0x3832, 0x00},
449 {0x3c80, 0x00},
450 {0x3c87, 0x01},
451 {0x3c8c, 0x19},
452 {0x3c8d, 0x1c},
453 {0x3c90, 0x00},
454 {0x3c91, 0x00},
455 {0x3c92, 0x00},
456 {0x3c93, 0x00},
457 {0x3c94, 0x40},
458 {0x3c95, 0x54},
459 {0x3c96, 0x34},
460 {0x3c97, 0x04},
461 {0x3c98, 0x00},
462 {0x3d8c, 0x73},
463 {0x3d8d, 0xc0},
464 {0x3f00, 0x0b},
465 {0x3f03, 0x00},
466 {0x4001, 0xe0},
467 {0x4008, 0x00},
468 {0x4009, 0x0d},
469 {0x4011, 0xf0},
470 {0x4017, 0x08},
471 {0x4050, 0x04},
472 {0x4051, 0x0b},
473 {0x4052, 0x00},
474 {0x4053, 0x80},
475 {0x4054, 0x00},
476 {0x4055, 0x80},
477 {0x4056, 0x00},
478 {0x4057, 0x80},
479 {0x4058, 0x00},
480 {0x4059, 0x80},
481 {0x405e, 0x20},
482 {0x4500, 0x07},
483 {0x4503, 0x00},
484 {0x450a, 0x04},
485 {0x4809, 0x04},
486 {0x480c, 0x12},
487 {0x481f, 0x30},
488 {0x4833, 0x10},
489 {0x4837, 0x1c},
490 {0x4902, 0x01},
491 {0x4d00, 0x03},
492 {0x4d01, 0xc9},
493 {0x4d02, 0xbc},
494 {0x4d03, 0xd7},
495 {0x4d04, 0xf0},
496 {0x4d05, 0xa2},
497 {0x5000, 0xfd},
498 {0x5001, 0x01},
499 {0x5040, 0x39},
500 {0x5041, 0x10},
501 {0x5042, 0x10},
502 {0x5043, 0x84},
503 {0x5044, 0x62},
504 {0x5180, 0x00},
505 {0x5181, 0x10},
506 {0x5182, 0x02},
507 {0x5183, 0x0f},
508 {0x5200, 0x1b},
509 {0x520b, 0x07},
510 {0x520c, 0x0f},
511 {0x5300, 0x04},
512 {0x5301, 0x0c},
513 {0x5302, 0x0c},
514 {0x5303, 0x0f},
515 {0x5304, 0x00},
516 {0x5305, 0x70},
517 {0x5306, 0x00},
518 {0x5307, 0x80},
519 {0x5308, 0x00},
520 {0x5309, 0xa5},
521 {0x530a, 0x00},
522 {0x530b, 0xd3},
523 {0x530c, 0x00},
524 {0x530d, 0xf0},
525 {0x530e, 0x01},
526 {0x530f, 0x10},
527 {0x5310, 0x01},
528 {0x5311, 0x20},
529 {0x5312, 0x01},
530 {0x5313, 0x20},
531 {0x5314, 0x01},
532 {0x5315, 0x20},
533 {0x5316, 0x08},
534 {0x5317, 0x08},
535 {0x5318, 0x10},
536 {0x5319, 0x88},
537 {0x531a, 0x88},
538 {0x531b, 0xa9},
539 {0x531c, 0xaa},
540 {0x531d, 0x0a},
541 {0x5405, 0x02},
542 {0x5406, 0x67},
543 {0x5407, 0x01},
544 {0x5408, 0x4a},
545 };
546
547 static const struct ov13858_reg mode_2112x1188_regs[] = {
548 {0x3013, 0x32},
549 {0x301b, 0xf0},
550 {0x301f, 0xd0},
551 {0x3106, 0x15},
552 {0x3107, 0x23},
553 {0x350a, 0x00},
554 {0x350e, 0x00},
555 {0x3510, 0x00},
556 {0x3511, 0x02},
557 {0x3512, 0x00},
558 {0x3600, 0x2b},
559 {0x3601, 0x52},
560 {0x3602, 0x60},
561 {0x3612, 0x05},
562 {0x3613, 0xa4},
563 {0x3620, 0x80},
564 {0x3621, 0x10},
565 {0x3622, 0x30},
566 {0x3624, 0x1c},
567 {0x3640, 0x10},
568 {0x3641, 0x70},
569 {0x3660, 0x04},
570 {0x3661, 0x80},
571 {0x3662, 0x10},
572 {0x3664, 0x73},
573 {0x3665, 0xa7},
574 {0x366e, 0xff},
575 {0x366f, 0xf4},
576 {0x3674, 0x00},
577 {0x3679, 0x0c},
578 {0x367f, 0x01},
579 {0x3680, 0x0c},
580 {0x3681, 0x50},
581 {0x3682, 0x50},
582 {0x3683, 0xa9},
583 {0x3684, 0xa9},
584 {0x3709, 0x5f},
585 {0x3714, 0x28},
586 {0x371a, 0x3e},
587 {0x3737, 0x08},
588 {0x3738, 0xcc},
589 {0x3739, 0x20},
590 {0x373d, 0x26},
591 {0x3764, 0x20},
592 {0x3765, 0x20},
593 {0x37a1, 0x36},
594 {0x37a8, 0x3b},
595 {0x37ab, 0x31},
596 {0x37c2, 0x14},
597 {0x37c3, 0xf1},
598 {0x37c5, 0x00},
599 {0x37d8, 0x03},
600 {0x37d9, 0x0c},
601 {0x37da, 0xc2},
602 {0x37dc, 0x02},
603 {0x37e0, 0x00},
604 {0x37e1, 0x0a},
605 {0x37e2, 0x14},
606 {0x37e3, 0x08},
607 {0x37e4, 0x38},
608 {0x37e5, 0x03},
609 {0x37e6, 0x08},
610 {0x3800, 0x00},
611 {0x3801, 0x00},
612 {0x3802, 0x01},
613 {0x3803, 0x84},
614 {0x3804, 0x10},
615 {0x3805, 0x9f},
616 {0x3806, 0x0a},
617 {0x3807, 0xd3},
618 {0x3808, 0x08},
619 {0x3809, 0x40},
620 {0x380a, 0x04},
621 {0x380b, 0xa4},
622 {0x380c, 0x04},
623 {0x380d, 0x62},
624 {0x380e, 0x0c},
625 {0x380f, 0x8e},
626 {0x3811, 0x08},
627 {0x3813, 0x03},
628 {0x3814, 0x03},
629 {0x3815, 0x01},
630 {0x3816, 0x03},
631 {0x3817, 0x01},
632 {0x3820, 0xab},
633 {0x3821, 0x00},
634 {0x3822, 0xc2},
635 {0x3823, 0x18},
636 {0x3826, 0x04},
637 {0x3827, 0x90},
638 {0x3829, 0x07},
639 {0x3832, 0x00},
640 {0x3c80, 0x00},
641 {0x3c87, 0x01},
642 {0x3c8c, 0x19},
643 {0x3c8d, 0x1c},
644 {0x3c90, 0x00},
645 {0x3c91, 0x00},
646 {0x3c92, 0x00},
647 {0x3c93, 0x00},
648 {0x3c94, 0x40},
649 {0x3c95, 0x54},
650 {0x3c96, 0x34},
651 {0x3c97, 0x04},
652 {0x3c98, 0x00},
653 {0x3d8c, 0x73},
654 {0x3d8d, 0xc0},
655 {0x3f00, 0x0b},
656 {0x3f03, 0x00},
657 {0x4001, 0xe0},
658 {0x4008, 0x00},
659 {0x4009, 0x0d},
660 {0x4011, 0xf0},
661 {0x4017, 0x08},
662 {0x4050, 0x04},
663 {0x4051, 0x0b},
664 {0x4052, 0x00},
665 {0x4053, 0x80},
666 {0x4054, 0x00},
667 {0x4055, 0x80},
668 {0x4056, 0x00},
669 {0x4057, 0x80},
670 {0x4058, 0x00},
671 {0x4059, 0x80},
672 {0x405e, 0x20},
673 {0x4500, 0x07},
674 {0x4503, 0x00},
675 {0x450a, 0x04},
676 {0x4809, 0x04},
677 {0x480c, 0x12},
678 {0x481f, 0x30},
679 {0x4833, 0x10},
680 {0x4837, 0x1c},
681 {0x4902, 0x01},
682 {0x4d00, 0x03},
683 {0x4d01, 0xc9},
684 {0x4d02, 0xbc},
685 {0x4d03, 0xd7},
686 {0x4d04, 0xf0},
687 {0x4d05, 0xa2},
688 {0x5000, 0xfd},
689 {0x5001, 0x01},
690 {0x5040, 0x39},
691 {0x5041, 0x10},
692 {0x5042, 0x10},
693 {0x5043, 0x84},
694 {0x5044, 0x62},
695 {0x5180, 0x00},
696 {0x5181, 0x10},
697 {0x5182, 0x02},
698 {0x5183, 0x0f},
699 {0x5200, 0x1b},
700 {0x520b, 0x07},
701 {0x520c, 0x0f},
702 {0x5300, 0x04},
703 {0x5301, 0x0c},
704 {0x5302, 0x0c},
705 {0x5303, 0x0f},
706 {0x5304, 0x00},
707 {0x5305, 0x70},
708 {0x5306, 0x00},
709 {0x5307, 0x80},
710 {0x5308, 0x00},
711 {0x5309, 0xa5},
712 {0x530a, 0x00},
713 {0x530b, 0xd3},
714 {0x530c, 0x00},
715 {0x530d, 0xf0},
716 {0x530e, 0x01},
717 {0x530f, 0x10},
718 {0x5310, 0x01},
719 {0x5311, 0x20},
720 {0x5312, 0x01},
721 {0x5313, 0x20},
722 {0x5314, 0x01},
723 {0x5315, 0x20},
724 {0x5316, 0x08},
725 {0x5317, 0x08},
726 {0x5318, 0x10},
727 {0x5319, 0x88},
728 {0x531a, 0x88},
729 {0x531b, 0xa9},
730 {0x531c, 0xaa},
731 {0x531d, 0x0a},
732 {0x5405, 0x02},
733 {0x5406, 0x67},
734 {0x5407, 0x01},
735 {0x5408, 0x4a},
736 };
737
738 static const struct ov13858_reg mode_1056x784_regs[] = {
739 {0x3013, 0x32},
740 {0x301b, 0xf0},
741 {0x301f, 0xd0},
742 {0x3106, 0x15},
743 {0x3107, 0x23},
744 {0x350a, 0x00},
745 {0x350e, 0x00},
746 {0x3510, 0x00},
747 {0x3511, 0x02},
748 {0x3512, 0x00},
749 {0x3600, 0x2b},
750 {0x3601, 0x52},
751 {0x3602, 0x60},
752 {0x3612, 0x05},
753 {0x3613, 0xa4},
754 {0x3620, 0x80},
755 {0x3621, 0x10},
756 {0x3622, 0x30},
757 {0x3624, 0x1c},
758 {0x3640, 0x10},
759 {0x3641, 0x70},
760 {0x3660, 0x04},
761 {0x3661, 0x80},
762 {0x3662, 0x08},
763 {0x3664, 0x73},
764 {0x3665, 0xa7},
765 {0x366e, 0xff},
766 {0x366f, 0xf4},
767 {0x3674, 0x00},
768 {0x3679, 0x0c},
769 {0x367f, 0x01},
770 {0x3680, 0x0c},
771 {0x3681, 0x50},
772 {0x3682, 0x50},
773 {0x3683, 0xa9},
774 {0x3684, 0xa9},
775 {0x3709, 0x5f},
776 {0x3714, 0x30},
777 {0x371a, 0x3e},
778 {0x3737, 0x08},
779 {0x3738, 0xcc},
780 {0x3739, 0x20},
781 {0x373d, 0x26},
782 {0x3764, 0x20},
783 {0x3765, 0x20},
784 {0x37a1, 0x36},
785 {0x37a8, 0x3b},
786 {0x37ab, 0x31},
787 {0x37c2, 0x2c},
788 {0x37c3, 0xf1},
789 {0x37c5, 0x00},
790 {0x37d8, 0x03},
791 {0x37d9, 0x06},
792 {0x37da, 0xc2},
793 {0x37dc, 0x02},
794 {0x37e0, 0x00},
795 {0x37e1, 0x0a},
796 {0x37e2, 0x14},
797 {0x37e3, 0x08},
798 {0x37e4, 0x36},
799 {0x37e5, 0x03},
800 {0x37e6, 0x08},
801 {0x3800, 0x00},
802 {0x3801, 0x00},
803 {0x3802, 0x00},
804 {0x3803, 0x00},
805 {0x3804, 0x10},
806 {0x3805, 0x9f},
807 {0x3806, 0x0c},
808 {0x3807, 0x5f},
809 {0x3808, 0x04},
810 {0x3809, 0x20},
811 {0x380a, 0x03},
812 {0x380b, 0x10},
813 {0x380c, 0x04},
814 {0x380d, 0x62},
815 {0x380e, 0x0c},
816 {0x380f, 0x8e},
817 {0x3811, 0x04},
818 {0x3813, 0x05},
819 {0x3814, 0x07},
820 {0x3815, 0x01},
821 {0x3816, 0x07},
822 {0x3817, 0x01},
823 {0x3820, 0xac},
824 {0x3821, 0x00},
825 {0x3822, 0xc2},
826 {0x3823, 0x18},
827 {0x3826, 0x04},
828 {0x3827, 0x48},
829 {0x3829, 0x03},
830 {0x3832, 0x00},
831 {0x3c80, 0x00},
832 {0x3c87, 0x01},
833 {0x3c8c, 0x19},
834 {0x3c8d, 0x1c},
835 {0x3c90, 0x00},
836 {0x3c91, 0x00},
837 {0x3c92, 0x00},
838 {0x3c93, 0x00},
839 {0x3c94, 0x40},
840 {0x3c95, 0x54},
841 {0x3c96, 0x34},
842 {0x3c97, 0x04},
843 {0x3c98, 0x00},
844 {0x3d8c, 0x73},
845 {0x3d8d, 0xc0},
846 {0x3f00, 0x0b},
847 {0x3f03, 0x00},
848 {0x4001, 0xe0},
849 {0x4008, 0x00},
850 {0x4009, 0x05},
851 {0x4011, 0xf0},
852 {0x4017, 0x08},
853 {0x4050, 0x02},
854 {0x4051, 0x05},
855 {0x4052, 0x00},
856 {0x4053, 0x80},
857 {0x4054, 0x00},
858 {0x4055, 0x80},
859 {0x4056, 0x00},
860 {0x4057, 0x80},
861 {0x4058, 0x00},
862 {0x4059, 0x80},
863 {0x405e, 0x20},
864 {0x4500, 0x07},
865 {0x4503, 0x00},
866 {0x450a, 0x04},
867 {0x4809, 0x04},
868 {0x480c, 0x12},
869 {0x481f, 0x30},
870 {0x4833, 0x10},
871 {0x4837, 0x1e},
872 {0x4902, 0x02},
873 {0x4d00, 0x03},
874 {0x4d01, 0xc9},
875 {0x4d02, 0xbc},
876 {0x4d03, 0xd7},
877 {0x4d04, 0xf0},
878 {0x4d05, 0xa2},
879 {0x5000, 0xfd},
880 {0x5001, 0x01},
881 {0x5040, 0x39},
882 {0x5041, 0x10},
883 {0x5042, 0x10},
884 {0x5043, 0x84},
885 {0x5044, 0x62},
886 {0x5180, 0x00},
887 {0x5181, 0x10},
888 {0x5182, 0x02},
889 {0x5183, 0x0f},
890 {0x5200, 0x1b},
891 {0x520b, 0x07},
892 {0x520c, 0x0f},
893 {0x5300, 0x04},
894 {0x5301, 0x0c},
895 {0x5302, 0x0c},
896 {0x5303, 0x0f},
897 {0x5304, 0x00},
898 {0x5305, 0x70},
899 {0x5306, 0x00},
900 {0x5307, 0x80},
901 {0x5308, 0x00},
902 {0x5309, 0xa5},
903 {0x530a, 0x00},
904 {0x530b, 0xd3},
905 {0x530c, 0x00},
906 {0x530d, 0xf0},
907 {0x530e, 0x01},
908 {0x530f, 0x10},
909 {0x5310, 0x01},
910 {0x5311, 0x20},
911 {0x5312, 0x01},
912 {0x5313, 0x20},
913 {0x5314, 0x01},
914 {0x5315, 0x20},
915 {0x5316, 0x08},
916 {0x5317, 0x08},
917 {0x5318, 0x10},
918 {0x5319, 0x88},
919 {0x531a, 0x88},
920 {0x531b, 0xa9},
921 {0x531c, 0xaa},
922 {0x531d, 0x0a},
923 {0x5405, 0x02},
924 {0x5406, 0x67},
925 {0x5407, 0x01},
926 {0x5408, 0x4a},
927 };
928
929 static const char * const ov13858_test_pattern_menu[] = {
930 "Disabled",
931 "Vertical Color Bar Type 1",
932 "Vertical Color Bar Type 2",
933 "Vertical Color Bar Type 3",
934 "Vertical Color Bar Type 4"
935 };
936
937 /* Configurations for supported link frequencies */
938 #define OV13858_NUM_OF_LINK_FREQS 2
939 #define OV13858_LINK_FREQ_540MHZ 540000000ULL
940 #define OV13858_LINK_FREQ_270MHZ 270000000ULL
941 #define OV13858_LINK_FREQ_INDEX_0 0
942 #define OV13858_LINK_FREQ_INDEX_1 1
943
944 /*
945 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
946 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
947 */
948 static u64 link_freq_to_pixel_rate(u64 f)
949 {
950 f *= 2 * 4;
951 do_div(f, 10);
952
953 return f;
954 }
955
956 /* Menu items for LINK_FREQ V4L2 control */
957 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
958 OV13858_LINK_FREQ_540MHZ,
959 OV13858_LINK_FREQ_270MHZ
960 };
961
962 /* Link frequency configs */
963 static const struct ov13858_link_freq_config
964 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
965 {
966 .pixels_per_line = OV13858_PPL_540MHZ,
967 .reg_list = {
968 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
969 .regs = mipi_data_rate_1080mbps,
970 }
971 },
972 {
973 .pixels_per_line = OV13858_PPL_270MHZ,
974 .reg_list = {
975 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
976 .regs = mipi_data_rate_540mbps,
977 }
978 }
979 };
980
981 /* Mode configs */
982 static const struct ov13858_mode supported_modes[] = {
983 {
984 .width = 4224,
985 .height = 3136,
986 .vts_def = OV13858_VTS_30FPS,
987 .vts_min = OV13858_VTS_30FPS,
988 .reg_list = {
989 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
990 .regs = mode_4224x3136_regs,
991 },
992 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
993 },
994 {
995 .width = 2112,
996 .height = 1568,
997 .vts_def = OV13858_VTS_30FPS,
998 .vts_min = 1608,
999 .reg_list = {
1000 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1001 .regs = mode_2112x1568_regs,
1002 },
1003 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1004 },
1005 {
1006 .width = 2112,
1007 .height = 1188,
1008 .vts_def = OV13858_VTS_30FPS,
1009 .vts_min = 1608,
1010 .reg_list = {
1011 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1012 .regs = mode_2112x1188_regs,
1013 },
1014 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1015 },
1016 {
1017 .width = 1056,
1018 .height = 784,
1019 .vts_def = OV13858_VTS_30FPS,
1020 .vts_min = 804,
1021 .reg_list = {
1022 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1023 .regs = mode_1056x784_regs,
1024 },
1025 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1026 }
1027 };
1028
1029 struct ov13858 {
1030 struct v4l2_subdev sd;
1031 struct media_pad pad;
1032
1033 struct v4l2_ctrl_handler ctrl_handler;
1034 /* V4L2 Controls */
1035 struct v4l2_ctrl *link_freq;
1036 struct v4l2_ctrl *pixel_rate;
1037 struct v4l2_ctrl *vblank;
1038 struct v4l2_ctrl *hblank;
1039 struct v4l2_ctrl *exposure;
1040
1041 /* Current mode */
1042 const struct ov13858_mode *cur_mode;
1043
1044 /* Mutex for serialized access */
1045 struct mutex mutex;
1046
1047 /* Streaming on/off */
1048 bool streaming;
1049 };
1050
1051 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1052
1053 /* Read registers up to 4 at a time */
1054 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1055 u32 *val)
1056 {
1057 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1058 struct i2c_msg msgs[2];
1059 u8 *data_be_p;
1060 int ret;
1061 __be32 data_be = 0;
1062 __be16 reg_addr_be = cpu_to_be16(reg);
1063
1064 if (len > 4)
1065 return -EINVAL;
1066
1067 data_be_p = (u8 *)&data_be;
1068 /* Write register address */
1069 msgs[0].addr = client->addr;
1070 msgs[0].flags = 0;
1071 msgs[0].len = 2;
1072 msgs[0].buf = (u8 *)&reg_addr_be;
1073
1074 /* Read data from register */
1075 msgs[1].addr = client->addr;
1076 msgs[1].flags = I2C_M_RD;
1077 msgs[1].len = len;
1078 msgs[1].buf = &data_be_p[4 - len];
1079
1080 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1081 if (ret != ARRAY_SIZE(msgs))
1082 return -EIO;
1083
1084 *val = be32_to_cpu(data_be);
1085
1086 return 0;
1087 }
1088
1089 /* Write registers up to 4 at a time */
1090 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1091 u32 __val)
1092 {
1093 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1094 int buf_i, val_i;
1095 u8 buf[6], *val_p;
1096 __be32 val;
1097
1098 if (len > 4)
1099 return -EINVAL;
1100
1101 buf[0] = reg >> 8;
1102 buf[1] = reg & 0xff;
1103
1104 val = cpu_to_be32(__val);
1105 val_p = (u8 *)&val;
1106 buf_i = 2;
1107 val_i = 4 - len;
1108
1109 while (val_i < 4)
1110 buf[buf_i++] = val_p[val_i++];
1111
1112 if (i2c_master_send(client, buf, len + 2) != len + 2)
1113 return -EIO;
1114
1115 return 0;
1116 }
1117
1118 /* Write a list of registers */
1119 static int ov13858_write_regs(struct ov13858 *ov13858,
1120 const struct ov13858_reg *regs, u32 len)
1121 {
1122 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1123 int ret;
1124 u32 i;
1125
1126 for (i = 0; i < len; i++) {
1127 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1128 regs[i].val);
1129 if (ret) {
1130 dev_err_ratelimited(
1131 &client->dev,
1132 "Failed to write reg 0x%4.4x. error = %d\n",
1133 regs[i].address, ret);
1134
1135 return ret;
1136 }
1137 }
1138
1139 return 0;
1140 }
1141
1142 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1143 const struct ov13858_reg_list *r_list)
1144 {
1145 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1146 }
1147
1148 /* Open sub-device */
1149 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1150 {
1151 struct ov13858 *ov13858 = to_ov13858(sd);
1152 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1153 fh->pad,
1154 0);
1155
1156 mutex_lock(&ov13858->mutex);
1157
1158 /* Initialize try_fmt */
1159 try_fmt->width = ov13858->cur_mode->width;
1160 try_fmt->height = ov13858->cur_mode->height;
1161 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1162 try_fmt->field = V4L2_FIELD_NONE;
1163
1164 /* No crop or compose */
1165 mutex_unlock(&ov13858->mutex);
1166
1167 return 0;
1168 }
1169
1170 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1171 {
1172 int ret;
1173
1174 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1175 OV13858_REG_VALUE_16BIT, d_gain);
1176 if (ret)
1177 return ret;
1178
1179 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1180 OV13858_REG_VALUE_16BIT, d_gain);
1181 if (ret)
1182 return ret;
1183
1184 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1185 OV13858_REG_VALUE_16BIT, d_gain);
1186
1187 return ret;
1188 }
1189
1190 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1191 {
1192 int ret;
1193 u32 val;
1194
1195 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1196 OV13858_REG_VALUE_08BIT, &val);
1197 if (ret)
1198 return ret;
1199
1200 if (pattern) {
1201 val &= OV13858_TEST_PATTERN_MASK;
1202 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1203 } else {
1204 val &= ~OV13858_TEST_PATTERN_ENABLE;
1205 }
1206
1207 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1208 OV13858_REG_VALUE_08BIT, val);
1209 }
1210
1211 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1212 {
1213 struct ov13858 *ov13858 = container_of(ctrl->handler,
1214 struct ov13858, ctrl_handler);
1215 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1216 s64 max;
1217 int ret;
1218
1219 /* Propagate change of current control to all related controls */
1220 switch (ctrl->id) {
1221 case V4L2_CID_VBLANK:
1222 /* Update max exposure while meeting expected vblanking */
1223 max = ov13858->cur_mode->height + ctrl->val - 8;
1224 __v4l2_ctrl_modify_range(ov13858->exposure,
1225 ov13858->exposure->minimum,
1226 max, ov13858->exposure->step, max);
1227 break;
1228 }
1229
1230 /*
1231 * Applying V4L2 control value only happens
1232 * when power is up for streaming
1233 */
1234 if (!pm_runtime_get_if_in_use(&client->dev))
1235 return 0;
1236
1237 ret = 0;
1238 switch (ctrl->id) {
1239 case V4L2_CID_ANALOGUE_GAIN:
1240 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1241 OV13858_REG_VALUE_16BIT, ctrl->val);
1242 break;
1243 case V4L2_CID_DIGITAL_GAIN:
1244 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1245 break;
1246 case V4L2_CID_EXPOSURE:
1247 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1248 OV13858_REG_VALUE_24BIT,
1249 ctrl->val << 4);
1250 break;
1251 case V4L2_CID_VBLANK:
1252 /* Update VTS that meets expected vertical blanking */
1253 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1254 OV13858_REG_VALUE_16BIT,
1255 ov13858->cur_mode->height
1256 + ctrl->val);
1257 break;
1258 case V4L2_CID_TEST_PATTERN:
1259 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1260 break;
1261 default:
1262 dev_info(&client->dev,
1263 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1264 ctrl->id, ctrl->val);
1265 break;
1266 }
1267
1268 pm_runtime_put(&client->dev);
1269
1270 return ret;
1271 }
1272
1273 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1274 .s_ctrl = ov13858_set_ctrl,
1275 };
1276
1277 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1278 struct v4l2_subdev_pad_config *cfg,
1279 struct v4l2_subdev_mbus_code_enum *code)
1280 {
1281 /* Only one bayer order(GRBG) is supported */
1282 if (code->index > 0)
1283 return -EINVAL;
1284
1285 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1286
1287 return 0;
1288 }
1289
1290 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1291 struct v4l2_subdev_pad_config *cfg,
1292 struct v4l2_subdev_frame_size_enum *fse)
1293 {
1294 if (fse->index >= ARRAY_SIZE(supported_modes))
1295 return -EINVAL;
1296
1297 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1298 return -EINVAL;
1299
1300 fse->min_width = supported_modes[fse->index].width;
1301 fse->max_width = fse->min_width;
1302 fse->min_height = supported_modes[fse->index].height;
1303 fse->max_height = fse->min_height;
1304
1305 return 0;
1306 }
1307
1308 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1309 struct v4l2_subdev_format *fmt)
1310 {
1311 fmt->format.width = mode->width;
1312 fmt->format.height = mode->height;
1313 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1314 fmt->format.field = V4L2_FIELD_NONE;
1315 }
1316
1317 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1318 struct v4l2_subdev_pad_config *cfg,
1319 struct v4l2_subdev_format *fmt)
1320 {
1321 struct v4l2_mbus_framefmt *framefmt;
1322 struct v4l2_subdev *sd = &ov13858->sd;
1323
1324 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1325 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1326 fmt->format = *framefmt;
1327 } else {
1328 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1329 }
1330
1331 return 0;
1332 }
1333
1334 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1335 struct v4l2_subdev_pad_config *cfg,
1336 struct v4l2_subdev_format *fmt)
1337 {
1338 struct ov13858 *ov13858 = to_ov13858(sd);
1339 int ret;
1340
1341 mutex_lock(&ov13858->mutex);
1342 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
1343 mutex_unlock(&ov13858->mutex);
1344
1345 return ret;
1346 }
1347
1348 static int
1349 ov13858_set_pad_format(struct v4l2_subdev *sd,
1350 struct v4l2_subdev_pad_config *cfg,
1351 struct v4l2_subdev_format *fmt)
1352 {
1353 struct ov13858 *ov13858 = to_ov13858(sd);
1354 const struct ov13858_mode *mode;
1355 struct v4l2_mbus_framefmt *framefmt;
1356 s32 vblank_def;
1357 s32 vblank_min;
1358 s64 h_blank;
1359 s64 pixel_rate;
1360 s64 link_freq;
1361
1362 mutex_lock(&ov13858->mutex);
1363
1364 /* Only one raw bayer(GRBG) order is supported */
1365 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1366 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1367
1368 mode = v4l2_find_nearest_size(supported_modes,
1369 ARRAY_SIZE(supported_modes),
1370 width, height,
1371 fmt->format.width, fmt->format.height);
1372 ov13858_update_pad_format(mode, fmt);
1373 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1374 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1375 *framefmt = fmt->format;
1376 } else {
1377 ov13858->cur_mode = mode;
1378 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1379 link_freq = link_freq_menu_items[mode->link_freq_index];
1380 pixel_rate = link_freq_to_pixel_rate(link_freq);
1381 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1382
1383 /* Update limits and set FPS to default */
1384 vblank_def = ov13858->cur_mode->vts_def -
1385 ov13858->cur_mode->height;
1386 vblank_min = ov13858->cur_mode->vts_min -
1387 ov13858->cur_mode->height;
1388 __v4l2_ctrl_modify_range(
1389 ov13858->vblank, vblank_min,
1390 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1391 vblank_def);
1392 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1393 h_blank =
1394 link_freq_configs[mode->link_freq_index].pixels_per_line
1395 - ov13858->cur_mode->width;
1396 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1397 h_blank, 1, h_blank);
1398 }
1399
1400 mutex_unlock(&ov13858->mutex);
1401
1402 return 0;
1403 }
1404
1405 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1406 {
1407 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1408
1409 return 0;
1410 }
1411
1412 /* Start streaming */
1413 static int ov13858_start_streaming(struct ov13858 *ov13858)
1414 {
1415 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1416 const struct ov13858_reg_list *reg_list;
1417 int ret, link_freq_index;
1418
1419 /* Get out of from software reset */
1420 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1421 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1422 if (ret) {
1423 dev_err(&client->dev, "%s failed to set powerup registers\n",
1424 __func__);
1425 return ret;
1426 }
1427
1428 /* Setup PLL */
1429 link_freq_index = ov13858->cur_mode->link_freq_index;
1430 reg_list = &link_freq_configs[link_freq_index].reg_list;
1431 ret = ov13858_write_reg_list(ov13858, reg_list);
1432 if (ret) {
1433 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1434 return ret;
1435 }
1436
1437 /* Apply default values of current mode */
1438 reg_list = &ov13858->cur_mode->reg_list;
1439 ret = ov13858_write_reg_list(ov13858, reg_list);
1440 if (ret) {
1441 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1442 return ret;
1443 }
1444
1445 /* Apply customized values from user */
1446 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1447 if (ret)
1448 return ret;
1449
1450 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1451 OV13858_REG_VALUE_08BIT,
1452 OV13858_MODE_STREAMING);
1453 }
1454
1455 /* Stop streaming */
1456 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1457 {
1458 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1459 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1460 }
1461
1462 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1463 {
1464 struct ov13858 *ov13858 = to_ov13858(sd);
1465 struct i2c_client *client = v4l2_get_subdevdata(sd);
1466 int ret = 0;
1467
1468 mutex_lock(&ov13858->mutex);
1469 if (ov13858->streaming == enable) {
1470 mutex_unlock(&ov13858->mutex);
1471 return 0;
1472 }
1473
1474 if (enable) {
1475 ret = pm_runtime_get_sync(&client->dev);
1476 if (ret < 0) {
1477 pm_runtime_put_noidle(&client->dev);
1478 goto err_unlock;
1479 }
1480
1481 /*
1482 * Apply default & customized values
1483 * and then start streaming.
1484 */
1485 ret = ov13858_start_streaming(ov13858);
1486 if (ret)
1487 goto err_rpm_put;
1488 } else {
1489 ov13858_stop_streaming(ov13858);
1490 pm_runtime_put(&client->dev);
1491 }
1492
1493 ov13858->streaming = enable;
1494 mutex_unlock(&ov13858->mutex);
1495
1496 return ret;
1497
1498 err_rpm_put:
1499 pm_runtime_put(&client->dev);
1500 err_unlock:
1501 mutex_unlock(&ov13858->mutex);
1502
1503 return ret;
1504 }
1505
1506 static int __maybe_unused ov13858_suspend(struct device *dev)
1507 {
1508 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1509 struct ov13858 *ov13858 = to_ov13858(sd);
1510
1511 if (ov13858->streaming)
1512 ov13858_stop_streaming(ov13858);
1513
1514 return 0;
1515 }
1516
1517 static int __maybe_unused ov13858_resume(struct device *dev)
1518 {
1519 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1520 struct ov13858 *ov13858 = to_ov13858(sd);
1521 int ret;
1522
1523 if (ov13858->streaming) {
1524 ret = ov13858_start_streaming(ov13858);
1525 if (ret)
1526 goto error;
1527 }
1528
1529 return 0;
1530
1531 error:
1532 ov13858_stop_streaming(ov13858);
1533 ov13858->streaming = false;
1534 return ret;
1535 }
1536
1537 /* Verify chip ID */
1538 static int ov13858_identify_module(struct ov13858 *ov13858)
1539 {
1540 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1541 int ret;
1542 u32 val;
1543
1544 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1545 OV13858_REG_VALUE_24BIT, &val);
1546 if (ret)
1547 return ret;
1548
1549 if (val != OV13858_CHIP_ID) {
1550 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1551 OV13858_CHIP_ID, val);
1552 return -EIO;
1553 }
1554
1555 return 0;
1556 }
1557
1558 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1559 .s_stream = ov13858_set_stream,
1560 };
1561
1562 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1563 .enum_mbus_code = ov13858_enum_mbus_code,
1564 .get_fmt = ov13858_get_pad_format,
1565 .set_fmt = ov13858_set_pad_format,
1566 .enum_frame_size = ov13858_enum_frame_size,
1567 };
1568
1569 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1570 .g_skip_frames = ov13858_get_skip_frames,
1571 };
1572
1573 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1574 .video = &ov13858_video_ops,
1575 .pad = &ov13858_pad_ops,
1576 .sensor = &ov13858_sensor_ops,
1577 };
1578
1579 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1580 .link_validate = v4l2_subdev_link_validate,
1581 };
1582
1583 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1584 .open = ov13858_open,
1585 };
1586
1587 /* Initialize control handlers */
1588 static int ov13858_init_controls(struct ov13858 *ov13858)
1589 {
1590 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1591 struct v4l2_fwnode_device_properties props;
1592 struct v4l2_ctrl_handler *ctrl_hdlr;
1593 s64 exposure_max;
1594 s64 vblank_def;
1595 s64 vblank_min;
1596 s64 hblank;
1597 s64 pixel_rate_min;
1598 s64 pixel_rate_max;
1599 const struct ov13858_mode *mode;
1600 int ret;
1601
1602 ctrl_hdlr = &ov13858->ctrl_handler;
1603 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1604 if (ret)
1605 return ret;
1606
1607 mutex_init(&ov13858->mutex);
1608 ctrl_hdlr->lock = &ov13858->mutex;
1609 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1610 &ov13858_ctrl_ops,
1611 V4L2_CID_LINK_FREQ,
1612 OV13858_NUM_OF_LINK_FREQS - 1,
1613 0,
1614 link_freq_menu_items);
1615 if (ov13858->link_freq)
1616 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1617
1618 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1619 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1620 /* By default, PIXEL_RATE is read only */
1621 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1622 V4L2_CID_PIXEL_RATE,
1623 pixel_rate_min, pixel_rate_max,
1624 1, pixel_rate_max);
1625
1626 mode = ov13858->cur_mode;
1627 vblank_def = mode->vts_def - mode->height;
1628 vblank_min = mode->vts_min - mode->height;
1629 ov13858->vblank = v4l2_ctrl_new_std(
1630 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1631 vblank_min, OV13858_VTS_MAX - mode->height, 1,
1632 vblank_def);
1633
1634 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1635 mode->width;
1636 ov13858->hblank = v4l2_ctrl_new_std(
1637 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1638 hblank, hblank, 1, hblank);
1639 if (ov13858->hblank)
1640 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1641
1642 exposure_max = mode->vts_def - 8;
1643 ov13858->exposure = v4l2_ctrl_new_std(
1644 ctrl_hdlr, &ov13858_ctrl_ops,
1645 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1646 exposure_max, OV13858_EXPOSURE_STEP,
1647 OV13858_EXPOSURE_DEFAULT);
1648
1649 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1650 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1651 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1652
1653 /* Digital gain */
1654 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1655 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1656 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1657
1658 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1659 V4L2_CID_TEST_PATTERN,
1660 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1661 0, 0, ov13858_test_pattern_menu);
1662 if (ctrl_hdlr->error) {
1663 ret = ctrl_hdlr->error;
1664 dev_err(&client->dev, "%s control init failed (%d)\n",
1665 __func__, ret);
1666 goto error;
1667 }
1668
1669 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1670 if (ret)
1671 goto error;
1672
1673 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13858_ctrl_ops,
1674 &props);
1675 if (ret)
1676 goto error;
1677
1678 ov13858->sd.ctrl_handler = ctrl_hdlr;
1679
1680 return 0;
1681
1682 error:
1683 v4l2_ctrl_handler_free(ctrl_hdlr);
1684 mutex_destroy(&ov13858->mutex);
1685
1686 return ret;
1687 }
1688
1689 static void ov13858_free_controls(struct ov13858 *ov13858)
1690 {
1691 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1692 mutex_destroy(&ov13858->mutex);
1693 }
1694
1695 static int ov13858_probe(struct i2c_client *client,
1696 const struct i2c_device_id *devid)
1697 {
1698 struct ov13858 *ov13858;
1699 int ret;
1700 u32 val = 0;
1701
1702 device_property_read_u32(&client->dev, "clock-frequency", &val);
1703 if (val != 19200000)
1704 return -EINVAL;
1705
1706 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1707 if (!ov13858)
1708 return -ENOMEM;
1709
1710 /* Initialize subdev */
1711 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1712
1713 /* Check module identity */
1714 ret = ov13858_identify_module(ov13858);
1715 if (ret) {
1716 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1717 return ret;
1718 }
1719
1720 /* Set default mode to max resolution */
1721 ov13858->cur_mode = &supported_modes[0];
1722
1723 ret = ov13858_init_controls(ov13858);
1724 if (ret)
1725 return ret;
1726
1727 /* Initialize subdev */
1728 ov13858->sd.internal_ops = &ov13858_internal_ops;
1729 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1730 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1731 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1732
1733 /* Initialize source pad */
1734 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1735 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1736 if (ret) {
1737 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1738 goto error_handler_free;
1739 }
1740
1741 ret = v4l2_async_register_subdev_sensor_common(&ov13858->sd);
1742 if (ret < 0)
1743 goto error_media_entity;
1744
1745 /*
1746 * Device is already turned on by i2c-core with ACPI domain PM.
1747 * Enable runtime PM and turn off the device.
1748 */
1749 pm_runtime_set_active(&client->dev);
1750 pm_runtime_enable(&client->dev);
1751 pm_runtime_idle(&client->dev);
1752
1753 return 0;
1754
1755 error_media_entity:
1756 media_entity_cleanup(&ov13858->sd.entity);
1757
1758 error_handler_free:
1759 ov13858_free_controls(ov13858);
1760 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1761
1762 return ret;
1763 }
1764
1765 static int ov13858_remove(struct i2c_client *client)
1766 {
1767 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1768 struct ov13858 *ov13858 = to_ov13858(sd);
1769
1770 v4l2_async_unregister_subdev(sd);
1771 media_entity_cleanup(&sd->entity);
1772 ov13858_free_controls(ov13858);
1773
1774 pm_runtime_disable(&client->dev);
1775
1776 return 0;
1777 }
1778
1779 static const struct i2c_device_id ov13858_id_table[] = {
1780 {"ov13858", 0},
1781 {},
1782 };
1783
1784 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1785
1786 static const struct dev_pm_ops ov13858_pm_ops = {
1787 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1788 };
1789
1790 #ifdef CONFIG_ACPI
1791 static const struct acpi_device_id ov13858_acpi_ids[] = {
1792 {"OVTID858"},
1793 { /* sentinel */ }
1794 };
1795
1796 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1797 #endif
1798
1799 static struct i2c_driver ov13858_i2c_driver = {
1800 .driver = {
1801 .name = "ov13858",
1802 .pm = &ov13858_pm_ops,
1803 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1804 },
1805 .probe = ov13858_probe,
1806 .remove = ov13858_remove,
1807 .id_table = ov13858_id_table,
1808 };
1809
1810 module_i2c_driver(ov13858_i2c_driver);
1811
1812 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1813 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1814 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
1815 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1816 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support