1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * cx18 ADEC audio functions
5 * Derived from cx25840-core.c
7 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
8 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
11 #include "cx18-driver.h"
13 #include "cx18-cards.h"
15 int cx18_av_write(struct cx18
*cx
, u16 addr
, u8 value
)
17 u32 reg
= 0xc40000 + (addr
& ~3);
19 int shift
= (addr
& 3) * 8;
20 u32 x
= cx18_read_reg(cx
, reg
);
22 x
= (x
& ~(mask
<< shift
)) | ((u32
)value
<< shift
);
23 cx18_write_reg(cx
, x
, reg
);
27 int cx18_av_write_expect(struct cx18
*cx
, u16 addr
, u8 value
, u8 eval
, u8 mask
)
29 u32 reg
= 0xc40000 + (addr
& ~3);
30 int shift
= (addr
& 3) * 8;
31 u32 x
= cx18_read_reg(cx
, reg
);
33 x
= (x
& ~((u32
)0xff << shift
)) | ((u32
)value
<< shift
);
34 cx18_write_reg_expect(cx
, x
, reg
,
35 ((u32
)eval
<< shift
), ((u32
)mask
<< shift
));
39 int cx18_av_write4(struct cx18
*cx
, u16 addr
, u32 value
)
41 cx18_write_reg(cx
, value
, 0xc40000 + addr
);
46 cx18_av_write4_expect(struct cx18
*cx
, u16 addr
, u32 value
, u32 eval
, u32 mask
)
48 cx18_write_reg_expect(cx
, value
, 0xc40000 + addr
, eval
, mask
);
52 int cx18_av_write4_noretry(struct cx18
*cx
, u16 addr
, u32 value
)
54 cx18_write_reg_noretry(cx
, value
, 0xc40000 + addr
);
58 u8
cx18_av_read(struct cx18
*cx
, u16 addr
)
60 u32 x
= cx18_read_reg(cx
, 0xc40000 + (addr
& ~3));
61 int shift
= (addr
& 3) * 8;
63 return (x
>> shift
) & 0xff;
66 u32
cx18_av_read4(struct cx18
*cx
, u16 addr
)
68 return cx18_read_reg(cx
, 0xc40000 + addr
);
71 int cx18_av_and_or(struct cx18
*cx
, u16 addr
, unsigned and_mask
,
74 return cx18_av_write(cx
, addr
,
75 (cx18_av_read(cx
, addr
) & and_mask
) |
79 int cx18_av_and_or4(struct cx18
*cx
, u16 addr
, u32 and_mask
,
82 return cx18_av_write4(cx
, addr
,
83 (cx18_av_read4(cx
, addr
) & and_mask
) |
87 static void cx18_av_init(struct cx18
*cx
)
90 * The crystal freq used in calculations in this driver will be
92 * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
96 * VDCLK Integer = 0x0f, Post Divider = 0x04
97 * AIMCLK Integer = 0x0e, Post Divider = 0x16
99 cx18_av_write4(cx
, CXADEC_PLL_CTRL1
, 0x160e040f);
101 /* VDCLK Fraction = 0x2be2fe */
102 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
103 cx18_av_write4(cx
, CXADEC_VID_PLL_FRAC
, 0x002be2fe);
105 /* AIMCLK Fraction = 0x05227ad */
106 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
107 cx18_av_write4(cx
, CXADEC_AUX_PLL_FRAC
, 0x005227ad);
109 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
110 cx18_av_write(cx
, CXADEC_I2S_MCLK
, 0x56);
113 static void cx18_av_initialize(struct v4l2_subdev
*sd
)
115 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
116 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
121 /* Stop 8051 code execution */
122 cx18_av_write4_expect(cx
, CXADEC_DL_CTL
, 0x03000000,
123 0x03000000, 0x13000000);
125 /* initallize the PLL by toggling sleep bit */
126 v
= cx18_av_read4(cx
, CXADEC_HOST_REG1
);
127 /* enable sleep mode - register appears to be read only... */
128 cx18_av_write4_expect(cx
, CXADEC_HOST_REG1
, v
| 1, v
, 0xfffe);
129 /* disable sleep mode */
130 cx18_av_write4_expect(cx
, CXADEC_HOST_REG1
, v
& 0xfffe,
133 /* initialize DLLs */
134 v
= cx18_av_read4(cx
, CXADEC_DLL1_DIAG_CTRL
) & 0xE1FFFEFF;
136 cx18_av_write4(cx
, CXADEC_DLL1_DIAG_CTRL
, v
);
138 cx18_av_write4(cx
, CXADEC_DLL1_DIAG_CTRL
, v
| 0x10000100);
140 v
= cx18_av_read4(cx
, CXADEC_DLL2_DIAG_CTRL
) & 0xE1FFFEFF;
142 cx18_av_write4(cx
, CXADEC_DLL2_DIAG_CTRL
, v
);
144 cx18_av_write4(cx
, CXADEC_DLL2_DIAG_CTRL
, v
| 0x06000100);
146 /* set analog bias currents. Set Vreg to 1.20V. */
147 cx18_av_write4(cx
, CXADEC_AFE_DIAG_CTRL1
, 0x000A1802);
149 v
= cx18_av_read4(cx
, CXADEC_AFE_DIAG_CTRL3
) | 1;
150 /* enable TUNE_FIL_RST */
151 cx18_av_write4_expect(cx
, CXADEC_AFE_DIAG_CTRL3
, v
, v
, 0x03009F0F);
152 /* disable TUNE_FIL_RST */
153 cx18_av_write4_expect(cx
, CXADEC_AFE_DIAG_CTRL3
,
154 v
& 0xFFFFFFFE, v
& 0xFFFFFFFE, 0x03009F0F);
156 /* enable 656 output */
157 cx18_av_and_or4(cx
, CXADEC_PIN_CTRL1
, ~0, 0x040C00);
159 /* video output drive strength */
160 cx18_av_and_or4(cx
, CXADEC_PIN_CTRL2
, ~0, 0x2);
163 cx18_av_write4(cx
, CXADEC_SOFT_RST_CTRL
, 0x8000);
164 cx18_av_write4(cx
, CXADEC_SOFT_RST_CTRL
, 0);
167 * Disable Video Auto-config of the Analog Front End and Video PLL.
169 * Since we only use BT.656 pixel mode, which works for both 525 and 625
170 * line systems, it's just easier for us to set registers
171 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
172 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
173 * ourselves, than to run around cleaning up after the auto-config.
175 * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
176 * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
177 * autoconfig either.)
179 * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
181 cx18_av_and_or4(cx
, CXADEC_CHIP_CTRL
, 0xFFFBFFFF, 0x00120000);
183 /* Setup the Video and and Aux/Audio PLLs */
186 /* set video to auto-detect */
187 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
188 /* set the comb notch = 1 */
189 cx18_av_and_or4(cx
, CXADEC_MODE_CTRL
, 0xFFF7E7F0, 0x02040800);
191 /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
192 /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
193 cx18_av_and_or4(cx
, CXADEC_CRUSH_CTRL
, ~0, 0x00500000);
195 /* Set VGA_TRACK_RANGE to 0x20 */
196 cx18_av_and_or4(cx
, CXADEC_DFE_CTRL2
, 0xFFFF00FF, 0x00002000);
200 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
201 * don't clamp raw samples when codes are in use, 1 byte user D-words,
202 * IDID0 has line #, RP code V bit transition on VBLANK, data during
205 cx18_av_write4(cx
, CXADEC_OUT_CTRL1
, 0x4013252e);
207 /* Set the video input.
208 The setting in MODE_CTRL gets lost when we do the above setup */
209 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
210 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
213 * Analog Front End (AFE)
214 * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
215 * bypass_ch[1-3] use filter
216 * droop_comp_ch[1-3] disable
217 * clamp_en_ch[1-3] disable
221 * clamp_sel_ch[2-3] midcode
222 * clamp_sel_ch1 video decoder
223 * vga_sel_ch3 audio decoder
224 * vga_sel_ch[1-2] video decoder
225 * half_bw_ch[1-3] disable
226 * +12db_ch[1-3] disable
228 cx18_av_and_or4(cx
, CXADEC_AFE_CTRL
, 0xFF000000, 0x00005D00);
230 /* if(dwEnable && dw3DCombAvailable) { */
231 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
233 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
235 cx18_av_write4(cx
, CXADEC_SRC_COMB_CFG
, 0x6628021F);
236 default_volume
= cx18_av_read(cx
, 0x8d4);
238 * Enforce the legacy volume scale mapping limits to avoid
239 * -ERANGE errors when initializing the volume control
241 if (default_volume
> 228) {
242 /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
243 default_volume
= 228;
244 cx18_av_write(cx
, 0x8d4, 228);
245 } else if (default_volume
< 20) {
246 /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
248 cx18_av_write(cx
, 0x8d4, 20);
250 default_volume
= (((228 - default_volume
) >> 1) + 23) << 9;
251 state
->volume
->cur
.val
= state
->volume
->default_value
= default_volume
;
252 v4l2_ctrl_handler_setup(&state
->hdl
);
255 static int cx18_av_reset(struct v4l2_subdev
*sd
, u32 val
)
257 cx18_av_initialize(sd
);
261 static int cx18_av_load_fw(struct v4l2_subdev
*sd
)
263 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
265 if (!state
->is_initialized
) {
266 /* initialize on first use */
267 state
->is_initialized
= 1;
268 cx18_av_initialize(sd
);
273 void cx18_av_std_setup(struct cx18
*cx
)
275 struct cx18_av_state
*state
= &cx
->av_state
;
276 struct v4l2_subdev
*sd
= &state
->sd
;
277 v4l2_std_id std
= state
->std
;
280 * Video ADC crystal clock to pixel clock SRC decimation ratio
281 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
283 const int src_decimation
= 0x21f;
285 int hblank
, hactive
, burst
, vblank
, vactive
, sc
;
287 int luma_lpf
, uv_lpf
, comb
;
288 u32 pll_int
, pll_frac
, pll_post
;
290 /* datasheet startup, step 8d */
291 if (std
& ~V4L2_STD_NTSC
)
292 cx18_av_write(cx
, 0x49f, 0x11);
294 cx18_av_write(cx
, 0x49f, 0x14);
297 * Note: At the end of a field, there are 3 sets of half line duration
298 * (double horizontal rate) pulses:
300 * 5 (625) or 6 (525) half-lines to blank for the vertical retrace
301 * 5 (625) or 6 (525) vertical sync pulses of half line duration
302 * 5 (625) or 6 (525) half-lines of equalization pulses
304 if (std
& V4L2_STD_625_50
) {
306 * The following relationships of half line counts should hold:
307 * 625 = vblank656 + vactive
308 * 10 = vblank656 - vblank = vsync pulses + equalization pulses
310 * vblank656: half lines after line 625/mid-313 of blanked video
311 * vblank: half lines, after line 5/317, of blanked video
312 * vactive: half lines of active video +
313 * 5 half lines after the end of active video
315 * As far as I can tell:
316 * vblank656 starts counting from the falling edge of the first
317 * vsync pulse (start of line 1 or mid-313)
318 * vblank starts counting from the after the 5 vsync pulses and
319 * 5 or 4 equalization pulses (start of line 6 or 318)
321 * For 625 line systems the driver will extract VBI information
322 * from lines 6-23 and lines 318-335 (but the slicer can only
323 * handle 17 lines, not the 18 in the vblank region).
324 * In addition, we need vblank656 and vblank to be one whole
325 * line longer, to cover line 24 and 336, so the SAV/EAV RP
326 * codes get generated such that the encoder can actually
327 * extract line 23 & 335 (WSS). We'll lose 1 line in each field
328 * at the top of the screen.
330 * It appears the 5 half lines that happen after active
331 * video must be included in vactive (579 instead of 574),
332 * otherwise the colors get badly displayed in various regions
333 * of the screen. I guess the chroma comb filter gets confused
334 * without them (at least when a PVR-350 is the PAL source).
336 vblank656
= 48; /* lines 1 - 24 & 313 - 336 */
337 vblank
= 38; /* lines 6 - 24 & 318 - 336 */
338 vactive
= 579; /* lines 24 - 313 & 337 - 626 */
341 * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is
342 * is 864 pixels = 720 active + 144 blanking. ITU-R BT.601
343 * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after
344 * the end of active video to start a horizontal line, so that
345 * leaves 132 pixels of hblank to ignore.
351 * Burst gate delay (for 625 line systems)
352 * Hsync leading edge to color burst rise = 5.6 us
353 * Color burst width = 2.25 us
354 * Gate width = 4 pixel clocks
355 * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
359 if (std
& V4L2_STD_PAL
) {
362 /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
364 } else if (std
== V4L2_STD_PAL_Nc
) {
367 /* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
372 /* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
373 /* sc = 4328130 * src_decimation/28636360 * 2^13 */
378 * The following relationships of half line counts should hold:
379 * 525 = prevsync + vblank656 + vactive
380 * 12 = vblank656 - vblank = vsync pulses + equalization pulses
382 * prevsync: 6 half-lines before the vsync pulses
383 * vblank656: half lines, after line 3/mid-266, of blanked video
384 * vblank: half lines, after line 9/272, of blanked video
385 * vactive: half lines of active video
387 * As far as I can tell:
388 * vblank656 starts counting from the falling edge of the first
389 * vsync pulse (start of line 4 or mid-266)
390 * vblank starts counting from the after the 6 vsync pulses and
391 * 6 or 5 equalization pulses (start of line 10 or 272)
393 * For 525 line systems the driver will extract VBI information
394 * from lines 10-21 and lines 273-284.
396 vblank656
= 38; /* lines 4 - 22 & 266 - 284 */
397 vblank
= 26; /* lines 10 - 22 & 272 - 284 */
398 vactive
= 481; /* lines 23 - 263 & 285 - 525 */
401 * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is
402 * is 858 pixels = 720 active + 138 blanking. The Hsync leading
403 * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the
404 * end of active video, leaving 122 pixels of hblank to ignore
405 * before active video starts.
413 * Burst gate delay (for 525 line systems)
414 * Hsync leading edge to color burst rise = 5.3 us
415 * Color burst width = 2.5 us
416 * Gate width = 4 pixel clocks
417 * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
419 if (std
== V4L2_STD_PAL_60
) {
423 /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
425 } else if (std
== V4L2_STD_PAL_M
) {
426 /* The 97 needs to be verified against PAL-M timings */
429 /* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
434 /* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
439 /* DEBUG: Displays configured PLL frequency */
440 pll_int
= cx18_av_read(cx
, 0x108);
441 pll_frac
= cx18_av_read4(cx
, 0x10c) & 0x1ffffff;
442 pll_post
= cx18_av_read(cx
, 0x109);
443 CX18_DEBUG_INFO_DEV(sd
, "PLL regs = int: %u, frac: %u, post: %u\n",
444 pll_int
, pll_frac
, pll_post
);
450 pll
= (28636360L * ((((u64
)pll_int
) << 25) + pll_frac
)) >> 25;
452 CX18_DEBUG_INFO_DEV(sd
, "Video PLL = %d.%06d MHz\n",
453 pll
/ 1000000, pll
% 1000000);
454 CX18_DEBUG_INFO_DEV(sd
, "Pixel rate = %d.%06d Mpixel/sec\n",
455 pll
/ 8000000, (pll
/ 8) % 1000000);
457 CX18_DEBUG_INFO_DEV(sd
, "ADC XTAL/pixel clock decimation ratio = %d.%03d\n",
458 src_decimation
/ 256,
459 ((src_decimation
% 256) * 1000) / 256);
461 tmp
= 28636360 * (u64
) sc
;
462 do_div(tmp
, src_decimation
);
464 CX18_DEBUG_INFO_DEV(sd
,
465 "Chroma sub-carrier initial freq = %d.%06d MHz\n",
466 fsc
/ 1000000, fsc
% 1000000);
468 CX18_DEBUG_INFO_DEV(sd
,
469 "hblank %i, hactive %i, vblank %i, vactive %i, vblank656 %i, src_dec %i, burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, sc 0x%06x\n",
470 hblank
, hactive
, vblank
, vactive
, vblank656
,
471 src_decimation
, burst
, luma_lpf
, uv_lpf
,
475 /* Sets horizontal blanking delay and active lines */
476 cx18_av_write(cx
, 0x470, hblank
);
477 cx18_av_write(cx
, 0x471,
478 (((hblank
>> 8) & 0x3) | (hactive
<< 4)) & 0xff);
479 cx18_av_write(cx
, 0x472, hactive
>> 4);
481 /* Sets burst gate delay */
482 cx18_av_write(cx
, 0x473, burst
);
484 /* Sets vertical blanking delay and active duration */
485 cx18_av_write(cx
, 0x474, vblank
);
486 cx18_av_write(cx
, 0x475,
487 (((vblank
>> 8) & 0x3) | (vactive
<< 4)) & 0xff);
488 cx18_av_write(cx
, 0x476, vactive
>> 4);
489 cx18_av_write(cx
, 0x477, vblank656
);
491 /* Sets src decimation rate */
492 cx18_av_write(cx
, 0x478, src_decimation
& 0xff);
493 cx18_av_write(cx
, 0x479, (src_decimation
>> 8) & 0xff);
495 /* Sets Luma and UV Low pass filters */
496 cx18_av_write(cx
, 0x47a, luma_lpf
<< 6 | ((uv_lpf
<< 4) & 0x30));
498 /* Enables comb filters */
499 cx18_av_write(cx
, 0x47b, comb
);
502 cx18_av_write(cx
, 0x47c, sc
);
503 cx18_av_write(cx
, 0x47d, (sc
>> 8) & 0xff);
504 cx18_av_write(cx
, 0x47e, (sc
>> 16) & 0xff);
506 if (std
& V4L2_STD_625_50
) {
507 state
->slicer_line_delay
= 1;
508 state
->slicer_line_offset
= (6 + state
->slicer_line_delay
- 2);
510 state
->slicer_line_delay
= 0;
511 state
->slicer_line_offset
= (10 + state
->slicer_line_delay
- 2);
513 cx18_av_write(cx
, 0x47f, state
->slicer_line_delay
);
516 static void input_change(struct cx18
*cx
)
518 struct cx18_av_state
*state
= &cx
->av_state
;
519 v4l2_std_id std
= state
->std
;
522 /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
523 cx18_av_write(cx
, 0x49f, (std
& V4L2_STD_NTSC
) ? 0x14 : 0x11);
524 cx18_av_and_or(cx
, 0x401, ~0x60, 0);
525 cx18_av_and_or(cx
, 0x401, ~0x60, 0x60);
527 if (std
& V4L2_STD_525_60
) {
528 if (std
== V4L2_STD_NTSC_M_JP
) {
529 /* Japan uses EIAJ audio standard */
530 cx18_av_write_expect(cx
, 0x808, 0xf7, 0xf7, 0xff);
531 cx18_av_write_expect(cx
, 0x80b, 0x02, 0x02, 0x3f);
532 } else if (std
== V4L2_STD_NTSC_M_KR
) {
533 /* South Korea uses A2 audio standard */
534 cx18_av_write_expect(cx
, 0x808, 0xf8, 0xf8, 0xff);
535 cx18_av_write_expect(cx
, 0x80b, 0x03, 0x03, 0x3f);
537 /* Others use the BTSC audio standard */
538 cx18_av_write_expect(cx
, 0x808, 0xf6, 0xf6, 0xff);
539 cx18_av_write_expect(cx
, 0x80b, 0x01, 0x01, 0x3f);
541 } else if (std
& V4L2_STD_PAL
) {
542 /* Follow tuner change procedure for PAL */
543 cx18_av_write_expect(cx
, 0x808, 0xff, 0xff, 0xff);
544 cx18_av_write_expect(cx
, 0x80b, 0x03, 0x03, 0x3f);
545 } else if (std
& V4L2_STD_SECAM
) {
546 /* Select autodetect for SECAM */
547 cx18_av_write_expect(cx
, 0x808, 0xff, 0xff, 0xff);
548 cx18_av_write_expect(cx
, 0x80b, 0x03, 0x03, 0x3f);
551 v
= cx18_av_read(cx
, 0x803);
553 /* restart audio decoder microcontroller */
555 cx18_av_write_expect(cx
, 0x803, v
, v
, 0x1f);
557 cx18_av_write_expect(cx
, 0x803, v
, v
, 0x1f);
561 static int cx18_av_s_frequency(struct v4l2_subdev
*sd
,
562 const struct v4l2_frequency
*freq
)
564 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
569 static int set_input(struct cx18
*cx
, enum cx18_av_video_input vid_input
,
570 enum cx18_av_audio_input aud_input
)
572 struct cx18_av_state
*state
= &cx
->av_state
;
573 struct v4l2_subdev
*sd
= &state
->sd
;
575 enum analog_signal_type
{
576 NONE
, CVBS
, Y
, C
, SIF
, Pb
, Pr
577 } ch
[3] = {NONE
, NONE
, NONE
};
585 CX18_DEBUG_INFO_DEV(sd
, "decoder set video input %d, audio input %d\n",
586 vid_input
, aud_input
);
588 if (vid_input
>= CX18_AV_COMPOSITE1
&&
589 vid_input
<= CX18_AV_COMPOSITE8
) {
590 afe_mux_cfg
= 0xf0 + (vid_input
- CX18_AV_COMPOSITE1
);
593 } else if (vid_input
>= CX18_AV_COMPONENT_LUMA1
) {
594 int luma
= vid_input
& 0xf000;
595 int r_chroma
= vid_input
& 0xf0000;
596 int b_chroma
= vid_input
& 0xf00000;
598 if ((vid_input
& ~0xfff000) ||
599 luma
< CX18_AV_COMPONENT_LUMA1
||
600 luma
> CX18_AV_COMPONENT_LUMA8
||
601 r_chroma
< CX18_AV_COMPONENT_R_CHROMA4
||
602 r_chroma
> CX18_AV_COMPONENT_R_CHROMA6
||
603 b_chroma
< CX18_AV_COMPONENT_B_CHROMA7
||
604 b_chroma
> CX18_AV_COMPONENT_B_CHROMA8
) {
605 CX18_ERR_DEV(sd
, "0x%06x is not a valid video input!\n",
609 afe_mux_cfg
= (luma
- CX18_AV_COMPONENT_LUMA1
) >> 12;
611 afe_mux_cfg
|= (r_chroma
- CX18_AV_COMPONENT_R_CHROMA4
) >> 12;
613 afe_mux_cfg
|= (b_chroma
- CX18_AV_COMPONENT_B_CHROMA7
) >> 14;
617 int luma
= vid_input
& 0xf0;
618 int chroma
= vid_input
& 0xf00;
620 if ((vid_input
& ~0xff0) ||
621 luma
< CX18_AV_SVIDEO_LUMA1
||
622 luma
> CX18_AV_SVIDEO_LUMA8
||
623 chroma
< CX18_AV_SVIDEO_CHROMA4
||
624 chroma
> CX18_AV_SVIDEO_CHROMA8
) {
625 CX18_ERR_DEV(sd
, "0x%06x is not a valid video input!\n",
629 afe_mux_cfg
= 0xf0 + ((luma
- CX18_AV_SVIDEO_LUMA1
) >> 4);
631 if (chroma
>= CX18_AV_SVIDEO_CHROMA7
) {
633 afe_mux_cfg
|= (chroma
- CX18_AV_SVIDEO_CHROMA7
) >> 2;
637 afe_mux_cfg
|= (chroma
- CX18_AV_SVIDEO_CHROMA4
) >> 4;
644 case CX18_AV_AUDIO_SERIAL1
:
645 case CX18_AV_AUDIO_SERIAL2
:
646 /* do nothing, use serial audio input */
649 afe_mux_cfg
&= ~0x30;
653 afe_mux_cfg
= (afe_mux_cfg
& ~0x30) | 0x10;
657 afe_mux_cfg
= (afe_mux_cfg
& ~0x30) | 0x20;
661 afe_mux_cfg
&= ~0xc0;
665 afe_mux_cfg
= (afe_mux_cfg
& ~0xc0) | 0x40;
670 CX18_ERR_DEV(sd
, "0x%04x is not a valid audio input!\n",
675 /* Set up analog front end multiplexers */
676 cx18_av_write_expect(cx
, 0x103, afe_mux_cfg
, afe_mux_cfg
, 0xf7);
677 /* Set INPUT_MODE to Composite, S-Video, or Component */
678 cx18_av_and_or(cx
, 0x401, ~0x6, input_mode
);
680 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
681 adc2_cfg
= cx18_av_read(cx
, 0x102);
683 adc2_cfg
&= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
685 adc2_cfg
|= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */
687 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
688 if (ch
[1] != NONE
&& ch
[2] != NONE
)
689 adc2_cfg
|= 0x4; /* Set dual mode */
691 adc2_cfg
&= ~0x4; /* Clear dual mode */
692 cx18_av_write_expect(cx
, 0x102, adc2_cfg
, adc2_cfg
, 0x17);
694 /* Configure the analog front end */
695 afe_cfg
= cx18_av_read4(cx
, CXADEC_AFE_CTRL
);
696 afe_cfg
&= 0xff000000;
697 afe_cfg
|= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
698 if (ch
[1] != NONE
&& ch
[2] != NONE
)
699 afe_cfg
|= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
701 for (i
= 0; i
< 3; i
++) {
705 /* CLAMP_SEL = Fixed to midcode clamp level */
706 afe_cfg
|= (0x00000200 << i
);
711 afe_cfg
|= 0x00002000; /* LUMA_IN_SEL: ADC2 */
716 /* CLAMP_SEL = Fixed to midcode clamp level */
717 afe_cfg
|= (0x00000200 << i
);
718 if (i
== 0 && ch
[i
] == C
)
719 afe_cfg
&= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
723 * VGA_GAIN_SEL = Audio Decoder
724 * CLAMP_SEL = Fixed to midcode clamp level
726 afe_cfg
|= (0x00000240 << i
);
728 afe_cfg
&= ~0x00004000; /* AUD_IN_SEL ADC1 */
733 cx18_av_write4(cx
, CXADEC_AFE_CTRL
, afe_cfg
);
735 state
->vid_input
= vid_input
;
736 state
->aud_input
= aud_input
;
737 cx18_av_audio_set_path(cx
);
742 static int cx18_av_s_video_routing(struct v4l2_subdev
*sd
,
743 u32 input
, u32 output
, u32 config
)
745 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
746 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
747 return set_input(cx
, input
, state
->aud_input
);
750 static int cx18_av_s_audio_routing(struct v4l2_subdev
*sd
,
751 u32 input
, u32 output
, u32 config
)
753 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
754 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
755 return set_input(cx
, state
->vid_input
, input
);
758 static int cx18_av_g_tuner(struct v4l2_subdev
*sd
, struct v4l2_tuner
*vt
)
760 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
761 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
769 vpres
= cx18_av_read(cx
, 0x40e) & 0x20;
770 vt
->signal
= vpres
? 0xffff : 0x0;
773 V4L2_TUNER_CAP_STEREO
| V4L2_TUNER_CAP_LANG1
|
774 V4L2_TUNER_CAP_LANG2
| V4L2_TUNER_CAP_SAP
;
776 mode
= cx18_av_read(cx
, 0x804);
778 /* get rxsubchans and audmode */
779 if ((mode
& 0xf) == 1)
780 val
|= V4L2_TUNER_SUB_STEREO
;
782 val
|= V4L2_TUNER_SUB_MONO
;
784 if (mode
== 2 || mode
== 4)
785 val
= V4L2_TUNER_SUB_LANG1
| V4L2_TUNER_SUB_LANG2
;
788 val
|= V4L2_TUNER_SUB_SAP
;
790 vt
->rxsubchans
= val
;
791 vt
->audmode
= state
->audmode
;
795 static int cx18_av_s_tuner(struct v4l2_subdev
*sd
, const struct v4l2_tuner
*vt
)
797 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
798 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
804 v
= cx18_av_read(cx
, 0x809);
807 switch (vt
->audmode
) {
808 case V4L2_TUNER_MODE_MONO
:
811 bilingual -> lang1 */
813 case V4L2_TUNER_MODE_STEREO
:
814 case V4L2_TUNER_MODE_LANG1
:
817 bilingual -> lang1 */
820 case V4L2_TUNER_MODE_LANG1_LANG2
:
823 bilingual -> lang1/lang2 */
826 case V4L2_TUNER_MODE_LANG2
:
829 bilingual -> lang2 */
835 cx18_av_write_expect(cx
, 0x809, v
, v
, 0xff);
836 state
->audmode
= vt
->audmode
;
840 static int cx18_av_s_std(struct v4l2_subdev
*sd
, v4l2_std_id norm
)
842 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
843 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
845 u8 fmt
= 0; /* zero is autodetect */
848 if (state
->radio
== 0 && state
->std
== norm
)
854 /* First tests should be against specific std */
855 if (state
->std
== V4L2_STD_NTSC_M_JP
) {
857 } else if (state
->std
== V4L2_STD_NTSC_443
) {
859 } else if (state
->std
== V4L2_STD_PAL_M
) {
862 } else if (state
->std
== V4L2_STD_PAL_N
) {
864 } else if (state
->std
== V4L2_STD_PAL_Nc
) {
866 } else if (state
->std
== V4L2_STD_PAL_60
) {
869 /* Then, test against generic ones */
870 if (state
->std
& V4L2_STD_NTSC
)
872 else if (state
->std
& V4L2_STD_PAL
)
874 else if (state
->std
& V4L2_STD_SECAM
)
878 CX18_DEBUG_INFO_DEV(sd
, "changing video std to fmt %i\n", fmt
);
880 /* Follow step 9 of section 3.16 in the cx18_av datasheet.
881 Without this PAL may display a vertical ghosting effect.
882 This happens for example with the Yuan MPC622. */
883 if (fmt
>= 4 && fmt
< 8) {
884 /* Set format to NTSC-M */
885 cx18_av_and_or(cx
, 0x400, ~0xf, 1);
887 cx18_av_and_or(cx
, 0x47b, ~6, 0);
889 cx18_av_and_or(cx
, 0x400, ~0x2f, fmt
| 0x20);
890 cx18_av_and_or(cx
, 0x403, ~0x3, pal_m
);
891 cx18_av_std_setup(cx
);
896 static int cx18_av_s_radio(struct v4l2_subdev
*sd
)
898 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
903 static int cx18_av_s_ctrl(struct v4l2_ctrl
*ctrl
)
905 struct v4l2_subdev
*sd
= to_sd(ctrl
);
906 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
909 case V4L2_CID_BRIGHTNESS
:
910 cx18_av_write(cx
, 0x414, ctrl
->val
- 128);
913 case V4L2_CID_CONTRAST
:
914 cx18_av_write(cx
, 0x415, ctrl
->val
<< 1);
917 case V4L2_CID_SATURATION
:
918 cx18_av_write(cx
, 0x420, ctrl
->val
<< 1);
919 cx18_av_write(cx
, 0x421, ctrl
->val
<< 1);
923 cx18_av_write(cx
, 0x422, ctrl
->val
);
932 static int cx18_av_set_fmt(struct v4l2_subdev
*sd
,
933 struct v4l2_subdev_pad_config
*cfg
,
934 struct v4l2_subdev_format
*format
)
936 struct v4l2_mbus_framefmt
*fmt
= &format
->format
;
937 struct cx18_av_state
*state
= to_cx18_av_state(sd
);
938 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
939 int HSC
, VSC
, Vsrc
, Hsrc
, filter
, Vlines
;
940 int is_50Hz
= !(state
->std
& V4L2_STD_525_60
);
942 if (format
->pad
|| fmt
->code
!= MEDIA_BUS_FMT_FIXED
)
945 fmt
->field
= V4L2_FIELD_INTERLACED
;
946 fmt
->colorspace
= V4L2_COLORSPACE_SMPTE170M
;
948 Vsrc
= (cx18_av_read(cx
, 0x476) & 0x3f) << 4;
949 Vsrc
|= (cx18_av_read(cx
, 0x475) & 0xf0) >> 4;
951 Hsrc
= (cx18_av_read(cx
, 0x472) & 0x3f) << 4;
952 Hsrc
|= (cx18_av_read(cx
, 0x471) & 0xf0) >> 4;
955 * This adjustment reflects the excess of vactive, set in
956 * cx18_av_std_setup(), above standard values:
958 * 480 + 1 for 60 Hz systems
959 * 576 + 3 for 50 Hz systems
961 Vlines
= fmt
->height
+ (is_50Hz
? 3 : 1);
964 * Invalid height and width scaling requests are:
965 * 1. width less than 1/16 of the source width
966 * 2. width greater than the source width
967 * 3. height less than 1/8 of the source height
968 * 4. height greater than the source height
970 if ((fmt
->width
* 16 < Hsrc
) || (Hsrc
< fmt
->width
) ||
971 (Vlines
* 8 < Vsrc
) || (Vsrc
< Vlines
)) {
972 CX18_ERR_DEV(sd
, "%dx%d is not a valid size!\n",
973 fmt
->width
, fmt
->height
);
977 if (format
->which
== V4L2_SUBDEV_FORMAT_TRY
)
980 HSC
= (Hsrc
* (1 << 20)) / fmt
->width
- (1 << 20);
981 VSC
= (1 << 16) - (Vsrc
* (1 << 9) / Vlines
- (1 << 9));
984 if (fmt
->width
>= 385)
986 else if (fmt
->width
> 192)
988 else if (fmt
->width
> 96)
993 CX18_DEBUG_INFO_DEV(sd
,
994 "decoder set size %dx%d -> scale %ux%u\n",
995 fmt
->width
, fmt
->height
, HSC
, VSC
);
998 cx18_av_write(cx
, 0x418, HSC
& 0xff);
999 cx18_av_write(cx
, 0x419, (HSC
>> 8) & 0xff);
1000 cx18_av_write(cx
, 0x41a, HSC
>> 16);
1002 cx18_av_write(cx
, 0x41c, VSC
& 0xff);
1003 cx18_av_write(cx
, 0x41d, VSC
>> 8);
1004 /* VS_INTRLACE=1 VFILT=filter */
1005 cx18_av_write(cx
, 0x41e, 0x8 | filter
);
1009 static int cx18_av_s_stream(struct v4l2_subdev
*sd
, int enable
)
1011 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
1013 CX18_DEBUG_INFO_DEV(sd
, "%s output\n", enable
? "enable" : "disable");
1015 cx18_av_write(cx
, 0x115, 0x8c);
1016 cx18_av_write(cx
, 0x116, 0x07);
1018 cx18_av_write(cx
, 0x115, 0x00);
1019 cx18_av_write(cx
, 0x116, 0x00);
1024 static void log_video_status(struct cx18
*cx
)
1026 static const char *const fmt_strs
[] = {
1028 "NTSC-M", "NTSC-J", "NTSC-4.43",
1029 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1030 "0x9", "0xA", "0xB",
1035 struct cx18_av_state
*state
= &cx
->av_state
;
1036 struct v4l2_subdev
*sd
= &state
->sd
;
1037 u8 vidfmt_sel
= cx18_av_read(cx
, 0x400) & 0xf;
1038 u8 gen_stat1
= cx18_av_read(cx
, 0x40d);
1039 u8 gen_stat2
= cx18_av_read(cx
, 0x40e);
1040 int vid_input
= state
->vid_input
;
1042 CX18_INFO_DEV(sd
, "Video signal: %spresent\n",
1043 (gen_stat2
& 0x20) ? "" : "not ");
1044 CX18_INFO_DEV(sd
, "Detected format: %s\n",
1045 fmt_strs
[gen_stat1
& 0xf]);
1047 CX18_INFO_DEV(sd
, "Specified standard: %s\n",
1048 vidfmt_sel
? fmt_strs
[vidfmt_sel
]
1049 : "automatic detection");
1051 if (vid_input
>= CX18_AV_COMPOSITE1
&&
1052 vid_input
<= CX18_AV_COMPOSITE8
) {
1053 CX18_INFO_DEV(sd
, "Specified video input: Composite %d\n",
1054 vid_input
- CX18_AV_COMPOSITE1
+ 1);
1056 CX18_INFO_DEV(sd
, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1057 (vid_input
& 0xf0) >> 4,
1058 (vid_input
& 0xf00) >> 8);
1061 CX18_INFO_DEV(sd
, "Specified audioclock freq: %d Hz\n",
1062 state
->audclk_freq
);
1065 static void log_audio_status(struct cx18
*cx
)
1067 struct cx18_av_state
*state
= &cx
->av_state
;
1068 struct v4l2_subdev
*sd
= &state
->sd
;
1069 u8 download_ctl
= cx18_av_read(cx
, 0x803);
1070 u8 mod_det_stat0
= cx18_av_read(cx
, 0x804);
1071 u8 mod_det_stat1
= cx18_av_read(cx
, 0x805);
1072 u8 audio_config
= cx18_av_read(cx
, 0x808);
1073 u8 pref_mode
= cx18_av_read(cx
, 0x809);
1074 u8 afc0
= cx18_av_read(cx
, 0x80b);
1075 u8 mute_ctl
= cx18_av_read(cx
, 0x8d3);
1076 int aud_input
= state
->aud_input
;
1079 switch (mod_det_stat0
) {
1080 case 0x00: p
= "mono"; break;
1081 case 0x01: p
= "stereo"; break;
1082 case 0x02: p
= "dual"; break;
1083 case 0x04: p
= "tri"; break;
1084 case 0x10: p
= "mono with SAP"; break;
1085 case 0x11: p
= "stereo with SAP"; break;
1086 case 0x12: p
= "dual with SAP"; break;
1087 case 0x14: p
= "tri with SAP"; break;
1088 case 0xfe: p
= "forced mode"; break;
1089 default: p
= "not defined"; break;
1091 CX18_INFO_DEV(sd
, "Detected audio mode: %s\n", p
);
1093 switch (mod_det_stat1
) {
1094 case 0x00: p
= "not defined"; break;
1095 case 0x01: p
= "EIAJ"; break;
1096 case 0x02: p
= "A2-M"; break;
1097 case 0x03: p
= "A2-BG"; break;
1098 case 0x04: p
= "A2-DK1"; break;
1099 case 0x05: p
= "A2-DK2"; break;
1100 case 0x06: p
= "A2-DK3"; break;
1101 case 0x07: p
= "A1 (6.0 MHz FM Mono)"; break;
1102 case 0x08: p
= "AM-L"; break;
1103 case 0x09: p
= "NICAM-BG"; break;
1104 case 0x0a: p
= "NICAM-DK"; break;
1105 case 0x0b: p
= "NICAM-I"; break;
1106 case 0x0c: p
= "NICAM-L"; break;
1107 case 0x0d: p
= "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1108 case 0x0e: p
= "IF FM Radio"; break;
1109 case 0x0f: p
= "BTSC"; break;
1110 case 0x10: p
= "detected chrominance"; break;
1111 case 0xfd: p
= "unknown audio standard"; break;
1112 case 0xfe: p
= "forced audio standard"; break;
1113 case 0xff: p
= "no detected audio standard"; break;
1114 default: p
= "not defined"; break;
1116 CX18_INFO_DEV(sd
, "Detected audio standard: %s\n", p
);
1117 CX18_INFO_DEV(sd
, "Audio muted: %s\n",
1118 (mute_ctl
& 0x2) ? "yes" : "no");
1119 CX18_INFO_DEV(sd
, "Audio microcontroller: %s\n",
1120 (download_ctl
& 0x10) ? "running" : "stopped");
1122 switch (audio_config
>> 4) {
1123 case 0x00: p
= "undefined"; break;
1124 case 0x01: p
= "BTSC"; break;
1125 case 0x02: p
= "EIAJ"; break;
1126 case 0x03: p
= "A2-M"; break;
1127 case 0x04: p
= "A2-BG"; break;
1128 case 0x05: p
= "A2-DK1"; break;
1129 case 0x06: p
= "A2-DK2"; break;
1130 case 0x07: p
= "A2-DK3"; break;
1131 case 0x08: p
= "A1 (6.0 MHz FM Mono)"; break;
1132 case 0x09: p
= "AM-L"; break;
1133 case 0x0a: p
= "NICAM-BG"; break;
1134 case 0x0b: p
= "NICAM-DK"; break;
1135 case 0x0c: p
= "NICAM-I"; break;
1136 case 0x0d: p
= "NICAM-L"; break;
1137 case 0x0e: p
= "FM radio"; break;
1138 case 0x0f: p
= "automatic detection"; break;
1139 default: p
= "undefined"; break;
1141 CX18_INFO_DEV(sd
, "Configured audio standard: %s\n", p
);
1143 if ((audio_config
>> 4) < 0xF) {
1144 switch (audio_config
& 0xF) {
1145 case 0x00: p
= "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1146 case 0x01: p
= "MONO2 (LANGUAGE B)"; break;
1147 case 0x02: p
= "MONO3 (STEREO forced MONO)"; break;
1148 case 0x03: p
= "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1149 case 0x04: p
= "STEREO"; break;
1150 case 0x05: p
= "DUAL1 (AC)"; break;
1151 case 0x06: p
= "DUAL2 (BC)"; break;
1152 case 0x07: p
= "DUAL3 (AB)"; break;
1153 default: p
= "undefined";
1155 CX18_INFO_DEV(sd
, "Configured audio mode: %s\n", p
);
1157 switch (audio_config
& 0xF) {
1158 case 0x00: p
= "BG"; break;
1159 case 0x01: p
= "DK1"; break;
1160 case 0x02: p
= "DK2"; break;
1161 case 0x03: p
= "DK3"; break;
1162 case 0x04: p
= "I"; break;
1163 case 0x05: p
= "L"; break;
1164 case 0x06: p
= "BTSC"; break;
1165 case 0x07: p
= "EIAJ"; break;
1166 case 0x08: p
= "A2-M"; break;
1167 case 0x09: p
= "FM Radio (4.5 MHz)"; break;
1168 case 0x0a: p
= "FM Radio (5.5 MHz)"; break;
1169 case 0x0b: p
= "S-Video"; break;
1170 case 0x0f: p
= "automatic standard and mode detection"; break;
1171 default: p
= "undefined"; break;
1173 CX18_INFO_DEV(sd
, "Configured audio system: %s\n", p
);
1177 CX18_INFO_DEV(sd
, "Specified audio input: Tuner (In%d)\n",
1180 CX18_INFO_DEV(sd
, "Specified audio input: External\n");
1182 switch (pref_mode
& 0xf) {
1183 case 0: p
= "mono/language A"; break;
1184 case 1: p
= "language B"; break;
1185 case 2: p
= "language C"; break;
1186 case 3: p
= "analog fallback"; break;
1187 case 4: p
= "stereo"; break;
1188 case 5: p
= "language AC"; break;
1189 case 6: p
= "language BC"; break;
1190 case 7: p
= "language AB"; break;
1191 default: p
= "undefined"; break;
1193 CX18_INFO_DEV(sd
, "Preferred audio mode: %s\n", p
);
1195 if ((audio_config
& 0xf) == 0xf) {
1196 switch ((afc0
>> 3) & 0x1) {
1197 case 0: p
= "system DK"; break;
1198 case 1: p
= "system L"; break;
1200 CX18_INFO_DEV(sd
, "Selected 65 MHz format: %s\n", p
);
1202 switch (afc0
& 0x7) {
1203 case 0: p
= "Chroma"; break;
1204 case 1: p
= "BTSC"; break;
1205 case 2: p
= "EIAJ"; break;
1206 case 3: p
= "A2-M"; break;
1207 case 4: p
= "autodetect"; break;
1208 default: p
= "undefined"; break;
1210 CX18_INFO_DEV(sd
, "Selected 45 MHz format: %s\n", p
);
1214 static int cx18_av_log_status(struct v4l2_subdev
*sd
)
1216 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
1217 log_video_status(cx
);
1218 log_audio_status(cx
);
1222 #ifdef CONFIG_VIDEO_ADV_DEBUG
1223 static int cx18_av_g_register(struct v4l2_subdev
*sd
,
1224 struct v4l2_dbg_register
*reg
)
1226 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
1228 if ((reg
->reg
& 0x3) != 0)
1231 reg
->val
= cx18_av_read4(cx
, reg
->reg
& 0x00000ffc);
1235 static int cx18_av_s_register(struct v4l2_subdev
*sd
,
1236 const struct v4l2_dbg_register
*reg
)
1238 struct cx18
*cx
= v4l2_get_subdevdata(sd
);
1240 if ((reg
->reg
& 0x3) != 0)
1242 cx18_av_write4(cx
, reg
->reg
& 0x00000ffc, reg
->val
);
1247 static const struct v4l2_ctrl_ops cx18_av_ctrl_ops
= {
1248 .s_ctrl
= cx18_av_s_ctrl
,
1251 static const struct v4l2_subdev_core_ops cx18_av_general_ops
= {
1252 .log_status
= cx18_av_log_status
,
1253 .load_fw
= cx18_av_load_fw
,
1254 .reset
= cx18_av_reset
,
1255 #ifdef CONFIG_VIDEO_ADV_DEBUG
1256 .g_register
= cx18_av_g_register
,
1257 .s_register
= cx18_av_s_register
,
1261 static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops
= {
1262 .s_radio
= cx18_av_s_radio
,
1263 .s_frequency
= cx18_av_s_frequency
,
1264 .g_tuner
= cx18_av_g_tuner
,
1265 .s_tuner
= cx18_av_s_tuner
,
1268 static const struct v4l2_subdev_audio_ops cx18_av_audio_ops
= {
1269 .s_clock_freq
= cx18_av_s_clock_freq
,
1270 .s_routing
= cx18_av_s_audio_routing
,
1273 static const struct v4l2_subdev_video_ops cx18_av_video_ops
= {
1274 .s_std
= cx18_av_s_std
,
1275 .s_routing
= cx18_av_s_video_routing
,
1276 .s_stream
= cx18_av_s_stream
,
1279 static const struct v4l2_subdev_vbi_ops cx18_av_vbi_ops
= {
1280 .decode_vbi_line
= cx18_av_decode_vbi_line
,
1281 .g_sliced_fmt
= cx18_av_g_sliced_fmt
,
1282 .s_sliced_fmt
= cx18_av_s_sliced_fmt
,
1283 .s_raw_fmt
= cx18_av_s_raw_fmt
,
1286 static const struct v4l2_subdev_pad_ops cx18_av_pad_ops
= {
1287 .set_fmt
= cx18_av_set_fmt
,
1290 static const struct v4l2_subdev_ops cx18_av_ops
= {
1291 .core
= &cx18_av_general_ops
,
1292 .tuner
= &cx18_av_tuner_ops
,
1293 .audio
= &cx18_av_audio_ops
,
1294 .video
= &cx18_av_video_ops
,
1295 .vbi
= &cx18_av_vbi_ops
,
1296 .pad
= &cx18_av_pad_ops
,
1299 int cx18_av_probe(struct cx18
*cx
)
1301 struct cx18_av_state
*state
= &cx
->av_state
;
1302 struct v4l2_subdev
*sd
;
1305 state
->rev
= cx18_av_read4(cx
, CXADEC_CHIP_CTRL
) & 0xffff;
1307 state
->vid_input
= CX18_AV_COMPOSITE7
;
1308 state
->aud_input
= CX18_AV_AUDIO8
;
1309 state
->audclk_freq
= 48000;
1310 state
->audmode
= V4L2_TUNER_MODE_LANG1
;
1311 state
->slicer_line_delay
= 0;
1312 state
->slicer_line_offset
= (10 + state
->slicer_line_delay
- 2);
1315 v4l2_subdev_init(sd
, &cx18_av_ops
);
1316 v4l2_set_subdevdata(sd
, cx
);
1317 snprintf(sd
->name
, sizeof(sd
->name
),
1318 "%s %03x", cx
->v4l2_dev
.name
, (state
->rev
>> 4));
1319 sd
->grp_id
= CX18_HW_418_AV
;
1320 v4l2_ctrl_handler_init(&state
->hdl
, 9);
1321 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_ctrl_ops
,
1322 V4L2_CID_BRIGHTNESS
, 0, 255, 1, 128);
1323 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_ctrl_ops
,
1324 V4L2_CID_CONTRAST
, 0, 127, 1, 64);
1325 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_ctrl_ops
,
1326 V4L2_CID_SATURATION
, 0, 127, 1, 64);
1327 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_ctrl_ops
,
1328 V4L2_CID_HUE
, -128, 127, 1, 0);
1330 state
->volume
= v4l2_ctrl_new_std(&state
->hdl
,
1331 &cx18_av_audio_ctrl_ops
, V4L2_CID_AUDIO_VOLUME
,
1332 0, 65535, 65535 / 100, 0);
1333 v4l2_ctrl_new_std(&state
->hdl
,
1334 &cx18_av_audio_ctrl_ops
, V4L2_CID_AUDIO_MUTE
,
1336 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_audio_ctrl_ops
,
1337 V4L2_CID_AUDIO_BALANCE
,
1338 0, 65535, 65535 / 100, 32768);
1339 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_audio_ctrl_ops
,
1340 V4L2_CID_AUDIO_BASS
,
1341 0, 65535, 65535 / 100, 32768);
1342 v4l2_ctrl_new_std(&state
->hdl
, &cx18_av_audio_ctrl_ops
,
1343 V4L2_CID_AUDIO_TREBLE
,
1344 0, 65535, 65535 / 100, 32768);
1345 sd
->ctrl_handler
= &state
->hdl
;
1346 if (state
->hdl
.error
) {
1347 int err
= state
->hdl
.error
;
1349 v4l2_ctrl_handler_free(&state
->hdl
);
1352 err
= v4l2_device_register_subdev(&cx
->v4l2_dev
, sd
);
1354 v4l2_ctrl_handler_free(&state
->hdl
);