drivers/media/pci/intel/ipu3/ipu3-cio2.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (C) 2017 Intel Corporation */
   3
   4 #ifndef __IPU3_CIO2_H
   5 #define __IPU3_CIO2_H
   6
   7 #include <linux/types.h>
   8
   9 #define CIO2_NAME                                       "ipu3-cio2"
  10 #define CIO2_DEVICE_NAME                                "Intel IPU3 CIO2"
  11 #define CIO2_ENTITY_NAME                                "ipu3-csi2"
  12 #define CIO2_PCI_ID                                     0x9d32
  13 #define CIO2_PCI_BAR                                    0
  14 #define CIO2_DMA_MASK                                   DMA_BIT_MASK(39)
  15
  16 #define CIO2_IMAGE_MAX_WIDTH                            4224U
  17 #define CIO2_IMAGE_MAX_HEIGHT                           3136U
  18
  19 /* 32MB = 8xFBPT_entry */
  20 #define CIO2_MAX_LOPS                                   8
  21 #define CIO2_MAX_BUFFERS                        (PAGE_SIZE / 16 / CIO2_MAX_LOPS)
  22 #define CIO2_LOP_ENTRIES                        (PAGE_SIZE / sizeof(u32))
  23
  24 #define CIO2_PAD_SINK                                   0U
  25 #define CIO2_PAD_SOURCE                                 1U
  26 #define CIO2_PADS                                       2U
  27
  28 #define CIO2_NUM_DMA_CHAN                               20U
  29 #define CIO2_NUM_PORTS                                  4U /* DPHYs */
  30
  31 /* 1 for each sensor */
  32 #define CIO2_QUEUES                                     CIO2_NUM_PORTS
  33
  34 /* Register and bit field definitions */
  35 #define CIO2_REG_PIPE_BASE(n)                   ((n) * 0x0400)  /* n = 0..3 */
  36 #define CIO2_REG_CSIRX_BASE                             0x000
  37 #define CIO2_REG_MIPIBE_BASE                            0x100
  38 #define CIO2_REG_PIXELGEN_BAS                           0x200
  39 #define CIO2_REG_IRQCTRL_BASE                           0x300
  40 #define CIO2_REG_GPREG_BASE                             0x1000
  41
  42 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_CSIRX_BASE */
  43 #define CIO2_REG_CSIRX_ENABLE                   (CIO2_REG_CSIRX_BASE + 0x0)
  44 #define CIO2_REG_CSIRX_NOF_ENABLED_LANES        (CIO2_REG_CSIRX_BASE + 0x4)
  45 #define CIO2_REG_CSIRX_SP_IF_CONFIG             (CIO2_REG_CSIRX_BASE + 0x10)
  46 #define CIO2_REG_CSIRX_LP_IF_CONFIG             (CIO2_REG_CSIRX_BASE + 0x14)
  47 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT                  0x00
  48 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT_VC_INACTIVE      0x01
  49 #define CIO2_CSIRX_IF_CONFIG_PASS                       0x02
  50 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR                 BIT(2)
  51 #define CIO2_REG_CSIRX_STATUS                   (CIO2_REG_CSIRX_BASE + 0x18)
  52 #define CIO2_REG_CSIRX_STATUS_DLANE_HS          (CIO2_REG_CSIRX_BASE + 0x1c)
  53 #define CIO2_CSIRX_STATUS_DLANE_HS_MASK                 0xff
  54 #define CIO2_REG_CSIRX_STATUS_DLANE_LP          (CIO2_REG_CSIRX_BASE + 0x20)
  55 #define CIO2_CSIRX_STATUS_DLANE_LP_MASK                 0xffffff
  56 /* Termination enable and settle in 0.0625ns units, lane=0..3 or -1 for clock */
  57 #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \
  58                                 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane))
  59 #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \
  60                                 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane))
  61 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_MIPIBE_BASE */
  62 #define CIO2_REG_MIPIBE_ENABLE          (CIO2_REG_MIPIBE_BASE + 0x0)
  63 #define CIO2_REG_MIPIBE_STATUS          (CIO2_REG_MIPIBE_BASE + 0x4)
  64 #define CIO2_REG_MIPIBE_COMP_FORMAT(vc) \
  65                                 (CIO2_REG_MIPIBE_BASE + 0x8 + 0x4 * (vc))
  66 #define CIO2_REG_MIPIBE_FORCE_RAW8      (CIO2_REG_MIPIBE_BASE + 0x20)
  67 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE               BIT(0)
  68 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID           BIT(1)
  69 #define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT         2U
  70
  71 #define CIO2_REG_MIPIBE_IRQ_STATUS      (CIO2_REG_MIPIBE_BASE + 0x24)
  72 #define CIO2_REG_MIPIBE_IRQ_CLEAR       (CIO2_REG_MIPIBE_BASE + 0x28)
  73 #define CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD (CIO2_REG_MIPIBE_BASE + 0x68)
  74 #define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD                1U
  75 #define CIO2_REG_MIPIBE_PKT_STALL_STATUS (CIO2_REG_MIPIBE_BASE + 0x6c)
  76 #define CIO2_REG_MIPIBE_PARSE_GSP_THROUGH_LP_LUT_REG_IDX \
  77                                         (CIO2_REG_MIPIBE_BASE + 0x70)
  78 #define CIO2_REG_MIPIBE_SP_LUT_ENTRY(vc) \
  79                                        (CIO2_REG_MIPIBE_BASE + 0x74 + 4 * (vc))
  80 #define CIO2_REG_MIPIBE_LP_LUT_ENTRY(m) /* m = 0..15 */ \
  81                                         (CIO2_REG_MIPIBE_BASE + 0x84 + 4 * (m))
  82 #define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD              1U
  83 #define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT              1U
  84 #define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT               5U
  85 #define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT      7U
  86
  87 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_IRQCTRL_BASE */
  88 /* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */
  89 #define CIO2_REG_IRQCTRL_EDGE           (CIO2_REG_IRQCTRL_BASE + 0x00)
  90 #define CIO2_REG_IRQCTRL_MASK           (CIO2_REG_IRQCTRL_BASE + 0x04)
  91 #define CIO2_REG_IRQCTRL_STATUS         (CIO2_REG_IRQCTRL_BASE + 0x08)
  92 #define CIO2_REG_IRQCTRL_CLEAR          (CIO2_REG_IRQCTRL_BASE + 0x0c)
  93 #define CIO2_REG_IRQCTRL_ENABLE         (CIO2_REG_IRQCTRL_BASE + 0x10)
  94 #define CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE        (CIO2_REG_IRQCTRL_BASE + 0x14)
  95
  96 #define CIO2_REG_GPREG_SRST             (CIO2_REG_GPREG_BASE + 0x0)
  97 #define CIO2_GPREG_SRST_ALL                             0xffff  /* Reset all */
  98 #define CIO2_REG_FB_HPLL_FREQ           (CIO2_REG_GPREG_BASE + 0x08)
  99 #define CIO2_REG_ISCLK_RATIO            (CIO2_REG_GPREG_BASE + 0xc)
 100
 101 #define CIO2_REG_CGC                                    0x1400
 102 #define CIO2_CGC_CSI2_TGE                               BIT(0)
 103 #define CIO2_CGC_PRIM_TGE                               BIT(1)
 104 #define CIO2_CGC_SIDE_TGE                               BIT(2)
 105 #define CIO2_CGC_XOSC_TGE                               BIT(3)
 106 #define CIO2_CGC_MPLL_SHUTDOWN_EN                       BIT(4)
 107 #define CIO2_CGC_D3I3_TGE                               BIT(5)
 108 #define CIO2_CGC_CSI2_INTERFRAME_TGE                    BIT(6)
 109 #define CIO2_CGC_CSI2_PORT_DCGE                         BIT(8)
 110 #define CIO2_CGC_CSI2_DCGE                              BIT(9)
 111 #define CIO2_CGC_SIDE_DCGE                              BIT(10)
 112 #define CIO2_CGC_PRIM_DCGE                              BIT(11)
 113 #define CIO2_CGC_ROSC_DCGE                              BIT(12)
 114 #define CIO2_CGC_XOSC_DCGE                              BIT(13)
 115 #define CIO2_CGC_FLIS_DCGE                              BIT(14)
 116 #define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT                  20U
 117 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT              24U
 118 #define CIO2_REG_D0I3C                                  0x1408
 119 #define CIO2_D0I3C_I3                                   BIT(2)  /* Set D0I3 */
 120 #define CIO2_D0I3C_RR                                   BIT(3)  /* Restore? */
 121 #define CIO2_REG_SWRESET                                0x140c
 122 #define CIO2_SWRESET_SWRESET                            1U
 123 #define CIO2_REG_SENSOR_ACTIVE                          0x1410
 124 #define CIO2_REG_INT_STS                                0x1414
 125 #define CIO2_REG_INT_STS_EXT_OE                         0x1418
 126 #define CIO2_INT_EXT_OE_DMAOE_SHIFT                     0U
 127 #define CIO2_INT_EXT_OE_DMAOE_MASK                      0x7ffff
 128 #define CIO2_INT_EXT_OE_OES_SHIFT                       24U
 129 #define CIO2_INT_EXT_OE_OES_MASK        (0xf << CIO2_INT_EXT_OE_OES_SHIFT)
 130 #define CIO2_REG_INT_EN                                 0x1420
 131 #define CIO2_REG_INT_EN_IRQ                             (1 << 24)
 132 #define CIO2_REG_INT_EN_IOS(dma)        (1U << (((dma) >> 1U) + 12U))
 133 /*
 134  * Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3,
 135  * DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera
 136  */
 137 #define CIO2_INT_IOC(dma)       (1U << ((dma) < 4U ? (dma) : ((dma) >> 1U) + 2U))
 138 #define CIO2_INT_IOC_SHIFT                              0
 139 #define CIO2_INT_IOC_MASK               (0x7ff << CIO2_INT_IOC_SHIFT)
 140 #define CIO2_INT_IOS_IOLN(dma)          (1U << (((dma) >> 1U) + 12U))
 141 #define CIO2_INT_IOS_IOLN_SHIFT                         12
 142 #define CIO2_INT_IOS_IOLN_MASK          (0x3ff << CIO2_INT_IOS_IOLN_SHIFT)
 143 #define CIO2_INT_IOIE                                   BIT(22)
 144 #define CIO2_INT_IOOE                                   BIT(23)
 145 #define CIO2_INT_IOIRQ                                  BIT(24)
 146 #define CIO2_REG_INT_EN_EXT_OE                          0x1424
 147 #define CIO2_REG_DMA_DBG                                0x1448
 148 #define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT                0U
 149 #define CIO2_REG_PBM_ARB_CTRL                           0x1460
 150 #define CIO2_PBM_ARB_CTRL_LANES_DIV                     0U /* 4-4-2-2 lanes */
 151 #define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT               0U
 152 #define CIO2_PBM_ARB_CTRL_LE_EN                         BIT(7)
 153 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN                2U
 154 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT          8U
 155 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP                 480U
 156 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT           16U
 157 #define CIO2_REG_PBM_WMCTRL1                            0x1464
 158 #define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT                  0U
 159 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT                 8U
 160 #define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT                 16U
 161 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE               BIT(31)
 162 #define CIO2_PBM_WMCTRL1_MIN_2CK        (4 << CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT)
 163 #define CIO2_PBM_WMCTRL1_MID1_2CK       (16 << CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT)
 164 #define CIO2_PBM_WMCTRL1_MID2_2CK       (21 << CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT)
 165 #define CIO2_REG_PBM_WMCTRL2                            0x1468
 166 #define CIO2_PBM_WMCTRL2_HWM_2CK                        40U
 167 #define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT                  0U
 168 #define CIO2_PBM_WMCTRL2_LWM_2CK                        22U
 169 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT                  8U
 170 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK                     2U
 171 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT               16U
 172 #define CIO2_PBM_WMCTRL2_TRANSDYN                       1U
 173 #define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT                 24U
 174 #define CIO2_PBM_WMCTRL2_DYNWMEN                        BIT(28)
 175 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN                    BIT(29)
 176 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN                    BIT(30)
 177 #define CIO2_PBM_WMCTRL2_DRAINNOW                       BIT(31)
 178 #define CIO2_REG_PBM_TS_COUNT                           0x146c
 179 #define CIO2_REG_PBM_FOPN_ABORT                         0x1474
 180 /* below n = 0..3 */
 181 #define CIO2_PBM_FOPN_ABORT(n)                          (0x1 << 8U * (n))
 182 #define CIO2_PBM_FOPN_FORCE_ABORT(n)                    (0x2 << 8U * (n))
 183 #define CIO2_PBM_FOPN_FRAMEOPEN(n)                      (0x8 << 8U * (n))
 184 #define CIO2_REG_LTRCTRL                                0x1480
 185 #define CIO2_LTRCTRL_LTRDYNEN                           BIT(16)
 186 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT                8U
 187 #define CIO2_LTRCTRL_LTRSTABLETIME_MASK                 0xff
 188 #define CIO2_LTRCTRL_LTRSEL1S3                          BIT(7)
 189 #define CIO2_LTRCTRL_LTRSEL1S2                          BIT(6)
 190 #define CIO2_LTRCTRL_LTRSEL1S1                          BIT(5)
 191 #define CIO2_LTRCTRL_LTRSEL1S0                          BIT(4)
 192 #define CIO2_LTRCTRL_LTRSEL2S3                          BIT(3)
 193 #define CIO2_LTRCTRL_LTRSEL2S2                          BIT(2)
 194 #define CIO2_LTRCTRL_LTRSEL2S1                          BIT(1)
 195 #define CIO2_LTRCTRL_LTRSEL2S0                          BIT(0)
 196 #define CIO2_REG_LTRVAL23                               0x1484
 197 #define CIO2_REG_LTRVAL01                               0x1488
 198 #define CIO2_LTRVAL02_VAL_SHIFT                         0U
 199 #define CIO2_LTRVAL02_SCALE_SHIFT                       10U
 200 #define CIO2_LTRVAL13_VAL_SHIFT                         16U
 201 #define CIO2_LTRVAL13_SCALE_SHIFT                       26U
 202
 203 #define CIO2_LTRVAL0_VAL                                175U
 204 /* Value times 1024 ns */
 205 #define CIO2_LTRVAL0_SCALE                              2U
 206 #define CIO2_LTRVAL1_VAL                                90U
 207 #define CIO2_LTRVAL1_SCALE                              2U
 208 #define CIO2_LTRVAL2_VAL                                90U
 209 #define CIO2_LTRVAL2_SCALE                              2U
 210 #define CIO2_LTRVAL3_VAL                                90U
 211 #define CIO2_LTRVAL3_SCALE                              2U
 212
 213 #define CIO2_REG_CDMABA(n)              (0x1500 + 0x10 * (n))   /* n = 0..19 */
 214 #define CIO2_REG_CDMARI(n)              (0x1504 + 0x10 * (n))
 215 #define CIO2_CDMARI_FBPT_RP_SHIFT                       0U
 216 #define CIO2_CDMARI_FBPT_RP_MASK                        0xff
 217 #define CIO2_REG_CDMAC0(n)              (0x1508 + 0x10 * (n))
 218 #define CIO2_CDMAC0_FBPT_LEN_SHIFT                      0U
 219 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT                    8U
 220 #define CIO2_CDMAC0_FBPT_NS                             BIT(25)
 221 #define CIO2_CDMAC0_DMA_INTR_ON_FS                      BIT(26)
 222 #define CIO2_CDMAC0_DMA_INTR_ON_FE                      BIT(27)
 223 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL               BIT(28)
 224 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS              BIT(29)
 225 #define CIO2_CDMAC0_DMA_EN                              BIT(30)
 226 #define CIO2_CDMAC0_DMA_HALTED                          BIT(31)
 227 #define CIO2_REG_CDMAC1(n)              (0x150c + 0x10 * (n))
 228 #define CIO2_CDMAC1_LINENUMINT_SHIFT                    0U
 229 #define CIO2_CDMAC1_LINENUMUPDATE_SHIFT                 16U
 230 /* n = 0..3 */
 231 #define CIO2_REG_PXM_PXF_FMT_CFG0(n)    (0x1700 + 0x30 * (n))
 232 #define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT                 0U
 233 #define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT                 16U
 234 #define CIO2_PXM_PXF_FMT_CFG_PCK_64B                    (0 << 0)
 235 #define CIO2_PXM_PXF_FMT_CFG_PCK_32B                    (1 << 0)
 236 #define CIO2_PXM_PXF_FMT_CFG_BPP_08                     (0 << 2)
 237 #define CIO2_PXM_PXF_FMT_CFG_BPP_10                     (1 << 2)
 238 #define CIO2_PXM_PXF_FMT_CFG_BPP_12                     (2 << 2)
 239 #define CIO2_PXM_PXF_FMT_CFG_BPP_14                     (3 << 2)
 240 #define CIO2_PXM_PXF_FMT_CFG_SPEC_4PPC                  (0 << 4)
 241 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_RGBA             (1 << 4)
 242 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_ARGB             (2 << 4)
 243 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR2               (3 << 4)
 244 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR3               (4 << 4)
 245 #define CIO2_PXM_PXF_FMT_CFG_SPEC_NV16                  (5 << 4)
 246 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_AB              (1 << 7)
 247 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD              (1 << 8)
 248 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_AC              (1 << 9)
 249 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_BD              (1 << 10)
 250 #define CIO2_REG_INT_STS_EXT_IE                         0x17e4
 251 #define CIO2_REG_INT_EN_EXT_IE                          0x17e8
 252 #define CIO2_INT_EXT_IE_ECC_RE(n)                       (0x01 << (8U * (n)))
 253 #define CIO2_INT_EXT_IE_DPHY_NR(n)                      (0x02 << (8U * (n)))
 254 #define CIO2_INT_EXT_IE_ECC_NR(n)                       (0x04 << (8U * (n)))
 255 #define CIO2_INT_EXT_IE_CRCERR(n)                       (0x08 << (8U * (n)))
 256 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n)               (0x10 << (8U * (n)))
 257 #define CIO2_INT_EXT_IE_PKT2SHORT(n)                    (0x20 << (8U * (n)))
 258 #define CIO2_INT_EXT_IE_PKT2LONG(n)                     (0x40 << (8U * (n)))
 259 #define CIO2_INT_EXT_IE_IRQ(n)                          (0x80 << (8U * (n)))
 260 #define CIO2_REG_PXM_FRF_CFG(n)                         (0x1720 + 0x30 * (n))
 261 #define CIO2_PXM_FRF_CFG_FNSEL                          BIT(0)
 262 #define CIO2_PXM_FRF_CFG_FN_RST                         BIT(1)
 263 #define CIO2_PXM_FRF_CFG_ABORT                          BIT(2)
 264 #define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT                   3U
 265 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR                BIT(8)
 266 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE                     BIT(9)
 267 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE                BIT(10)
 268 #define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT            11U
 269 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES                 BIT(13)
 270 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT                BIT(14)
 271 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE                  BIT(15)
 272 #define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT           16U
 273 #define CIO2_REG_PXM_SID2BID0(n)                        (0x1724 + 0x30 * (n))
 274 #define CIO2_FB_HPLL_FREQ                               0x2
 275 #define CIO2_ISCLK_RATIO                                0xc
 276
 277 #define CIO2_IRQCTRL_MASK                               0x3ffff
 278
 279 #define CIO2_INT_EN_EXT_OE_MASK                         0x8f0fffff
 280
 281 #define CIO2_CGC_CLKGATE_HOLDOFF                        3U
 282 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF                    5U
 283
 284 #define CIO2_PXM_FRF_CFG_CRC_TH                         16
 285
 286 #define CIO2_INT_EN_EXT_IE_MASK                         0xffffffff
 287
 288 #define CIO2_DMA_CHAN                                   0U
 289
 290 #define CIO2_CSIRX_DLY_CNT_CLANE_IDX                    -1
 291
 292 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A               0
 293 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_B               0
 294 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A               95
 295 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B               -8
 296
 297 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A               0
 298 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_B               0
 299 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A               85
 300 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_B               -2
 301
 302 #define CIO2_CSIRX_DLY_CNT_TERMEN_DEFAULT               0x4
 303 #define CIO2_CSIRX_DLY_CNT_SETTLE_DEFAULT               0x570
 304
 305 #define CIO2_PMCSR_OFFSET                               4U
 306 #define CIO2_PMCSR_D0D3_SHIFT                           2U
 307 #define CIO2_PMCSR_D3                                   0x3
 308
 309 struct cio2_csi2_timing {
 310         s32 clk_termen;
 311         s32 clk_settle;
 312         s32 dat_termen;
 313         s32 dat_settle;
 314 };
 315
 316 struct cio2_buffer {
 317         struct vb2_v4l2_buffer vbb;
 318         u32 *lop[CIO2_MAX_LOPS];
 319         dma_addr_t lop_bus_addr[CIO2_MAX_LOPS];
 320         unsigned int offset;
 321 };
 322
 323 struct csi2_bus_info {
 324         u32 port;
 325         u32 lanes;
 326 };
 327
 328 struct cio2_queue {
 329         /* mutex to be used by vb2_queue */
 330         struct mutex lock;
 331         struct media_pipeline pipe;
 332         struct csi2_bus_info csi2;
 333         struct v4l2_subdev *sensor;
 334         void __iomem *csi_rx_base;
 335
 336         /* Subdev, /dev/v4l-subdevX */
 337         struct v4l2_subdev subdev;
 338         struct mutex subdev_lock; /* Serialise acces to subdev_fmt field */
 339         struct media_pad subdev_pads[CIO2_PADS];
 340         struct v4l2_mbus_framefmt subdev_fmt;
 341         atomic_t frame_sequence;
 342
 343         /* Video device, /dev/videoX */
 344         struct video_device vdev;
 345         struct media_pad vdev_pad;
 346         struct v4l2_pix_format_mplane format;
 347         struct vb2_queue vbq;
 348
 349         /* Buffer queue handling */
 350         struct cio2_fbpt_entry *fbpt;   /* Frame buffer pointer table */
 351         dma_addr_t fbpt_bus_addr;
 352         struct cio2_buffer *bufs[CIO2_MAX_BUFFERS];
 353         unsigned int bufs_first;        /* Index of the first used entry */
 354         unsigned int bufs_next; /* Index of the first unused entry */
 355         atomic_t bufs_queued;
 356 };
 357
 358 struct cio2_device {
 359         struct pci_dev *pci_dev;
 360         void __iomem *base;
 361         struct v4l2_device v4l2_dev;
 362         struct cio2_queue queue[CIO2_QUEUES];
 363         struct cio2_queue *cur_queue;
 364         /* mutex to be used by video_device */
 365         struct mutex lock;
 366
 367         bool streaming;
 368         struct v4l2_async_notifier notifier;
 369         struct media_device media_dev;
 370
 371         /*
 372          * Safety net to catch DMA fetch ahead
 373          * when reaching the end of LOP
 374          */
 375         void *dummy_page;
 376         /* DMA handle of dummy_page */
 377         dma_addr_t dummy_page_bus_addr;
 378         /* single List of Pointers (LOP) page */
 379         u32 *dummy_lop;
 380         /* DMA handle of dummy_lop */
 381         dma_addr_t dummy_lop_bus_addr;
 382 };
 383
 384 /**************** Virtual channel ****************/
 385 /*
 386  * This should come from sensor driver. No
 387  * driver interface nor requirement yet.
 388  */
 389 #define SENSOR_VIR_CH_DFLT              0
 390
 391 /**************** FBPT operations ****************/
 392 #define CIO2_FBPT_SIZE                  (CIO2_MAX_BUFFERS * CIO2_MAX_LOPS * \
 393                                          sizeof(struct cio2_fbpt_entry))
 394
 395 #define CIO2_FBPT_SUBENTRY_UNIT         4
 396
 397 /* cio2 fbpt first_entry ctrl status */
 398 #define CIO2_FBPT_CTRL_VALID            BIT(0)
 399 #define CIO2_FBPT_CTRL_IOC              BIT(1)
 400 #define CIO2_FBPT_CTRL_IOS              BIT(2)
 401 #define CIO2_FBPT_CTRL_SUCCXFAIL        BIT(3)
 402 #define CIO2_FBPT_CTRL_CMPLCODE_SHIFT   4
 403
 404 /*
 405  * Frame Buffer Pointer Table(FBPT) entry
 406  * each entry describe an output buffer and consists of
 407  * several sub-entries
 408  */
 409 struct __packed cio2_fbpt_entry {
 410         union {
 411                 struct __packed {
 412                         u32 ctrl; /* status ctrl */
 413                         u16 cur_line_num; /* current line # written to DDR */
 414                         u16 frame_num; /* updated by DMA upon FE */
 415                         u32 first_page_offset; /* offset for 1st page in LOP */
 416                 } first_entry;
 417                 /* Second entry per buffer */
 418                 struct __packed {
 419                         u32 timestamp;
 420                         u32 num_of_bytes;
 421                         /* the number of bytes for write on last page */
 422                         u16 last_page_available_bytes;
 423                         /* the number of pages allocated for this buf */
 424                         u16 num_of_pages;
 425                 } second_entry;
 426         };
 427         u32 lop_page_addr;      /* Points to list of pointers (LOP) table */
 428 };
 429
 430 static inline struct cio2_queue *file_to_cio2_queue(struct file *file)
 431 {
 432         return container_of(video_devdata(file), struct cio2_queue, vdev);
 433 }
 434
 435 static inline struct cio2_queue *vb2q_to_cio2_queue(struct vb2_queue *vq)
 436 {
 437         return container_of(vq, struct cio2_queue, vbq);
 438 }
 439
 440 #endif