1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Driver for the NXP SAA7164 PCIe bridge
5 * Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com>
8 /* TODO: Retest the driver with errors expressed as negatives */
12 #define SAA_ERR_BAD_PARAMETER 0x09
13 #define SAA_ERR_NO_RESOURCES 0x0c
14 #define SAA_ERR_NOT_SUPPORTED 0x13
15 #define SAA_ERR_BUSY 0x15
16 #define SAA_ERR_READ 0x17
17 #define SAA_ERR_TIMEOUT 0x1f
18 #define SAA_ERR_OVERFLOW 0x20
19 #define SAA_ERR_EMPTY 0x22
20 #define SAA_ERR_NOT_STARTED 0x23
21 #define SAA_ERR_ALREADY_STARTED 0x24
22 #define SAA_ERR_NOT_STOPPED 0x25
23 #define SAA_ERR_ALREADY_STOPPED 0x26
24 #define SAA_ERR_INVALID_COMMAND 0x3e
25 #define SAA_ERR_NULL_PACKET 0x59
27 /* Errors and flags from the silicon */
28 #define PVC_ERRORCODE_UNKNOWN 0x00
29 #define PVC_ERRORCODE_INVALID_COMMAND 0x01
30 #define PVC_ERRORCODE_INVALID_CONTROL 0x02
31 #define PVC_ERRORCODE_INVALID_DATA 0x03
32 #define PVC_ERRORCODE_TIMEOUT 0x04
33 #define PVC_ERRORCODE_NAK 0x05
34 #define PVC_RESPONSEFLAG_ERROR 0x01
35 #define PVC_RESPONSEFLAG_OVERFLOW 0x02
36 #define PVC_RESPONSEFLAG_RESET 0x04
37 #define PVC_RESPONSEFLAG_INTERFACE 0x08
38 #define PVC_RESPONSEFLAG_CONTINUED 0x10
39 #define PVC_CMDFLAG_INTERRUPT 0x02
40 #define PVC_CMDFLAG_INTERFACE 0x04
41 #define PVC_CMDFLAG_SERIALIZE 0x08
42 #define PVC_CMDFLAG_CONTINUE 0x10
44 /* Silicon Commands */
45 #define GET_DESCRIPTORS_CONTROL 0x01
46 #define GET_STRING_CONTROL 0x03
47 #define GET_LANGUAGE_CONTROL 0x05
48 #define SET_POWER_CONTROL 0x07
49 #define GET_FW_STATUS_CONTROL 0x08
50 #define GET_FW_VERSION_CONTROL 0x09
51 #define SET_DEBUG_LEVEL_CONTROL 0x0B
52 #define GET_DEBUG_DATA_CONTROL 0x0C
53 #define GET_PRODUCTION_INFO_CONTROL 0x0D
56 #define SAA_CMDFLAG_CONTINUE 0x10
57 #define SAA_CMD_MAX_MSG_UNITS 256
60 #define SAA_BUS_TIMEOUT 50
61 #define SAA_DEVICE_TIMEOUT 5000
62 #define SAA_DEVICE_MAXREQUESTSIZE 256
64 /* Register addresses */
65 #define SAA_DEVICE_VERSION 0x30
66 #define SAA_DOWNLOAD_FLAGS 0x34
67 #define SAA_DOWNLOAD_FLAG 0x34
68 #define SAA_DOWNLOAD_FLAG_ACK 0x38
69 #define SAA_DATAREADY_FLAG 0x3C
70 #define SAA_DATAREADY_FLAG_ACK 0x40
72 /* Boot loader register and bit definitions */
73 #define SAA_BOOTLOADERERROR_FLAGS 0x44
74 #define SAA_DEVICE_IMAGE_SEARCHING 0x01
75 #define SAA_DEVICE_IMAGE_LOADING 0x02
76 #define SAA_DEVICE_IMAGE_BOOTING 0x03
77 #define SAA_DEVICE_IMAGE_CORRUPT 0x04
78 #define SAA_DEVICE_MEMORY_CORRUPT 0x08
79 #define SAA_DEVICE_NO_IMAGE 0x10
81 /* Register addresses */
82 #define SAA_DEVICE_2ND_VERSION 0x50
83 #define SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET 0x54
85 /* Register addresses */
86 #define SAA_SECONDSTAGEERROR_FLAGS 0x64
88 /* Bootloader regs and flags */
89 #define SAA_DEVICE_DEADLOCK_DETECTED_OFFSET 0x6C
90 #define SAA_DEVICE_DEADLOCK_DETECTED 0xDEADDEAD
92 /* Basic firmware status registers */
93 #define SAA_DEVICE_SYSINIT_STATUS_OFFSET 0x70
94 #define SAA_DEVICE_SYSINIT_STATUS 0x70
95 #define SAA_DEVICE_SYSINIT_MODE 0x74
96 #define SAA_DEVICE_SYSINIT_SPEC 0x78
97 #define SAA_DEVICE_SYSINIT_INST 0x7C
98 #define SAA_DEVICE_SYSINIT_CPULOAD 0x80
99 #define SAA_DEVICE_SYSINIT_REMAINHEAP 0x84
101 #define SAA_DEVICE_DOWNLOAD_OFFSET 0x1000
102 #define SAA_DEVICE_BUFFERBLOCKSIZE 0x1000
104 #define SAA_DEVICE_2ND_BUFFERBLOCKSIZE 0x100000
105 #define SAA_DEVICE_2ND_DOWNLOAD_OFFSET 0x200000
108 #define CS_INTERFACE 0x24
110 /* Descriptor subtypes */
111 #define VC_INPUT_TERMINAL 0x02
112 #define VC_OUTPUT_TERMINAL 0x03
113 #define VC_SELECTOR_UNIT 0x04
114 #define VC_PROCESSING_UNIT 0x05
115 #define FEATURE_UNIT 0x06
116 #define TUNER_UNIT 0x09
117 #define ENCODER_UNIT 0x0A
118 #define EXTENSION_UNIT 0x0B
119 #define VC_TUNER_PATH 0xF0
120 #define PVC_HARDWARE_DESCRIPTOR 0xF1
121 #define PVC_INTERFACE_DESCRIPTOR 0xF2
122 #define PVC_INFRARED_UNIT 0xF3
123 #define DRM_UNIT 0xF4
124 #define GENERAL_REQUEST 0xF5
127 #define VS_FORMAT_TYPE 0x02
128 #define VS_FORMAT_TYPE_I 0x01
129 #define VS_FORMAT_UNCOMPRESSED 0x04
130 #define VS_FRAME_UNCOMPRESSED 0x05
131 #define VS_FORMAT_MPEG2PS 0x09
132 #define VS_FORMAT_MPEG2TS 0x0A
133 #define VS_FORMAT_MPEG4SL 0x0B
134 #define VS_FORMAT_WM9 0x0C
135 #define VS_FORMAT_DIVX 0x0D
136 #define VS_FORMAT_VBI 0x0E
137 #define VS_FORMAT_RDS 0x0F
139 /* Device extension commands */
140 #define EXU_REGISTER_ACCESS_CONTROL 0x00
141 #define EXU_GPIO_CONTROL 0x01
142 #define EXU_GPIO_GROUP_CONTROL 0x02
143 #define EXU_INTERRUPT_CONTROL 0x03
145 /* State Transition and args */
146 #define SAA_PROBE_CONTROL 0x01
147 #define SAA_COMMIT_CONTROL 0x02
148 #define SAA_STATE_CONTROL 0x03
149 #define SAA_DMASTATE_STOP 0x00
150 #define SAA_DMASTATE_ACQUIRE 0x01
151 #define SAA_DMASTATE_PAUSE 0x02
152 #define SAA_DMASTATE_RUN 0x03
154 /* A/V Mux Input Selector */
155 #define SU_INPUT_SELECT_CONTROL 0x01
157 /* Encoder Profiles */
158 #define EU_PROFILE_PS_DVD 0x06
159 #define EU_PROFILE_TS_HQ 0x09
160 #define EU_VIDEO_FORMAT_MPEG_2 0x02
163 #define TU_AUDIO_MODE_CONTROL 0x17
166 #define TU_STANDARD_CONTROL 0x00
167 #define TU_STANDARD_AUTO_CONTROL 0x01
168 #define TU_STANDARD_NONE 0x00
169 #define TU_STANDARD_NTSC_M 0x01
170 #define TU_STANDARD_PAL_I 0x08
171 #define TU_STANDARD_MANUAL 0x00
172 #define TU_STANDARD_AUTO 0x01
175 #define PU_BRIGHTNESS_CONTROL 0x02
176 #define PU_CONTRAST_CONTROL 0x03
177 #define PU_HUE_CONTROL 0x06
178 #define PU_SATURATION_CONTROL 0x07
179 #define PU_SHARPNESS_CONTROL 0x08
182 #define MUTE_CONTROL 0x01
183 #define VOLUME_CONTROL 0x02
184 #define AUDIO_DEFAULT_CONTROL 0x0D
186 /* Default Volume Levels */
187 #define TMHW_LEV_ADJ_DECLEV_DEFAULT 0x00
188 #define TMHW_LEV_ADJ_MONOLEV_DEFAULT 0x00
189 #define TMHW_LEV_ADJ_NICLEV_DEFAULT 0x00
190 #define TMHW_LEV_ADJ_SAPLEV_DEFAULT 0x00
191 #define TMHW_LEV_ADJ_ADCLEV_DEFAULT 0x00
193 /* Encoder Related Commands */
194 #define EU_PROFILE_CONTROL 0x00
195 #define EU_VIDEO_FORMAT_CONTROL 0x01
196 #define EU_VIDEO_BIT_RATE_CONTROL 0x02
197 #define EU_VIDEO_RESOLUTION_CONTROL 0x03
198 #define EU_VIDEO_GOP_STRUCTURE_CONTROL 0x04
199 #define EU_VIDEO_INPUT_ASPECT_CONTROL 0x0A
200 #define EU_AUDIO_FORMAT_CONTROL 0x0C
201 #define EU_AUDIO_BIT_RATE_CONTROL 0x0D
203 /* Firmware Debugging */
204 #define SET_DEBUG_LEVEL_CONTROL 0x0B
205 #define GET_DEBUG_DATA_CONTROL 0x0C