drivers/media/pci/solo6x10/solo6x10-p2m.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
   4  *
   5  * Original author:
   6  * Ben Collins <bcollins@ubuntu.com>
   7  *
   8  * Additional work by:
   9  * John Brooks <john.brooks@bluecherry.net>
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15
  16 #include "solo6x10.h"
  17
  18 static int multi_p2m;
  19 module_param(multi_p2m, uint, 0644);
  20 MODULE_PARM_DESC(multi_p2m,
  21                  "Use multiple P2M DMA channels (default: no, 6010-only)");
  22
  23 static int desc_mode;
  24 module_param(desc_mode, uint, 0644);
  25 MODULE_PARM_DESC(desc_mode,
  26                  "Allow use of descriptor mode DMA (default: no, 6010-only)");
  27
  28 int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
  29                  void *sys_addr, u32 ext_addr, u32 size,
  30                  int repeat, u32 ext_size)
  31 {
  32         dma_addr_t dma_addr;
  33         int ret;
  34
  35         if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
  36                 return -EINVAL;
  37         if (WARN_ON_ONCE(!size))
  38                 return -EINVAL;
  39
  40         dma_addr = dma_map_single(&solo_dev->pdev->dev, sys_addr, size,
  41                                   wr ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  42         if (dma_mapping_error(&solo_dev->pdev->dev, dma_addr))
  43                 return -ENOMEM;
  44
  45         ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
  46                              repeat, ext_size);
  47
  48         dma_unmap_single(&solo_dev->pdev->dev, dma_addr, size,
  49                          wr ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  50
  51         return ret;
  52 }
  53
  54 /* Mutex must be held for p2m_id before calling this!! */
  55 int solo_p2m_dma_desc(struct solo_dev *solo_dev,
  56                       struct solo_p2m_desc *desc, dma_addr_t desc_dma,
  57                       int desc_cnt)
  58 {
  59         struct solo_p2m_dev *p2m_dev;
  60         unsigned int timeout;
  61         unsigned int config = 0;
  62         int ret = 0;
  63         unsigned int p2m_id = 0;
  64
  65         /* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
  66         if (solo_dev->type != SOLO_DEV_6110 && multi_p2m)
  67                 p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
  68
  69         p2m_dev = &solo_dev->p2m_dev[p2m_id];
  70
  71         if (mutex_lock_interruptible(&p2m_dev->mutex))
  72                 return -EINTR;
  73
  74         reinit_completion(&p2m_dev->completion);
  75         p2m_dev->error = 0;
  76
  77         if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
  78                 /* For 6010 with more than one desc, we can do a one-shot */
  79                 p2m_dev->desc_count = p2m_dev->desc_idx = 0;
  80                 config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
  81
  82                 solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
  83                 solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
  84                 solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
  85                                SOLO_P2M_DESC_MODE);
  86         } else {
  87                 /* For single descriptors and 6110, we need to run each desc */
  88                 p2m_dev->desc_count = desc_cnt;
  89                 p2m_dev->desc_idx = 1;
  90                 p2m_dev->descs = desc;
  91
  92                 solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
  93                                desc[1].dma_addr);
  94                 solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
  95                                desc[1].ext_addr);
  96                 solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
  97                                desc[1].cfg);
  98                 solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
  99                                desc[1].ctrl);
 100         }
 101
 102         timeout = wait_for_completion_timeout(&p2m_dev->completion,
 103                                               solo_dev->p2m_jiffies);
 104
 105         if (WARN_ON_ONCE(p2m_dev->error))
 106                 ret = -EIO;
 107         else if (timeout == 0) {
 108                 solo_dev->p2m_timeouts++;
 109                 ret = -EAGAIN;
 110         }
 111
 112         solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
 113
 114         /* Don't write here for the no_desc_mode case, because config is 0.
 115          * We can't test no_desc_mode again, it might race. */
 116         if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
 117                 solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
 118
 119         mutex_unlock(&p2m_dev->mutex);
 120
 121         return ret;
 122 }
 123
 124 void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
 125                         dma_addr_t dma_addr, u32 ext_addr, u32 size,
 126                         int repeat, u32 ext_size)
 127 {
 128         WARN_ON_ONCE(dma_addr & 0x03);
 129         WARN_ON_ONCE(!size);
 130
 131         desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
 132         desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
 133                 (wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;
 134
 135         if (repeat) {
 136                 desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
 137                 desc->ctrl |=  SOLO_P2M_PCI_INC(size >> 2) |
 138                          SOLO_P2M_REPEAT(repeat);
 139         }
 140
 141         desc->dma_addr = dma_addr;
 142         desc->ext_addr = ext_addr;
 143 }
 144
 145 int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
 146                    dma_addr_t dma_addr, u32 ext_addr, u32 size,
 147                    int repeat, u32 ext_size)
 148 {
 149         struct solo_p2m_desc desc[2];
 150
 151         solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
 152                            ext_size);
 153
 154         /* No need for desc_dma since we know it is a single-shot */
 155         return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
 156 }
 157
 158 void solo_p2m_isr(struct solo_dev *solo_dev, int id)
 159 {
 160         struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
 161         struct solo_p2m_desc *desc;
 162
 163         if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
 164                 complete(&p2m_dev->completion);
 165                 return;
 166         }
 167
 168         /* Setup next descriptor */
 169         p2m_dev->desc_idx++;
 170         desc = &p2m_dev->descs[p2m_dev->desc_idx];
 171
 172         solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
 173         solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
 174         solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
 175         solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
 176         solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
 177 }
 178
 179 void solo_p2m_error_isr(struct solo_dev *solo_dev)
 180 {
 181         unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
 182         struct solo_p2m_dev *p2m_dev;
 183         int i;
 184
 185         if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
 186                 return;
 187
 188         for (i = 0; i < SOLO_NR_P2M; i++) {
 189                 p2m_dev = &solo_dev->p2m_dev[i];
 190                 p2m_dev->error = 1;
 191                 solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
 192                 complete(&p2m_dev->completion);
 193         }
 194 }
 195
 196 void solo_p2m_exit(struct solo_dev *solo_dev)
 197 {
 198         int i;
 199
 200         for (i = 0; i < SOLO_NR_P2M; i++)
 201                 solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
 202 }
 203
 204 static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
 205 {
 206         u32 *wr_buf;
 207         u32 *rd_buf;
 208         int i;
 209         int ret = -EIO;
 210         int order = get_order(size);
 211
 212         wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
 213         if (wr_buf == NULL)
 214                 return -1;
 215
 216         rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
 217         if (rd_buf == NULL) {
 218                 free_pages((unsigned long)wr_buf, order);
 219                 return -1;
 220         }
 221
 222         for (i = 0; i < (size >> 3); i++)
 223                 *(wr_buf + i) = (i << 16) | (i + 1);
 224
 225         for (i = (size >> 3); i < (size >> 2); i++)
 226                 *(wr_buf + i) = ~((i << 16) | (i + 1));
 227
 228         memset(rd_buf, 0x55, size);
 229
 230         if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
 231                 goto test_fail;
 232
 233         if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
 234                 goto test_fail;
 235
 236         for (i = 0; i < (size >> 2); i++) {
 237                 if (*(wr_buf + i) != *(rd_buf + i))
 238                         goto test_fail;
 239         }
 240
 241         ret = 0;
 242
 243 test_fail:
 244         free_pages((unsigned long)wr_buf, order);
 245         free_pages((unsigned long)rd_buf, order);
 246
 247         return ret;
 248 }
 249
 250 int solo_p2m_init(struct solo_dev *solo_dev)
 251 {
 252         struct solo_p2m_dev *p2m_dev;
 253         int i;
 254
 255         for (i = 0; i < SOLO_NR_P2M; i++) {
 256                 p2m_dev = &solo_dev->p2m_dev[i];
 257
 258                 mutex_init(&p2m_dev->mutex);
 259                 init_completion(&p2m_dev->completion);
 260
 261                 solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
 262                 solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
 263                                SOLO_P2M_CSC_16BIT_565 |
 264                                SOLO_P2M_DESC_INTR_OPT |
 265                                SOLO_P2M_DMA_INTERVAL(0) |
 266                                SOLO_P2M_PCI_MASTER_MODE);
 267                 solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
 268         }
 269
 270         /* Find correct SDRAM size */
 271         for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
 272                 solo_reg_write(solo_dev, SOLO_DMA_CTRL,
 273                                SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
 274                                SOLO_DMA_CTRL_SDRAM_SIZE(i) |
 275                                SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
 276                                SOLO_DMA_CTRL_READ_CLK_SELECT |
 277                                SOLO_DMA_CTRL_LATENCY(1));
 278
 279                 solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
 280                                SOLO_SYS_CFG_RESET);
 281                 solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
 282
 283                 switch (i) {
 284                 case 2:
 285                         if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
 286                             solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
 287                                 continue;
 288                         break;
 289
 290                 case 1:
 291                         if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
 292                                 continue;
 293                         break;
 294
 295                 default:
 296                         if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
 297                                 continue;
 298                 }
 299
 300                 solo_dev->sdram_size = (32 << 20) << i;
 301                 break;
 302         }
 303
 304         if (!solo_dev->sdram_size) {
 305                 dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
 306                 return -EIO;
 307         }
 308
 309         if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
 310                 dev_err(&solo_dev->pdev->dev,
 311                         "SDRAM is not large enough (%u < %u)\n",
 312                         solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
 313                 return -EIO;
 314         }
 315
 316         return 0;
 317 }