drivers/media/usb/cx231xx/cx231xx-conf-reg.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3    cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
   4                         video capture devices
   5
   6    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   7
   8  */
   9
  10 #ifndef _POLARIS_REG_H_
  11 #define _POLARIS_REG_H_
  12
  13 #define BOARD_CFG_STAT          0x0
  14 #define TS_MODE_REG             0x4
  15 #define TS1_CFG_REG             0x8
  16 #define TS1_LENGTH_REG          0xc
  17 #define TS2_CFG_REG             0x10
  18 #define TS2_LENGTH_REG          0x14
  19 #define EP_MODE_SET             0x18
  20 #define CIR_PWR_PTN1            0x1c
  21 #define CIR_PWR_PTN2            0x20
  22 #define CIR_PWR_PTN3            0x24
  23 #define CIR_PWR_MASK0           0x28
  24 #define CIR_PWR_MASK1           0x2c
  25 #define CIR_PWR_MASK2           0x30
  26 #define CIR_GAIN                0x34
  27 #define CIR_CAR_REG             0x38
  28 #define CIR_OT_CFG1             0x40
  29 #define CIR_OT_CFG2             0x44
  30 #define GBULK_BIT_EN            0x68
  31 #define PWR_CTL_EN              0x74
  32
  33 /* Polaris Endpoints capture mask for register EP_MODE_SET */
  34 #define ENABLE_EP1              0x01   /* Bit[0]=1 */
  35 #define ENABLE_EP2              0x02   /* Bit[1]=1 */
  36 #define ENABLE_EP3              0x04   /* Bit[2]=1 */
  37 #define ENABLE_EP4              0x08   /* Bit[3]=1 */
  38 #define ENABLE_EP5              0x10   /* Bit[4]=1 */
  39 #define ENABLE_EP6              0x20   /* Bit[5]=1 */
  40
  41 /* Bit definition for register PWR_CTL_EN */
  42 #define PWR_MODE_MASK           0x17f
  43 #define PWR_AV_EN               0x08   /* bit3 */
  44 #define PWR_ISO_EN              0x40   /* bit6 */
  45 #define PWR_AV_MODE             0x30   /* bit4,5  */
  46 #define PWR_TUNER_EN            0x04   /* bit2 */
  47 #define PWR_DEMOD_EN            0x02   /* bit1 */
  48 #define I2C_DEMOD_EN            0x01   /* bit0 */
  49 #define PWR_RESETOUT_EN         0x100  /* bit8 */
  50
  51 enum AV_MODE{
  52         POLARIS_AVMODE_DEFAULT = 0,
  53         POLARIS_AVMODE_DIGITAL = 0x10,
  54         POLARIS_AVMODE_ANALOGT_TV = 0x20,
  55         POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
  56
  57 };
  58
  59 /* Colibri Registers */
  60
  61 #define SINGLE_ENDED            0x0
  62 #define LOW_IF                  0x4
  63 #define EU_IF                   0x9
  64 #define US_IF                   0xa
  65
  66 #define SUP_BLK_TUNE1           0x00
  67 #define SUP_BLK_TUNE2           0x01
  68 #define SUP_BLK_TUNE3           0x02
  69 #define SUP_BLK_XTAL            0x03
  70 #define SUP_BLK_PLL1            0x04
  71 #define SUP_BLK_PLL2            0x05
  72 #define SUP_BLK_PLL3            0x06
  73 #define SUP_BLK_REF             0x07
  74 #define SUP_BLK_PWRDN           0x08
  75 #define SUP_BLK_TESTPAD         0x09
  76 #define ADC_COM_INT5_STAB_REF   0x0a
  77 #define ADC_COM_QUANT           0x0b
  78 #define ADC_COM_BIAS1           0x0c
  79 #define ADC_COM_BIAS2           0x0d
  80 #define ADC_COM_BIAS3           0x0e
  81 #define TESTBUS_CTRL            0x12
  82
  83 #define FLD_PWRDN_TUNING_BIAS   0x10
  84 #define FLD_PWRDN_ENABLE_PLL    0x08
  85 #define FLD_PWRDN_PD_BANDGAP    0x04
  86 #define FLD_PWRDN_PD_BIAS       0x02
  87 #define FLD_PWRDN_PD_TUNECK     0x01
  88
  89
  90 #define ADC_STATUS_CH1          0x20
  91 #define ADC_STATUS_CH2          0x40
  92 #define ADC_STATUS_CH3          0x60
  93
  94 #define ADC_STATUS2_CH1         0x21
  95 #define ADC_STATUS2_CH2         0x41
  96 #define ADC_STATUS2_CH3         0x61
  97
  98 #define ADC_CAL_ATEST_CH1       0x22
  99 #define ADC_CAL_ATEST_CH2       0x42
 100 #define ADC_CAL_ATEST_CH3       0x62
 101
 102 #define ADC_PWRDN_CLAMP_CH1     0x23
 103 #define ADC_PWRDN_CLAMP_CH2     0x43
 104 #define ADC_PWRDN_CLAMP_CH3     0x63
 105
 106 #define ADC_CTRL_DAC23_CH1      0x24
 107 #define ADC_CTRL_DAC23_CH2      0x44
 108 #define ADC_CTRL_DAC23_CH3      0x64
 109
 110 #define ADC_CTRL_DAC1_CH1       0x25
 111 #define ADC_CTRL_DAC1_CH2       0x45
 112 #define ADC_CTRL_DAC1_CH3       0x65
 113
 114 #define ADC_DCSERVO_DEM_CH1     0x26
 115 #define ADC_DCSERVO_DEM_CH2     0x46
 116 #define ADC_DCSERVO_DEM_CH3     0x66
 117
 118 #define ADC_FB_FRCRST_CH1       0x27
 119 #define ADC_FB_FRCRST_CH2       0x47
 120 #define ADC_FB_FRCRST_CH3       0x67
 121
 122 #define ADC_INPUT_CH1           0x28
 123 #define ADC_INPUT_CH2           0x48
 124 #define ADC_INPUT_CH3           0x68
 125 #define INPUT_SEL_MASK          0x30   /* [5:4] in_sel */
 126
 127 #define ADC_NTF_PRECLMP_EN_CH1  0x29
 128 #define ADC_NTF_PRECLMP_EN_CH2  0x49
 129 #define ADC_NTF_PRECLMP_EN_CH3  0x69
 130
 131 #define ADC_QGAIN_RES_TRM_CH1   0x2a
 132 #define ADC_QGAIN_RES_TRM_CH2   0x4a
 133 #define ADC_QGAIN_RES_TRM_CH3   0x6a
 134
 135 #define ADC_SOC_PRECLMP_TERM_CH1    0x2b
 136 #define ADC_SOC_PRECLMP_TERM_CH2    0x4b
 137 #define ADC_SOC_PRECLMP_TERM_CH3    0x6b
 138
 139 #define TESTBUS_CTRL_CH1        0x32
 140 #define TESTBUS_CTRL_CH2        0x52
 141 #define TESTBUS_CTRL_CH3        0x72
 142
 143 /******************************************************************************
 144                             * DIF registers *
 145  ******************************************************************************/
 146 #define      DIRECT_IF_REVB_BASE  0x00300
 147
 148 /*****************************************************************************/
 149 #define      DIF_PLL_FREQ_WORD        (DIRECT_IF_REVB_BASE + 0x00000000)
 150 /*****************************************************************************/
 151 #define      FLD_DIF_PLL_LOCK                           0x80000000
 152 /*  Reserved                                [30:29] */
 153 #define      FLD_DIF_PLL_FREE_RUN                       0x10000000
 154 #define      FLD_DIF_PLL_FREQ                           0x0fffffff
 155
 156 /*****************************************************************************/
 157 #define      DIF_PLL_CTRL             (DIRECT_IF_REVB_BASE + 0x00000004)
 158 /*****************************************************************************/
 159 #define      FLD_DIF_KD_PD                              0xff000000
 160 /*  Reserved                             [23:20] */
 161 #define      FLD_DIF_KDS_PD                             0x000f0000
 162 #define      FLD_DIF_KI_PD                              0x0000ff00
 163 /*  Reserved                             [7:4] */
 164 #define      FLD_DIF_KIS_PD                             0x0000000f
 165
 166 /*****************************************************************************/
 167 #define      DIF_PLL_CTRL1            (DIRECT_IF_REVB_BASE + 0x00000008)
 168 /*****************************************************************************/
 169 #define      FLD_DIF_KD_FD                              0xff000000
 170 /*  Reserved                             [23:20] */
 171 #define      FLD_DIF_KDS_FD                             0x000f0000
 172 #define      FLD_DIF_KI_FD                              0x0000ff00
 173 #define      FLD_DIF_SIG_PROP_SZ                        0x000000f0
 174 #define      FLD_DIF_KIS_FD                             0x0000000f
 175
 176 /*****************************************************************************/
 177 #define      DIF_PLL_CTRL2            (DIRECT_IF_REVB_BASE + 0x0000000c)
 178 /*****************************************************************************/
 179 #define      FLD_DIF_PLL_AGC_REF                        0xfff00000
 180 #define      FLD_DIF_PLL_AGC_KI                         0x000f0000
 181 /*  Reserved                             [15] */
 182 #define      FLD_DIF_FREQ_LIMIT                         0x00007000
 183 #define      FLD_DIF_K_FD                               0x00000f00
 184 #define      FLD_DIF_DOWNSMPL_FD                        0x000000ff
 185
 186 /*****************************************************************************/
 187 #define      DIF_PLL_CTRL3            (DIRECT_IF_REVB_BASE + 0x00000010)
 188 /*****************************************************************************/
 189 /*  Reserved                             [31:16] */
 190 #define      FLD_DIF_PLL_AGC_EN                         0x00008000
 191 /*  Reserved                             [14:12] */
 192 #define      FLD_DIF_PLL_MAN_GAIN                       0x00000fff
 193
 194 /*****************************************************************************/
 195 #define      DIF_AGC_IF_REF           (DIRECT_IF_REVB_BASE + 0x00000014)
 196 /*****************************************************************************/
 197 #define      FLD_DIF_K_AGC_RF                           0xf0000000
 198 #define      FLD_DIF_K_AGC_IF                           0x0f000000
 199 #define      FLD_DIF_K_AGC_INT                          0x00f00000
 200 /*  Reserved                             [19:12] */
 201 #define      FLD_DIF_IF_REF                             0x00000fff
 202
 203 /*****************************************************************************/
 204 #define      DIF_AGC_CTRL_IF          (DIRECT_IF_REVB_BASE + 0x00000018)
 205 /*****************************************************************************/
 206 #define      FLD_DIF_IF_MAX                             0xff000000
 207 #define      FLD_DIF_IF_MIN                             0x00ff0000
 208 #define      FLD_DIF_IF_AGC                             0x0000ffff
 209
 210 /*****************************************************************************/
 211 #define      DIF_AGC_CTRL_INT         (DIRECT_IF_REVB_BASE + 0x0000001c)
 212 /*****************************************************************************/
 213 #define      FLD_DIF_INT_MAX                            0xff000000
 214 #define      FLD_DIF_INT_MIN                            0x00ff0000
 215 #define      FLD_DIF_INT_AGC                            0x0000ffff
 216
 217 /*****************************************************************************/
 218 #define      DIF_AGC_CTRL_RF          (DIRECT_IF_REVB_BASE + 0x00000020)
 219 /*****************************************************************************/
 220 #define      FLD_DIF_RF_MAX                             0xff000000
 221 #define      FLD_DIF_RF_MIN                             0x00ff0000
 222 #define      FLD_DIF_RF_AGC                             0x0000ffff
 223
 224 /*****************************************************************************/
 225 #define      DIF_AGC_IF_INT_CURRENT   (DIRECT_IF_REVB_BASE + 0x00000024)
 226 /*****************************************************************************/
 227 #define      FLD_DIF_IF_AGC_IN                          0xffff0000
 228 #define      FLD_DIF_INT_AGC_IN                         0x0000ffff
 229
 230 /*****************************************************************************/
 231 #define      DIF_AGC_RF_CURRENT       (DIRECT_IF_REVB_BASE + 0x00000028)
 232 /*****************************************************************************/
 233 /*  Reserved                            [31:16] */
 234 #define      FLD_DIF_RF_AGC_IN                          0x0000ffff
 235
 236 /*****************************************************************************/
 237 #define      DIF_VIDEO_AGC_CTRL       (DIRECT_IF_REVB_BASE + 0x0000002c)
 238 /*****************************************************************************/
 239 #define      FLD_DIF_AFD                                0xc0000000
 240 #define      FLD_DIF_K_VID_AGC                          0x30000000
 241 #define      FLD_DIF_LINE_LENGTH                        0x0fff0000
 242 #define      FLD_DIF_AGC_GAIN                           0x0000ffff
 243
 244 /*****************************************************************************/
 245 #define      DIF_VID_AUD_OVERRIDE     (DIRECT_IF_REVB_BASE + 0x00000030)
 246 /*****************************************************************************/
 247 #define      FLD_DIF_AUDIO_AGC_OVERRIDE                 0x80000000
 248 /*  Reserved                             [30:30] */
 249 #define      FLD_DIF_AUDIO_MAN_GAIN                     0x3f000000
 250 /*  Reserved                             [23:17] */
 251 #define      FLD_DIF_VID_AGC_OVERRIDE                   0x00010000
 252 #define      FLD_DIF_VID_MAN_GAIN                       0x0000ffff
 253
 254 /*****************************************************************************/
 255 #define      DIF_AV_SEP_CTRL          (DIRECT_IF_REVB_BASE + 0x00000034)
 256 /*****************************************************************************/
 257 #define      FLD_DIF_LPF_FREQ                           0xc0000000
 258 #define      FLD_DIF_AV_PHASE_INC                       0x3f000000
 259 #define      FLD_DIF_AUDIO_FREQ                         0x00ffffff
 260
 261 /*****************************************************************************/
 262 #define      DIF_COMP_FLT_CTRL        (DIRECT_IF_REVB_BASE + 0x00000038)
 263 /*****************************************************************************/
 264 /*  Reserved                            [31:24] */
 265 #define      FLD_DIF_IIR23_R2                           0x00ff0000
 266 #define      FLD_DIF_IIR23_R1                           0x0000ff00
 267 #define      FLD_DIF_IIR1_R1                            0x000000ff
 268
 269 /*****************************************************************************/
 270 #define      DIF_MISC_CTRL            (DIRECT_IF_REVB_BASE + 0x0000003c)
 271 /*****************************************************************************/
 272 #define      FLD_DIF_DIF_BYPASS                         0x80000000
 273 #define      FLD_DIF_FM_NYQ_GAIN                        0x40000000
 274 #define      FLD_DIF_RF_AGC_ENA                         0x20000000
 275 #define      FLD_DIF_INT_AGC_ENA                        0x10000000
 276 #define      FLD_DIF_IF_AGC_ENA                         0x08000000
 277 #define      FLD_DIF_FORCE_RF_IF_LOCK                   0x04000000
 278 #define      FLD_DIF_VIDEO_AGC_ENA                      0x02000000
 279 #define      FLD_DIF_RF_AGC_INV                         0x01000000
 280 #define      FLD_DIF_INT_AGC_INV                        0x00800000
 281 #define      FLD_DIF_IF_AGC_INV                         0x00400000
 282 #define      FLD_DIF_SPEC_INV                           0x00200000
 283 #define      FLD_DIF_AUD_FULL_BW                        0x00100000
 284 #define      FLD_DIF_AUD_SRC_SEL                        0x00080000
 285 /*  Reserved                             [18] */
 286 #define      FLD_DIF_IF_FREQ                            0x00030000
 287 /*  Reserved                             [15:14] */
 288 #define      FLD_DIF_TIP_OFFSET                         0x00003f00
 289 /*  Reserved                             [7:5] */
 290 #define      FLD_DIF_DITHER_ENA                         0x00000010
 291 /*  Reserved                             [3:1] */
 292 #define      FLD_DIF_RF_IF_LOCK                         0x00000001
 293
 294 /*****************************************************************************/
 295 #define      DIF_SRC_PHASE_INC        (DIRECT_IF_REVB_BASE + 0x00000040)
 296 /*****************************************************************************/
 297 /*  Reserved                             [31:29] */
 298 #define      FLD_DIF_PHASE_INC                          0x1fffffff
 299
 300 /*****************************************************************************/
 301 #define      DIF_SRC_GAIN_CONTROL     (DIRECT_IF_REVB_BASE + 0x00000044)
 302 /*****************************************************************************/
 303 /*  Reserved                             [31:16] */
 304 #define      FLD_DIF_SRC_KI                             0x0000ff00
 305 #define      FLD_DIF_SRC_KD                             0x000000ff
 306
 307 /*****************************************************************************/
 308 #define      DIF_BPF_COEFF01          (DIRECT_IF_REVB_BASE + 0x00000048)
 309 /*****************************************************************************/
 310 /*  Reserved                             [31:19] */
 311 #define      FLD_DIF_BPF_COEFF_0                        0x00070000
 312 /*  Reserved                             [15:4] */
 313 #define      FLD_DIF_BPF_COEFF_1                        0x0000000f
 314
 315 /*****************************************************************************/
 316 #define      DIF_BPF_COEFF23          (DIRECT_IF_REVB_BASE + 0x0000004c)
 317 /*****************************************************************************/
 318 /*  Reserved                             [31:22] */
 319 #define      FLD_DIF_BPF_COEFF_2                        0x003f0000
 320 /*  Reserved                             [15:7] */
 321 #define      FLD_DIF_BPF_COEFF_3                        0x0000007f
 322
 323 /*****************************************************************************/
 324 #define      DIF_BPF_COEFF45          (DIRECT_IF_REVB_BASE + 0x00000050)
 325 /*****************************************************************************/
 326 /*  Reserved                             [31:24] */
 327 #define      FLD_DIF_BPF_COEFF_4                        0x00ff0000
 328 /*  Reserved                             [15:8] */
 329 #define      FLD_DIF_BPF_COEFF_5                        0x000000ff
 330
 331 /*****************************************************************************/
 332 #define      DIF_BPF_COEFF67          (DIRECT_IF_REVB_BASE + 0x00000054)
 333 /*****************************************************************************/
 334 /*  Reserved                             [31:25] */
 335 #define      FLD_DIF_BPF_COEFF_6                        0x01ff0000
 336 /*  Reserved                             [15:9] */
 337 #define      FLD_DIF_BPF_COEFF_7                        0x000001ff
 338
 339 /*****************************************************************************/
 340 #define      DIF_BPF_COEFF89          (DIRECT_IF_REVB_BASE + 0x00000058)
 341 /*****************************************************************************/
 342 /*  Reserved                             [31:26] */
 343 #define      FLD_DIF_BPF_COEFF_8                        0x03ff0000
 344 /*  Reserved                             [15:10] */
 345 #define      FLD_DIF_BPF_COEFF_9                        0x000003ff
 346
 347 /*****************************************************************************/
 348 #define      DIF_BPF_COEFF1011        (DIRECT_IF_REVB_BASE + 0x0000005c)
 349 /*****************************************************************************/
 350 /*  Reserved                             [31:27] */
 351 #define      FLD_DIF_BPF_COEFF_10                       0x07ff0000
 352 /*  Reserved                             [15:11] */
 353 #define      FLD_DIF_BPF_COEFF_11                       0x000007ff
 354
 355 /*****************************************************************************/
 356 #define      DIF_BPF_COEFF1213        (DIRECT_IF_REVB_BASE + 0x00000060)
 357 /*****************************************************************************/
 358 /*  Reserved                             [31:27] */
 359 #define      FLD_DIF_BPF_COEFF_12                       0x07ff0000
 360 /*  Reserved                             [15:12] */
 361 #define      FLD_DIF_BPF_COEFF_13                       0x00000fff
 362
 363 /*****************************************************************************/
 364 #define      DIF_BPF_COEFF1415        (DIRECT_IF_REVB_BASE + 0x00000064)
 365 /*****************************************************************************/
 366 /*  Reserved                             [31:28] */
 367 #define      FLD_DIF_BPF_COEFF_14                       0x0fff0000
 368 /*  Reserved                             [15:12] */
 369 #define      FLD_DIF_BPF_COEFF_15                       0x00000fff
 370
 371 /*****************************************************************************/
 372 #define      DIF_BPF_COEFF1617        (DIRECT_IF_REVB_BASE + 0x00000068)
 373 /*****************************************************************************/
 374 /*  Reserved                             [31:29] */
 375 #define      FLD_DIF_BPF_COEFF_16                       0x1fff0000
 376 /*  Reserved                             [15:13] */
 377 #define      FLD_DIF_BPF_COEFF_17                       0x00001fff
 378
 379 /*****************************************************************************/
 380 #define      DIF_BPF_COEFF1819        (DIRECT_IF_REVB_BASE + 0x0000006c)
 381 /*****************************************************************************/
 382 /*  Reserved                             [31:29] */
 383 #define      FLD_DIF_BPF_COEFF_18                       0x1fff0000
 384 /*  Reserved                             [15:13] */
 385 #define      FLD_DIF_BPF_COEFF_19                       0x00001fff
 386
 387 /*****************************************************************************/
 388 #define      DIF_BPF_COEFF2021        (DIRECT_IF_REVB_BASE + 0x00000070)
 389 /*****************************************************************************/
 390 /*  Reserved                             [31:29] */
 391 #define      FLD_DIF_BPF_COEFF_20                       0x1fff0000
 392 /*  Reserved                             [15:14] */
 393 #define      FLD_DIF_BPF_COEFF_21                       0x00003fff
 394
 395 /*****************************************************************************/
 396 #define      DIF_BPF_COEFF2223        (DIRECT_IF_REVB_BASE + 0x00000074)
 397 /*****************************************************************************/
 398 /*  Reserved                             [31:30] */
 399 #define      FLD_DIF_BPF_COEFF_22                       0x3fff0000
 400 /*  Reserved                             [15:14] */
 401 #define      FLD_DIF_BPF_COEFF_23                       0x00003fff
 402
 403 /*****************************************************************************/
 404 #define      DIF_BPF_COEFF2425        (DIRECT_IF_REVB_BASE + 0x00000078)
 405 /*****************************************************************************/
 406 /*  Reserved                             [31:30] */
 407 #define      FLD_DIF_BPF_COEFF_24                       0x3fff0000
 408 /*  Reserved                             [15:14] */
 409 #define      FLD_DIF_BPF_COEFF_25                       0x00003fff
 410
 411 /*****************************************************************************/
 412 #define      DIF_BPF_COEFF2627        (DIRECT_IF_REVB_BASE + 0x0000007c)
 413 /*****************************************************************************/
 414 /*  Reserved                             [31:30] */
 415 #define      FLD_DIF_BPF_COEFF_26                       0x3fff0000
 416 /*  Reserved                             [15:14] */
 417 #define      FLD_DIF_BPF_COEFF_27                       0x00003fff
 418
 419 /*****************************************************************************/
 420 #define      DIF_BPF_COEFF2829        (DIRECT_IF_REVB_BASE + 0x00000080)
 421 /*****************************************************************************/
 422 /*  Reserved                             [31:30] */
 423 #define      FLD_DIF_BPF_COEFF_28                       0x3fff0000
 424 /*  Reserved                             [15:14] */
 425 #define      FLD_DIF_BPF_COEFF_29                       0x00003fff
 426
 427 /*****************************************************************************/
 428 #define      DIF_BPF_COEFF3031        (DIRECT_IF_REVB_BASE + 0x00000084)
 429 /*****************************************************************************/
 430 /*  Reserved                             [31:30] */
 431 #define      FLD_DIF_BPF_COEFF_30                       0x3fff0000
 432 /*  Reserved                             [15:14] */
 433 #define      FLD_DIF_BPF_COEFF_31                       0x00003fff
 434
 435 /*****************************************************************************/
 436 #define      DIF_BPF_COEFF3233        (DIRECT_IF_REVB_BASE + 0x00000088)
 437 /*****************************************************************************/
 438 /*  Reserved                             [31:30] */
 439 #define      FLD_DIF_BPF_COEFF_32                       0x3fff0000
 440 /*  Reserved                             [15:14] */
 441 #define      FLD_DIF_BPF_COEFF_33                       0x00003fff
 442
 443 /*****************************************************************************/
 444 #define      DIF_BPF_COEFF3435        (DIRECT_IF_REVB_BASE + 0x0000008c)
 445 /*****************************************************************************/
 446 /*  Reserved                             [31:30] */
 447 #define      FLD_DIF_BPF_COEFF_34                       0x3fff0000
 448 /*  Reserved                             [15:14] */
 449 #define      FLD_DIF_BPF_COEFF_35                       0x00003fff
 450
 451 /*****************************************************************************/
 452 #define      DIF_BPF_COEFF36          (DIRECT_IF_REVB_BASE + 0x00000090)
 453 /*****************************************************************************/
 454 /*  Reserved                             [31:30] */
 455 #define      FLD_DIF_BPF_COEFF_36                       0x3fff0000
 456 /*  Reserved                             [15:0] */
 457
 458 /*****************************************************************************/
 459 #define      DIF_RPT_VARIANCE         (DIRECT_IF_REVB_BASE + 0x00000094)
 460 /*****************************************************************************/
 461 /*  Reserved                             [31:20] */
 462 #define      FLD_DIF_RPT_VARIANCE                       0x000fffff
 463
 464 /*****************************************************************************/
 465 #define      DIF_SOFT_RST_CTRL_REVB       (DIRECT_IF_REVB_BASE + 0x00000098)
 466 /*****************************************************************************/
 467 /*  Reserved                             [31:8] */
 468 #define      FLD_DIF_DIF_SOFT_RST                       0x00000080
 469 #define      FLD_DIF_DIF_REG_RST_MSK                    0x00000040
 470 #define      FLD_DIF_AGC_RST_MSK                        0x00000020
 471 #define      FLD_DIF_CMP_RST_MSK                        0x00000010
 472 #define      FLD_DIF_AVS_RST_MSK                        0x00000008
 473 #define      FLD_DIF_NYQ_RST_MSK                        0x00000004
 474 #define      FLD_DIF_DIF_SRC_RST_MSK                    0x00000002
 475 #define      FLD_DIF_PLL_RST_MSK                        0x00000001
 476
 477 /*****************************************************************************/
 478 #define      DIF_PLL_FREQ_ERR         (DIRECT_IF_REVB_BASE + 0x0000009c)
 479 /*****************************************************************************/
 480 /*  Reserved                             [31:25] */
 481 #define      FLD_DIF_CTL_IP                             0x01ffffff
 482
 483 #endif