1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/debugfs.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/platform_device.h>
12 #include <soc/tegra/bpmp.h>
14 struct tegra186_emc_dvfs
{
15 unsigned long latency
;
20 struct tegra_bpmp
*bpmp
;
24 struct tegra186_emc_dvfs
*dvfs
;
25 unsigned int num_dvfs
;
29 unsigned long min_rate
;
30 unsigned long max_rate
;
37 * The memory controller driver exposes some files in debugfs that can be used
38 * to control the EMC frequency. The top-level directory can be found here:
40 * /sys/kernel/debug/emc
42 * It contains the following files:
44 * - available_rates: This file contains a list of valid, space-separated
47 * - min_rate: Writing a value to this file sets the given frequency as the
48 * floor of the permitted range. If this is higher than the currently
49 * configured EMC frequency, this will cause the frequency to be
50 * increased so that it stays within the valid range.
52 * - max_rate: Similarily to the min_rate file, writing a value to this file
53 * sets the given frequency as the ceiling of the permitted range. If
54 * the value is lower than the currently configured EMC frequency, this
55 * will cause the frequency to be decreased so that it stays within the
59 static bool tegra186_emc_validate_rate(struct tegra186_emc
*emc
,
64 for (i
= 0; i
< emc
->num_dvfs
; i
++)
65 if (rate
== emc
->dvfs
[i
].rate
)
71 static int tegra186_emc_debug_available_rates_show(struct seq_file
*s
,
74 struct tegra186_emc
*emc
= s
->private;
75 const char *prefix
= "";
78 for (i
= 0; i
< emc
->num_dvfs
; i
++) {
79 seq_printf(s
, "%s%lu", prefix
, emc
->dvfs
[i
].rate
);
88 static int tegra186_emc_debug_available_rates_open(struct inode
*inode
,
91 return single_open(file
, tegra186_emc_debug_available_rates_show
,
95 static const struct file_operations tegra186_emc_debug_available_rates_fops
= {
96 .open
= tegra186_emc_debug_available_rates_open
,
99 .release
= single_release
,
102 static int tegra186_emc_debug_min_rate_get(void *data
, u64
*rate
)
104 struct tegra186_emc
*emc
= data
;
106 *rate
= emc
->debugfs
.min_rate
;
111 static int tegra186_emc_debug_min_rate_set(void *data
, u64 rate
)
113 struct tegra186_emc
*emc
= data
;
116 if (!tegra186_emc_validate_rate(emc
, rate
))
119 err
= clk_set_min_rate(emc
->clk
, rate
);
123 emc
->debugfs
.min_rate
= rate
;
128 DEFINE_SIMPLE_ATTRIBUTE(tegra186_emc_debug_min_rate_fops
,
129 tegra186_emc_debug_min_rate_get
,
130 tegra186_emc_debug_min_rate_set
, "%llu\n");
132 static int tegra186_emc_debug_max_rate_get(void *data
, u64
*rate
)
134 struct tegra186_emc
*emc
= data
;
136 *rate
= emc
->debugfs
.max_rate
;
141 static int tegra186_emc_debug_max_rate_set(void *data
, u64 rate
)
143 struct tegra186_emc
*emc
= data
;
146 if (!tegra186_emc_validate_rate(emc
, rate
))
149 err
= clk_set_max_rate(emc
->clk
, rate
);
153 emc
->debugfs
.max_rate
= rate
;
158 DEFINE_SIMPLE_ATTRIBUTE(tegra186_emc_debug_max_rate_fops
,
159 tegra186_emc_debug_max_rate_get
,
160 tegra186_emc_debug_max_rate_set
, "%llu\n");
162 static int tegra186_emc_probe(struct platform_device
*pdev
)
164 struct mrq_emc_dvfs_latency_response response
;
165 struct tegra_bpmp_message msg
;
166 struct tegra186_emc
*emc
;
170 emc
= devm_kzalloc(&pdev
->dev
, sizeof(*emc
), GFP_KERNEL
);
174 emc
->bpmp
= tegra_bpmp_get(&pdev
->dev
);
175 if (IS_ERR(emc
->bpmp
))
176 return dev_err_probe(&pdev
->dev
, PTR_ERR(emc
->bpmp
), "failed to get BPMP\n");
178 emc
->clk
= devm_clk_get(&pdev
->dev
, "emc");
179 if (IS_ERR(emc
->clk
)) {
180 err
= PTR_ERR(emc
->clk
);
181 dev_err(&pdev
->dev
, "failed to get EMC clock: %d\n", err
);
185 platform_set_drvdata(pdev
, emc
);
186 emc
->dev
= &pdev
->dev
;
188 memset(&msg
, 0, sizeof(msg
));
189 msg
.mrq
= MRQ_EMC_DVFS_LATENCY
;
192 msg
.rx
.data
= &response
;
193 msg
.rx
.size
= sizeof(response
);
195 err
= tegra_bpmp_transfer(emc
->bpmp
, &msg
);
197 dev_err(&pdev
->dev
, "failed to EMC DVFS pairs: %d\n", err
);
201 emc
->debugfs
.min_rate
= ULONG_MAX
;
202 emc
->debugfs
.max_rate
= 0;
204 emc
->num_dvfs
= response
.num_pairs
;
206 emc
->dvfs
= devm_kmalloc_array(&pdev
->dev
, emc
->num_dvfs
,
207 sizeof(*emc
->dvfs
), GFP_KERNEL
);
213 dev_dbg(&pdev
->dev
, "%u DVFS pairs:\n", emc
->num_dvfs
);
215 for (i
= 0; i
< emc
->num_dvfs
; i
++) {
216 emc
->dvfs
[i
].rate
= response
.pairs
[i
].freq
* 1000;
217 emc
->dvfs
[i
].latency
= response
.pairs
[i
].latency
;
219 if (emc
->dvfs
[i
].rate
< emc
->debugfs
.min_rate
)
220 emc
->debugfs
.min_rate
= emc
->dvfs
[i
].rate
;
222 if (emc
->dvfs
[i
].rate
> emc
->debugfs
.max_rate
)
223 emc
->debugfs
.max_rate
= emc
->dvfs
[i
].rate
;
225 dev_dbg(&pdev
->dev
, " %2u: %lu Hz -> %lu us\n", i
,
226 emc
->dvfs
[i
].rate
, emc
->dvfs
[i
].latency
);
229 err
= clk_set_rate_range(emc
->clk
, emc
->debugfs
.min_rate
,
230 emc
->debugfs
.max_rate
);
233 "failed to set rate range [%lu-%lu] for %pC\n",
234 emc
->debugfs
.min_rate
, emc
->debugfs
.max_rate
,
239 emc
->debugfs
.root
= debugfs_create_dir("emc", NULL
);
240 debugfs_create_file("available_rates", S_IRUGO
, emc
->debugfs
.root
,
241 emc
, &tegra186_emc_debug_available_rates_fops
);
242 debugfs_create_file("min_rate", S_IRUGO
| S_IWUSR
, emc
->debugfs
.root
,
243 emc
, &tegra186_emc_debug_min_rate_fops
);
244 debugfs_create_file("max_rate", S_IRUGO
| S_IWUSR
, emc
->debugfs
.root
,
245 emc
, &tegra186_emc_debug_max_rate_fops
);
250 tegra_bpmp_put(emc
->bpmp
);
254 static int tegra186_emc_remove(struct platform_device
*pdev
)
256 struct tegra186_emc
*emc
= platform_get_drvdata(pdev
);
258 debugfs_remove_recursive(emc
->debugfs
.root
);
259 tegra_bpmp_put(emc
->bpmp
);
264 static const struct of_device_id tegra186_emc_of_match
[] = {
265 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
266 { .compatible
= "nvidia,tegra186-emc" },
268 #if defined(CONFIG_ARCH_TEGRA_194_SOC)
269 { .compatible
= "nvidia,tegra194-emc" },
273 MODULE_DEVICE_TABLE(of
, tegra186_emc_of_match
);
275 static struct platform_driver tegra186_emc_driver
= {
277 .name
= "tegra186-emc",
278 .of_match_table
= tegra186_emc_of_match
,
279 .suppress_bind_attrs
= true,
281 .probe
= tegra186_emc_probe
,
282 .remove
= tegra186_emc_remove
,
284 module_platform_driver(tegra186_emc_driver
);
286 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
287 MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver");
288 MODULE_LICENSE("GPL v2");