drivers/misc/genwqe/card_ddcb.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 #ifndef __CARD_DDCB_H__
   3 #define __CARD_DDCB_H__
   4
   5 /**
   6  * IBM Accelerator Family 'GenWQE'
   7  *
   8  * (C) Copyright IBM Corp. 2013
   9  *
  10  * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
  11  * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
  12  * Author: Michael Jung <mijung@gmx.net>
  13  * Author: Michael Ruettger <michael@ibmra.de>
  14  */
  15
  16 #include <linux/types.h>
  17 #include <asm/byteorder.h>
  18
  19 #include "genwqe_driver.h"
  20 #include "card_base.h"
  21
  22 /**
  23  * struct ddcb - Device Driver Control Block DDCB
  24  * @hsi:        Hardware software interlock
  25  * @shi:        Software hardware interlock. Hsi and shi are used to interlock
  26  *              software and hardware activities. We are using a compare and
  27  *              swap operation to ensure that there are no races when
  28  *              activating new DDCBs on the queue, or when we need to
  29  *              purge a DDCB from a running queue.
  30  * @acfunc:     Accelerator function addresses a unit within the chip
  31  * @cmd:        Command to work on
  32  * @cmdopts_16: Options for the command
  33  * @asiv:       Input data
  34  * @asv:        Output data
  35  *
  36  * The DDCB data format is big endian. Multiple consequtive DDBCs form
  37  * a DDCB queue.
  38  */
  39 #define ASIV_LENGTH             104 /* Old specification without ATS field */
  40 #define ASIV_LENGTH_ATS         96  /* New specification with ATS field */
  41 #define ASV_LENGTH              64
  42
  43 struct ddcb {
  44         union {
  45                 __be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
  46                 struct {
  47                         __be16  icrc_16;
  48                         u8      hsi;
  49                         u8      shi;
  50                 };
  51         };
  52         u8  pre;                /* Preamble */
  53         u8  xdir;               /* Execution Directives */
  54         __be16 seqnum_16;       /* Sequence Number */
  55
  56         u8  acfunc;             /* Accelerator Function.. */
  57         u8  cmd;                /* Command. */
  58         __be16 cmdopts_16;      /* Command Options */
  59         u8  sur;                /* Status Update Rate */
  60         u8  psp;                /* Protection Section Pointer */
  61         __be16 rsvd_0e_16;      /* Reserved invariant */
  62
  63         __be64 fwiv_64;         /* Firmware Invariant. */
  64
  65         union {
  66                 struct {
  67                         __be64 ats_64;  /* Address Translation Spec */
  68                         u8     asiv[ASIV_LENGTH_ATS]; /* New ASIV */
  69                 } n;
  70                 u8  __asiv[ASIV_LENGTH];        /* obsolete */
  71         };
  72         u8     asv[ASV_LENGTH]; /* Appl Spec Variant */
  73
  74         __be16 rsvd_c0_16;      /* Reserved Variant */
  75         __be16 vcrc_16;         /* Variant CRC */
  76         __be32 rsvd_32;         /* Reserved unprotected */
  77
  78         __be64 deque_ts_64;     /* Deque Time Stamp. */
  79
  80         __be16 retc_16;         /* Return Code */
  81         __be16 attn_16;         /* Attention/Extended Error Codes */
  82         __be32 progress_32;     /* Progress indicator. */
  83
  84         __be64 cmplt_ts_64;     /* Completion Time Stamp. */
  85
  86         /* The following layout matches the new service layer format */
  87         __be32 ibdc_32;         /* Inbound Data Count  (* 256) */
  88         __be32 obdc_32;         /* Outbound Data Count (* 256) */
  89
  90         __be64 rsvd_SLH_64;     /* Reserved for hardware */
  91         union {                 /* private data for driver */
  92                 u8      priv[8];
  93                 __be64  priv_64;
  94         };
  95         __be64 disp_ts_64;      /* Dispatch TimeStamp */
  96 } __attribute__((__packed__));
  97
  98 /* CRC polynomials for DDCB */
  99 #define CRC16_POLYNOMIAL        0x1021
 100
 101 /*
 102  * SHI: Software to Hardware Interlock
 103  *   This 1 byte field is written by software to interlock the
 104  *   movement of one queue entry to another with the hardware in the
 105  *   chip.
 106  */
 107 #define DDCB_SHI_INTR           0x04 /* Bit 2 */
 108 #define DDCB_SHI_PURGE          0x02 /* Bit 1 */
 109 #define DDCB_SHI_NEXT           0x01 /* Bit 0 */
 110
 111 /*
 112  * HSI: Hardware to Software interlock
 113  * This 1 byte field is written by hardware to interlock the movement
 114  * of one queue entry to another with the software in the chip.
 115  */
 116 #define DDCB_HSI_COMPLETED      0x40 /* Bit 6 */
 117 #define DDCB_HSI_FETCHED        0x04 /* Bit 2 */
 118
 119 /*
 120  * Accessing HSI/SHI is done 32-bit wide
 121  *   Normally 16-bit access would work too, but on some platforms the
 122  *   16 compare and swap operation is not supported. Therefore
 123  *   switching to 32-bit such that those platforms will work too.
 124  *
 125  *                                         iCRC HSI/SHI
 126  */
 127 #define DDCB_INTR_BE32          cpu_to_be32(0x00000004)
 128 #define DDCB_PURGE_BE32         cpu_to_be32(0x00000002)
 129 #define DDCB_NEXT_BE32          cpu_to_be32(0x00000001)
 130 #define DDCB_COMPLETED_BE32     cpu_to_be32(0x00004000)
 131 #define DDCB_FETCHED_BE32       cpu_to_be32(0x00000400)
 132
 133 /* Definitions of DDCB presets */
 134 #define DDCB_PRESET_PRE         0x80
 135 #define ICRC_LENGTH(n)          ((n) + 8 + 8 + 8)  /* used ASIV + hdr fields */
 136 #define VCRC_LENGTH(n)          ((n))              /* used ASV */
 137
 138 /*
 139  * Genwqe Scatter Gather list
 140  *   Each element has up to 8 entries.
 141  *   The chaining element is element 0 cause of prefetching needs.
 142  */
 143
 144 /*
 145  * 0b0110 Chained descriptor. The descriptor is describing the next
 146  * descriptor list.
 147  */
 148 #define SG_CHAINED              (0x6)
 149
 150 /*
 151  * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
 152  * condition.
 153  */
 154 #define SG_DATA                 (0x2)
 155
 156 /*
 157  * 0b0000 Early terminator. This is the last entry on the list
 158  * irregardless of the length indicated.
 159  */
 160 #define SG_END_LIST             (0x0)
 161
 162 /**
 163  * struct sglist - Scatter gather list
 164  * @target_addr:       Either a dma addr of memory to work on or a
 165  *                     dma addr or a subsequent sglist block.
 166  * @len:               Length of the data block.
 167  * @flags:             See above.
 168  *
 169  * Depending on the command the GenWQE card can use a scatter gather
 170  * list to describe the memory it works on. Always 8 sg_entry's form
 171  * a block.
 172  */
 173 struct sg_entry {
 174         __be64 target_addr;
 175         __be32 len;
 176         __be32 flags;
 177 };
 178
 179 #endif /* __CARD_DDCB_H__ */