drivers/misc/mei/hw-me-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /*
   3  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6 #ifndef _MEI_HW_MEI_REGS_H_
   7 #define _MEI_HW_MEI_REGS_H_
   8
   9 /*
  10  * MEI device IDs
  11  */
  12 #define MEI_DEV_ID_82946GZ    0x2974  /* 82946GZ/GL */
  13 #define MEI_DEV_ID_82G35      0x2984  /* 82G35 Express */
  14 #define MEI_DEV_ID_82Q965     0x2994  /* 82Q963/Q965 */
  15 #define MEI_DEV_ID_82G965     0x29A4  /* 82P965/G965 */
  16
  17 #define MEI_DEV_ID_82GM965    0x2A04  /* Mobile PM965/GM965 */
  18 #define MEI_DEV_ID_82GME965   0x2A14  /* Mobile GME965/GLE960 */
  19
  20 #define MEI_DEV_ID_ICH9_82Q35 0x29B4  /* 82Q35 Express */
  21 #define MEI_DEV_ID_ICH9_82G33 0x29C4  /* 82G33/G31/P35/P31 Express */
  22 #define MEI_DEV_ID_ICH9_82Q33 0x29D4  /* 82Q33 Express */
  23 #define MEI_DEV_ID_ICH9_82X38 0x29E4  /* 82X38/X48 Express */
  24 #define MEI_DEV_ID_ICH9_3200  0x29F4  /* 3200/3210 Server */
  25
  26 #define MEI_DEV_ID_ICH9_6     0x28B4  /* Bearlake */
  27 #define MEI_DEV_ID_ICH9_7     0x28C4  /* Bearlake */
  28 #define MEI_DEV_ID_ICH9_8     0x28D4  /* Bearlake */
  29 #define MEI_DEV_ID_ICH9_9     0x28E4  /* Bearlake */
  30 #define MEI_DEV_ID_ICH9_10    0x28F4  /* Bearlake */
  31
  32 #define MEI_DEV_ID_ICH9M_1    0x2A44  /* Cantiga */
  33 #define MEI_DEV_ID_ICH9M_2    0x2A54  /* Cantiga */
  34 #define MEI_DEV_ID_ICH9M_3    0x2A64  /* Cantiga */
  35 #define MEI_DEV_ID_ICH9M_4    0x2A74  /* Cantiga */
  36
  37 #define MEI_DEV_ID_ICH10_1    0x2E04  /* Eaglelake */
  38 #define MEI_DEV_ID_ICH10_2    0x2E14  /* Eaglelake */
  39 #define MEI_DEV_ID_ICH10_3    0x2E24  /* Eaglelake */
  40 #define MEI_DEV_ID_ICH10_4    0x2E34  /* Eaglelake */
  41
  42 #define MEI_DEV_ID_IBXPK_1    0x3B64  /* Calpella */
  43 #define MEI_DEV_ID_IBXPK_2    0x3B65  /* Calpella */
  44
  45 #define MEI_DEV_ID_CPT_1      0x1C3A  /* Couger Point */
  46 #define MEI_DEV_ID_PBG_1      0x1D3A  /* C600/X79 Patsburg */
  47
  48 #define MEI_DEV_ID_PPT_1      0x1E3A  /* Panther Point */
  49 #define MEI_DEV_ID_PPT_2      0x1CBA  /* Panther Point */
  50 #define MEI_DEV_ID_PPT_3      0x1DBA  /* Panther Point */
  51
  52 #define MEI_DEV_ID_LPT_H      0x8C3A  /* Lynx Point H */
  53 #define MEI_DEV_ID_LPT_W      0x8D3A  /* Lynx Point - Wellsburg */
  54 #define MEI_DEV_ID_LPT_LP     0x9C3A  /* Lynx Point LP */
  55 #define MEI_DEV_ID_LPT_HR     0x8CBA  /* Lynx Point H Refresh */
  56
  57 #define MEI_DEV_ID_WPT_LP     0x9CBA  /* Wildcat Point LP */
  58 #define MEI_DEV_ID_WPT_LP_2   0x9CBB  /* Wildcat Point LP 2 */
  59
  60 #define MEI_DEV_ID_SPT        0x9D3A  /* Sunrise Point */
  61 #define MEI_DEV_ID_SPT_2      0x9D3B  /* Sunrise Point 2 */
  62 #define MEI_DEV_ID_SPT_3      0x9D3E  /* Sunrise Point 3 (iToutch) */
  63 #define MEI_DEV_ID_SPT_H      0xA13A  /* Sunrise Point H */
  64 #define MEI_DEV_ID_SPT_H_2    0xA13B  /* Sunrise Point H 2 */
  65
  66 #define MEI_DEV_ID_LBG        0xA1BA  /* Lewisburg (SPT) */
  67
  68 #define MEI_DEV_ID_BXT_M      0x1A9A  /* Broxton M */
  69 #define MEI_DEV_ID_APL_I      0x5A9A  /* Apollo Lake I */
  70
  71 #define MEI_DEV_ID_DNV_IE     0x19E5  /* Denverton IE */
  72
  73 #define MEI_DEV_ID_GLK        0x319A  /* Gemini Lake */
  74
  75 #define MEI_DEV_ID_KBP        0xA2BA  /* Kaby Point */
  76 #define MEI_DEV_ID_KBP_2      0xA2BB  /* Kaby Point 2 */
  77 #define MEI_DEV_ID_KBP_3      0xA2BE  /* Kaby Point 3 (iTouch) */
  78
  79 #define MEI_DEV_ID_CNP_LP     0x9DE0  /* Cannon Point LP */
  80 #define MEI_DEV_ID_CNP_LP_3   0x9DE4  /* Cannon Point LP 3 (iTouch) */
  81 #define MEI_DEV_ID_CNP_H      0xA360  /* Cannon Point H */
  82 #define MEI_DEV_ID_CNP_H_3    0xA364  /* Cannon Point H 3 (iTouch) */
  83
  84 #define MEI_DEV_ID_CMP_LP     0x02e0  /* Comet Point LP */
  85 #define MEI_DEV_ID_CMP_LP_3   0x02e4  /* Comet Point LP 3 (iTouch) */
  86
  87 #define MEI_DEV_ID_CMP_V      0xA3BA  /* Comet Point Lake V */
  88
  89 #define MEI_DEV_ID_CMP_H      0x06e0  /* Comet Lake H */
  90 #define MEI_DEV_ID_CMP_H_3    0x06e4  /* Comet Lake H 3 (iTouch) */
  91
  92 #define MEI_DEV_ID_CDF        0x18D3  /* Cedar Fork */
  93
  94 #define MEI_DEV_ID_ICP_LP     0x34E0  /* Ice Lake Point LP */
  95
  96 #define MEI_DEV_ID_JSP_N      0x4DE0  /* Jasper Lake Point N */
  97
  98 #define MEI_DEV_ID_TGP_LP     0xA0E0  /* Tiger Lake Point LP */
  99 #define MEI_DEV_ID_TGP_H      0x43E0  /* Tiger Lake Point H */
 100
 101 #define MEI_DEV_ID_MCC        0x4B70  /* Mule Creek Canyon (EHL) */
 102 #define MEI_DEV_ID_MCC_4      0x4B75  /* Mule Creek Canyon 4 (EHL) */
 103
 104 /*
 105  * MEI HW Section
 106  */
 107
 108 /* Host Firmware Status Registers in PCI Config Space */
 109 #define PCI_CFG_HFS_1         0x40
 110 #  define PCI_CFG_HFS_1_D0I3_MSK     0x80000000
 111 #  define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */
 112 #  define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */
 113 #define PCI_CFG_HFS_2         0x48
 114 #define PCI_CFG_HFS_3         0x60
 115 #  define PCI_CFG_HFS_3_FW_SKU_MSK   0x00000070
 116 #  define PCI_CFG_HFS_3_FW_SKU_SPS   0x00000060
 117 #define PCI_CFG_HFS_4         0x64
 118 #define PCI_CFG_HFS_5         0x68
 119 #define PCI_CFG_HFS_6         0x6C
 120
 121 /* MEI registers */
 122 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
 123 #define H_CB_WW    0
 124 /* H_CSR - Host Control Status register */
 125 #define H_CSR      4
 126 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
 127 #define ME_CB_RW   8
 128 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
 129 #define ME_CSR_HA  0xC
 130 /* H_HGC_CSR - PGI register */
 131 #define H_HPG_CSR  0x10
 132 /* H_D0I3C - D0I3 Control  */
 133 #define H_D0I3C    0x800
 134
 135 /* register bits of H_CSR (Host Control Status register) */
 136 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
 137 #define H_CBD             0xFF000000
 138 /* Host Circular Buffer Write Pointer */
 139 #define H_CBWP            0x00FF0000
 140 /* Host Circular Buffer Read Pointer */
 141 #define H_CBRP            0x0000FF00
 142 /* Host Reset */
 143 #define H_RST             0x00000010
 144 /* Host Ready */
 145 #define H_RDY             0x00000008
 146 /* Host Interrupt Generate */
 147 #define H_IG              0x00000004
 148 /* Host Interrupt Status */
 149 #define H_IS              0x00000002
 150 /* Host Interrupt Enable */
 151 #define H_IE              0x00000001
 152 /* Host D0I3 Interrupt Enable */
 153 #define H_D0I3C_IE        0x00000020
 154 /* Host D0I3 Interrupt Status */
 155 #define H_D0I3C_IS        0x00000040
 156
 157 /* H_CSR masks */
 158 #define H_CSR_IE_MASK     (H_IE | H_D0I3C_IE)
 159 #define H_CSR_IS_MASK     (H_IS | H_D0I3C_IS)
 160
 161 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
 162 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
 163 access to ME_CBD */
 164 #define ME_CBD_HRA        0xFF000000
 165 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
 166 #define ME_CBWP_HRA       0x00FF0000
 167 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
 168 #define ME_CBRP_HRA       0x0000FF00
 169 /* ME Power Gate Isolation Capability HRA  - host ready only access */
 170 #define ME_PGIC_HRA       0x00000040
 171 /* ME Reset HRA - host read only access to ME_RST */
 172 #define ME_RST_HRA        0x00000010
 173 /* ME Ready HRA - host read only access to ME_RDY */
 174 #define ME_RDY_HRA        0x00000008
 175 /* ME Interrupt Generate HRA - host read only access to ME_IG */
 176 #define ME_IG_HRA         0x00000004
 177 /* ME Interrupt Status HRA - host read only access to ME_IS */
 178 #define ME_IS_HRA         0x00000002
 179 /* ME Interrupt Enable HRA - host read only access to ME_IE */
 180 #define ME_IE_HRA         0x00000001
 181 /* TRC control shadow register */
 182 #define ME_TRC            0x00000030
 183
 184 /* H_HPG_CSR register bits */
 185 #define H_HPG_CSR_PGIHEXR 0x00000001
 186 #define H_HPG_CSR_PGI     0x00000002
 187
 188 /* H_D0I3C register bits */
 189 #define H_D0I3C_CIP      0x00000001
 190 #define H_D0I3C_IR       0x00000002
 191 #define H_D0I3C_I3       0x00000004
 192 #define H_D0I3C_RR       0x00000008
 193
 194 #endif /* _MEI_HW_MEI_REGS_H_ */