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WIP FPC-III support
[linux/fpc-iii.git] / drivers / mtd / nand / raw / marvell_nand.c
blob42d4881d598df5f040c1d7ede810272c7cf70285
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Marvell NAND flash controller driver
4 *
5 * Copyright (C) 2017 Marvell
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
7 *
8 *
9 * This NAND controller driver handles two versions of the hardware,
10 * one is called NFCv1 and is available on PXA SoCs and the other is
11 * called NFCv2 and is available on Armada SoCs.
12 *
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
15 * is not used with NFCv2.
16 *
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
18 * is a brief description.
19 *
20 * When using Hamming, the data is split in 512B chunks (either 1, 2
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
22 * beginning of the OOB area and eventually the remaining free OOB
23 * bytes (also called "spare" bytes in the driver). This engine
24 * corrects up to 1 bit per chunk and detects reliably an error if
25 * there are at most 2 bitflips. Here is the page layout used by the
26 * controller when Hamming is chosen:
27 *
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
31 *
32 * When using the BCH engine, there are N identical (data + free OOB +
33 * ECC) sections and potentially an extra one to deal with
34 * configurations where the chosen (data + free OOB + ECC) sizes do
35 * not align with the page (data + OOB) size. ECC bytes are always
36 * 30B per ECC chunk. Here is the page layout used by the controller
37 * when BCH is chosen:
38 *
39 * +-----------------------------------------
40 * | Data 1 | Free OOB bytes 1 | ECC 1 | ...
41 * +-----------------------------------------
42 *
43 * -------------------------------------------
44 * ... | Data N | Free OOB bytes N | ECC N |
45 * -------------------------------------------
46 *
47 * --------------------------------------------+
48 * Last Data | Last Free OOB bytes | Last ECC |
49 * --------------------------------------------+
50 *
51 * In both cases, the layout seen by the user is always: all data
52 * first, then all free OOB bytes and finally all ECC bytes. With BCH,
53 * ECC bytes are 30B long and are padded with 0xFF to align on 32
54 * bytes.
55 *
56 * The controller has certain limitations that are handled by the
57 * driver:
58 * - It can only read 2k at a time. To overcome this limitation, the
59 * driver issues data cycles on the bus, without issuing new
60 * CMD + ADDR cycles. The Marvell term is "naked" operations.
61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
62 * bits. What can be tuned is the ECC block size as long as it
63 * stays between 512B and 2kiB. It's usually chosen based on the
64 * chip ECC requirements. For instance, using 2kiB ECC chunks
65 * provides 4b/512B correctability.
66 * - The controller will always treat data bytes, free OOB bytes
67 * and ECC bytes in that order, no matter what the real layout is
68 * (which is usually all data then all OOB bytes). The
69 * marvell_nfc_layouts array below contains the currently
70 * supported layouts.
71 * - Because of these weird layouts, the Bad Block Markers can be
72 * located in data section. In this case, the NAND_BBT_NO_OOB_BBM
73 * option must be set to prevent scanning/writing bad block
74 * markers.
75 */
76
77 #include <linux/module.h>
78 #include <linux/clk.h>
79 #include <linux/mtd/rawnand.h>
80 #include <linux/of_platform.h>
81 #include <linux/iopoll.h>
82 #include <linux/interrupt.h>
83 #include <linux/slab.h>
84 #include <linux/mfd/syscon.h>
85 #include <linux/regmap.h>
86 #include <asm/unaligned.h>
87
88 #include <linux/dmaengine.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/dma/pxa-dma.h>
91 #include <linux/platform_data/mtd-nand-pxa3xx.h>
92
93 /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */
94 #define FIFO_DEPTH 8
95 #define FIFO_REP(x) (x / sizeof(u32))
96 #define BCH_SEQ_READS (32 / FIFO_DEPTH)
97 /* NFC does not support transfers of larger chunks at a time */
98 #define MAX_CHUNK_SIZE 2112
99 /* NFCv1 cannot read more that 7 bytes of ID */
100 #define NFCV1_READID_LEN 7
101 /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */
102 #define POLL_PERIOD 0
103 #define POLL_TIMEOUT 100000
104 /* Interrupt maximum wait period in ms */
105 #define IRQ_TIMEOUT 1000
106 /* Latency in clock cycles between SoC pins and NFC logic */
107 #define MIN_RD_DEL_CNT 3
108 /* Maximum number of contiguous address cycles */
109 #define MAX_ADDRESS_CYC_NFCV1 5
110 #define MAX_ADDRESS_CYC_NFCV2 7
111 /* System control registers/bits to enable the NAND controller on some SoCs */
112 #define GENCONF_SOC_DEVICE_MUX 0x208
113 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
114 #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20)
115 #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21)
116 #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25)
117 #define GENCONF_CLK_GATING_CTRL 0x220
118 #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2)
119 #define GENCONF_ND_CLK_CTRL 0x700
120 #define GENCONF_ND_CLK_CTRL_EN BIT(0)
121
122 /* NAND controller data flash control register */
123 #define NDCR 0x00
124 #define NDCR_ALL_INT GENMASK(11, 0)
125 #define NDCR_CS1_CMDDM BIT(7)
126 #define NDCR_CS0_CMDDM BIT(8)
127 #define NDCR_RDYM BIT(11)
128 #define NDCR_ND_ARB_EN BIT(12)
129 #define NDCR_RA_START BIT(15)
130 #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16)
131 #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0)
132 #define NDCR_DWIDTH_M BIT(26)
133 #define NDCR_DWIDTH_C BIT(27)
134 #define NDCR_ND_RUN BIT(28)
135 #define NDCR_DMA_EN BIT(29)
136 #define NDCR_ECC_EN BIT(30)
137 #define NDCR_SPARE_EN BIT(31)
138 #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \
139 NDCR_DWIDTH_M | NDCR_DWIDTH_C))
140
141 /* NAND interface timing parameter 0 register */
142 #define NDTR0 0x04
143 #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0)
144 #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3)
145 #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3)
146 #define NDTR0_SEL_NRE_EDGE BIT(7)
147 #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8)
148 #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11)
149 #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16)
150 #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19)
151 #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22)
152 #define NDTR0_SELCNTR BIT(26)
153 #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27)
154
155 /* NAND interface timing parameter 1 register */
156 #define NDTR1 0x0C
157 #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0)
158 #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4)
159 #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8)
160 #define NDTR1_PRESCALE BIT(14)
161 #define NDTR1_WAIT_MODE BIT(15)
162 #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16)
163
164 /* NAND controller status register */
165 #define NDSR 0x14
166 #define NDSR_WRCMDREQ BIT(0)
167 #define NDSR_RDDREQ BIT(1)
168 #define NDSR_WRDREQ BIT(2)
169 #define NDSR_CORERR BIT(3)
170 #define NDSR_UNCERR BIT(4)
171 #define NDSR_CMDD(cs) BIT(8 - cs)
172 #define NDSR_RDY(rb) BIT(11 + rb)
173 #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F)
174
175 /* NAND ECC control register */
176 #define NDECCCTRL 0x28
177 #define NDECCCTRL_BCH_EN BIT(0)
178
179 /* NAND controller data buffer register */
180 #define NDDB 0x40
181
182 /* NAND controller command buffer 0 register */
183 #define NDCB0 0x48
184 #define NDCB0_CMD1(x) ((x & 0xFF) << 0)
185 #define NDCB0_CMD2(x) ((x & 0xFF) << 8)
186 #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16)
187 #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7)
188 #define NDCB0_DBC BIT(19)
189 #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21)
190 #define NDCB0_CSEL BIT(24)
191 #define NDCB0_RDY_BYP BIT(27)
192 #define NDCB0_LEN_OVRD BIT(28)
193 #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29)
194
195 /* NAND controller command buffer 1 register */
196 #define NDCB1 0x4C
197 #define NDCB1_COLS(x) ((x & 0xFFFF) << 0)
198 #define NDCB1_ADDRS_PAGE(x) (x << 16)
199
200 /* NAND controller command buffer 2 register */
201 #define NDCB2 0x50
202 #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0)
203 #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0)
204
205 /* NAND controller command buffer 3 register */
206 #define NDCB3 0x54
207 #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16)
208 #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24)
209
210 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
211 #define TYPE_READ 0
212 #define TYPE_WRITE 1
213 #define TYPE_ERASE 2
214 #define TYPE_READ_ID 3
215 #define TYPE_STATUS 4
216 #define TYPE_RESET 5
217 #define TYPE_NAKED_CMD 6
218 #define TYPE_NAKED_ADDR 7
219 #define TYPE_MASK 7
220 #define XTYPE_MONOLITHIC_RW 0
221 #define XTYPE_LAST_NAKED_RW 1
222 #define XTYPE_FINAL_COMMAND 3
223 #define XTYPE_READ 4
224 #define XTYPE_WRITE_DISPATCH 4
225 #define XTYPE_NAKED_RW 5
226 #define XTYPE_COMMAND_DISPATCH 6
227 #define XTYPE_MASK 7
228
229 /**
230 * struct marvell_hw_ecc_layout - layout of Marvell ECC
231 *
232 * Marvell ECC engine works differently than the others, in order to limit the
233 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
234 * per subpage, and depending on a the desired strength needed by the NAND chip,
235 * a particular layout mixing data/spare/ecc is defined, with a possible last
236 * chunk smaller that the others.
237 *
238 * @writesize: Full page size on which the layout applies
239 * @chunk: Desired ECC chunk size on which the layout applies
240 * @strength: Desired ECC strength (per chunk size bytes) on which the
241 * layout applies
242 * @nchunks: Total number of chunks
243 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
244 * repetitions of the pattern:
245 * (data_bytes + spare_bytes + ecc_bytes).
246 * @data_bytes: Number of data bytes per chunk
247 * @spare_bytes: Number of spare bytes per chunk
248 * @ecc_bytes: Number of ecc bytes per chunk
249 * @last_data_bytes: Number of data bytes in the last chunk
250 * @last_spare_bytes: Number of spare bytes in the last chunk
251 * @last_ecc_bytes: Number of ecc bytes in the last chunk
252 */
253 struct marvell_hw_ecc_layout {
254 /* Constraints */
255 int writesize;
256 int chunk;
257 int strength;
258 /* Corresponding layout */
259 int nchunks;
260 int full_chunk_cnt;
261 int data_bytes;
262 int spare_bytes;
263 int ecc_bytes;
264 int last_data_bytes;
265 int last_spare_bytes;
266 int last_ecc_bytes;
267 };
268
269 #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \
270 { \
271 .writesize = ws, \
272 .chunk = dc, \
273 .strength = ds, \
274 .nchunks = nc, \
275 .full_chunk_cnt = fcc, \
276 .data_bytes = db, \
277 .spare_bytes = sb, \
278 .ecc_bytes = eb, \
279 .last_data_bytes = ldb, \
280 .last_spare_bytes = lsb, \
281 .last_ecc_bytes = leb, \
282 }
283
284 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
285 static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
286 MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0),
287 MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0),
288 MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0),
289 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30),
290 MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0),
291 MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30),
292 MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0),
293 MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30),
294 };
295
296 /**
297 * struct marvell_nand_chip_sel - CS line description
298 *
299 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
300 * is made by a field in NDCB0 register, and in another field in NDCB2 register.
301 * The datasheet describes the logic with an error: ADDR5 field is once
302 * declared at the beginning of NDCB2, and another time at its end. Because the
303 * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical
304 * to use the last bit of this field instead of the first ones.
305 *
306 * @cs: Wanted CE lane.
307 * @ndcb0_csel: Value of the NDCB0 register with or without the flag
308 * selecting the wanted CE lane. This is set once when
309 * the Device Tree is probed.
310 * @rb: Ready/Busy pin for the flash chip
311 */
312 struct marvell_nand_chip_sel {
313 unsigned int cs;
314 u32 ndcb0_csel;
315 unsigned int rb;
316 };
317
318 /**
319 * struct marvell_nand_chip - stores NAND chip device related information
320 *
321 * @chip: Base NAND chip structure
322 * @node: Used to store NAND chips into a list
323 * @layout: NAND layout when using hardware ECC
324 * @ndcr: Controller register value for this NAND chip
325 * @ndtr0: Timing registers 0 value for this NAND chip
326 * @ndtr1: Timing registers 1 value for this NAND chip
327 * @addr_cyc: Amount of cycles needed to pass column address
328 * @selected_die: Current active CS
329 * @nsels: Number of CS lines required by the NAND chip
330 * @sels: Array of CS lines descriptions
331 */
332 struct marvell_nand_chip {
333 struct nand_chip chip;
334 struct list_head node;
335 const struct marvell_hw_ecc_layout *layout;
336 u32 ndcr;
337 u32 ndtr0;
338 u32 ndtr1;
339 int addr_cyc;
340 int selected_die;
341 unsigned int nsels;
342 struct marvell_nand_chip_sel sels[];
343 };
344
345 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
346 {
347 return container_of(chip, struct marvell_nand_chip, chip);
348 }
349
350 static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
351 *nand)
352 {
353 return &nand->sels[nand->selected_die];
354 }
355
356 /**
357 * struct marvell_nfc_caps - NAND controller capabilities for distinction
358 * between compatible strings
359 *
360 * @max_cs_nb: Number of Chip Select lines available
361 * @max_rb_nb: Number of Ready/Busy lines available
362 * @need_system_controller: Indicates if the SoC needs to have access to the
363 * system controller (ie. to enable the NAND controller)
364 * @legacy_of_bindings: Indicates if DT parsing must be done using the old
365 * fashion way
366 * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie.
367 * BCH error detection and correction algorithm,
368 * NDCB3 register has been added
369 * @use_dma: Use dma for data transfers
370 */
371 struct marvell_nfc_caps {
372 unsigned int max_cs_nb;
373 unsigned int max_rb_nb;
374 bool need_system_controller;
375 bool legacy_of_bindings;
376 bool is_nfcv2;
377 bool use_dma;
378 };
379
380 /**
381 * struct marvell_nfc - stores Marvell NAND controller information
382 *
383 * @controller: Base controller structure
384 * @dev: Parent device (used to print error messages)
385 * @regs: NAND controller registers
386 * @core_clk: Core clock
387 * @reg_clk: Registers clock
388 * @complete: Completion object to wait for NAND controller events
389 * @assigned_cs: Bitmask describing already assigned CS lines
390 * @chips: List containing all the NAND chips attached to
391 * this NAND controller
392 * @selected_chip: Currently selected target chip
393 * @caps: NAND controller capabilities for each compatible string
394 * @use_dma: Whetner DMA is used
395 * @dma_chan: DMA channel (NFCv1 only)
396 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
397 */
398 struct marvell_nfc {
399 struct nand_controller controller;
400 struct device *dev;
401 void __iomem *regs;
402 struct clk *core_clk;
403 struct clk *reg_clk;
404 struct completion complete;
405 unsigned long assigned_cs;
406 struct list_head chips;
407 struct nand_chip *selected_chip;
408 const struct marvell_nfc_caps *caps;
409
410 /* DMA (NFCv1 only) */
411 bool use_dma;
412 struct dma_chan *dma_chan;
413 u8 *dma_buf;
414 };
415
416 static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl)
417 {
418 return container_of(ctrl, struct marvell_nfc, controller);
419 }
420
421 /**
422 * struct marvell_nfc_timings - NAND controller timings expressed in NAND
423 * Controller clock cycles
424 *
425 * @tRP: ND_nRE pulse width
426 * @tRH: ND_nRE high duration
427 * @tWP: ND_nWE pulse time
428 * @tWH: ND_nWE high duration
429 * @tCS: Enable signal setup time
430 * @tCH: Enable signal hold time
431 * @tADL: Address to write data delay
432 * @tAR: ND_ALE low to ND_nRE low delay
433 * @tWHR: ND_nWE high to ND_nRE low for status read
434 * @tRHW: ND_nRE high duration, read to write delay
435 * @tR: ND_nWE high to ND_nRE low for read
436 */
437 struct marvell_nfc_timings {
438 /* NDTR0 fields */
439 unsigned int tRP;
440 unsigned int tRH;
441 unsigned int tWP;
442 unsigned int tWH;
443 unsigned int tCS;
444 unsigned int tCH;
445 unsigned int tADL;
446 /* NDTR1 fields */
447 unsigned int tAR;
448 unsigned int tWHR;
449 unsigned int tRHW;
450 unsigned int tR;
451 };
452
453 /**
454 * Derives a duration in numbers of clock cycles.
455 *
456 * @ps: Duration in pico-seconds
457 * @period_ns: Clock period in nano-seconds
458 *
459 * Convert the duration in nano-seconds, then divide by the period and
460 * return the number of clock periods.
461 */
462 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns))
463 #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \
464 period_ns))
465
466 /**
467 * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
468 * subop subset of instructions.
469 *
470 * @ndcb: Array of values written to NDCBx registers
471 * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle
472 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
473 * @rdy_delay_ns: Optional delay after waiting for the RB pin
474 * @data_delay_ns: Optional delay after the data xfer
475 * @data_instr_idx: Index of the data instruction in the subop
476 * @data_instr: Pointer to the data instruction in the subop
477 */
478 struct marvell_nfc_op {
479 u32 ndcb[4];
480 unsigned int cle_ale_delay_ns;
481 unsigned int rdy_timeout_ms;
482 unsigned int rdy_delay_ns;
483 unsigned int data_delay_ns;
484 unsigned int data_instr_idx;
485 const struct nand_op_instr *data_instr;
486 };
487
488 /*
489 * Internal helper to conditionnally apply a delay (from the above structure,
490 * most of the time).
491 */
492 static void cond_delay(unsigned int ns)
493 {
494 if (!ns)
495 return;
496
497 if (ns < 10000)
498 ndelay(ns);
499 else
500 udelay(DIV_ROUND_UP(ns, 1000));
501 }
502
503 /*
504 * The controller has many flags that could generate interrupts, most of them
505 * are disabled and polling is used. For the very slow signals, using interrupts
506 * may relax the CPU charge.
507 */
508 static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask)
509 {
510 u32 reg;
511
512 /* Writing 1 disables the interrupt */
513 reg = readl_relaxed(nfc->regs + NDCR);
514 writel_relaxed(reg | int_mask, nfc->regs + NDCR);
515 }
516
517 static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask)
518 {
519 u32 reg;
520
521 /* Writing 0 enables the interrupt */
522 reg = readl_relaxed(nfc->regs + NDCR);
523 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
524 }
525
526 static u32 marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask)
527 {
528 u32 reg;
529
530 reg = readl_relaxed(nfc->regs + NDSR);
531 writel_relaxed(int_mask, nfc->regs + NDSR);
532
533 return reg & int_mask;
534 }
535
536 static void marvell_nfc_force_byte_access(struct nand_chip *chip,
537 bool force_8bit)
538 {
539 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
540 u32 ndcr;
541
542 /*
543 * Callers of this function do not verify if the NAND is using a 16-bit
544 * an 8-bit bus for normal operations, so we need to take care of that
545 * here by leaving the configuration unchanged if the NAND does not have
546 * the NAND_BUSWIDTH_16 flag set.
547 */
548 if (!(chip->options & NAND_BUSWIDTH_16))
549 return;
550
551 ndcr = readl_relaxed(nfc->regs + NDCR);
552
553 if (force_8bit)
554 ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C);
555 else
556 ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
557
558 writel_relaxed(ndcr, nfc->regs + NDCR);
559 }
560
561 static int marvell_nfc_wait_ndrun(struct nand_chip *chip)
562 {
563 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
564 u32 val;
565 int ret;
566
567 /*
568 * The command is being processed, wait for the ND_RUN bit to be
569 * cleared by the NFC. If not, we must clear it by hand.
570 */
571 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
572 (val & NDCR_ND_RUN) == 0,
573 POLL_PERIOD, POLL_TIMEOUT);
574 if (ret) {
575 dev_err(nfc->dev, "Timeout on NAND controller run mode\n");
576 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
577 nfc->regs + NDCR);
578 return ret;
579 }
580
581 return 0;
582 }
583
584 /*
585 * Any time a command has to be sent to the controller, the following sequence
586 * has to be followed:
587 * - call marvell_nfc_prepare_cmd()
588 * -> activate the ND_RUN bit that will kind of 'start a job'
589 * -> wait the signal indicating the NFC is waiting for a command
590 * - send the command (cmd and address cycles)
591 * - enventually send or receive the data
592 * - call marvell_nfc_end_cmd() with the corresponding flag
593 * -> wait the flag to be triggered or cancel the job with a timeout
594 *
595 * The following helpers are here to factorize the code a bit so that
596 * specialized functions responsible for executing the actual NAND
597 * operations do not have to replicate the same code blocks.
598 */
599 static int marvell_nfc_prepare_cmd(struct nand_chip *chip)
600 {
601 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
602 u32 ndcr, val;
603 int ret;
604
605 /* Poll ND_RUN and clear NDSR before issuing any command */
606 ret = marvell_nfc_wait_ndrun(chip);
607 if (ret) {
608 dev_err(nfc->dev, "Last operation did not succeed\n");
609 return ret;
610 }
611
612 ndcr = readl_relaxed(nfc->regs + NDCR);
613 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR);
614
615 /* Assert ND_RUN bit and wait the NFC to be ready */
616 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
617 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
618 val & NDSR_WRCMDREQ,
619 POLL_PERIOD, POLL_TIMEOUT);
620 if (ret) {
621 dev_err(nfc->dev, "Timeout on WRCMDRE\n");
622 return -ETIMEDOUT;
623 }
624
625 /* Command may be written, clear WRCMDREQ status bit */
626 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR);
627
628 return 0;
629 }
630
631 static void marvell_nfc_send_cmd(struct nand_chip *chip,
632 struct marvell_nfc_op *nfc_op)
633 {
634 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
635 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
636
637 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n"
638 "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n",
639 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
640 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]);
641
642 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0],
643 nfc->regs + NDCB0);
644 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0);
645 writel(nfc_op->ndcb[2], nfc->regs + NDCB0);
646
647 /*
648 * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7
649 * fields are used (only available on NFCv2).
650 */
651 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD ||
652 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) {
653 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2))
654 writel(nfc_op->ndcb[3], nfc->regs + NDCB0);
655 }
656 }
657
658 static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag,
659 const char *label)
660 {
661 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
662 u32 val;
663 int ret;
664
665 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
666 val & flag,
667 POLL_PERIOD, POLL_TIMEOUT);
668
669 if (ret) {
670 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n",
671 label, val);
672 if (nfc->dma_chan)
673 dmaengine_terminate_all(nfc->dma_chan);
674 return ret;
675 }
676
677 /*
678 * DMA function uses this helper to poll on CMDD bits without wanting
679 * them to be cleared.
680 */
681 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
682 return 0;
683
684 writel_relaxed(flag, nfc->regs + NDSR);
685
686 return 0;
687 }
688
689 static int marvell_nfc_wait_cmdd(struct nand_chip *chip)
690 {
691 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
692 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel);
693
694 return marvell_nfc_end_cmd(chip, cs_flag, "CMDD");
695 }
696
697 static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask,
698 u32 expected_val, unsigned long timeout_ms)
699 {
700 unsigned long limit;
701 u32 st;
702
703 limit = jiffies + msecs_to_jiffies(timeout_ms);
704 do {
705 st = readl_relaxed(nfc->regs + NDSR);
706 if (st & NDSR_RDY(1))
707 st |= NDSR_RDY(0);
708
709 if ((st & mask) == expected_val)
710 return 0;
711
712 cpu_relax();
713 } while (time_after(limit, jiffies));
714
715 return -ETIMEDOUT;
716 }
717
718 static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms)
719 {
720 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
721 struct mtd_info *mtd = nand_to_mtd(chip);
722 u32 pending;
723 int ret;
724
725 /* Timeout is expressed in ms */
726 if (!timeout_ms)
727 timeout_ms = IRQ_TIMEOUT;
728
729 if (mtd->oops_panic_write) {
730 ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0),
731 NDSR_RDY(0),
732 timeout_ms);
733 } else {
734 init_completion(&nfc->complete);
735
736 marvell_nfc_enable_int(nfc, NDCR_RDYM);
737 ret = wait_for_completion_timeout(&nfc->complete,
738 msecs_to_jiffies(timeout_ms));
739 marvell_nfc_disable_int(nfc, NDCR_RDYM);
740 }
741 pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1));
742
743 /*
744 * In case the interrupt was not served in the required time frame,
745 * check if the ISR was not served or if something went actually wrong.
746 */
747 if (!ret && !pending) {
748 dev_err(nfc->dev, "Timeout waiting for RB signal\n");
749 return -ETIMEDOUT;
750 }
751
752 return 0;
753 }
754
755 static void marvell_nfc_select_target(struct nand_chip *chip,
756 unsigned int die_nr)
757 {
758 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
759 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
760 u32 ndcr_generic;
761
762 /*
763 * Reset the NDCR register to a clean state for this particular chip,
764 * also clear ND_RUN bit.
765 */
766 ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
767 NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN;
768 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
769
770 /* Also reset the interrupt status register */
771 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
772
773 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
774 return;
775
776 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
777 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
778
779 nfc->selected_chip = chip;
780 marvell_nand->selected_die = die_nr;
781 }
782
783 static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
784 {
785 struct marvell_nfc *nfc = dev_id;
786 u32 st = readl_relaxed(nfc->regs + NDSR);
787 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
788
789 /*
790 * RDY interrupt mask is one bit in NDCR while there are two status
791 * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]).
792 */
793 if (st & NDSR_RDY(1))
794 st |= NDSR_RDY(0);
795
796 if (!(st & ien))
797 return IRQ_NONE;
798
799 marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
800
801 if (st & (NDSR_RDY(0) | NDSR_RDY(1)))
802 complete(&nfc->complete);
803
804 return IRQ_HANDLED;
805 }
806
807 /* HW ECC related functions */
808 static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
809 {
810 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
811 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
812
813 if (!(ndcr & NDCR_ECC_EN)) {
814 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
815
816 /*
817 * When enabling BCH, set threshold to 0 to always know the
818 * number of corrected bitflips.
819 */
820 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
821 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
822 }
823 }
824
825 static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
826 {
827 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
828 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
829
830 if (ndcr & NDCR_ECC_EN) {
831 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
832 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
833 writel_relaxed(0, nfc->regs + NDECCCTRL);
834 }
835 }
836
837 /* DMA related helpers */
838 static void marvell_nfc_enable_dma(struct marvell_nfc *nfc)
839 {
840 u32 reg;
841
842 reg = readl_relaxed(nfc->regs + NDCR);
843 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
844 }
845
846 static void marvell_nfc_disable_dma(struct marvell_nfc *nfc)
847 {
848 u32 reg;
849
850 reg = readl_relaxed(nfc->regs + NDCR);
851 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
852 }
853
854 /* Read/write PIO/DMA accessors */
855 static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc,
856 enum dma_data_direction direction,
857 unsigned int len)
858 {
859 unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE);
860 struct dma_async_tx_descriptor *tx;
861 struct scatterlist sg;
862 dma_cookie_t cookie;
863 int ret;
864
865 marvell_nfc_enable_dma(nfc);
866 /* Prepare the DMA transfer */
867 sg_init_one(&sg, nfc->dma_buf, dma_len);
868 dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
869 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1,
870 direction == DMA_FROM_DEVICE ?
871 DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
872 DMA_PREP_INTERRUPT);
873 if (!tx) {
874 dev_err(nfc->dev, "Could not prepare DMA S/G list\n");
875 return -ENXIO;
876 }
877
878 /* Do the task and wait for it to finish */
879 cookie = dmaengine_submit(tx);
880 ret = dma_submit_error(cookie);
881 if (ret)
882 return -EIO;
883
884 dma_async_issue_pending(nfc->dma_chan);
885 ret = marvell_nfc_wait_cmdd(nfc->selected_chip);
886 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
887 marvell_nfc_disable_dma(nfc);
888 if (ret) {
889 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n",
890 dmaengine_tx_status(nfc->dma_chan, cookie, NULL));
891 dmaengine_terminate_all(nfc->dma_chan);
892 return -ETIMEDOUT;
893 }
894
895 return 0;
896 }
897
898 static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in,
899 unsigned int len)
900 {
901 unsigned int last_len = len % FIFO_DEPTH;
902 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
903 int i;
904
905 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
906 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH));
907
908 if (last_len) {
909 u8 tmp_buf[FIFO_DEPTH];
910
911 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
912 memcpy(in + last_full_offset, tmp_buf, last_len);
913 }
914
915 return 0;
916 }
917
918 static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out,
919 unsigned int len)
920 {
921 unsigned int last_len = len % FIFO_DEPTH;
922 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
923 int i;
924
925 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
926 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH));
927
928 if (last_len) {
929 u8 tmp_buf[FIFO_DEPTH];
930
931 memcpy(tmp_buf, out + last_full_offset, last_len);
932 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
933 }
934
935 return 0;
936 }
937
938 static void marvell_nfc_check_empty_chunk(struct nand_chip *chip,
939 u8 *data, int data_len,
940 u8 *spare, int spare_len,
941 u8 *ecc, int ecc_len,
942 unsigned int *max_bitflips)
943 {
944 struct mtd_info *mtd = nand_to_mtd(chip);
945 int bf;
946
947 /*
948 * Blank pages (all 0xFF) that have not been written may be recognized
949 * as bad if bitflips occur, so whenever an uncorrectable error occurs,
950 * check if the entire page (with ECC bytes) is actually blank or not.
951 */
952 if (!data)
953 data_len = 0;
954 if (!spare)
955 spare_len = 0;
956 if (!ecc)
957 ecc_len = 0;
958
959 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
960 spare, spare_len, chip->ecc.strength);
961 if (bf < 0) {
962 mtd->ecc_stats.failed++;
963 return;
964 }
965
966 /* Update the stats and max_bitflips */
967 mtd->ecc_stats.corrected += bf;
968 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
969 }
970
971 /*
972 * Check if a chunk is correct or not according to the hardware ECC engine.
973 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
974 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
975 * value indicating that a check on the emptyness of the subpage must be
976 * performed before actually declaring the subpage as "corrupted".
977 */
978 static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip,
979 unsigned int *max_bitflips)
980 {
981 struct mtd_info *mtd = nand_to_mtd(chip);
982 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
983 int bf = 0;
984 u32 ndsr;
985
986 ndsr = readl_relaxed(nfc->regs + NDSR);
987
988 /* Check uncorrectable error flag */
989 if (ndsr & NDSR_UNCERR) {
990 writel_relaxed(ndsr, nfc->regs + NDSR);
991
992 /*
993 * Do not increment ->ecc_stats.failed now, instead, return a
994 * non-zero value to indicate that this chunk was apparently
995 * bad, and it should be check to see if it empty or not. If
996 * the chunk (with ECC bytes) is not declared empty, the calling
997 * function must increment the failure count.
998 */
999 return -EBADMSG;
1000 }
1001
1002 /* Check correctable error flag */
1003 if (ndsr & NDSR_CORERR) {
1004 writel_relaxed(ndsr, nfc->regs + NDSR);
1005
1006 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
1007 bf = NDSR_ERRCNT(ndsr);
1008 else
1009 bf = 1;
1010 }
1011
1012 /* Update the stats and max_bitflips */
1013 mtd->ecc_stats.corrected += bf;
1014 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
1015
1016 return 0;
1017 }
1018
1019 /* Hamming read helpers */
1020 static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip,
1021 u8 *data_buf, u8 *oob_buf,
1022 bool raw, int page)
1023 {
1024 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1025 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1026 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1027 struct marvell_nfc_op nfc_op = {
1028 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
1029 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1030 NDCB0_DBC |
1031 NDCB0_CMD1(NAND_CMD_READ0) |
1032 NDCB0_CMD2(NAND_CMD_READSTART),
1033 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1034 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1035 };
1036 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
1037 int ret;
1038
1039 /* NFCv2 needs more information about the operation being executed */
1040 if (nfc->caps->is_nfcv2)
1041 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1042
1043 ret = marvell_nfc_prepare_cmd(chip);
1044 if (ret)
1045 return ret;
1046
1047 marvell_nfc_send_cmd(chip, &nfc_op);
1048 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1049 "RDDREQ while draining FIFO (data/oob)");
1050 if (ret)
1051 return ret;
1052
1053 /*
1054 * Read the page then the OOB area. Unlike what is shown in current
1055 * documentation, spare bytes are protected by the ECC engine, and must
1056 * be at the beginning of the OOB area or running this driver on legacy
1057 * systems will prevent the discovery of the BBM/BBT.
1058 */
1059 if (nfc->use_dma) {
1060 marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE,
1061 lt->data_bytes + oob_bytes);
1062 memcpy(data_buf, nfc->dma_buf, lt->data_bytes);
1063 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes);
1064 } else {
1065 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes);
1066 marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes);
1067 }
1068
1069 ret = marvell_nfc_wait_cmdd(chip);
1070 return ret;
1071 }
1072
1073 static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf,
1074 int oob_required, int page)
1075 {
1076 marvell_nfc_select_target(chip, chip->cur_cs);
1077 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
1078 true, page);
1079 }
1080
1081 static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf,
1082 int oob_required, int page)
1083 {
1084 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1085 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1086 int max_bitflips = 0, ret;
1087 u8 *raw_buf;
1088
1089 marvell_nfc_select_target(chip, chip->cur_cs);
1090 marvell_nfc_enable_hw_ecc(chip);
1091 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
1092 page);
1093 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
1094 marvell_nfc_disable_hw_ecc(chip);
1095
1096 if (!ret)
1097 return max_bitflips;
1098
1099 /*
1100 * When ECC failures are detected, check if the full page has been
1101 * written or not. Ignore the failure if it is actually empty.
1102 */
1103 raw_buf = kmalloc(full_sz, GFP_KERNEL);
1104 if (!raw_buf)
1105 return -ENOMEM;
1106
1107 marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf +
1108 lt->data_bytes, true, page);
1109 marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0,
1110 &max_bitflips);
1111 kfree(raw_buf);
1112
1113 return max_bitflips;
1114 }
1115
1116 /*
1117 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1118 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1119 * also stands for ->read_oob().
1120 */
1121 static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page)
1122 {
1123 u8 *buf = nand_get_data_buf(chip);
1124
1125 marvell_nfc_select_target(chip, chip->cur_cs);
1126 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
1127 true, page);
1128 }
1129
1130 /* Hamming write helpers */
1131 static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
1132 const u8 *data_buf,
1133 const u8 *oob_buf, bool raw,
1134 int page)
1135 {
1136 const struct nand_sdr_timings *sdr =
1137 nand_get_sdr_timings(nand_get_interface_config(chip));
1138 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1139 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1140 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1141 struct marvell_nfc_op nfc_op = {
1142 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) |
1143 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1144 NDCB0_CMD1(NAND_CMD_SEQIN) |
1145 NDCB0_CMD2(NAND_CMD_PAGEPROG) |
1146 NDCB0_DBC,
1147 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1148 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1149 };
1150 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
1151 int ret;
1152
1153 /* NFCv2 needs more information about the operation being executed */
1154 if (nfc->caps->is_nfcv2)
1155 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1156
1157 ret = marvell_nfc_prepare_cmd(chip);
1158 if (ret)
1159 return ret;
1160
1161 marvell_nfc_send_cmd(chip, &nfc_op);
1162 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1163 "WRDREQ while loading FIFO (data)");
1164 if (ret)
1165 return ret;
1166
1167 /* Write the page then the OOB area */
1168 if (nfc->use_dma) {
1169 memcpy(nfc->dma_buf, data_buf, lt->data_bytes);
1170 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes);
1171 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes +
1172 lt->ecc_bytes + lt->spare_bytes);
1173 } else {
1174 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes);
1175 marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes);
1176 }
1177
1178 ret = marvell_nfc_wait_cmdd(chip);
1179 if (ret)
1180 return ret;
1181
1182 ret = marvell_nfc_wait_op(chip,
1183 PSEC_TO_MSEC(sdr->tPROG_max));
1184 return ret;
1185 }
1186
1187 static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip,
1188 const u8 *buf,
1189 int oob_required, int page)
1190 {
1191 marvell_nfc_select_target(chip, chip->cur_cs);
1192 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1193 true, page);
1194 }
1195
1196 static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip,
1197 const u8 *buf,
1198 int oob_required, int page)
1199 {
1200 int ret;
1201
1202 marvell_nfc_select_target(chip, chip->cur_cs);
1203 marvell_nfc_enable_hw_ecc(chip);
1204 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1205 false, page);
1206 marvell_nfc_disable_hw_ecc(chip);
1207
1208 return ret;
1209 }
1210
1211 /*
1212 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1213 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1214 * also stands for ->write_oob().
1215 */
1216 static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip,
1217 int page)
1218 {
1219 struct mtd_info *mtd = nand_to_mtd(chip);
1220 u8 *buf = nand_get_data_buf(chip);
1221
1222 memset(buf, 0xFF, mtd->writesize);
1223
1224 marvell_nfc_select_target(chip, chip->cur_cs);
1225 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1226 true, page);
1227 }
1228
1229 /* BCH read helpers */
1230 static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf,
1231 int oob_required, int page)
1232 {
1233 struct mtd_info *mtd = nand_to_mtd(chip);
1234 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1235 u8 *oob = chip->oob_poi;
1236 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1237 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1238 lt->last_spare_bytes;
1239 int data_len = lt->data_bytes;
1240 int spare_len = lt->spare_bytes;
1241 int ecc_len = lt->ecc_bytes;
1242 int chunk;
1243
1244 marvell_nfc_select_target(chip, chip->cur_cs);
1245
1246 if (oob_required)
1247 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1248
1249 nand_read_page_op(chip, page, 0, NULL, 0);
1250
1251 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1252 /* Update last chunk length */
1253 if (chunk >= lt->full_chunk_cnt) {
1254 data_len = lt->last_data_bytes;
1255 spare_len = lt->last_spare_bytes;
1256 ecc_len = lt->last_ecc_bytes;
1257 }
1258
1259 /* Read data bytes*/
1260 nand_change_read_column_op(chip, chunk * chunk_size,
1261 buf + (lt->data_bytes * chunk),
1262 data_len, false);
1263
1264 /* Read spare bytes */
1265 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk),
1266 spare_len, false, false);
1267
1268 /* Read ECC bytes */
1269 nand_read_data_op(chip, oob + ecc_offset +
1270 (ALIGN(lt->ecc_bytes, 32) * chunk),
1271 ecc_len, false, false);
1272 }
1273
1274 return 0;
1275 }
1276
1277 static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk,
1278 u8 *data, unsigned int data_len,
1279 u8 *spare, unsigned int spare_len,
1280 int page)
1281 {
1282 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1283 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1284 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1285 int i, ret;
1286 struct marvell_nfc_op nfc_op = {
1287 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
1288 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1289 NDCB0_LEN_OVRD,
1290 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1291 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1292 .ndcb[3] = data_len + spare_len,
1293 };
1294
1295 ret = marvell_nfc_prepare_cmd(chip);
1296 if (ret)
1297 return;
1298
1299 if (chunk == 0)
1300 nfc_op.ndcb[0] |= NDCB0_DBC |
1301 NDCB0_CMD1(NAND_CMD_READ0) |
1302 NDCB0_CMD2(NAND_CMD_READSTART);
1303
1304 /*
1305 * Trigger the monolithic read on the first chunk, then naked read on
1306 * intermediate chunks and finally a last naked read on the last chunk.
1307 */
1308 if (chunk == 0)
1309 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1310 else if (chunk < lt->nchunks - 1)
1311 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
1312 else
1313 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1314
1315 marvell_nfc_send_cmd(chip, &nfc_op);
1316
1317 /*
1318 * According to the datasheet, when reading from NDDB
1319 * with BCH enabled, after each 32 bytes reads, we
1320 * have to make sure that the NDSR.RDDREQ bit is set.
1321 *
1322 * Drain the FIFO, 8 32-bit reads at a time, and skip
1323 * the polling on the last read.
1324 *
1325 * Length is a multiple of 32 bytes, hence it is a multiple of 8 too.
1326 */
1327 for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1328 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1329 "RDDREQ while draining FIFO (data)");
1330 marvell_nfc_xfer_data_in_pio(nfc, data,
1331 FIFO_DEPTH * BCH_SEQ_READS);
1332 data += FIFO_DEPTH * BCH_SEQ_READS;
1333 }
1334
1335 for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1336 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1337 "RDDREQ while draining FIFO (OOB)");
1338 marvell_nfc_xfer_data_in_pio(nfc, spare,
1339 FIFO_DEPTH * BCH_SEQ_READS);
1340 spare += FIFO_DEPTH * BCH_SEQ_READS;
1341 }
1342 }
1343
1344 static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip,
1345 u8 *buf, int oob_required,
1346 int page)
1347 {
1348 struct mtd_info *mtd = nand_to_mtd(chip);
1349 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1350 int data_len = lt->data_bytes, spare_len = lt->spare_bytes;
1351 u8 *data = buf, *spare = chip->oob_poi;
1352 int max_bitflips = 0;
1353 u32 failure_mask = 0;
1354 int chunk, ret;
1355
1356 marvell_nfc_select_target(chip, chip->cur_cs);
1357
1358 /*
1359 * With BCH, OOB is not fully used (and thus not read entirely), not
1360 * expected bytes could show up at the end of the OOB buffer if not
1361 * explicitly erased.
1362 */
1363 if (oob_required)
1364 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1365
1366 marvell_nfc_enable_hw_ecc(chip);
1367
1368 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1369 /* Update length for the last chunk */
1370 if (chunk >= lt->full_chunk_cnt) {
1371 data_len = lt->last_data_bytes;
1372 spare_len = lt->last_spare_bytes;
1373 }
1374
1375 /* Read the chunk and detect number of bitflips */
1376 marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len,
1377 spare, spare_len, page);
1378 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
1379 if (ret)
1380 failure_mask |= BIT(chunk);
1381
1382 data += data_len;
1383 spare += spare_len;
1384 }
1385
1386 marvell_nfc_disable_hw_ecc(chip);
1387
1388 if (!failure_mask)
1389 return max_bitflips;
1390
1391 /*
1392 * Please note that dumping the ECC bytes during a normal read with OOB
1393 * area would add a significant overhead as ECC bytes are "consumed" by
1394 * the controller in normal mode and must be re-read in raw mode. To
1395 * avoid dropping the performances, we prefer not to include them. The
1396 * user should re-read the page in raw mode if ECC bytes are required.
1397 */
1398
1399 /*
1400 * In case there is any subpage read error, we usually re-read only ECC
1401 * bytes in raw mode and check if the whole page is empty. In this case,
1402 * it is normal that the ECC check failed and we just ignore the error.
1403 *
1404 * However, it has been empirically observed that for some layouts (e.g
1405 * 2k page, 8b strength per 512B chunk), the controller tries to correct
1406 * bits and may create itself bitflips in the erased area. To overcome
1407 * this strange behavior, the whole page is re-read in raw mode, not
1408 * only the ECC bytes.
1409 */
1410 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1411 int data_off_in_page, spare_off_in_page, ecc_off_in_page;
1412 int data_off, spare_off, ecc_off;
1413 int data_len, spare_len, ecc_len;
1414
1415 /* No failure reported for this chunk, move to the next one */
1416 if (!(failure_mask & BIT(chunk)))
1417 continue;
1418
1419 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes +
1420 lt->ecc_bytes);
1421 spare_off_in_page = data_off_in_page +
1422 (chunk < lt->full_chunk_cnt ? lt->data_bytes :
1423 lt->last_data_bytes);
1424 ecc_off_in_page = spare_off_in_page +
1425 (chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1426 lt->last_spare_bytes);
1427
1428 data_off = chunk * lt->data_bytes;
1429 spare_off = chunk * lt->spare_bytes;
1430 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) +
1431 lt->last_spare_bytes +
1432 (chunk * (lt->ecc_bytes + 2));
1433
1434 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes :
1435 lt->last_data_bytes;
1436 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1437 lt->last_spare_bytes;
1438 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes :
1439 lt->last_ecc_bytes;
1440
1441 /*
1442 * Only re-read the ECC bytes, unless we are using the 2k/8b
1443 * layout which is buggy in the sense that the ECC engine will
1444 * try to correct data bytes anyway, creating bitflips. In this
1445 * case, re-read the entire page.
1446 */
1447 if (lt->writesize == 2048 && lt->strength == 8) {
1448 nand_change_read_column_op(chip, data_off_in_page,
1449 buf + data_off, data_len,
1450 false);
1451 nand_change_read_column_op(chip, spare_off_in_page,
1452 chip->oob_poi + spare_off, spare_len,
1453 false);
1454 }
1455
1456 nand_change_read_column_op(chip, ecc_off_in_page,
1457 chip->oob_poi + ecc_off, ecc_len,
1458 false);
1459
1460 /* Check the entire chunk (data + spare + ecc) for emptyness */
1461 marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len,
1462 chip->oob_poi + spare_off, spare_len,
1463 chip->oob_poi + ecc_off, ecc_len,
1464 &max_bitflips);
1465 }
1466
1467 return max_bitflips;
1468 }
1469
1470 static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
1471 {
1472 u8 *buf = nand_get_data_buf(chip);
1473
1474 return chip->ecc.read_page_raw(chip, buf, true, page);
1475 }
1476
1477 static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page)
1478 {
1479 u8 *buf = nand_get_data_buf(chip);
1480
1481 return chip->ecc.read_page(chip, buf, true, page);
1482 }
1483
1484 /* BCH write helpers */
1485 static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip,
1486 const u8 *buf,
1487 int oob_required, int page)
1488 {
1489 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1490 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1491 int data_len = lt->data_bytes;
1492 int spare_len = lt->spare_bytes;
1493 int ecc_len = lt->ecc_bytes;
1494 int spare_offset = 0;
1495 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1496 lt->last_spare_bytes;
1497 int chunk;
1498
1499 marvell_nfc_select_target(chip, chip->cur_cs);
1500
1501 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1502
1503 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1504 if (chunk >= lt->full_chunk_cnt) {
1505 data_len = lt->last_data_bytes;
1506 spare_len = lt->last_spare_bytes;
1507 ecc_len = lt->last_ecc_bytes;
1508 }
1509
1510 /* Point to the column of the next chunk */
1511 nand_change_write_column_op(chip, chunk * full_chunk_size,
1512 NULL, 0, false);
1513
1514 /* Write the data */
1515 nand_write_data_op(chip, buf + (chunk * lt->data_bytes),
1516 data_len, false);
1517
1518 if (!oob_required)
1519 continue;
1520
1521 /* Write the spare bytes */
1522 if (spare_len)
1523 nand_write_data_op(chip, chip->oob_poi + spare_offset,
1524 spare_len, false);
1525
1526 /* Write the ECC bytes */
1527 if (ecc_len)
1528 nand_write_data_op(chip, chip->oob_poi + ecc_offset,
1529 ecc_len, false);
1530
1531 spare_offset += spare_len;
1532 ecc_offset += ALIGN(ecc_len, 32);
1533 }
1534
1535 return nand_prog_page_end_op(chip);
1536 }
1537
1538 static int
1539 marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
1540 const u8 *data, unsigned int data_len,
1541 const u8 *spare, unsigned int spare_len,
1542 int page)
1543 {
1544 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1545 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1546 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1547 u32 xtype;
1548 int ret;
1549 struct marvell_nfc_op nfc_op = {
1550 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
1551 .ndcb[3] = data_len + spare_len,
1552 };
1553
1554 /*
1555 * First operation dispatches the CMD_SEQIN command, issue the address
1556 * cycles and asks for the first chunk of data.
1557 * All operations in the middle (if any) will issue a naked write and
1558 * also ask for data.
1559 * Last operation (if any) asks for the last chunk of data through a
1560 * last naked write.
1561 */
1562 if (chunk == 0) {
1563 if (lt->nchunks == 1)
1564 xtype = XTYPE_MONOLITHIC_RW;
1565 else
1566 xtype = XTYPE_WRITE_DISPATCH;
1567
1568 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) |
1569 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1570 NDCB0_CMD1(NAND_CMD_SEQIN);
1571 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
1572 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
1573 } else if (chunk < lt->nchunks - 1) {
1574 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
1575 } else {
1576 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1577 }
1578
1579 /* Always dispatch the PAGEPROG command on the last chunk */
1580 if (chunk == lt->nchunks - 1)
1581 nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC;
1582
1583 ret = marvell_nfc_prepare_cmd(chip);
1584 if (ret)
1585 return ret;
1586
1587 marvell_nfc_send_cmd(chip, &nfc_op);
1588 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1589 "WRDREQ while loading FIFO (data)");
1590 if (ret)
1591 return ret;
1592
1593 /* Transfer the contents */
1594 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len));
1595 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len));
1596
1597 return 0;
1598 }
1599
1600 static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
1601 const u8 *buf,
1602 int oob_required, int page)
1603 {
1604 const struct nand_sdr_timings *sdr =
1605 nand_get_sdr_timings(nand_get_interface_config(chip));
1606 struct mtd_info *mtd = nand_to_mtd(chip);
1607 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1608 const u8 *data = buf;
1609 const u8 *spare = chip->oob_poi;
1610 int data_len = lt->data_bytes;
1611 int spare_len = lt->spare_bytes;
1612 int chunk, ret;
1613
1614 marvell_nfc_select_target(chip, chip->cur_cs);
1615
1616 /* Spare data will be written anyway, so clear it to avoid garbage */
1617 if (!oob_required)
1618 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1619
1620 marvell_nfc_enable_hw_ecc(chip);
1621
1622 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1623 if (chunk >= lt->full_chunk_cnt) {
1624 data_len = lt->last_data_bytes;
1625 spare_len = lt->last_spare_bytes;
1626 }
1627
1628 marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len,
1629 spare, spare_len, page);
1630 data += data_len;
1631 spare += spare_len;
1632
1633 /*
1634 * Waiting only for CMDD or PAGED is not enough, ECC are
1635 * partially written. No flag is set once the operation is
1636 * really finished but the ND_RUN bit is cleared, so wait for it
1637 * before stepping into the next command.
1638 */
1639 marvell_nfc_wait_ndrun(chip);
1640 }
1641
1642 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
1643
1644 marvell_nfc_disable_hw_ecc(chip);
1645
1646 if (ret)
1647 return ret;
1648
1649 return 0;
1650 }
1651
1652 static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip,
1653 int page)
1654 {
1655 struct mtd_info *mtd = nand_to_mtd(chip);
1656 u8 *buf = nand_get_data_buf(chip);
1657
1658 memset(buf, 0xFF, mtd->writesize);
1659
1660 return chip->ecc.write_page_raw(chip, buf, true, page);
1661 }
1662
1663 static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
1664 {
1665 struct mtd_info *mtd = nand_to_mtd(chip);
1666 u8 *buf = nand_get_data_buf(chip);
1667
1668 memset(buf, 0xFF, mtd->writesize);
1669
1670 return chip->ecc.write_page(chip, buf, true, page);
1671 }
1672
1673 /* NAND framework ->exec_op() hooks and related helpers */
1674 static void marvell_nfc_parse_instructions(struct nand_chip *chip,
1675 const struct nand_subop *subop,
1676 struct marvell_nfc_op *nfc_op)
1677 {
1678 const struct nand_op_instr *instr = NULL;
1679 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1680 bool first_cmd = true;
1681 unsigned int op_id;
1682 int i;
1683
1684 /* Reset the input structure as most of its fields will be OR'ed */
1685 memset(nfc_op, 0, sizeof(struct marvell_nfc_op));
1686
1687 for (op_id = 0; op_id < subop->ninstrs; op_id++) {
1688 unsigned int offset, naddrs;
1689 const u8 *addrs;
1690 int len;
1691
1692 instr = &subop->instrs[op_id];
1693
1694 switch (instr->type) {
1695 case NAND_OP_CMD_INSTR:
1696 if (first_cmd)
1697 nfc_op->ndcb[0] |=
1698 NDCB0_CMD1(instr->ctx.cmd.opcode);
1699 else
1700 nfc_op->ndcb[0] |=
1701 NDCB0_CMD2(instr->ctx.cmd.opcode) |
1702 NDCB0_DBC;
1703
1704 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1705 first_cmd = false;
1706 break;
1707
1708 case NAND_OP_ADDR_INSTR:
1709 offset = nand_subop_get_addr_start_off(subop, op_id);
1710 naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
1711 addrs = &instr->ctx.addr.addrs[offset];
1712
1713 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs);
1714
1715 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
1716 nfc_op->ndcb[1] |= addrs[i] << (8 * i);
1717
1718 if (naddrs >= 5)
1719 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]);
1720 if (naddrs >= 6)
1721 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]);
1722 if (naddrs == 7)
1723 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]);
1724
1725 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1726 break;
1727
1728 case NAND_OP_DATA_IN_INSTR:
1729 nfc_op->data_instr = instr;
1730 nfc_op->data_instr_idx = op_id;
1731 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ);
1732 if (nfc->caps->is_nfcv2) {
1733 nfc_op->ndcb[0] |=
1734 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1735 NDCB0_LEN_OVRD;
1736 len = nand_subop_get_data_len(subop, op_id);
1737 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1738 }
1739 nfc_op->data_delay_ns = instr->delay_ns;
1740 break;
1741
1742 case NAND_OP_DATA_OUT_INSTR:
1743 nfc_op->data_instr = instr;
1744 nfc_op->data_instr_idx = op_id;
1745 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE);
1746 if (nfc->caps->is_nfcv2) {
1747 nfc_op->ndcb[0] |=
1748 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1749 NDCB0_LEN_OVRD;
1750 len = nand_subop_get_data_len(subop, op_id);
1751 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1752 }
1753 nfc_op->data_delay_ns = instr->delay_ns;
1754 break;
1755
1756 case NAND_OP_WAITRDY_INSTR:
1757 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
1758 nfc_op->rdy_delay_ns = instr->delay_ns;
1759 break;
1760 }
1761 }
1762 }
1763
1764 static int marvell_nfc_xfer_data_pio(struct nand_chip *chip,
1765 const struct nand_subop *subop,
1766 struct marvell_nfc_op *nfc_op)
1767 {
1768 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1769 const struct nand_op_instr *instr = nfc_op->data_instr;
1770 unsigned int op_id = nfc_op->data_instr_idx;
1771 unsigned int len = nand_subop_get_data_len(subop, op_id);
1772 unsigned int offset = nand_subop_get_data_start_off(subop, op_id);
1773 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR);
1774 int ret;
1775
1776 if (instr->ctx.data.force_8bit)
1777 marvell_nfc_force_byte_access(chip, true);
1778
1779 if (reading) {
1780 u8 *in = instr->ctx.data.buf.in + offset;
1781
1782 ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
1783 } else {
1784 const u8 *out = instr->ctx.data.buf.out + offset;
1785
1786 ret = marvell_nfc_xfer_data_out_pio(nfc, out, len);
1787 }
1788
1789 if (instr->ctx.data.force_8bit)
1790 marvell_nfc_force_byte_access(chip, false);
1791
1792 return ret;
1793 }
1794
1795 static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip,
1796 const struct nand_subop *subop)
1797 {
1798 struct marvell_nfc_op nfc_op;
1799 bool reading;
1800 int ret;
1801
1802 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1803 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
1804
1805 ret = marvell_nfc_prepare_cmd(chip);
1806 if (ret)
1807 return ret;
1808
1809 marvell_nfc_send_cmd(chip, &nfc_op);
1810 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1811 "RDDREQ/WRDREQ while draining raw data");
1812 if (ret)
1813 return ret;
1814
1815 cond_delay(nfc_op.cle_ale_delay_ns);
1816
1817 if (reading) {
1818 if (nfc_op.rdy_timeout_ms) {
1819 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1820 if (ret)
1821 return ret;
1822 }
1823
1824 cond_delay(nfc_op.rdy_delay_ns);
1825 }
1826
1827 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1828 ret = marvell_nfc_wait_cmdd(chip);
1829 if (ret)
1830 return ret;
1831
1832 cond_delay(nfc_op.data_delay_ns);
1833
1834 if (!reading) {
1835 if (nfc_op.rdy_timeout_ms) {
1836 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1837 if (ret)
1838 return ret;
1839 }
1840
1841 cond_delay(nfc_op.rdy_delay_ns);
1842 }
1843
1844 /*
1845 * NDCR ND_RUN bit should be cleared automatically at the end of each
1846 * operation but experience shows that the behavior is buggy when it
1847 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1848 */
1849 if (!reading) {
1850 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1851
1852 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1853 nfc->regs + NDCR);
1854 }
1855
1856 return 0;
1857 }
1858
1859 static int marvell_nfc_naked_access_exec(struct nand_chip *chip,
1860 const struct nand_subop *subop)
1861 {
1862 struct marvell_nfc_op nfc_op;
1863 int ret;
1864
1865 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1866
1867 /*
1868 * Naked access are different in that they need to be flagged as naked
1869 * by the controller. Reset the controller registers fields that inform
1870 * on the type and refill them according to the ongoing operation.
1871 */
1872 nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) |
1873 NDCB0_CMD_XTYPE(XTYPE_MASK));
1874 switch (subop->instrs[0].type) {
1875 case NAND_OP_CMD_INSTR:
1876 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD);
1877 break;
1878 case NAND_OP_ADDR_INSTR:
1879 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR);
1880 break;
1881 case NAND_OP_DATA_IN_INSTR:
1882 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) |
1883 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1884 break;
1885 case NAND_OP_DATA_OUT_INSTR:
1886 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) |
1887 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1888 break;
1889 default:
1890 /* This should never happen */
1891 break;
1892 }
1893
1894 ret = marvell_nfc_prepare_cmd(chip);
1895 if (ret)
1896 return ret;
1897
1898 marvell_nfc_send_cmd(chip, &nfc_op);
1899
1900 if (!nfc_op.data_instr) {
1901 ret = marvell_nfc_wait_cmdd(chip);
1902 cond_delay(nfc_op.cle_ale_delay_ns);
1903 return ret;
1904 }
1905
1906 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1907 "RDDREQ/WRDREQ while draining raw data");
1908 if (ret)
1909 return ret;
1910
1911 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1912 ret = marvell_nfc_wait_cmdd(chip);
1913 if (ret)
1914 return ret;
1915
1916 /*
1917 * NDCR ND_RUN bit should be cleared automatically at the end of each
1918 * operation but experience shows that the behavior is buggy when it
1919 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1920 */
1921 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) {
1922 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1923
1924 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1925 nfc->regs + NDCR);
1926 }
1927
1928 return 0;
1929 }
1930
1931 static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip,
1932 const struct nand_subop *subop)
1933 {
1934 struct marvell_nfc_op nfc_op;
1935 int ret;
1936
1937 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1938
1939 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1940 cond_delay(nfc_op.rdy_delay_ns);
1941
1942 return ret;
1943 }
1944
1945 static int marvell_nfc_read_id_type_exec(struct nand_chip *chip,
1946 const struct nand_subop *subop)
1947 {
1948 struct marvell_nfc_op nfc_op;
1949 int ret;
1950
1951 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1952 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1953 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID);
1954
1955 ret = marvell_nfc_prepare_cmd(chip);
1956 if (ret)
1957 return ret;
1958
1959 marvell_nfc_send_cmd(chip, &nfc_op);
1960 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1961 "RDDREQ while reading ID");
1962 if (ret)
1963 return ret;
1964
1965 cond_delay(nfc_op.cle_ale_delay_ns);
1966
1967 if (nfc_op.rdy_timeout_ms) {
1968 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1969 if (ret)
1970 return ret;
1971 }
1972
1973 cond_delay(nfc_op.rdy_delay_ns);
1974
1975 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1976 ret = marvell_nfc_wait_cmdd(chip);
1977 if (ret)
1978 return ret;
1979
1980 cond_delay(nfc_op.data_delay_ns);
1981
1982 return 0;
1983 }
1984
1985 static int marvell_nfc_read_status_exec(struct nand_chip *chip,
1986 const struct nand_subop *subop)
1987 {
1988 struct marvell_nfc_op nfc_op;
1989 int ret;
1990
1991 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1992 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1993 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS);
1994
1995 ret = marvell_nfc_prepare_cmd(chip);
1996 if (ret)
1997 return ret;
1998
1999 marvell_nfc_send_cmd(chip, &nfc_op);
2000 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
2001 "RDDREQ while reading status");
2002 if (ret)
2003 return ret;
2004
2005 cond_delay(nfc_op.cle_ale_delay_ns);
2006
2007 if (nfc_op.rdy_timeout_ms) {
2008 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2009 if (ret)
2010 return ret;
2011 }
2012
2013 cond_delay(nfc_op.rdy_delay_ns);
2014
2015 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
2016 ret = marvell_nfc_wait_cmdd(chip);
2017 if (ret)
2018 return ret;
2019
2020 cond_delay(nfc_op.data_delay_ns);
2021
2022 return 0;
2023 }
2024
2025 static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip,
2026 const struct nand_subop *subop)
2027 {
2028 struct marvell_nfc_op nfc_op;
2029 int ret;
2030
2031 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
2032 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET);
2033
2034 ret = marvell_nfc_prepare_cmd(chip);
2035 if (ret)
2036 return ret;
2037
2038 marvell_nfc_send_cmd(chip, &nfc_op);
2039 ret = marvell_nfc_wait_cmdd(chip);
2040 if (ret)
2041 return ret;
2042
2043 cond_delay(nfc_op.cle_ale_delay_ns);
2044
2045 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2046 if (ret)
2047 return ret;
2048
2049 cond_delay(nfc_op.rdy_delay_ns);
2050
2051 return 0;
2052 }
2053
2054 static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip,
2055 const struct nand_subop *subop)
2056 {
2057 struct marvell_nfc_op nfc_op;
2058 int ret;
2059
2060 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
2061 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE);
2062
2063 ret = marvell_nfc_prepare_cmd(chip);
2064 if (ret)
2065 return ret;
2066
2067 marvell_nfc_send_cmd(chip, &nfc_op);
2068 ret = marvell_nfc_wait_cmdd(chip);
2069 if (ret)
2070 return ret;
2071
2072 cond_delay(nfc_op.cle_ale_delay_ns);
2073
2074 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2075 if (ret)
2076 return ret;
2077
2078 cond_delay(nfc_op.rdy_delay_ns);
2079
2080 return 0;
2081 }
2082
2083 static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER(
2084 /* Monolithic reads/writes */
2085 NAND_OP_PARSER_PATTERN(
2086 marvell_nfc_monolithic_access_exec,
2087 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2088 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2),
2089 NAND_OP_PARSER_PAT_CMD_ELEM(true),
2090 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
2091 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
2092 NAND_OP_PARSER_PATTERN(
2093 marvell_nfc_monolithic_access_exec,
2094 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2095 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2),
2096 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE),
2097 NAND_OP_PARSER_PAT_CMD_ELEM(true),
2098 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
2099 /* Naked commands */
2100 NAND_OP_PARSER_PATTERN(
2101 marvell_nfc_naked_access_exec,
2102 NAND_OP_PARSER_PAT_CMD_ELEM(false)),
2103 NAND_OP_PARSER_PATTERN(
2104 marvell_nfc_naked_access_exec,
2105 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)),
2106 NAND_OP_PARSER_PATTERN(
2107 marvell_nfc_naked_access_exec,
2108 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
2109 NAND_OP_PARSER_PATTERN(
2110 marvell_nfc_naked_access_exec,
2111 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)),
2112 NAND_OP_PARSER_PATTERN(
2113 marvell_nfc_naked_waitrdy_exec,
2114 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2115 );
2116
2117 static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
2118 /* Naked commands not supported, use a function for each pattern */
2119 NAND_OP_PARSER_PATTERN(
2120 marvell_nfc_read_id_type_exec,
2121 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2122 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
2123 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)),
2124 NAND_OP_PARSER_PATTERN(
2125 marvell_nfc_erase_cmd_type_exec,
2126 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2127 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
2128 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2129 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2130 NAND_OP_PARSER_PATTERN(
2131 marvell_nfc_read_status_exec,
2132 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2133 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)),
2134 NAND_OP_PARSER_PATTERN(
2135 marvell_nfc_reset_cmd_type_exec,
2136 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2137 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2138 NAND_OP_PARSER_PATTERN(
2139 marvell_nfc_naked_waitrdy_exec,
2140 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2141 );
2142
2143 static int marvell_nfc_exec_op(struct nand_chip *chip,
2144 const struct nand_operation *op,
2145 bool check_only)
2146 {
2147 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2148
2149 if (!check_only)
2150 marvell_nfc_select_target(chip, op->cs);
2151
2152 if (nfc->caps->is_nfcv2)
2153 return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser,
2154 op, check_only);
2155 else
2156 return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser,
2157 op, check_only);
2158 }
2159
2160 /*
2161 * Layouts were broken in old pxa3xx_nand driver, these are supposed to be
2162 * usable.
2163 */
2164 static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2165 struct mtd_oob_region *oobregion)
2166 {
2167 struct nand_chip *chip = mtd_to_nand(mtd);
2168 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2169
2170 if (section)
2171 return -ERANGE;
2172
2173 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) +
2174 lt->last_ecc_bytes;
2175 oobregion->offset = mtd->oobsize - oobregion->length;
2176
2177 return 0;
2178 }
2179
2180 static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section,
2181 struct mtd_oob_region *oobregion)
2182 {
2183 struct nand_chip *chip = mtd_to_nand(mtd);
2184 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2185
2186 if (section)
2187 return -ERANGE;
2188
2189 /*
2190 * Bootrom looks in bytes 0 & 5 for bad blocks for the
2191 * 4KB page / 4bit BCH combination.
2192 */
2193 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K)
2194 oobregion->offset = 6;
2195 else
2196 oobregion->offset = 2;
2197
2198 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) +
2199 lt->last_spare_bytes - oobregion->offset;
2200
2201 return 0;
2202 }
2203
2204 static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = {
2205 .ecc = marvell_nand_ooblayout_ecc,
2206 .free = marvell_nand_ooblayout_free,
2207 };
2208
2209 static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
2210 struct nand_ecc_ctrl *ecc)
2211 {
2212 struct nand_chip *chip = mtd_to_nand(mtd);
2213 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2214 const struct marvell_hw_ecc_layout *l;
2215 int i;
2216
2217 if (!nfc->caps->is_nfcv2 &&
2218 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) {
2219 dev_err(nfc->dev,
2220 "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n",
2221 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize);
2222 return -ENOTSUPP;
2223 }
2224
2225 to_marvell_nand(chip)->layout = NULL;
2226 for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) {
2227 l = &marvell_nfc_layouts[i];
2228 if (mtd->writesize == l->writesize &&
2229 ecc->size == l->chunk && ecc->strength == l->strength) {
2230 to_marvell_nand(chip)->layout = l;
2231 break;
2232 }
2233 }
2234
2235 if (!to_marvell_nand(chip)->layout ||
2236 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
2237 dev_err(nfc->dev,
2238 "ECC strength %d at page size %d is not supported\n",
2239 ecc->strength, mtd->writesize);
2240 return -ENOTSUPP;
2241 }
2242
2243 /* Special care for the layout 2k/8-bit/512B */
2244 if (l->writesize == 2048 && l->strength == 8) {
2245 if (mtd->oobsize < 128) {
2246 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n");
2247 return -ENOTSUPP;
2248 } else {
2249 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2250 }
2251 }
2252
2253 mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops);
2254 ecc->steps = l->nchunks;
2255 ecc->size = l->data_bytes;
2256
2257 if (ecc->strength == 1) {
2258 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2259 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
2260 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
2261 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
2262 ecc->read_oob = ecc->read_oob_raw;
2263 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
2264 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
2265 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
2266 ecc->write_oob = ecc->write_oob_raw;
2267 } else {
2268 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2269 ecc->strength = 16;
2270 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
2271 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
2272 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
2273 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
2274 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
2275 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
2276 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
2277 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
2278 }
2279
2280 return 0;
2281 }
2282
2283 static int marvell_nand_ecc_init(struct mtd_info *mtd,
2284 struct nand_ecc_ctrl *ecc)
2285 {
2286 struct nand_chip *chip = mtd_to_nand(mtd);
2287 const struct nand_ecc_props *requirements =
2288 nanddev_get_ecc_requirements(&chip->base);
2289 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2290 int ret;
2291
2292 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2293 (!ecc->size || !ecc->strength)) {
2294 if (requirements->step_size && requirements->strength) {
2295 ecc->size = requirements->step_size;
2296 ecc->strength = requirements->strength;
2297 } else {
2298 dev_info(nfc->dev,
2299 "No minimum ECC strength, using 1b/512B\n");
2300 ecc->size = 512;
2301 ecc->strength = 1;
2302 }
2303 }
2304
2305 switch (ecc->engine_type) {
2306 case NAND_ECC_ENGINE_TYPE_ON_HOST:
2307 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
2308 if (ret)
2309 return ret;
2310 break;
2311 case NAND_ECC_ENGINE_TYPE_NONE:
2312 case NAND_ECC_ENGINE_TYPE_SOFT:
2313 case NAND_ECC_ENGINE_TYPE_ON_DIE:
2314 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
2315 mtd->writesize != SZ_2K) {
2316 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
2317 mtd->writesize);
2318 return -EINVAL;
2319 }
2320 break;
2321 default:
2322 return -EINVAL;
2323 }
2324
2325 return 0;
2326 }
2327
2328 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
2329 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
2330
2331 static struct nand_bbt_descr bbt_main_descr = {
2332 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2333 NAND_BBT_2BIT | NAND_BBT_VERSION,
2334 .offs = 8,
2335 .len = 6,
2336 .veroffs = 14,
2337 .maxblocks = 8, /* Last 8 blocks in each chip */
2338 .pattern = bbt_pattern
2339 };
2340
2341 static struct nand_bbt_descr bbt_mirror_descr = {
2342 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2343 NAND_BBT_2BIT | NAND_BBT_VERSION,
2344 .offs = 8,
2345 .len = 6,
2346 .veroffs = 14,
2347 .maxblocks = 8, /* Last 8 blocks in each chip */
2348 .pattern = bbt_mirror_pattern
2349 };
2350
2351 static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
2352 const struct nand_interface_config *conf)
2353 {
2354 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2355 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2356 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2;
2357 const struct nand_sdr_timings *sdr;
2358 struct marvell_nfc_timings nfc_tmg;
2359 int read_delay;
2360
2361 sdr = nand_get_sdr_timings(conf);
2362 if (IS_ERR(sdr))
2363 return PTR_ERR(sdr);
2364
2365 /*
2366 * SDR timings are given in pico-seconds while NFC timings must be
2367 * expressed in NAND controller clock cycles, which is half of the
2368 * frequency of the accessible ECC clock retrieved by clk_get_rate().
2369 * This is not written anywhere in the datasheet but was observed
2370 * with an oscilloscope.
2371 *
2372 * NFC datasheet gives equations from which thoses calculations
2373 * are derived, they tend to be slightly more restrictives than the
2374 * given core timings and may improve the overall speed.
2375 */
2376 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
2377 nfc_tmg.tRH = nfc_tmg.tRP;
2378 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
2379 nfc_tmg.tWH = nfc_tmg.tWP;
2380 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
2381 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
2382 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
2383 /*
2384 * Read delay is the time of propagation from SoC pins to NFC internal
2385 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In
2386 * EDO mode, an additional delay of tRH must be taken into account so
2387 * the data is sampled on the falling edge instead of the rising edge.
2388 */
2389 read_delay = sdr->tRC_min >= 30000 ?
2390 MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH;
2391
2392 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
2393 /*
2394 * tWHR and tRHW are supposed to be read to write delays (and vice
2395 * versa) but in some cases, ie. when doing a change column, they must
2396 * be greater than that to be sure tCCS delay is respected.
2397 */
2398 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
2399 period_ns) - 2,
2400 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
2401 period_ns);
2402
2403 /*
2404 * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays.
2405 * NFCv1: No WAIT_MODE, tR must be maximal.
2406 */
2407 if (nfc->caps->is_nfcv2) {
2408 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
2409 } else {
2410 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,
2411 period_ns);
2412 if (nfc_tmg.tR + 3 > nfc_tmg.tCH)
2413 nfc_tmg.tR = nfc_tmg.tCH - 3;
2414 else
2415 nfc_tmg.tR = 0;
2416 }
2417
2418 if (chipnr < 0)
2419 return 0;
2420
2421 marvell_nand->ndtr0 =
2422 NDTR0_TRP(nfc_tmg.tRP) |
2423 NDTR0_TRH(nfc_tmg.tRH) |
2424 NDTR0_ETRP(nfc_tmg.tRP) |
2425 NDTR0_TWP(nfc_tmg.tWP) |
2426 NDTR0_TWH(nfc_tmg.tWH) |
2427 NDTR0_TCS(nfc_tmg.tCS) |
2428 NDTR0_TCH(nfc_tmg.tCH);
2429
2430 marvell_nand->ndtr1 =
2431 NDTR1_TAR(nfc_tmg.tAR) |
2432 NDTR1_TWHR(nfc_tmg.tWHR) |
2433 NDTR1_TR(nfc_tmg.tR);
2434
2435 if (nfc->caps->is_nfcv2) {
2436 marvell_nand->ndtr0 |=
2437 NDTR0_RD_CNT_DEL(read_delay) |
2438 NDTR0_SELCNTR |
2439 NDTR0_TADL(nfc_tmg.tADL);
2440
2441 marvell_nand->ndtr1 |=
2442 NDTR1_TRHW(nfc_tmg.tRHW) |
2443 NDTR1_WAIT_MODE;
2444 }
2445
2446 return 0;
2447 }
2448
2449 static int marvell_nand_attach_chip(struct nand_chip *chip)
2450 {
2451 struct mtd_info *mtd = nand_to_mtd(chip);
2452 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2453 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2454 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev);
2455 int ret;
2456
2457 if (pdata && pdata->flash_bbt)
2458 chip->bbt_options |= NAND_BBT_USE_FLASH;
2459
2460 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
2461 /*
2462 * We'll use a bad block table stored in-flash and don't
2463 * allow writing the bad block marker to the flash.
2464 */
2465 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2466 chip->bbt_td = &bbt_main_descr;
2467 chip->bbt_md = &bbt_mirror_descr;
2468 }
2469
2470 /* Save the chip-specific fields of NDCR */
2471 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
2472 if (chip->options & NAND_BUSWIDTH_16)
2473 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
2474
2475 /*
2476 * On small page NANDs, only one cycle is needed to pass the
2477 * column address.
2478 */
2479 if (mtd->writesize <= 512) {
2480 marvell_nand->addr_cyc = 1;
2481 } else {
2482 marvell_nand->addr_cyc = 2;
2483 marvell_nand->ndcr |= NDCR_RA_START;
2484 }
2485
2486 /*
2487 * Now add the number of cycles needed to pass the row
2488 * address.
2489 *
2490 * Addressing a chip using CS 2 or 3 should also need the third row
2491 * cycle but due to inconsistance in the documentation and lack of
2492 * hardware to test this situation, this case is not supported.
2493 */
2494 if (chip->options & NAND_ROW_ADDR_3)
2495 marvell_nand->addr_cyc += 3;
2496 else
2497 marvell_nand->addr_cyc += 2;
2498
2499 if (pdata) {
2500 chip->ecc.size = pdata->ecc_step_size;
2501 chip->ecc.strength = pdata->ecc_strength;
2502 }
2503
2504 ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2505 if (ret) {
2506 dev_err(nfc->dev, "ECC init failed: %d\n", ret);
2507 return ret;
2508 }
2509
2510 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
2511 /*
2512 * Subpage write not available with hardware ECC, prohibit also
2513 * subpage read as in userspace subpage access would still be
2514 * allowed and subpage write, if used, would lead to numerous
2515 * uncorrectable ECC errors.
2516 */
2517 chip->options |= NAND_NO_SUBPAGE_WRITE;
2518 }
2519
2520 if (pdata || nfc->caps->legacy_of_bindings) {
2521 /*
2522 * We keep the MTD name unchanged to avoid breaking platforms
2523 * where the MTD cmdline parser is used and the bootloader
2524 * has not been updated to use the new naming scheme.
2525 */
2526 mtd->name = "pxa3xx_nand-0";
2527 } else if (!mtd->name) {
2528 /*
2529 * If the new bindings are used and the bootloader has not been
2530 * updated to pass a new mtdparts parameter on the cmdline, you
2531 * should define the following property in your NAND node, ie:
2532 *
2533 * label = "main-storage";
2534 *
2535 * This way, mtd->name will be set by the core when
2536 * nand_set_flash_node() is called.
2537 */
2538 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
2539 "%s:nand.%d", dev_name(nfc->dev),
2540 marvell_nand->sels[0].cs);
2541 if (!mtd->name) {
2542 dev_err(nfc->dev, "Failed to allocate mtd->name\n");
2543 return -ENOMEM;
2544 }
2545 }
2546
2547 return 0;
2548 }
2549
2550 static const struct nand_controller_ops marvell_nand_controller_ops = {
2551 .attach_chip = marvell_nand_attach_chip,
2552 .exec_op = marvell_nfc_exec_op,
2553 .setup_interface = marvell_nfc_setup_interface,
2554 };
2555
2556 static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
2557 struct device_node *np)
2558 {
2559 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev);
2560 struct marvell_nand_chip *marvell_nand;
2561 struct mtd_info *mtd;
2562 struct nand_chip *chip;
2563 int nsels, ret, i;
2564 u32 cs, rb;
2565
2566 /*
2567 * The legacy "num-cs" property indicates the number of CS on the only
2568 * chip connected to the controller (legacy bindings does not support
2569 * more than one chip). The CS and RB pins are always the #0.
2570 *
2571 * When not using legacy bindings, a couple of "reg" and "nand-rb"
2572 * properties must be filled. For each chip, expressed as a subnode,
2573 * "reg" points to the CS lines and "nand-rb" to the RB line.
2574 */
2575 if (pdata || nfc->caps->legacy_of_bindings) {
2576 nsels = 1;
2577 } else {
2578 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
2579 if (nsels <= 0) {
2580 dev_err(dev, "missing/invalid reg property\n");
2581 return -EINVAL;
2582 }
2583 }
2584
2585 /* Alloc the nand chip structure */
2586 marvell_nand = devm_kzalloc(dev,
2587 struct_size(marvell_nand, sels, nsels),
2588 GFP_KERNEL);
2589 if (!marvell_nand) {
2590 dev_err(dev, "could not allocate chip structure\n");
2591 return -ENOMEM;
2592 }
2593
2594 marvell_nand->nsels = nsels;
2595 marvell_nand->selected_die = -1;
2596
2597 for (i = 0; i < nsels; i++) {
2598 if (pdata || nfc->caps->legacy_of_bindings) {
2599 /*
2600 * Legacy bindings use the CS lines in natural
2601 * order (0, 1, ...)
2602 */
2603 cs = i;
2604 } else {
2605 /* Retrieve CS id */
2606 ret = of_property_read_u32_index(np, "reg", i, &cs);
2607 if (ret) {
2608 dev_err(dev, "could not retrieve reg property: %d\n",
2609 ret);
2610 return ret;
2611 }
2612 }
2613
2614 if (cs >= nfc->caps->max_cs_nb) {
2615 dev_err(dev, "invalid reg value: %u (max CS = %d)\n",
2616 cs, nfc->caps->max_cs_nb);
2617 return -EINVAL;
2618 }
2619
2620 if (test_and_set_bit(cs, &nfc->assigned_cs)) {
2621 dev_err(dev, "CS %d already assigned\n", cs);
2622 return -EINVAL;
2623 }
2624
2625 /*
2626 * The cs variable represents the chip select id, which must be
2627 * converted in bit fields for NDCB0 and NDCB2 to select the
2628 * right chip. Unfortunately, due to a lack of information on
2629 * the subject and incoherent documentation, the user should not
2630 * use CS1 and CS3 at all as asserting them is not supported in
2631 * a reliable way (due to multiplexing inside ADDR5 field).
2632 */
2633 marvell_nand->sels[i].cs = cs;
2634 switch (cs) {
2635 case 0:
2636 case 2:
2637 marvell_nand->sels[i].ndcb0_csel = 0;
2638 break;
2639 case 1:
2640 case 3:
2641 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL;
2642 break;
2643 default:
2644 return -EINVAL;
2645 }
2646
2647 /* Retrieve RB id */
2648 if (pdata || nfc->caps->legacy_of_bindings) {
2649 /* Legacy bindings always use RB #0 */
2650 rb = 0;
2651 } else {
2652 ret = of_property_read_u32_index(np, "nand-rb", i,
2653 &rb);
2654 if (ret) {
2655 dev_err(dev,
2656 "could not retrieve RB property: %d\n",
2657 ret);
2658 return ret;
2659 }
2660 }
2661
2662 if (rb >= nfc->caps->max_rb_nb) {
2663 dev_err(dev, "invalid reg value: %u (max RB = %d)\n",
2664 rb, nfc->caps->max_rb_nb);
2665 return -EINVAL;
2666 }
2667
2668 marvell_nand->sels[i].rb = rb;
2669 }
2670
2671 chip = &marvell_nand->chip;
2672 chip->controller = &nfc->controller;
2673 nand_set_flash_node(chip, np);
2674
2675 if (!of_property_read_bool(np, "marvell,nand-keep-config"))
2676 chip->options |= NAND_KEEP_TIMINGS;
2677
2678 mtd = nand_to_mtd(chip);
2679 mtd->dev.parent = dev;
2680
2681 /*
2682 * Save a reference value for timing registers before
2683 * ->setup_interface() is called.
2684 */
2685 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
2686 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
2687
2688 chip->options |= NAND_BUSWIDTH_AUTO;
2689
2690 ret = nand_scan(chip, marvell_nand->nsels);
2691 if (ret) {
2692 dev_err(dev, "could not scan the nand chip\n");
2693 return ret;
2694 }
2695
2696 if (pdata)
2697 /* Legacy bindings support only one chip */
2698 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2699 else
2700 ret = mtd_device_register(mtd, NULL, 0);
2701 if (ret) {
2702 dev_err(dev, "failed to register mtd device: %d\n", ret);
2703 nand_cleanup(chip);
2704 return ret;
2705 }
2706
2707 list_add_tail(&marvell_nand->node, &nfc->chips);
2708
2709 return 0;
2710 }
2711
2712 static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc)
2713 {
2714 struct marvell_nand_chip *entry, *temp;
2715 struct nand_chip *chip;
2716 int ret;
2717
2718 list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
2719 chip = &entry->chip;
2720 ret = mtd_device_unregister(nand_to_mtd(chip));
2721 WARN_ON(ret);
2722 nand_cleanup(chip);
2723 list_del(&entry->node);
2724 }
2725 }
2726
2727 static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc)
2728 {
2729 struct device_node *np = dev->of_node;
2730 struct device_node *nand_np;
2731 int max_cs = nfc->caps->max_cs_nb;
2732 int nchips;
2733 int ret;
2734
2735 if (!np)
2736 nchips = 1;
2737 else
2738 nchips = of_get_child_count(np);
2739
2740 if (nchips > max_cs) {
2741 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips,
2742 max_cs);
2743 return -EINVAL;
2744 }
2745
2746 /*
2747 * Legacy bindings do not use child nodes to exhibit NAND chip
2748 * properties and layout. Instead, NAND properties are mixed with the
2749 * controller ones, and partitions are defined as direct subnodes of the
2750 * NAND controller node.
2751 */
2752 if (nfc->caps->legacy_of_bindings) {
2753 ret = marvell_nand_chip_init(dev, nfc, np);
2754 return ret;
2755 }
2756
2757 for_each_child_of_node(np, nand_np) {
2758 ret = marvell_nand_chip_init(dev, nfc, nand_np);
2759 if (ret) {
2760 of_node_put(nand_np);
2761 goto cleanup_chips;
2762 }
2763 }
2764
2765 return 0;
2766
2767 cleanup_chips:
2768 marvell_nand_chips_cleanup(nfc);
2769
2770 return ret;
2771 }
2772
2773 static int marvell_nfc_init_dma(struct marvell_nfc *nfc)
2774 {
2775 struct platform_device *pdev = container_of(nfc->dev,
2776 struct platform_device,
2777 dev);
2778 struct dma_slave_config config = {};
2779 struct resource *r;
2780 int ret;
2781
2782 if (!IS_ENABLED(CONFIG_PXA_DMA)) {
2783 dev_warn(nfc->dev,
2784 "DMA not enabled in configuration\n");
2785 return -ENOTSUPP;
2786 }
2787
2788 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32));
2789 if (ret)
2790 return ret;
2791
2792 nfc->dma_chan = dma_request_chan(nfc->dev, "data");
2793 if (IS_ERR(nfc->dma_chan)) {
2794 ret = PTR_ERR(nfc->dma_chan);
2795 nfc->dma_chan = NULL;
2796 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n");
2797 }
2798
2799 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2800 if (!r) {
2801 ret = -ENXIO;
2802 goto release_channel;
2803 }
2804
2805 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2806 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2807 config.src_addr = r->start + NDDB;
2808 config.dst_addr = r->start + NDDB;
2809 config.src_maxburst = 32;
2810 config.dst_maxburst = 32;
2811 ret = dmaengine_slave_config(nfc->dma_chan, &config);
2812 if (ret < 0) {
2813 dev_err(nfc->dev, "Failed to configure DMA channel\n");
2814 goto release_channel;
2815 }
2816
2817 /*
2818 * DMA must act on length multiple of 32 and this length may be
2819 * bigger than the destination buffer. Use this buffer instead
2820 * for DMA transfers and then copy the desired amount of data to
2821 * the provided buffer.
2822 */
2823 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
2824 if (!nfc->dma_buf) {
2825 ret = -ENOMEM;
2826 goto release_channel;
2827 }
2828
2829 nfc->use_dma = true;
2830
2831 return 0;
2832
2833 release_channel:
2834 dma_release_channel(nfc->dma_chan);
2835 nfc->dma_chan = NULL;
2836
2837 return ret;
2838 }
2839
2840 static void marvell_nfc_reset(struct marvell_nfc *nfc)
2841 {
2842 /*
2843 * ECC operations and interruptions are only enabled when specifically
2844 * needed. ECC shall not be activated in the early stages (fails probe).
2845 * Arbiter flag, even if marked as "reserved", must be set (empirical).
2846 * SPARE_EN bit must always be set or ECC bytes will not be at the same
2847 * offset in the read page and this will fail the protection.
2848 */
2849 writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN |
2850 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);
2851 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR);
2852 writel_relaxed(0, nfc->regs + NDECCCTRL);
2853 }
2854
2855 static int marvell_nfc_init(struct marvell_nfc *nfc)
2856 {
2857 struct device_node *np = nfc->dev->of_node;
2858
2859 /*
2860 * Some SoCs like A7k/A8k need to enable manually the NAND
2861 * controller, gated clocks and reset bits to avoid being bootloader
2862 * dependent. This is done through the use of the System Functions
2863 * registers.
2864 */
2865 if (nfc->caps->need_system_controller) {
2866 struct regmap *sysctrl_base =
2867 syscon_regmap_lookup_by_phandle(np,
2868 "marvell,system-controller");
2869
2870 if (IS_ERR(sysctrl_base))
2871 return PTR_ERR(sysctrl_base);
2872
2873 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX,
2874 GENCONF_SOC_DEVICE_MUX_NFC_EN |
2875 GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
2876 GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
2877 GENCONF_SOC_DEVICE_MUX_NFC_INT_EN);
2878
2879 regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL,
2880 GENCONF_CLK_GATING_CTRL_ND_GATE,
2881 GENCONF_CLK_GATING_CTRL_ND_GATE);
2882
2883 regmap_update_bits(sysctrl_base, GENCONF_ND_CLK_CTRL,
2884 GENCONF_ND_CLK_CTRL_EN,
2885 GENCONF_ND_CLK_CTRL_EN);
2886 }
2887
2888 /* Configure the DMA if appropriate */
2889 if (!nfc->caps->is_nfcv2)
2890 marvell_nfc_init_dma(nfc);
2891
2892 marvell_nfc_reset(nfc);
2893
2894 return 0;
2895 }
2896
2897 static int marvell_nfc_probe(struct platform_device *pdev)
2898 {
2899 struct device *dev = &pdev->dev;
2900 struct marvell_nfc *nfc;
2901 int ret;
2902 int irq;
2903
2904 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc),
2905 GFP_KERNEL);
2906 if (!nfc)
2907 return -ENOMEM;
2908
2909 nfc->dev = dev;
2910 nand_controller_init(&nfc->controller);
2911 nfc->controller.ops = &marvell_nand_controller_ops;
2912 INIT_LIST_HEAD(&nfc->chips);
2913
2914 nfc->regs = devm_platform_ioremap_resource(pdev, 0);
2915 if (IS_ERR(nfc->regs))
2916 return PTR_ERR(nfc->regs);
2917
2918 irq = platform_get_irq(pdev, 0);
2919 if (irq < 0)
2920 return irq;
2921
2922 nfc->core_clk = devm_clk_get(&pdev->dev, "core");
2923
2924 /* Managed the legacy case (when the first clock was not named) */
2925 if (nfc->core_clk == ERR_PTR(-ENOENT))
2926 nfc->core_clk = devm_clk_get(&pdev->dev, NULL);
2927
2928 if (IS_ERR(nfc->core_clk))
2929 return PTR_ERR(nfc->core_clk);
2930
2931 ret = clk_prepare_enable(nfc->core_clk);
2932 if (ret)
2933 return ret;
2934
2935 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg");
2936 if (IS_ERR(nfc->reg_clk)) {
2937 if (PTR_ERR(nfc->reg_clk) != -ENOENT) {
2938 ret = PTR_ERR(nfc->reg_clk);
2939 goto unprepare_core_clk;
2940 }
2941
2942 nfc->reg_clk = NULL;
2943 }
2944
2945 ret = clk_prepare_enable(nfc->reg_clk);
2946 if (ret)
2947 goto unprepare_core_clk;
2948
2949 marvell_nfc_disable_int(nfc, NDCR_ALL_INT);
2950 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
2951 ret = devm_request_irq(dev, irq, marvell_nfc_isr,
2952 0, "marvell-nfc", nfc);
2953 if (ret)
2954 goto unprepare_reg_clk;
2955
2956 /* Get NAND controller capabilities */
2957 if (pdev->id_entry)
2958 nfc->caps = (void *)pdev->id_entry->driver_data;
2959 else
2960 nfc->caps = of_device_get_match_data(&pdev->dev);
2961
2962 if (!nfc->caps) {
2963 dev_err(dev, "Could not retrieve NFC caps\n");
2964 ret = -EINVAL;
2965 goto unprepare_reg_clk;
2966 }
2967
2968 /* Init the controller and then probe the chips */
2969 ret = marvell_nfc_init(nfc);
2970 if (ret)
2971 goto unprepare_reg_clk;
2972
2973 platform_set_drvdata(pdev, nfc);
2974
2975 ret = marvell_nand_chips_init(dev, nfc);
2976 if (ret)
2977 goto release_dma;
2978
2979 return 0;
2980
2981 release_dma:
2982 if (nfc->use_dma)
2983 dma_release_channel(nfc->dma_chan);
2984 unprepare_reg_clk:
2985 clk_disable_unprepare(nfc->reg_clk);
2986 unprepare_core_clk:
2987 clk_disable_unprepare(nfc->core_clk);
2988
2989 return ret;
2990 }
2991
2992 static int marvell_nfc_remove(struct platform_device *pdev)
2993 {
2994 struct marvell_nfc *nfc = platform_get_drvdata(pdev);
2995
2996 marvell_nand_chips_cleanup(nfc);
2997
2998 if (nfc->use_dma) {
2999 dmaengine_terminate_all(nfc->dma_chan);
3000 dma_release_channel(nfc->dma_chan);
3001 }
3002
3003 clk_disable_unprepare(nfc->reg_clk);
3004 clk_disable_unprepare(nfc->core_clk);
3005
3006 return 0;
3007 }
3008
3009 static int __maybe_unused marvell_nfc_suspend(struct device *dev)
3010 {
3011 struct marvell_nfc *nfc = dev_get_drvdata(dev);
3012 struct marvell_nand_chip *chip;
3013
3014 list_for_each_entry(chip, &nfc->chips, node)
3015 marvell_nfc_wait_ndrun(&chip->chip);
3016
3017 clk_disable_unprepare(nfc->reg_clk);
3018 clk_disable_unprepare(nfc->core_clk);
3019
3020 return 0;
3021 }
3022
3023 static int __maybe_unused marvell_nfc_resume(struct device *dev)
3024 {
3025 struct marvell_nfc *nfc = dev_get_drvdata(dev);
3026 int ret;
3027
3028 ret = clk_prepare_enable(nfc->core_clk);
3029 if (ret < 0)
3030 return ret;
3031
3032 ret = clk_prepare_enable(nfc->reg_clk);
3033 if (ret < 0)
3034 return ret;
3035
3036 /*
3037 * Reset nfc->selected_chip so the next command will cause the timing
3038 * registers to be restored in marvell_nfc_select_target().
3039 */
3040 nfc->selected_chip = NULL;
3041
3042 /* Reset registers that have lost their contents */
3043 marvell_nfc_reset(nfc);
3044
3045 return 0;
3046 }
3047
3048 static const struct dev_pm_ops marvell_nfc_pm_ops = {
3049 SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume)
3050 };
3051
3052 static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
3053 .max_cs_nb = 4,
3054 .max_rb_nb = 2,
3055 .need_system_controller = true,
3056 .is_nfcv2 = true,
3057 };
3058
3059 static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
3060 .max_cs_nb = 4,
3061 .max_rb_nb = 2,
3062 .is_nfcv2 = true,
3063 };
3064
3065 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = {
3066 .max_cs_nb = 2,
3067 .max_rb_nb = 1,
3068 .use_dma = true,
3069 };
3070
3071 static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = {
3072 .max_cs_nb = 4,
3073 .max_rb_nb = 2,
3074 .need_system_controller = true,
3075 .legacy_of_bindings = true,
3076 .is_nfcv2 = true,
3077 };
3078
3079 static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = {
3080 .max_cs_nb = 4,
3081 .max_rb_nb = 2,
3082 .legacy_of_bindings = true,
3083 .is_nfcv2 = true,
3084 };
3085
3086 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = {
3087 .max_cs_nb = 2,
3088 .max_rb_nb = 1,
3089 .legacy_of_bindings = true,
3090 .use_dma = true,
3091 };
3092
3093 static const struct platform_device_id marvell_nfc_platform_ids[] = {
3094 {
3095 .name = "pxa3xx-nand",
3096 .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps,
3097 },
3098 { /* sentinel */ },
3099 };
3100 MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids);
3101
3102 static const struct of_device_id marvell_nfc_of_ids[] = {
3103 {
3104 .compatible = "marvell,armada-8k-nand-controller",
3105 .data = &marvell_armada_8k_nfc_caps,
3106 },
3107 {
3108 .compatible = "marvell,armada370-nand-controller",
3109 .data = &marvell_armada370_nfc_caps,
3110 },
3111 {
3112 .compatible = "marvell,pxa3xx-nand-controller",
3113 .data = &marvell_pxa3xx_nfc_caps,
3114 },
3115 /* Support for old/deprecated bindings: */
3116 {
3117 .compatible = "marvell,armada-8k-nand",
3118 .data = &marvell_armada_8k_nfc_legacy_caps,
3119 },
3120 {
3121 .compatible = "marvell,armada370-nand",
3122 .data = &marvell_armada370_nfc_legacy_caps,
3123 },
3124 {
3125 .compatible = "marvell,pxa3xx-nand",
3126 .data = &marvell_pxa3xx_nfc_legacy_caps,
3127 },
3128 { /* sentinel */ },
3129 };
3130 MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids);
3131
3132 static struct platform_driver marvell_nfc_driver = {
3133 .driver = {
3134 .name = "marvell-nfc",
3135 .of_match_table = marvell_nfc_of_ids,
3136 .pm = &marvell_nfc_pm_ops,
3137 },
3138 .id_table = marvell_nfc_platform_ids,
3139 .probe = marvell_nfc_probe,
3140 .remove = marvell_nfc_remove,
3141 };
3142 module_platform_driver(marvell_nfc_driver);
3143
3144 MODULE_LICENSE("GPL");
3145 MODULE_DESCRIPTION("Marvell NAND controller driver");
Linux with added FPC-III support