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WIP FPC-III support
[linux/fpc-iii.git] / drivers / mtd / nand / raw / meson_nand.c
blob817bddccb775f60f4636ee627d20e15a425b7e3f
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Amlogic Meson Nand Flash Controller Driver
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Liang Yang <liang.yang@amlogic.com>
7 */
8
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/clk.h>
13 #include <linux/mtd/rawnand.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/iopoll.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/sched/task_stack.h>
23
24 #define NFC_REG_CMD 0x00
25 #define NFC_CMD_IDLE (0xc << 14)
26 #define NFC_CMD_CLE (0x5 << 14)
27 #define NFC_CMD_ALE (0x6 << 14)
28 #define NFC_CMD_ADL ((0 << 16) | (3 << 20))
29 #define NFC_CMD_ADH ((1 << 16) | (3 << 20))
30 #define NFC_CMD_AIL ((2 << 16) | (3 << 20))
31 #define NFC_CMD_AIH ((3 << 16) | (3 << 20))
32 #define NFC_CMD_SEED ((8 << 16) | (3 << 20))
33 #define NFC_CMD_M2N ((0 << 17) | (2 << 20))
34 #define NFC_CMD_N2M ((1 << 17) | (2 << 20))
35 #define NFC_CMD_RB BIT(20)
36 #define NFC_CMD_SCRAMBLER_ENABLE BIT(19)
37 #define NFC_CMD_SCRAMBLER_DISABLE 0
38 #define NFC_CMD_SHORTMODE_DISABLE 0
39 #define NFC_CMD_RB_INT BIT(14)
40
41 #define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0))
42
43 #define NFC_REG_CFG 0x04
44 #define NFC_REG_DADR 0x08
45 #define NFC_REG_IADR 0x0c
46 #define NFC_REG_BUF 0x10
47 #define NFC_REG_INFO 0x14
48 #define NFC_REG_DC 0x18
49 #define NFC_REG_ADR 0x1c
50 #define NFC_REG_DL 0x20
51 #define NFC_REG_DH 0x24
52 #define NFC_REG_CADR 0x28
53 #define NFC_REG_SADR 0x2c
54 #define NFC_REG_PINS 0x30
55 #define NFC_REG_VER 0x38
56
57 #define NFC_RB_IRQ_EN BIT(21)
58
59 #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \
60 ( \
61 (cmd_dir) | \
62 ((ran) << 19) | \
63 ((bch) << 14) | \
64 ((short_mode) << 13) | \
65 (((page_size) & 0x7f) << 6) | \
66 ((pages) & 0x3f) \
67 )
68
69 #define GENCMDDADDRL(adl, addr) ((adl) | ((addr) & 0xffff))
70 #define GENCMDDADDRH(adh, addr) ((adh) | (((addr) >> 16) & 0xffff))
71 #define GENCMDIADDRL(ail, addr) ((ail) | ((addr) & 0xffff))
72 #define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff))
73
74 #define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
75
76 #define ECC_CHECK_RETURN_FF (-1)
77
78 #define NAND_CE0 (0xe << 10)
79 #define NAND_CE1 (0xd << 10)
80
81 #define DMA_BUSY_TIMEOUT 0x100000
82 #define CMD_FIFO_EMPTY_TIMEOUT 1000
83
84 #define MAX_CE_NUM 2
85
86 /* eMMC clock register, misc control */
87 #define CLK_SELECT_NAND BIT(31)
88
89 #define NFC_CLK_CYCLE 6
90
91 /* nand flash controller delay 3 ns */
92 #define NFC_DEFAULT_DELAY 3000
93
94 #define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff)
95 #define MAX_CYCLE_ADDRS 5
96 #define DIRREAD 1
97 #define DIRWRITE 0
98
99 #define ECC_PARITY_BCH8_512B 14
100 #define ECC_COMPLETE BIT(31)
101 #define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0))
102 #define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0))
103 #define ECC_UNCORRECTABLE 0x3f
104
105 #define PER_INFO_BYTE 8
106
107 struct meson_nfc_nand_chip {
108 struct list_head node;
109 struct nand_chip nand;
110 unsigned long clk_rate;
111 unsigned long level1_divider;
112 u32 bus_timing;
113 u32 twb;
114 u32 tadl;
115 u32 tbers_max;
116
117 u32 bch_mode;
118 u8 *data_buf;
119 __le64 *info_buf;
120 u32 nsels;
121 u8 sels[];
122 };
123
124 struct meson_nand_ecc {
125 u32 bch;
126 u32 strength;
127 };
128
129 struct meson_nfc_data {
130 const struct nand_ecc_caps *ecc_caps;
131 };
132
133 struct meson_nfc_param {
134 u32 chip_select;
135 u32 rb_select;
136 };
137
138 struct nand_rw_cmd {
139 u32 cmd0;
140 u32 addrs[MAX_CYCLE_ADDRS];
141 u32 cmd1;
142 };
143
144 struct nand_timing {
145 u32 twb;
146 u32 tadl;
147 u32 tbers_max;
148 };
149
150 struct meson_nfc {
151 struct nand_controller controller;
152 struct clk *core_clk;
153 struct clk *device_clk;
154 struct clk *phase_tx;
155 struct clk *phase_rx;
156
157 unsigned long clk_rate;
158 u32 bus_timing;
159
160 struct device *dev;
161 void __iomem *reg_base;
162 struct regmap *reg_clk;
163 struct completion completion;
164 struct list_head chips;
165 const struct meson_nfc_data *data;
166 struct meson_nfc_param param;
167 struct nand_timing timing;
168 union {
169 int cmd[32];
170 struct nand_rw_cmd rw;
171 } cmdfifo;
172
173 dma_addr_t daddr;
174 dma_addr_t iaddr;
175
176 unsigned long assigned_cs;
177 };
178
179 enum {
180 NFC_ECC_BCH8_1K = 2,
181 NFC_ECC_BCH24_1K,
182 NFC_ECC_BCH30_1K,
183 NFC_ECC_BCH40_1K,
184 NFC_ECC_BCH50_1K,
185 NFC_ECC_BCH60_1K,
186 };
187
188 #define MESON_ECC_DATA(b, s) { .bch = (b), .strength = (s)}
189
190 static struct meson_nand_ecc meson_ecc[] = {
191 MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8),
192 MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24),
193 MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30),
194 MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40),
195 MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50),
196 MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60),
197 };
198
199 static int meson_nand_calc_ecc_bytes(int step_size, int strength)
200 {
201 int ecc_bytes;
202
203 if (step_size == 512 && strength == 8)
204 return ECC_PARITY_BCH8_512B;
205
206 ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8);
207 ecc_bytes = ALIGN(ecc_bytes, 2);
208
209 return ecc_bytes;
210 }
211
212 NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps,
213 meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60);
214 NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps,
215 meson_nand_calc_ecc_bytes, 1024, 8);
216
217 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand)
218 {
219 return container_of(nand, struct meson_nfc_nand_chip, nand);
220 }
221
222 static void meson_nfc_select_chip(struct nand_chip *nand, int chip)
223 {
224 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
225 struct meson_nfc *nfc = nand_get_controller_data(nand);
226 int ret, value;
227
228 if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels))
229 return;
230
231 nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
232 nfc->param.rb_select = nfc->param.chip_select;
233 nfc->timing.twb = meson_chip->twb;
234 nfc->timing.tadl = meson_chip->tadl;
235 nfc->timing.tbers_max = meson_chip->tbers_max;
236
237 if (nfc->clk_rate != meson_chip->clk_rate) {
238 ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate);
239 if (ret) {
240 dev_err(nfc->dev, "failed to set clock rate\n");
241 return;
242 }
243 nfc->clk_rate = meson_chip->clk_rate;
244 }
245 if (nfc->bus_timing != meson_chip->bus_timing) {
246 value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5);
247 writel(value, nfc->reg_base + NFC_REG_CFG);
248 writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
249 nfc->bus_timing = meson_chip->bus_timing;
250 }
251 }
252
253 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
254 {
255 writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
256 nfc->reg_base + NFC_REG_CMD);
257 }
258
259 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
260 {
261 writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)),
262 nfc->reg_base + NFC_REG_CMD);
263 }
264
265 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir,
266 int scrambler)
267 {
268 struct mtd_info *mtd = nand_to_mtd(nand);
269 struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
270 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
271 u32 bch = meson_chip->bch_mode, cmd;
272 int len = mtd->writesize, pagesize, pages;
273
274 pagesize = nand->ecc.size;
275
276 if (raw) {
277 len = mtd->writesize + mtd->oobsize;
278 cmd = (len & GENMASK(5, 0)) | scrambler | DMA_DIR(dir);
279 writel(cmd, nfc->reg_base + NFC_REG_CMD);
280 return;
281 }
282
283 pages = len / nand->ecc.size;
284
285 cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
286 NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
287
288 writel(cmd, nfc->reg_base + NFC_REG_CMD);
289 }
290
291 static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
292 {
293 /*
294 * Insert two commands to make sure all valid commands are finished.
295 *
296 * The Nand flash controller is designed as two stages pipleline -
297 * a) fetch and b) excute.
298 * There might be cases when the driver see command queue is empty,
299 * but the Nand flash controller still has two commands buffered,
300 * one is fetched into NFC request queue (ready to run), and another
301 * is actively executing. So pushing 2 "IDLE" commands guarantees that
302 * the pipeline is emptied.
303 */
304 meson_nfc_cmd_idle(nfc, 0);
305 meson_nfc_cmd_idle(nfc, 0);
306 }
307
308 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
309 unsigned int timeout_ms)
310 {
311 u32 cmd_size = 0;
312 int ret;
313
314 /* wait cmd fifo is empty */
315 ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
316 !NFC_CMD_GET_SIZE(cmd_size),
317 10, timeout_ms * 1000);
318 if (ret)
319 dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
320
321 return ret;
322 }
323
324 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
325 {
326 meson_nfc_drain_cmd(nfc);
327
328 return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
329 }
330
331 static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i)
332 {
333 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
334 int len;
335
336 len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i;
337
338 return meson_chip->data_buf + len;
339 }
340
341 static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i)
342 {
343 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
344 int len, temp;
345
346 temp = nand->ecc.size + nand->ecc.bytes;
347 len = (temp + 2) * i;
348
349 return meson_chip->data_buf + len;
350 }
351
352 static void meson_nfc_get_data_oob(struct nand_chip *nand,
353 u8 *buf, u8 *oobbuf)
354 {
355 int i, oob_len = 0;
356 u8 *dsrc, *osrc;
357
358 oob_len = nand->ecc.bytes + 2;
359 for (i = 0; i < nand->ecc.steps; i++) {
360 if (buf) {
361 dsrc = meson_nfc_data_ptr(nand, i);
362 memcpy(buf, dsrc, nand->ecc.size);
363 buf += nand->ecc.size;
364 }
365 osrc = meson_nfc_oob_ptr(nand, i);
366 memcpy(oobbuf, osrc, oob_len);
367 oobbuf += oob_len;
368 }
369 }
370
371 static void meson_nfc_set_data_oob(struct nand_chip *nand,
372 const u8 *buf, u8 *oobbuf)
373 {
374 int i, oob_len = 0;
375 u8 *dsrc, *osrc;
376
377 oob_len = nand->ecc.bytes + 2;
378 for (i = 0; i < nand->ecc.steps; i++) {
379 if (buf) {
380 dsrc = meson_nfc_data_ptr(nand, i);
381 memcpy(dsrc, buf, nand->ecc.size);
382 buf += nand->ecc.size;
383 }
384 osrc = meson_nfc_oob_ptr(nand, i);
385 memcpy(osrc, oobbuf, oob_len);
386 oobbuf += oob_len;
387 }
388 }
389
390 static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
391 {
392 u32 cmd, cfg;
393 int ret = 0;
394
395 meson_nfc_cmd_idle(nfc, nfc->timing.twb);
396 meson_nfc_drain_cmd(nfc);
397 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
398
399 cfg = readl(nfc->reg_base + NFC_REG_CFG);
400 cfg |= NFC_RB_IRQ_EN;
401 writel(cfg, nfc->reg_base + NFC_REG_CFG);
402
403 reinit_completion(&nfc->completion);
404
405 /* use the max erase time as the maximum clock for waiting R/B */
406 cmd = NFC_CMD_RB | NFC_CMD_RB_INT
407 | nfc->param.chip_select | nfc->timing.tbers_max;
408 writel(cmd, nfc->reg_base + NFC_REG_CMD);
409
410 ret = wait_for_completion_timeout(&nfc->completion,
411 msecs_to_jiffies(timeout_ms));
412 if (ret == 0)
413 ret = -1;
414
415 return ret;
416 }
417
418 static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)
419 {
420 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
421 __le64 *info;
422 int i, count;
423
424 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
425 info = &meson_chip->info_buf[i];
426 *info |= oob_buf[count];
427 *info |= oob_buf[count + 1] << 8;
428 }
429 }
430
431 static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf)
432 {
433 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
434 __le64 *info;
435 int i, count;
436
437 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
438 info = &meson_chip->info_buf[i];
439 oob_buf[count] = *info;
440 oob_buf[count + 1] = *info >> 8;
441 }
442 }
443
444 static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips,
445 u64 *correct_bitmap)
446 {
447 struct mtd_info *mtd = nand_to_mtd(nand);
448 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
449 __le64 *info;
450 int ret = 0, i;
451
452 for (i = 0; i < nand->ecc.steps; i++) {
453 info = &meson_chip->info_buf[i];
454 if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) {
455 mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
456 *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info));
457 *correct_bitmap |= 1 >> i;
458 continue;
459 }
460 if ((nand->options & NAND_NEED_SCRAMBLING) &&
461 ECC_ZERO_CNT(*info) < nand->ecc.strength) {
462 mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info);
463 *bitflips = max_t(u32, *bitflips,
464 ECC_ZERO_CNT(*info));
465 ret = ECC_CHECK_RETURN_FF;
466 } else {
467 ret = -EBADMSG;
468 }
469 }
470 return ret;
471 }
472
473 static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf,
474 int datalen, void *infobuf, int infolen,
475 enum dma_data_direction dir)
476 {
477 struct meson_nfc *nfc = nand_get_controller_data(nand);
478 u32 cmd;
479 int ret = 0;
480
481 nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir);
482 ret = dma_mapping_error(nfc->dev, nfc->daddr);
483 if (ret) {
484 dev_err(nfc->dev, "DMA mapping error\n");
485 return ret;
486 }
487 cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
488 writel(cmd, nfc->reg_base + NFC_REG_CMD);
489
490 cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
491 writel(cmd, nfc->reg_base + NFC_REG_CMD);
492
493 if (infobuf) {
494 nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
495 ret = dma_mapping_error(nfc->dev, nfc->iaddr);
496 if (ret) {
497 dev_err(nfc->dev, "DMA mapping error\n");
498 dma_unmap_single(nfc->dev,
499 nfc->daddr, datalen, dir);
500 return ret;
501 }
502 cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
503 writel(cmd, nfc->reg_base + NFC_REG_CMD);
504
505 cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
506 writel(cmd, nfc->reg_base + NFC_REG_CMD);
507 }
508
509 return ret;
510 }
511
512 static void meson_nfc_dma_buffer_release(struct nand_chip *nand,
513 int datalen, int infolen,
514 enum dma_data_direction dir)
515 {
516 struct meson_nfc *nfc = nand_get_controller_data(nand);
517
518 dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
519 if (infolen)
520 dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
521 }
522
523 static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
524 {
525 struct meson_nfc *nfc = nand_get_controller_data(nand);
526 int ret = 0;
527 u32 cmd;
528 u8 *info;
529
530 info = kzalloc(PER_INFO_BYTE, GFP_KERNEL);
531 if (!info)
532 return -ENOMEM;
533
534 ret = meson_nfc_dma_buffer_setup(nand, buf, len, info,
535 PER_INFO_BYTE, DMA_FROM_DEVICE);
536 if (ret)
537 goto out;
538
539 cmd = NFC_CMD_N2M | (len & GENMASK(5, 0));
540 writel(cmd, nfc->reg_base + NFC_REG_CMD);
541
542 meson_nfc_drain_cmd(nfc);
543 meson_nfc_wait_cmd_finish(nfc, 1000);
544 meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE);
545
546 out:
547 kfree(info);
548
549 return ret;
550 }
551
552 static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len)
553 {
554 struct meson_nfc *nfc = nand_get_controller_data(nand);
555 int ret = 0;
556 u32 cmd;
557
558 ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL,
559 0, DMA_TO_DEVICE);
560 if (ret)
561 return ret;
562
563 cmd = NFC_CMD_M2N | (len & GENMASK(5, 0));
564 writel(cmd, nfc->reg_base + NFC_REG_CMD);
565
566 meson_nfc_drain_cmd(nfc);
567 meson_nfc_wait_cmd_finish(nfc, 1000);
568 meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE);
569
570 return ret;
571 }
572
573 static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
574 int page, bool in)
575 {
576 const struct nand_sdr_timings *sdr =
577 nand_get_sdr_timings(nand_get_interface_config(nand));
578 struct mtd_info *mtd = nand_to_mtd(nand);
579 struct meson_nfc *nfc = nand_get_controller_data(nand);
580 u32 *addrs = nfc->cmdfifo.rw.addrs;
581 u32 cs = nfc->param.chip_select;
582 u32 cmd0, cmd_num, row_start;
583 int ret = 0, i;
584
585 cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int);
586
587 cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
588 nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
589
590 addrs[0] = cs | NFC_CMD_ALE | 0;
591 if (mtd->writesize <= 512) {
592 cmd_num--;
593 row_start = 1;
594 } else {
595 addrs[1] = cs | NFC_CMD_ALE | 0;
596 row_start = 2;
597 }
598
599 addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0);
600 addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1);
601
602 if (nand->options & NAND_ROW_ADDR_3)
603 addrs[row_start + 2] =
604 cs | NFC_CMD_ALE | ROW_ADDER(page, 2);
605 else
606 cmd_num--;
607
608 /* subtract cmd1 */
609 cmd_num--;
610
611 for (i = 0; i < cmd_num; i++)
612 writel_relaxed(nfc->cmdfifo.cmd[i],
613 nfc->reg_base + NFC_REG_CMD);
614
615 if (in) {
616 nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
617 writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
618 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max));
619 } else {
620 meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
621 }
622
623 return ret;
624 }
625
626 static int meson_nfc_write_page_sub(struct nand_chip *nand,
627 int page, int raw)
628 {
629 const struct nand_sdr_timings *sdr =
630 nand_get_sdr_timings(nand_get_interface_config(nand));
631 struct mtd_info *mtd = nand_to_mtd(nand);
632 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
633 struct meson_nfc *nfc = nand_get_controller_data(nand);
634 int data_len, info_len;
635 u32 cmd;
636 int ret;
637
638 meson_nfc_select_chip(nand, nand->cur_cs);
639
640 data_len = mtd->writesize + mtd->oobsize;
641 info_len = nand->ecc.steps * PER_INFO_BYTE;
642
643 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE);
644 if (ret)
645 return ret;
646
647 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
648 data_len, meson_chip->info_buf,
649 info_len, DMA_TO_DEVICE);
650 if (ret)
651 return ret;
652
653 if (nand->options & NAND_NEED_SCRAMBLING) {
654 meson_nfc_cmd_seed(nfc, page);
655 meson_nfc_cmd_access(nand, raw, DIRWRITE,
656 NFC_CMD_SCRAMBLER_ENABLE);
657 } else {
658 meson_nfc_cmd_access(nand, raw, DIRWRITE,
659 NFC_CMD_SCRAMBLER_DISABLE);
660 }
661
662 cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
663 writel(cmd, nfc->reg_base + NFC_REG_CMD);
664 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max));
665
666 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE);
667
668 return ret;
669 }
670
671 static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf,
672 int oob_required, int page)
673 {
674 u8 *oob_buf = nand->oob_poi;
675
676 meson_nfc_set_data_oob(nand, buf, oob_buf);
677
678 return meson_nfc_write_page_sub(nand, page, 1);
679 }
680
681 static int meson_nfc_write_page_hwecc(struct nand_chip *nand,
682 const u8 *buf, int oob_required, int page)
683 {
684 struct mtd_info *mtd = nand_to_mtd(nand);
685 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
686 u8 *oob_buf = nand->oob_poi;
687
688 memcpy(meson_chip->data_buf, buf, mtd->writesize);
689 memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);
690 meson_nfc_set_user_byte(nand, oob_buf);
691
692 return meson_nfc_write_page_sub(nand, page, 0);
693 }
694
695 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
696 struct nand_chip *nand, int raw)
697 {
698 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
699 __le64 *info;
700 u32 neccpages;
701 int ret;
702
703 neccpages = raw ? 1 : nand->ecc.steps;
704 info = &meson_chip->info_buf[neccpages - 1];
705 do {
706 usleep_range(10, 15);
707 /* info is updated by nfc dma engine*/
708 smp_rmb();
709 ret = *info & ECC_COMPLETE;
710 } while (!ret);
711 }
712
713 static int meson_nfc_read_page_sub(struct nand_chip *nand,
714 int page, int raw)
715 {
716 struct mtd_info *mtd = nand_to_mtd(nand);
717 struct meson_nfc *nfc = nand_get_controller_data(nand);
718 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
719 int data_len, info_len;
720 int ret;
721
722 meson_nfc_select_chip(nand, nand->cur_cs);
723
724 data_len = mtd->writesize + mtd->oobsize;
725 info_len = nand->ecc.steps * PER_INFO_BYTE;
726
727 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD);
728 if (ret)
729 return ret;
730
731 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
732 data_len, meson_chip->info_buf,
733 info_len, DMA_FROM_DEVICE);
734 if (ret)
735 return ret;
736
737 if (nand->options & NAND_NEED_SCRAMBLING) {
738 meson_nfc_cmd_seed(nfc, page);
739 meson_nfc_cmd_access(nand, raw, DIRREAD,
740 NFC_CMD_SCRAMBLER_ENABLE);
741 } else {
742 meson_nfc_cmd_access(nand, raw, DIRREAD,
743 NFC_CMD_SCRAMBLER_DISABLE);
744 }
745
746 ret = meson_nfc_wait_dma_finish(nfc);
747 meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
748
749 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE);
750
751 return ret;
752 }
753
754 static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf,
755 int oob_required, int page)
756 {
757 u8 *oob_buf = nand->oob_poi;
758 int ret;
759
760 ret = meson_nfc_read_page_sub(nand, page, 1);
761 if (ret)
762 return ret;
763
764 meson_nfc_get_data_oob(nand, buf, oob_buf);
765
766 return 0;
767 }
768
769 static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf,
770 int oob_required, int page)
771 {
772 struct mtd_info *mtd = nand_to_mtd(nand);
773 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
774 struct nand_ecc_ctrl *ecc = &nand->ecc;
775 u64 correct_bitmap = 0;
776 u32 bitflips = 0;
777 u8 *oob_buf = nand->oob_poi;
778 int ret, i;
779
780 ret = meson_nfc_read_page_sub(nand, page, 0);
781 if (ret)
782 return ret;
783
784 meson_nfc_get_user_byte(nand, oob_buf);
785 ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap);
786 if (ret == ECC_CHECK_RETURN_FF) {
787 if (buf)
788 memset(buf, 0xff, mtd->writesize);
789 memset(oob_buf, 0xff, mtd->oobsize);
790 } else if (ret < 0) {
791 if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) {
792 mtd->ecc_stats.failed++;
793 return bitflips;
794 }
795 ret = meson_nfc_read_page_raw(nand, buf, 0, page);
796 if (ret)
797 return ret;
798
799 for (i = 0; i < nand->ecc.steps ; i++) {
800 u8 *data = buf + i * ecc->size;
801 u8 *oob = nand->oob_poi + i * (ecc->bytes + 2);
802
803 if (correct_bitmap & (1 << i))
804 continue;
805 ret = nand_check_erased_ecc_chunk(data, ecc->size,
806 oob, ecc->bytes + 2,
807 NULL, 0,
808 ecc->strength);
809 if (ret < 0) {
810 mtd->ecc_stats.failed++;
811 } else {
812 mtd->ecc_stats.corrected += ret;
813 bitflips = max_t(u32, bitflips, ret);
814 }
815 }
816 } else if (buf && buf != meson_chip->data_buf) {
817 memcpy(buf, meson_chip->data_buf, mtd->writesize);
818 }
819
820 return bitflips;
821 }
822
823 static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page)
824 {
825 return meson_nfc_read_page_raw(nand, NULL, 1, page);
826 }
827
828 static int meson_nfc_read_oob(struct nand_chip *nand, int page)
829 {
830 return meson_nfc_read_page_hwecc(nand, NULL, 1, page);
831 }
832
833 static bool meson_nfc_is_buffer_dma_safe(const void *buffer)
834 {
835 if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer)))
836 return true;
837 return false;
838 }
839
840 static void *
841 meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr)
842 {
843 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR))
844 return NULL;
845
846 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in))
847 return instr->ctx.data.buf.in;
848
849 return kzalloc(instr->ctx.data.len, GFP_KERNEL);
850 }
851
852 static void
853 meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr,
854 void *buf)
855 {
856 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) ||
857 WARN_ON(!buf))
858 return;
859
860 if (buf == instr->ctx.data.buf.in)
861 return;
862
863 memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len);
864 kfree(buf);
865 }
866
867 static void *
868 meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr)
869 {
870 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR))
871 return NULL;
872
873 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out))
874 return (void *)instr->ctx.data.buf.out;
875
876 return kmemdup(instr->ctx.data.buf.out,
877 instr->ctx.data.len, GFP_KERNEL);
878 }
879
880 static void
881 meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr,
882 const void *buf)
883 {
884 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) ||
885 WARN_ON(!buf))
886 return;
887
888 if (buf != instr->ctx.data.buf.out)
889 kfree(buf);
890 }
891
892 static int meson_nfc_exec_op(struct nand_chip *nand,
893 const struct nand_operation *op, bool check_only)
894 {
895 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
896 struct meson_nfc *nfc = nand_get_controller_data(nand);
897 const struct nand_op_instr *instr = NULL;
898 void *buf;
899 u32 op_id, delay_idle, cmd;
900 int i;
901
902 if (check_only)
903 return 0;
904
905 meson_nfc_select_chip(nand, op->cs);
906 for (op_id = 0; op_id < op->ninstrs; op_id++) {
907 instr = &op->instrs[op_id];
908 delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns),
909 meson_chip->level1_divider *
910 NFC_CLK_CYCLE);
911 switch (instr->type) {
912 case NAND_OP_CMD_INSTR:
913 cmd = nfc->param.chip_select | NFC_CMD_CLE;
914 cmd |= instr->ctx.cmd.opcode & 0xff;
915 writel(cmd, nfc->reg_base + NFC_REG_CMD);
916 meson_nfc_cmd_idle(nfc, delay_idle);
917 break;
918
919 case NAND_OP_ADDR_INSTR:
920 for (i = 0; i < instr->ctx.addr.naddrs; i++) {
921 cmd = nfc->param.chip_select | NFC_CMD_ALE;
922 cmd |= instr->ctx.addr.addrs[i] & 0xff;
923 writel(cmd, nfc->reg_base + NFC_REG_CMD);
924 }
925 meson_nfc_cmd_idle(nfc, delay_idle);
926 break;
927
928 case NAND_OP_DATA_IN_INSTR:
929 buf = meson_nand_op_get_dma_safe_input_buf(instr);
930 if (!buf)
931 return -ENOMEM;
932 meson_nfc_read_buf(nand, buf, instr->ctx.data.len);
933 meson_nand_op_put_dma_safe_input_buf(instr, buf);
934 break;
935
936 case NAND_OP_DATA_OUT_INSTR:
937 buf = meson_nand_op_get_dma_safe_output_buf(instr);
938 if (!buf)
939 return -ENOMEM;
940 meson_nfc_write_buf(nand, buf, instr->ctx.data.len);
941 meson_nand_op_put_dma_safe_output_buf(instr, buf);
942 break;
943
944 case NAND_OP_WAITRDY_INSTR:
945 meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms);
946 if (instr->delay_ns)
947 meson_nfc_cmd_idle(nfc, delay_idle);
948 break;
949 }
950 }
951 meson_nfc_wait_cmd_finish(nfc, 1000);
952 return 0;
953 }
954
955 static int meson_ooblayout_ecc(struct mtd_info *mtd, int section,
956 struct mtd_oob_region *oobregion)
957 {
958 struct nand_chip *nand = mtd_to_nand(mtd);
959
960 if (section >= nand->ecc.steps)
961 return -ERANGE;
962
963 oobregion->offset = 2 + (section * (2 + nand->ecc.bytes));
964 oobregion->length = nand->ecc.bytes;
965
966 return 0;
967 }
968
969 static int meson_ooblayout_free(struct mtd_info *mtd, int section,
970 struct mtd_oob_region *oobregion)
971 {
972 struct nand_chip *nand = mtd_to_nand(mtd);
973
974 if (section >= nand->ecc.steps)
975 return -ERANGE;
976
977 oobregion->offset = section * (2 + nand->ecc.bytes);
978 oobregion->length = 2;
979
980 return 0;
981 }
982
983 static const struct mtd_ooblayout_ops meson_ooblayout_ops = {
984 .ecc = meson_ooblayout_ecc,
985 .free = meson_ooblayout_free,
986 };
987
988 static int meson_nfc_clk_init(struct meson_nfc *nfc)
989 {
990 int ret;
991
992 /* request core clock */
993 nfc->core_clk = devm_clk_get(nfc->dev, "core");
994 if (IS_ERR(nfc->core_clk)) {
995 dev_err(nfc->dev, "failed to get core clock\n");
996 return PTR_ERR(nfc->core_clk);
997 }
998
999 nfc->device_clk = devm_clk_get(nfc->dev, "device");
1000 if (IS_ERR(nfc->device_clk)) {
1001 dev_err(nfc->dev, "failed to get device clock\n");
1002 return PTR_ERR(nfc->device_clk);
1003 }
1004
1005 nfc->phase_tx = devm_clk_get(nfc->dev, "tx");
1006 if (IS_ERR(nfc->phase_tx)) {
1007 dev_err(nfc->dev, "failed to get TX clk\n");
1008 return PTR_ERR(nfc->phase_tx);
1009 }
1010
1011 nfc->phase_rx = devm_clk_get(nfc->dev, "rx");
1012 if (IS_ERR(nfc->phase_rx)) {
1013 dev_err(nfc->dev, "failed to get RX clk\n");
1014 return PTR_ERR(nfc->phase_rx);
1015 }
1016
1017 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
1018 regmap_update_bits(nfc->reg_clk,
1019 0, CLK_SELECT_NAND, CLK_SELECT_NAND);
1020
1021 ret = clk_prepare_enable(nfc->core_clk);
1022 if (ret) {
1023 dev_err(nfc->dev, "failed to enable core clock\n");
1024 return ret;
1025 }
1026
1027 ret = clk_prepare_enable(nfc->device_clk);
1028 if (ret) {
1029 dev_err(nfc->dev, "failed to enable device clock\n");
1030 goto err_device_clk;
1031 }
1032
1033 ret = clk_prepare_enable(nfc->phase_tx);
1034 if (ret) {
1035 dev_err(nfc->dev, "failed to enable TX clock\n");
1036 goto err_phase_tx;
1037 }
1038
1039 ret = clk_prepare_enable(nfc->phase_rx);
1040 if (ret) {
1041 dev_err(nfc->dev, "failed to enable RX clock\n");
1042 goto err_phase_rx;
1043 }
1044
1045 ret = clk_set_rate(nfc->device_clk, 24000000);
1046 if (ret)
1047 goto err_disable_rx;
1048
1049 return 0;
1050
1051 err_disable_rx:
1052 clk_disable_unprepare(nfc->phase_rx);
1053 err_phase_rx:
1054 clk_disable_unprepare(nfc->phase_tx);
1055 err_phase_tx:
1056 clk_disable_unprepare(nfc->device_clk);
1057 err_device_clk:
1058 clk_disable_unprepare(nfc->core_clk);
1059 return ret;
1060 }
1061
1062 static void meson_nfc_disable_clk(struct meson_nfc *nfc)
1063 {
1064 clk_disable_unprepare(nfc->phase_rx);
1065 clk_disable_unprepare(nfc->phase_tx);
1066 clk_disable_unprepare(nfc->device_clk);
1067 clk_disable_unprepare(nfc->core_clk);
1068 }
1069
1070 static void meson_nfc_free_buffer(struct nand_chip *nand)
1071 {
1072 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1073
1074 kfree(meson_chip->info_buf);
1075 kfree(meson_chip->data_buf);
1076 }
1077
1078 static int meson_chip_buffer_init(struct nand_chip *nand)
1079 {
1080 struct mtd_info *mtd = nand_to_mtd(nand);
1081 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1082 u32 page_bytes, info_bytes, nsectors;
1083
1084 nsectors = mtd->writesize / nand->ecc.size;
1085
1086 page_bytes = mtd->writesize + mtd->oobsize;
1087 info_bytes = nsectors * PER_INFO_BYTE;
1088
1089 meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL);
1090 if (!meson_chip->data_buf)
1091 return -ENOMEM;
1092
1093 meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL);
1094 if (!meson_chip->info_buf) {
1095 kfree(meson_chip->data_buf);
1096 return -ENOMEM;
1097 }
1098
1099 return 0;
1100 }
1101
1102 static
1103 int meson_nfc_setup_interface(struct nand_chip *nand, int csline,
1104 const struct nand_interface_config *conf)
1105 {
1106 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1107 const struct nand_sdr_timings *timings;
1108 u32 div, bt_min, bt_max, tbers_clocks;
1109
1110 timings = nand_get_sdr_timings(conf);
1111 if (IS_ERR(timings))
1112 return -ENOTSUPP;
1113
1114 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1115 return 0;
1116
1117 div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE);
1118 bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div;
1119 bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min +
1120 timings->tRC_min / 2) / div;
1121
1122 meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
1123 div * NFC_CLK_CYCLE);
1124 meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min),
1125 div * NFC_CLK_CYCLE);
1126 tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max),
1127 div * NFC_CLK_CYCLE);
1128 meson_chip->tbers_max = ilog2(tbers_clocks);
1129 if (!is_power_of_2(tbers_clocks))
1130 meson_chip->tbers_max++;
1131
1132 bt_min = DIV_ROUND_UP(bt_min, 1000);
1133 bt_max = DIV_ROUND_UP(bt_max, 1000);
1134
1135 if (bt_max < bt_min)
1136 return -EINVAL;
1137
1138 meson_chip->level1_divider = div;
1139 meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
1140 meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1;
1141
1142 return 0;
1143 }
1144
1145 static int meson_nand_bch_mode(struct nand_chip *nand)
1146 {
1147 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1148 int i;
1149
1150 if (nand->ecc.strength > 60 || nand->ecc.strength < 8)
1151 return -EINVAL;
1152
1153 for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) {
1154 if (meson_ecc[i].strength == nand->ecc.strength) {
1155 meson_chip->bch_mode = meson_ecc[i].bch;
1156 return 0;
1157 }
1158 }
1159
1160 return -EINVAL;
1161 }
1162
1163 static void meson_nand_detach_chip(struct nand_chip *nand)
1164 {
1165 meson_nfc_free_buffer(nand);
1166 }
1167
1168 static int meson_nand_attach_chip(struct nand_chip *nand)
1169 {
1170 struct meson_nfc *nfc = nand_get_controller_data(nand);
1171 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1172 struct mtd_info *mtd = nand_to_mtd(nand);
1173 int nsectors = mtd->writesize / 1024;
1174 int ret;
1175
1176 if (!mtd->name) {
1177 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1178 "%s:nand%d",
1179 dev_name(nfc->dev),
1180 meson_chip->sels[0]);
1181 if (!mtd->name)
1182 return -ENOMEM;
1183 }
1184
1185 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1186 nand->bbt_options |= NAND_BBT_NO_OOB;
1187
1188 nand->options |= NAND_NO_SUBPAGE_WRITE;
1189
1190 ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
1191 mtd->oobsize - 2 * nsectors);
1192 if (ret) {
1193 dev_err(nfc->dev, "failed to ECC init\n");
1194 return -EINVAL;
1195 }
1196
1197 mtd_set_ooblayout(mtd, &meson_ooblayout_ops);
1198
1199 ret = meson_nand_bch_mode(nand);
1200 if (ret)
1201 return -EINVAL;
1202
1203 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1204 nand->ecc.write_page_raw = meson_nfc_write_page_raw;
1205 nand->ecc.write_page = meson_nfc_write_page_hwecc;
1206 nand->ecc.write_oob_raw = nand_write_oob_std;
1207 nand->ecc.write_oob = nand_write_oob_std;
1208
1209 nand->ecc.read_page_raw = meson_nfc_read_page_raw;
1210 nand->ecc.read_page = meson_nfc_read_page_hwecc;
1211 nand->ecc.read_oob_raw = meson_nfc_read_oob_raw;
1212 nand->ecc.read_oob = meson_nfc_read_oob;
1213
1214 if (nand->options & NAND_BUSWIDTH_16) {
1215 dev_err(nfc->dev, "16bits bus width not supported");
1216 return -EINVAL;
1217 }
1218 ret = meson_chip_buffer_init(nand);
1219 if (ret)
1220 return -ENOMEM;
1221
1222 return ret;
1223 }
1224
1225 static const struct nand_controller_ops meson_nand_controller_ops = {
1226 .attach_chip = meson_nand_attach_chip,
1227 .detach_chip = meson_nand_detach_chip,
1228 .setup_interface = meson_nfc_setup_interface,
1229 .exec_op = meson_nfc_exec_op,
1230 };
1231
1232 static int
1233 meson_nfc_nand_chip_init(struct device *dev,
1234 struct meson_nfc *nfc, struct device_node *np)
1235 {
1236 struct meson_nfc_nand_chip *meson_chip;
1237 struct nand_chip *nand;
1238 struct mtd_info *mtd;
1239 int ret, i;
1240 u32 tmp, nsels;
1241
1242 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
1243 if (!nsels || nsels > MAX_CE_NUM) {
1244 dev_err(dev, "invalid register property size\n");
1245 return -EINVAL;
1246 }
1247
1248 meson_chip = devm_kzalloc(dev, struct_size(meson_chip, sels, nsels),
1249 GFP_KERNEL);
1250 if (!meson_chip)
1251 return -ENOMEM;
1252
1253 meson_chip->nsels = nsels;
1254
1255 for (i = 0; i < nsels; i++) {
1256 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1257 if (ret) {
1258 dev_err(dev, "could not retrieve register property: %d\n",
1259 ret);
1260 return ret;
1261 }
1262
1263 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1264 dev_err(dev, "CS %d already assigned\n", tmp);
1265 return -EINVAL;
1266 }
1267 }
1268
1269 nand = &meson_chip->nand;
1270 nand->controller = &nfc->controller;
1271 nand->controller->ops = &meson_nand_controller_ops;
1272 nand_set_flash_node(nand, np);
1273 nand_set_controller_data(nand, nfc);
1274
1275 nand->options |= NAND_USES_DMA;
1276 mtd = nand_to_mtd(nand);
1277 mtd->owner = THIS_MODULE;
1278 mtd->dev.parent = dev;
1279
1280 ret = nand_scan(nand, nsels);
1281 if (ret)
1282 return ret;
1283
1284 ret = mtd_device_register(mtd, NULL, 0);
1285 if (ret) {
1286 dev_err(dev, "failed to register MTD device: %d\n", ret);
1287 nand_cleanup(nand);
1288 return ret;
1289 }
1290
1291 list_add_tail(&meson_chip->node, &nfc->chips);
1292
1293 return 0;
1294 }
1295
1296 static int meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1297 {
1298 struct meson_nfc_nand_chip *meson_chip;
1299 struct mtd_info *mtd;
1300 int ret;
1301
1302 while (!list_empty(&nfc->chips)) {
1303 meson_chip = list_first_entry(&nfc->chips,
1304 struct meson_nfc_nand_chip, node);
1305 mtd = nand_to_mtd(&meson_chip->nand);
1306 ret = mtd_device_unregister(mtd);
1307 if (ret)
1308 return ret;
1309
1310 meson_nfc_free_buffer(&meson_chip->nand);
1311 nand_cleanup(&meson_chip->nand);
1312 list_del(&meson_chip->node);
1313 }
1314
1315 return 0;
1316 }
1317
1318 static int meson_nfc_nand_chips_init(struct device *dev,
1319 struct meson_nfc *nfc)
1320 {
1321 struct device_node *np = dev->of_node;
1322 struct device_node *nand_np;
1323 int ret;
1324
1325 for_each_child_of_node(np, nand_np) {
1326 ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1327 if (ret) {
1328 meson_nfc_nand_chip_cleanup(nfc);
1329 of_node_put(nand_np);
1330 return ret;
1331 }
1332 }
1333
1334 return 0;
1335 }
1336
1337 static irqreturn_t meson_nfc_irq(int irq, void *id)
1338 {
1339 struct meson_nfc *nfc = id;
1340 u32 cfg;
1341
1342 cfg = readl(nfc->reg_base + NFC_REG_CFG);
1343 if (!(cfg & NFC_RB_IRQ_EN))
1344 return IRQ_NONE;
1345
1346 cfg &= ~(NFC_RB_IRQ_EN);
1347 writel(cfg, nfc->reg_base + NFC_REG_CFG);
1348
1349 complete(&nfc->completion);
1350 return IRQ_HANDLED;
1351 }
1352
1353 static const struct meson_nfc_data meson_gxl_data = {
1354 .ecc_caps = &meson_gxl_ecc_caps,
1355 };
1356
1357 static const struct meson_nfc_data meson_axg_data = {
1358 .ecc_caps = &meson_axg_ecc_caps,
1359 };
1360
1361 static const struct of_device_id meson_nfc_id_table[] = {
1362 {
1363 .compatible = "amlogic,meson-gxl-nfc",
1364 .data = &meson_gxl_data,
1365 }, {
1366 .compatible = "amlogic,meson-axg-nfc",
1367 .data = &meson_axg_data,
1368 },
1369 {}
1370 };
1371 MODULE_DEVICE_TABLE(of, meson_nfc_id_table);
1372
1373 static int meson_nfc_probe(struct platform_device *pdev)
1374 {
1375 struct device *dev = &pdev->dev;
1376 struct meson_nfc *nfc;
1377 struct resource *res;
1378 int ret, irq;
1379
1380 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1381 if (!nfc)
1382 return -ENOMEM;
1383
1384 nfc->data = of_device_get_match_data(&pdev->dev);
1385 if (!nfc->data)
1386 return -ENODEV;
1387
1388 nand_controller_init(&nfc->controller);
1389 INIT_LIST_HEAD(&nfc->chips);
1390 init_completion(&nfc->completion);
1391
1392 nfc->dev = dev;
1393
1394 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1395 nfc->reg_base = devm_ioremap_resource(dev, res);
1396 if (IS_ERR(nfc->reg_base))
1397 return PTR_ERR(nfc->reg_base);
1398
1399 nfc->reg_clk =
1400 syscon_regmap_lookup_by_phandle(dev->of_node,
1401 "amlogic,mmc-syscon");
1402 if (IS_ERR(nfc->reg_clk)) {
1403 dev_err(dev, "Failed to lookup clock base\n");
1404 return PTR_ERR(nfc->reg_clk);
1405 }
1406
1407 irq = platform_get_irq(pdev, 0);
1408 if (irq < 0)
1409 return -EINVAL;
1410
1411 ret = meson_nfc_clk_init(nfc);
1412 if (ret) {
1413 dev_err(dev, "failed to initialize NAND clock\n");
1414 return ret;
1415 }
1416
1417 writel(0, nfc->reg_base + NFC_REG_CFG);
1418 ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
1419 if (ret) {
1420 dev_err(dev, "failed to request NFC IRQ\n");
1421 ret = -EINVAL;
1422 goto err_clk;
1423 }
1424
1425 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1426 if (ret) {
1427 dev_err(dev, "failed to set DMA mask\n");
1428 goto err_clk;
1429 }
1430
1431 platform_set_drvdata(pdev, nfc);
1432
1433 ret = meson_nfc_nand_chips_init(dev, nfc);
1434 if (ret) {
1435 dev_err(dev, "failed to init NAND chips\n");
1436 goto err_clk;
1437 }
1438
1439 return 0;
1440 err_clk:
1441 meson_nfc_disable_clk(nfc);
1442 return ret;
1443 }
1444
1445 static int meson_nfc_remove(struct platform_device *pdev)
1446 {
1447 struct meson_nfc *nfc = platform_get_drvdata(pdev);
1448 int ret;
1449
1450 ret = meson_nfc_nand_chip_cleanup(nfc);
1451 if (ret)
1452 return ret;
1453
1454 meson_nfc_disable_clk(nfc);
1455
1456 platform_set_drvdata(pdev, NULL);
1457
1458 return 0;
1459 }
1460
1461 static struct platform_driver meson_nfc_driver = {
1462 .probe = meson_nfc_probe,
1463 .remove = meson_nfc_remove,
1464 .driver = {
1465 .name = "meson-nand",
1466 .of_match_table = meson_nfc_id_table,
1467 },
1468 };
1469 module_platform_driver(meson_nfc_driver);
1470
1471 MODULE_LICENSE("Dual MIT/GPL");
1472 MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>");
1473 MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver");
Linux with added FPC-III support