drivers/mtd/nand/raw/nand_legacy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
   4  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
   5  *
   6  *  Credits:
   7  *      David Woodhouse for adding multichip support
   8  *
   9  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  10  *      rework for 2K page size chips
  11  *
  12  * This file contains all legacy helpers/code that should be removed
  13  * at some point.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/io.h>
  18 #include <linux/nmi.h>
  19
  20 #include "internals.h"
  21
  22 /**
  23  * nand_read_byte - [DEFAULT] read one byte from the chip
  24  * @chip: NAND chip object
  25  *
  26  * Default read function for 8bit buswidth
  27  */
  28 static uint8_t nand_read_byte(struct nand_chip *chip)
  29 {
  30         return readb(chip->legacy.IO_ADDR_R);
  31 }
  32
  33 /**
  34  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  35  * @chip: NAND chip object
  36  *
  37  * Default read function for 16bit buswidth with endianness conversion.
  38  *
  39  */
  40 static uint8_t nand_read_byte16(struct nand_chip *chip)
  41 {
  42         return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
  43 }
  44
  45 /**
  46  * nand_select_chip - [DEFAULT] control CE line
  47  * @chip: NAND chip object
  48  * @chipnr: chipnumber to select, -1 for deselect
  49  *
  50  * Default select function for 1 chip devices.
  51  */
  52 static void nand_select_chip(struct nand_chip *chip, int chipnr)
  53 {
  54         switch (chipnr) {
  55         case -1:
  56                 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
  57                                       0 | NAND_CTRL_CHANGE);
  58                 break;
  59         case 0:
  60                 break;
  61
  62         default:
  63                 BUG();
  64         }
  65 }
  66
  67 /**
  68  * nand_write_byte - [DEFAULT] write single byte to chip
  69  * @chip: NAND chip object
  70  * @byte: value to write
  71  *
  72  * Default function to write a byte to I/O[7:0]
  73  */
  74 static void nand_write_byte(struct nand_chip *chip, uint8_t byte)
  75 {
  76         chip->legacy.write_buf(chip, &byte, 1);
  77 }
  78
  79 /**
  80  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
  81  * @chip: NAND chip object
  82  * @byte: value to write
  83  *
  84  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
  85  */
  86 static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)
  87 {
  88         uint16_t word = byte;
  89
  90         /*
  91          * It's not entirely clear what should happen to I/O[15:8] when writing
  92          * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
  93          *
  94          *    When the host supports a 16-bit bus width, only data is
  95          *    transferred at the 16-bit width. All address and command line
  96          *    transfers shall use only the lower 8-bits of the data bus. During
  97          *    command transfers, the host may place any value on the upper
  98          *    8-bits of the data bus. During address transfers, the host shall
  99          *    set the upper 8-bits of the data bus to 00h.
 100          *
 101          * One user of the write_byte callback is nand_set_features. The
 102          * four parameters are specified to be written to I/O[7:0], but this is
 103          * neither an address nor a command transfer. Let's assume a 0 on the
 104          * upper I/O lines is OK.
 105          */
 106         chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
 107 }
 108
 109 /**
 110  * nand_write_buf - [DEFAULT] write buffer to chip
 111  * @chip: NAND chip object
 112  * @buf: data buffer
 113  * @len: number of bytes to write
 114  *
 115  * Default write function for 8bit buswidth.
 116  */
 117 static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
 118 {
 119         iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
 120 }
 121
 122 /**
 123  * nand_read_buf - [DEFAULT] read chip data into buffer
 124  * @chip: NAND chip object
 125  * @buf: buffer to store date
 126  * @len: number of bytes to read
 127  *
 128  * Default read function for 8bit buswidth.
 129  */
 130 static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 131 {
 132         ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
 133 }
 134
 135 /**
 136  * nand_write_buf16 - [DEFAULT] write buffer to chip
 137  * @chip: NAND chip object
 138  * @buf: data buffer
 139  * @len: number of bytes to write
 140  *
 141  * Default write function for 16bit buswidth.
 142  */
 143 static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,
 144                              int len)
 145 {
 146         u16 *p = (u16 *) buf;
 147
 148         iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
 149 }
 150
 151 /**
 152  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 153  * @chip: NAND chip object
 154  * @buf: buffer to store date
 155  * @len: number of bytes to read
 156  *
 157  * Default read function for 16bit buswidth.
 158  */
 159 static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
 160 {
 161         u16 *p = (u16 *) buf;
 162
 163         ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
 164 }
 165
 166 /**
 167  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 168  * @chip: NAND chip object
 169  * @timeo: Timeout
 170  *
 171  * Helper function for nand_wait_ready used when needing to wait in interrupt
 172  * context.
 173  */
 174 static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo)
 175 {
 176         int i;
 177
 178         /* Wait for the device to get ready */
 179         for (i = 0; i < timeo; i++) {
 180                 if (chip->legacy.dev_ready(chip))
 181                         break;
 182                 touch_softlockup_watchdog();
 183                 mdelay(1);
 184         }
 185 }
 186
 187 /**
 188  * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 189  * @chip: NAND chip object
 190  *
 191  * Wait for the ready pin after a command, and warn if a timeout occurs.
 192  */
 193 void nand_wait_ready(struct nand_chip *chip)
 194 {
 195         struct mtd_info *mtd = nand_to_mtd(chip);
 196         unsigned long timeo = 400;
 197
 198         if (mtd->oops_panic_write)
 199                 return panic_nand_wait_ready(chip, timeo);
 200
 201         /* Wait until command is processed or timeout occurs */
 202         timeo = jiffies + msecs_to_jiffies(timeo);
 203         do {
 204                 if (chip->legacy.dev_ready(chip))
 205                         return;
 206                 cond_resched();
 207         } while (time_before(jiffies, timeo));
 208
 209         if (!chip->legacy.dev_ready(chip))
 210                 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
 211 }
 212 EXPORT_SYMBOL_GPL(nand_wait_ready);
 213
 214 /**
 215  * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
 216  * @chip: NAND chip object
 217  * @timeo: Timeout in ms
 218  *
 219  * Wait for status ready (i.e. command done) or timeout.
 220  */
 221 static void nand_wait_status_ready(struct nand_chip *chip, unsigned long timeo)
 222 {
 223         int ret;
 224
 225         timeo = jiffies + msecs_to_jiffies(timeo);
 226         do {
 227                 u8 status;
 228
 229                 ret = nand_read_data_op(chip, &status, sizeof(status), true,
 230                                         false);
 231                 if (ret)
 232                         return;
 233
 234                 if (status & NAND_STATUS_READY)
 235                         break;
 236                 touch_softlockup_watchdog();
 237         } while (time_before(jiffies, timeo));
 238 };
 239
 240 /**
 241  * nand_command - [DEFAULT] Send command to NAND device
 242  * @chip: NAND chip object
 243  * @command: the command to be sent
 244  * @column: the column address for this command, -1 if none
 245  * @page_addr: the page address for this command, -1 if none
 246  *
 247  * Send command to NAND device. This function is used for small page devices
 248  * (512 Bytes per page).
 249  */
 250 static void nand_command(struct nand_chip *chip, unsigned int command,
 251                          int column, int page_addr)
 252 {
 253         struct mtd_info *mtd = nand_to_mtd(chip);
 254         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 255
 256         /* Write out the command to the device */
 257         if (command == NAND_CMD_SEQIN) {
 258                 int readcmd;
 259
 260                 if (column >= mtd->writesize) {
 261                         /* OOB area */
 262                         column -= mtd->writesize;
 263                         readcmd = NAND_CMD_READOOB;
 264                 } else if (column < 256) {
 265                         /* First 256 bytes --> READ0 */
 266                         readcmd = NAND_CMD_READ0;
 267                 } else {
 268                         column -= 256;
 269                         readcmd = NAND_CMD_READ1;
 270                 }
 271                 chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
 272                 ctrl &= ~NAND_CTRL_CHANGE;
 273         }
 274         if (command != NAND_CMD_NONE)
 275                 chip->legacy.cmd_ctrl(chip, command, ctrl);
 276
 277         /* Address cycle, when necessary */
 278         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 279         /* Serially input address */
 280         if (column != -1) {
 281                 /* Adjust columns for 16 bit buswidth */
 282                 if (chip->options & NAND_BUSWIDTH_16 &&
 283                                 !nand_opcode_8bits(command))
 284                         column >>= 1;
 285                 chip->legacy.cmd_ctrl(chip, column, ctrl);
 286                 ctrl &= ~NAND_CTRL_CHANGE;
 287         }
 288         if (page_addr != -1) {
 289                 chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
 290                 ctrl &= ~NAND_CTRL_CHANGE;
 291                 chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
 292                 if (chip->options & NAND_ROW_ADDR_3)
 293                         chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
 294         }
 295         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 296                               NAND_NCE | NAND_CTRL_CHANGE);
 297
 298         /*
 299          * Program and erase have their own busy handlers status and sequential
 300          * in needs no delay
 301          */
 302         switch (command) {
 303
 304         case NAND_CMD_NONE:
 305         case NAND_CMD_PAGEPROG:
 306         case NAND_CMD_ERASE1:
 307         case NAND_CMD_ERASE2:
 308         case NAND_CMD_SEQIN:
 309         case NAND_CMD_STATUS:
 310         case NAND_CMD_READID:
 311         case NAND_CMD_SET_FEATURES:
 312                 return;
 313
 314         case NAND_CMD_RESET:
 315                 if (chip->legacy.dev_ready)
 316                         break;
 317                 udelay(chip->legacy.chip_delay);
 318                 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
 319                                       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 320                 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 321                                       NAND_NCE | NAND_CTRL_CHANGE);
 322                 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
 323                 nand_wait_status_ready(chip, 250);
 324                 return;
 325
 326                 /* This applies to read commands */
 327         case NAND_CMD_READ0:
 328                 /*
 329                  * READ0 is sometimes used to exit GET STATUS mode. When this
 330                  * is the case no address cycles are requested, and we can use
 331                  * this information to detect that we should not wait for the
 332                  * device to be ready.
 333                  */
 334                 if (column == -1 && page_addr == -1)
 335                         return;
 336                 fallthrough;
 337         default:
 338                 /*
 339                  * If we don't have access to the busy pin, we apply the given
 340                  * command delay
 341                  */
 342                 if (!chip->legacy.dev_ready) {
 343                         udelay(chip->legacy.chip_delay);
 344                         return;
 345                 }
 346         }
 347         /*
 348          * Apply this short delay always to ensure that we do wait tWB in
 349          * any case on any machine.
 350          */
 351         ndelay(100);
 352
 353         nand_wait_ready(chip);
 354 }
 355
 356 static void nand_ccs_delay(struct nand_chip *chip)
 357 {
 358         const struct nand_sdr_timings *sdr =
 359                 nand_get_sdr_timings(nand_get_interface_config(chip));
 360
 361         /*
 362          * The controller already takes care of waiting for tCCS when the RNDIN
 363          * or RNDOUT command is sent, return directly.
 364          */
 365         if (!(chip->options & NAND_WAIT_TCCS))
 366                 return;
 367
 368         /*
 369          * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
 370          * (which should be safe for all NANDs).
 371          */
 372         if (nand_controller_can_setup_interface(chip))
 373                 ndelay(sdr->tCCS_min / 1000);
 374         else
 375                 ndelay(500);
 376 }
 377
 378 /**
 379  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 380  * @chip: NAND chip object
 381  * @command: the command to be sent
 382  * @column: the column address for this command, -1 if none
 383  * @page_addr: the page address for this command, -1 if none
 384  *
 385  * Send command to NAND device. This is the version for the new large page
 386  * devices. We don't have the separate regions as we have in the small page
 387  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 388  */
 389 static void nand_command_lp(struct nand_chip *chip, unsigned int command,
 390                             int column, int page_addr)
 391 {
 392         struct mtd_info *mtd = nand_to_mtd(chip);
 393
 394         /* Emulate NAND_CMD_READOOB */
 395         if (command == NAND_CMD_READOOB) {
 396                 column += mtd->writesize;
 397                 command = NAND_CMD_READ0;
 398         }
 399
 400         /* Command latch cycle */
 401         if (command != NAND_CMD_NONE)
 402                 chip->legacy.cmd_ctrl(chip, command,
 403                                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 404
 405         if (column != -1 || page_addr != -1) {
 406                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 407
 408                 /* Serially input address */
 409                 if (column != -1) {
 410                         /* Adjust columns for 16 bit buswidth */
 411                         if (chip->options & NAND_BUSWIDTH_16 &&
 412                                         !nand_opcode_8bits(command))
 413                                 column >>= 1;
 414                         chip->legacy.cmd_ctrl(chip, column, ctrl);
 415                         ctrl &= ~NAND_CTRL_CHANGE;
 416
 417                         /* Only output a single addr cycle for 8bits opcodes. */
 418                         if (!nand_opcode_8bits(command))
 419                                 chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
 420                 }
 421                 if (page_addr != -1) {
 422                         chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
 423                         chip->legacy.cmd_ctrl(chip, page_addr >> 8,
 424                                              NAND_NCE | NAND_ALE);
 425                         if (chip->options & NAND_ROW_ADDR_3)
 426                                 chip->legacy.cmd_ctrl(chip, page_addr >> 16,
 427                                                       NAND_NCE | NAND_ALE);
 428                 }
 429         }
 430         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 431                               NAND_NCE | NAND_CTRL_CHANGE);
 432
 433         /*
 434          * Program and erase have their own busy handlers status, sequential
 435          * in and status need no delay.
 436          */
 437         switch (command) {
 438
 439         case NAND_CMD_NONE:
 440         case NAND_CMD_CACHEDPROG:
 441         case NAND_CMD_PAGEPROG:
 442         case NAND_CMD_ERASE1:
 443         case NAND_CMD_ERASE2:
 444         case NAND_CMD_SEQIN:
 445         case NAND_CMD_STATUS:
 446         case NAND_CMD_READID:
 447         case NAND_CMD_SET_FEATURES:
 448                 return;
 449
 450         case NAND_CMD_RNDIN:
 451                 nand_ccs_delay(chip);
 452                 return;
 453
 454         case NAND_CMD_RESET:
 455                 if (chip->legacy.dev_ready)
 456                         break;
 457                 udelay(chip->legacy.chip_delay);
 458                 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
 459                                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 460                 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 461                                       NAND_NCE | NAND_CTRL_CHANGE);
 462                 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
 463                 nand_wait_status_ready(chip, 250);
 464                 return;
 465
 466         case NAND_CMD_RNDOUT:
 467                 /* No ready / busy check necessary */
 468                 chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
 469                                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 470                 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 471                                       NAND_NCE | NAND_CTRL_CHANGE);
 472
 473                 nand_ccs_delay(chip);
 474                 return;
 475
 476         case NAND_CMD_READ0:
 477                 /*
 478                  * READ0 is sometimes used to exit GET STATUS mode. When this
 479                  * is the case no address cycles are requested, and we can use
 480                  * this information to detect that READSTART should not be
 481                  * issued.
 482                  */
 483                 if (column == -1 && page_addr == -1)
 484                         return;
 485
 486                 chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
 487                                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 488                 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 489                                       NAND_NCE | NAND_CTRL_CHANGE);
 490                 fallthrough;    /* This applies to read commands */
 491         default:
 492                 /*
 493                  * If we don't have access to the busy pin, we apply the given
 494                  * command delay.
 495                  */
 496                 if (!chip->legacy.dev_ready) {
 497                         udelay(chip->legacy.chip_delay);
 498                         return;
 499                 }
 500         }
 501
 502         /*
 503          * Apply this short delay always to ensure that we do wait tWB in
 504          * any case on any machine.
 505          */
 506         ndelay(100);
 507
 508         nand_wait_ready(chip);
 509 }
 510
 511 /**
 512  * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
 513  * @chip: nand chip info structure
 514  * @addr: feature address.
 515  * @subfeature_param: the subfeature parameters, a four bytes array.
 516  *
 517  * Should be used by NAND controller drivers that do not support the SET/GET
 518  * FEATURES operations.
 519  */
 520 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
 521                                   u8 *subfeature_param)
 522 {
 523         return -ENOTSUPP;
 524 }
 525 EXPORT_SYMBOL(nand_get_set_features_notsupp);
 526
 527 /**
 528  * nand_wait - [DEFAULT] wait until the command is done
 529  * @chip: NAND chip structure
 530  *
 531  * Wait for command done. This applies to erase and program only.
 532  */
 533 static int nand_wait(struct nand_chip *chip)
 534 {
 535         struct mtd_info *mtd = nand_to_mtd(chip);
 536         unsigned long timeo = 400;
 537         u8 status;
 538         int ret;
 539
 540         /*
 541          * Apply this short delay always to ensure that we do wait tWB in any
 542          * case on any machine.
 543          */
 544         ndelay(100);
 545
 546         ret = nand_status_op(chip, NULL);
 547         if (ret)
 548                 return ret;
 549
 550         if (mtd->oops_panic_write) {
 551                 panic_nand_wait(chip, timeo);
 552         } else {
 553                 timeo = jiffies + msecs_to_jiffies(timeo);
 554                 do {
 555                         if (chip->legacy.dev_ready) {
 556                                 if (chip->legacy.dev_ready(chip))
 557                                         break;
 558                         } else {
 559                                 ret = nand_read_data_op(chip, &status,
 560                                                         sizeof(status), true,
 561                                                         false);
 562                                 if (ret)
 563                                         return ret;
 564
 565                                 if (status & NAND_STATUS_READY)
 566                                         break;
 567                         }
 568                         cond_resched();
 569                 } while (time_before(jiffies, timeo));
 570         }
 571
 572         ret = nand_read_data_op(chip, &status, sizeof(status), true, false);
 573         if (ret)
 574                 return ret;
 575
 576         /* This can happen if in case of timeout or buggy dev_ready */
 577         WARN_ON(!(status & NAND_STATUS_READY));
 578         return status;
 579 }
 580
 581 void nand_legacy_set_defaults(struct nand_chip *chip)
 582 {
 583         unsigned int busw = chip->options & NAND_BUSWIDTH_16;
 584
 585         if (nand_has_exec_op(chip))
 586                 return;
 587
 588         /* check for proper chip_delay setup, set 20us if not */
 589         if (!chip->legacy.chip_delay)
 590                 chip->legacy.chip_delay = 20;
 591
 592         /* check, if a user supplied command function given */
 593         if (!chip->legacy.cmdfunc)
 594                 chip->legacy.cmdfunc = nand_command;
 595
 596         /* check, if a user supplied wait function given */
 597         if (chip->legacy.waitfunc == NULL)
 598                 chip->legacy.waitfunc = nand_wait;
 599
 600         if (!chip->legacy.select_chip)
 601                 chip->legacy.select_chip = nand_select_chip;
 602
 603         /* If called twice, pointers that depend on busw may need to be reset */
 604         if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
 605                 chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
 606         if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
 607                 chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
 608         if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
 609                 chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
 610         if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
 611                 chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
 612 }
 613
 614 void nand_legacy_adjust_cmdfunc(struct nand_chip *chip)
 615 {
 616         struct mtd_info *mtd = nand_to_mtd(chip);
 617
 618         /* Do not replace user supplied command function! */
 619         if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
 620                 chip->legacy.cmdfunc = nand_command_lp;
 621 }
 622
 623 int nand_legacy_check_hooks(struct nand_chip *chip)
 624 {
 625         /*
 626          * ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is
 627          * not populated.
 628          */
 629         if (nand_has_exec_op(chip))
 630                 return 0;
 631
 632         /*
 633          * Default functions assigned for ->legacy.cmdfunc() and
 634          * ->legacy.select_chip() both expect ->legacy.cmd_ctrl() to be
 635          *  populated.
 636          */
 637         if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
 638             !chip->legacy.cmd_ctrl) {
 639                 pr_err("->legacy.cmd_ctrl() should be provided\n");
 640                 return -EINVAL;
 641         }
 642
 643         return 0;
 644 }