2 * NAND support for Marvell Orion SoC platforms
4 * Tzachi Perelstein <tzachi@marvell.com>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
21 #include <linux/sizes.h>
22 #include <linux/platform_data/mtd-orion_nand.h>
24 struct orion_nand_info
{
25 struct nand_controller controller
;
26 struct nand_chip chip
;
30 static void orion_nand_cmd_ctrl(struct nand_chip
*nc
, int cmd
,
33 struct orion_nand_data
*board
= nand_get_controller_data(nc
);
36 if (cmd
== NAND_CMD_NONE
)
40 offs
= (1 << board
->cle
);
41 else if (ctrl
& NAND_ALE
)
42 offs
= (1 << board
->ale
);
46 if (nc
->options
& NAND_BUSWIDTH_16
)
49 writeb(cmd
, nc
->legacy
.IO_ADDR_W
+ offs
);
52 static void orion_nand_read_buf(struct nand_chip
*chip
, uint8_t *buf
, int len
)
54 void __iomem
*io_base
= chip
->legacy
.IO_ADDR_R
;
55 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
60 while (len
&& (unsigned long)buf
& 7) {
61 *buf
++ = readb(io_base
);
64 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
65 buf64
= (uint64_t *)buf
;
68 * Since GCC has no proper constraint (PR 43518)
69 * force x variable to r2/r3 registers as ldrd instruction
70 * requires first register to be even.
72 register uint64_t x
asm ("r2");
74 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x
) : "r" (io_base
));
79 readsl(io_base
, buf
, len
/4);
83 buf
[i
++] = readb(io_base
);
86 static int orion_nand_attach_chip(struct nand_chip
*chip
)
88 chip
->ecc
.engine_type
= NAND_ECC_ENGINE_TYPE_SOFT
;
90 if (chip
->ecc
.algo
== NAND_ECC_ALGO_UNKNOWN
)
91 chip
->ecc
.algo
= NAND_ECC_ALGO_HAMMING
;
96 static const struct nand_controller_ops orion_nand_ops
= {
97 .attach_chip
= orion_nand_attach_chip
,
100 static int __init
orion_nand_probe(struct platform_device
*pdev
)
102 struct orion_nand_info
*info
;
103 struct mtd_info
*mtd
;
104 struct nand_chip
*nc
;
105 struct orion_nand_data
*board
;
106 struct resource
*res
;
107 void __iomem
*io_base
;
111 info
= devm_kzalloc(&pdev
->dev
,
112 sizeof(struct orion_nand_info
),
117 mtd
= nand_to_mtd(nc
);
119 nand_controller_init(&info
->controller
);
120 info
->controller
.ops
= &orion_nand_ops
;
121 nc
->controller
= &info
->controller
;
123 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
124 io_base
= devm_ioremap_resource(&pdev
->dev
, res
);
127 return PTR_ERR(io_base
);
129 if (pdev
->dev
.of_node
) {
130 board
= devm_kzalloc(&pdev
->dev
, sizeof(struct orion_nand_data
),
134 if (!of_property_read_u32(pdev
->dev
.of_node
, "cle", &val
))
135 board
->cle
= (u8
)val
;
138 if (!of_property_read_u32(pdev
->dev
.of_node
, "ale", &val
))
139 board
->ale
= (u8
)val
;
142 if (!of_property_read_u32(pdev
->dev
.of_node
,
144 board
->width
= (u8
)val
* 8;
147 if (!of_property_read_u32(pdev
->dev
.of_node
,
149 board
->chip_delay
= (u8
)val
;
151 board
= dev_get_platdata(&pdev
->dev
);
154 mtd
->dev
.parent
= &pdev
->dev
;
156 nand_set_controller_data(nc
, board
);
157 nand_set_flash_node(nc
, pdev
->dev
.of_node
);
158 nc
->legacy
.IO_ADDR_R
= nc
->legacy
.IO_ADDR_W
= io_base
;
159 nc
->legacy
.cmd_ctrl
= orion_nand_cmd_ctrl
;
160 nc
->legacy
.read_buf
= orion_nand_read_buf
;
162 if (board
->chip_delay
)
163 nc
->legacy
.chip_delay
= board
->chip_delay
;
165 WARN(board
->width
> 16,
166 "%d bit bus width out of range",
169 if (board
->width
== 16)
170 nc
->options
|= NAND_BUSWIDTH_16
;
172 platform_set_drvdata(pdev
, info
);
174 /* Not all platforms can gate the clock, so it is not
175 an error if the clock does not exists. */
176 info
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
177 if (IS_ERR(info
->clk
)) {
178 ret
= PTR_ERR(info
->clk
);
179 if (ret
== -ENOENT
) {
182 dev_err(&pdev
->dev
, "failed to get clock!\n");
187 ret
= clk_prepare_enable(info
->clk
);
189 dev_err(&pdev
->dev
, "failed to prepare clock!\n");
193 ret
= nand_scan(nc
, 1);
197 mtd
->name
= "orion_nand";
198 ret
= mtd_device_register(mtd
, board
->parts
, board
->nr_parts
);
207 clk_disable_unprepare(info
->clk
);
211 static int orion_nand_remove(struct platform_device
*pdev
)
213 struct orion_nand_info
*info
= platform_get_drvdata(pdev
);
214 struct nand_chip
*chip
= &info
->chip
;
217 ret
= mtd_device_unregister(nand_to_mtd(chip
));
222 clk_disable_unprepare(info
->clk
);
228 static const struct of_device_id orion_nand_of_match_table
[] = {
229 { .compatible
= "marvell,orion-nand", },
232 MODULE_DEVICE_TABLE(of
, orion_nand_of_match_table
);
235 static struct platform_driver orion_nand_driver
= {
236 .remove
= orion_nand_remove
,
238 .name
= "orion_nand",
239 .of_match_table
= of_match_ptr(orion_nand_of_match_table
),
243 module_platform_driver_probe(orion_nand_driver
, orion_nand_probe
);
245 MODULE_LICENSE("GPL");
246 MODULE_AUTHOR("Tzachi Perelstein");
247 MODULE_DESCRIPTION("NAND glue for Orion platforms");
248 MODULE_ALIAS("platform:orion_nand");