drivers/mtd/spi-nor/gigadevice.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 static void gd25q256_default_init(struct spi_nor *nor)
  12 {
  13         /*
  14          * Some manufacturer like GigaDevice may use different
  15          * bit to set QE on different memories, so the MFR can't
  16          * indicate the quad_enable method for this case, we need
  17          * to set it in the default_init fixup hook.
  18          */
  19         nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
  20 }
  21
  22 static struct spi_nor_fixups gd25q256_fixups = {
  23         .default_init = gd25q256_default_init,
  24 };
  25
  26 static const struct flash_info gigadevice_parts[] = {
  27         { "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32,
  28                           SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  29                           SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  30         { "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64,
  31                           SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  32                           SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  33         { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
  34                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  35                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  36         { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
  37                           SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  38                           SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  39         { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
  40                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  41                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  42         { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
  43                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  44                              SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  45         { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
  46                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  47                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  48         { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
  49                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  50                            SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
  51                            SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
  52                 .fixups = &gd25q256_fixups },
  53 };
  54
  55 const struct spi_nor_manufacturer spi_nor_gigadevice = {
  56         .name = "gigadevice",
  57         .parts = gigadevice_parts,
  58         .nparts = ARRAY_SIZE(gigadevice_parts),
  59 };