drivers/mtd/spi-nor/winbond.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 static int
  12 w25q256_post_bfpt_fixups(struct spi_nor *nor,
  13                          const struct sfdp_parameter_header *bfpt_header,
  14                          const struct sfdp_bfpt *bfpt,
  15                          struct spi_nor_flash_parameter *params)
  16 {
  17         /*
  18          * W25Q256JV supports 4B opcodes but W25Q256FV does not.
  19          * Unfortunately, Winbond has re-used the same JEDEC ID for both
  20          * variants which prevents us from defining a new entry in the parts
  21          * table.
  22          * To differentiate between W25Q256JV and W25Q256FV check SFDP header
  23          * version: only JV has JESD216A compliant structure (version 5).
  24          */
  25         if (bfpt_header->major == SFDP_JESD216_MAJOR &&
  26             bfpt_header->minor == SFDP_JESD216A_MINOR)
  27                 nor->flags |= SNOR_F_4B_OPCODES;
  28
  29         return 0;
  30 }
  31
  32 static struct spi_nor_fixups w25q256_fixups = {
  33         .post_bfpt = w25q256_post_bfpt_fixups,
  34 };
  35
  36 static const struct flash_info winbond_parts[] = {
  37         /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  38         { "w25x05", INFO(0xef3010, 0, 64 * 1024,  1,  SECT_4K) },
  39         { "w25x10", INFO(0xef3011, 0, 64 * 1024,  2,  SECT_4K) },
  40         { "w25x20", INFO(0xef3012, 0, 64 * 1024,  4,  SECT_4K) },
  41         { "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
  42         { "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
  43         { "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
  44         { "w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
  45                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  46                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  47         { "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
  48         { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024,  32,
  49                                  SECT_4K | SPI_NOR_DUAL_READ |
  50                                  SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
  51                                  SPI_NOR_HAS_TB) },
  52         { "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
  53         { "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
  54         { "w25q20ew", INFO(0xef6012, 0, 64 * 1024,  4, SECT_4K) },
  55         { "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
  56         { "w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
  57                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  58                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  59         { "w25q32jv", INFO(0xef7016, 0, 64 * 1024,  64,
  60                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  61                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  62         },
  63         { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024,  64,
  64                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  65                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  66         { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128,
  67                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  68                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  69         { "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256,
  70                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  71                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  72         { "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512,
  73                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  74                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  75         { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
  76         { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128,
  77                          SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  78         { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
  79                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  80                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  81         { "w25q64jvm", INFO(0xef7017, 0, 64 * 1024, 128, SECT_4K) },
  82         { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
  83                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  84                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  85         { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
  86                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  87                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  88         { "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
  89         { "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
  90         { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
  91         { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
  92                           SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  93           .fixups = &w25q256_fixups },
  94         { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
  95                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  96         { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
  97                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  98         { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
  99                             SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
 100 };
 101
 102 /**
 103  * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
 104  * @nor:        pointer to 'struct spi_nor'.
 105  * @enable:     true to enter the 4-byte address mode, false to exit the 4-byte
 106  *              address mode.
 107  *
 108  * Return: 0 on success, -errno otherwise.
 109  */
 110 static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
 111 {
 112         int ret;
 113
 114         ret = spi_nor_set_4byte_addr_mode(nor, enable);
 115         if (ret || enable)
 116                 return ret;
 117
 118         /*
 119          * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
 120          * Register to be set to 1, so all 3-byte-address reads come from the
 121          * second 16M. We must clear the register to enable normal behavior.
 122          */
 123         ret = spi_nor_write_enable(nor);
 124         if (ret)
 125                 return ret;
 126
 127         ret = spi_nor_write_ear(nor, 0);
 128         if (ret)
 129                 return ret;
 130
 131         return spi_nor_write_disable(nor);
 132 }
 133
 134 static void winbond_default_init(struct spi_nor *nor)
 135 {
 136         nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
 137 }
 138
 139 static const struct spi_nor_fixups winbond_fixups = {
 140         .default_init = winbond_default_init,
 141 };
 142
 143 const struct spi_nor_manufacturer spi_nor_winbond = {
 144         .name = "winbond",
 145         .parts = winbond_parts,
 146         .nparts = ARRAY_SIZE(winbond_parts),
 147         .fixups = &winbond_fixups,
 148 };