drivers/net/can/mscan/mscan.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Definitions of consts/structs to drive the Freescale MSCAN.
   4  *
   5  * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
   6  *                         Varma Electronics Oy
   7  */
   8
   9 #ifndef __MSCAN_H__
  10 #define __MSCAN_H__
  11
  12 #include <linux/clk.h>
  13 #include <linux/types.h>
  14
  15 /* MSCAN control register 0 (CANCTL0) bits */
  16 #define MSCAN_RXFRM             0x80
  17 #define MSCAN_RXACT             0x40
  18 #define MSCAN_CSWAI             0x20
  19 #define MSCAN_SYNCH             0x10
  20 #define MSCAN_TIME              0x08
  21 #define MSCAN_WUPE              0x04
  22 #define MSCAN_SLPRQ             0x02
  23 #define MSCAN_INITRQ            0x01
  24
  25 /* MSCAN control register 1 (CANCTL1) bits */
  26 #define MSCAN_CANE              0x80
  27 #define MSCAN_CLKSRC            0x40
  28 #define MSCAN_LOOPB             0x20
  29 #define MSCAN_LISTEN            0x10
  30 #define MSCAN_BORM              0x08
  31 #define MSCAN_WUPM              0x04
  32 #define MSCAN_SLPAK             0x02
  33 #define MSCAN_INITAK            0x01
  34
  35 /* Use the MPC5XXX MSCAN variant? */
  36 #ifdef CONFIG_PPC
  37 #define MSCAN_FOR_MPC5XXX
  38 #endif
  39
  40 #ifdef MSCAN_FOR_MPC5XXX
  41 #define MSCAN_CLKSRC_BUS        0
  42 #define MSCAN_CLKSRC_XTAL       MSCAN_CLKSRC
  43 #define MSCAN_CLKSRC_IPS        MSCAN_CLKSRC
  44 #else
  45 #define MSCAN_CLKSRC_BUS        MSCAN_CLKSRC
  46 #define MSCAN_CLKSRC_XTAL       0
  47 #endif
  48
  49 /* MSCAN receiver flag register (CANRFLG) bits */
  50 #define MSCAN_WUPIF             0x80
  51 #define MSCAN_CSCIF             0x40
  52 #define MSCAN_RSTAT1            0x20
  53 #define MSCAN_RSTAT0            0x10
  54 #define MSCAN_TSTAT1            0x08
  55 #define MSCAN_TSTAT0            0x04
  56 #define MSCAN_OVRIF             0x02
  57 #define MSCAN_RXF               0x01
  58 #define MSCAN_ERR_IF            (MSCAN_OVRIF | MSCAN_CSCIF)
  59 #define MSCAN_RSTAT_MSK         (MSCAN_RSTAT1 | MSCAN_RSTAT0)
  60 #define MSCAN_TSTAT_MSK         (MSCAN_TSTAT1 | MSCAN_TSTAT0)
  61 #define MSCAN_STAT_MSK          (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
  62
  63 #define MSCAN_STATE_BUS_OFF     (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
  64                                  MSCAN_TSTAT1 | MSCAN_TSTAT0)
  65 #define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
  66 #define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
  67 #define MSCAN_STATE_ACTIVE      0
  68 #define MSCAN_STATE_WARNING     1
  69 #define MSCAN_STATE_PASSIVE     2
  70 #define MSCAN_STATE_BUSOFF      3
  71
  72 /* MSCAN receiver interrupt enable register (CANRIER) bits */
  73 #define MSCAN_WUPIE             0x80
  74 #define MSCAN_CSCIE             0x40
  75 #define MSCAN_RSTATE1           0x20
  76 #define MSCAN_RSTATE0           0x10
  77 #define MSCAN_TSTATE1           0x08
  78 #define MSCAN_TSTATE0           0x04
  79 #define MSCAN_OVRIE             0x02
  80 #define MSCAN_RXFIE             0x01
  81
  82 /* MSCAN transmitter flag register (CANTFLG) bits */
  83 #define MSCAN_TXE2              0x04
  84 #define MSCAN_TXE1              0x02
  85 #define MSCAN_TXE0              0x01
  86 #define MSCAN_TXE               (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
  87
  88 /* MSCAN transmitter interrupt enable register (CANTIER) bits */
  89 #define MSCAN_TXIE2             0x04
  90 #define MSCAN_TXIE1             0x02
  91 #define MSCAN_TXIE0             0x01
  92 #define MSCAN_TXIE              (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
  93
  94 /* MSCAN transmitter message abort request (CANTARQ) bits */
  95 #define MSCAN_ABTRQ2            0x04
  96 #define MSCAN_ABTRQ1            0x02
  97 #define MSCAN_ABTRQ0            0x01
  98
  99 /* MSCAN transmitter message abort ack (CANTAAK) bits */
 100 #define MSCAN_ABTAK2            0x04
 101 #define MSCAN_ABTAK1            0x02
 102 #define MSCAN_ABTAK0            0x01
 103
 104 /* MSCAN transmit buffer selection (CANTBSEL) bits */
 105 #define MSCAN_TX2               0x04
 106 #define MSCAN_TX1               0x02
 107 #define MSCAN_TX0               0x01
 108
 109 /* MSCAN ID acceptance control register (CANIDAC) bits */
 110 #define MSCAN_IDAM1             0x20
 111 #define MSCAN_IDAM0             0x10
 112 #define MSCAN_IDHIT2            0x04
 113 #define MSCAN_IDHIT1            0x02
 114 #define MSCAN_IDHIT0            0x01
 115
 116 #define MSCAN_AF_32BIT          0x00
 117 #define MSCAN_AF_16BIT          MSCAN_IDAM0
 118 #define MSCAN_AF_8BIT           MSCAN_IDAM1
 119 #define MSCAN_AF_CLOSED         (MSCAN_IDAM0|MSCAN_IDAM1)
 120 #define MSCAN_AF_MASK           (~(MSCAN_IDAM0|MSCAN_IDAM1))
 121
 122 /* MSCAN Miscellaneous Register (CANMISC) bits */
 123 #define MSCAN_BOHOLD            0x01
 124
 125 /* MSCAN Identifier Register (IDR) bits */
 126 #define MSCAN_SFF_RTR_SHIFT     4
 127 #define MSCAN_EFF_RTR_SHIFT     0
 128 #define MSCAN_EFF_FLAGS         0x18    /* IDE + SRR */
 129
 130 #ifdef MSCAN_FOR_MPC5XXX
 131 #define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
 132 #define _MSCAN_RESERVED_DSR_SIZE        2
 133 #else
 134 #define _MSCAN_RESERVED_(n, num)
 135 #define _MSCAN_RESERVED_DSR_SIZE        0
 136 #endif
 137
 138 /* Structure of the hardware registers */
 139 struct mscan_regs {
 140         /* (see doc S12MSCANV3/D)                 MPC5200    MSCAN */
 141         u8 canctl0;                             /* + 0x00     0x00 */
 142         u8 canctl1;                             /* + 0x01     0x01 */
 143         _MSCAN_RESERVED_(1, 2);                 /* + 0x02          */
 144         u8 canbtr0;                             /* + 0x04     0x02 */
 145         u8 canbtr1;                             /* + 0x05     0x03 */
 146         _MSCAN_RESERVED_(2, 2);                 /* + 0x06          */
 147         u8 canrflg;                             /* + 0x08     0x04 */
 148         u8 canrier;                             /* + 0x09     0x05 */
 149         _MSCAN_RESERVED_(3, 2);                 /* + 0x0a          */
 150         u8 cantflg;                             /* + 0x0c     0x06 */
 151         u8 cantier;                             /* + 0x0d     0x07 */
 152         _MSCAN_RESERVED_(4, 2);                 /* + 0x0e          */
 153         u8 cantarq;                             /* + 0x10     0x08 */
 154         u8 cantaak;                             /* + 0x11     0x09 */
 155         _MSCAN_RESERVED_(5, 2);                 /* + 0x12          */
 156         u8 cantbsel;                            /* + 0x14     0x0a */
 157         u8 canidac;                             /* + 0x15     0x0b */
 158         u8 reserved;                            /* + 0x16     0x0c */
 159         _MSCAN_RESERVED_(6, 2);                 /* + 0x17          */
 160         u8 canmisc;                             /* + 0x19     0x0d */
 161         _MSCAN_RESERVED_(7, 2);                 /* + 0x1a          */
 162         u8 canrxerr;                            /* + 0x1c     0x0e */
 163         u8 cantxerr;                            /* + 0x1d     0x0f */
 164         _MSCAN_RESERVED_(8, 2);                 /* + 0x1e          */
 165         u16 canidar1_0;                         /* + 0x20     0x10 */
 166         _MSCAN_RESERVED_(9, 2);                 /* + 0x22          */
 167         u16 canidar3_2;                         /* + 0x24     0x12 */
 168         _MSCAN_RESERVED_(10, 2);                /* + 0x26          */
 169         u16 canidmr1_0;                         /* + 0x28     0x14 */
 170         _MSCAN_RESERVED_(11, 2);                /* + 0x2a          */
 171         u16 canidmr3_2;                         /* + 0x2c     0x16 */
 172         _MSCAN_RESERVED_(12, 2);                /* + 0x2e          */
 173         u16 canidar5_4;                         /* + 0x30     0x18 */
 174         _MSCAN_RESERVED_(13, 2);                /* + 0x32          */
 175         u16 canidar7_6;                         /* + 0x34     0x1a */
 176         _MSCAN_RESERVED_(14, 2);                /* + 0x36          */
 177         u16 canidmr5_4;                         /* + 0x38     0x1c */
 178         _MSCAN_RESERVED_(15, 2);                /* + 0x3a          */
 179         u16 canidmr7_6;                         /* + 0x3c     0x1e */
 180         _MSCAN_RESERVED_(16, 2);                /* + 0x3e          */
 181         struct {
 182                 u16 idr1_0;                     /* + 0x40     0x20 */
 183                 _MSCAN_RESERVED_(17, 2);        /* + 0x42          */
 184                 u16 idr3_2;                     /* + 0x44     0x22 */
 185                 _MSCAN_RESERVED_(18, 2);        /* + 0x46          */
 186                 u16 dsr1_0;                     /* + 0x48     0x24 */
 187                 _MSCAN_RESERVED_(19, 2);        /* + 0x4a          */
 188                 u16 dsr3_2;                     /* + 0x4c     0x26 */
 189                 _MSCAN_RESERVED_(20, 2);        /* + 0x4e          */
 190                 u16 dsr5_4;                     /* + 0x50     0x28 */
 191                 _MSCAN_RESERVED_(21, 2);        /* + 0x52          */
 192                 u16 dsr7_6;                     /* + 0x54     0x2a */
 193                 _MSCAN_RESERVED_(22, 2);        /* + 0x56          */
 194                 u8 dlr;                         /* + 0x58     0x2c */
 195                 u8 reserved;                    /* + 0x59     0x2d */
 196                 _MSCAN_RESERVED_(23, 2);        /* + 0x5a          */
 197                 u16 time;                       /* + 0x5c     0x2e */
 198         } rx;
 199         _MSCAN_RESERVED_(24, 2);                /* + 0x5e          */
 200         struct {
 201                 u16 idr1_0;                     /* + 0x60     0x30 */
 202                 _MSCAN_RESERVED_(25, 2);        /* + 0x62          */
 203                 u16 idr3_2;                     /* + 0x64     0x32 */
 204                 _MSCAN_RESERVED_(26, 2);        /* + 0x66          */
 205                 u16 dsr1_0;                     /* + 0x68     0x34 */
 206                 _MSCAN_RESERVED_(27, 2);        /* + 0x6a          */
 207                 u16 dsr3_2;                     /* + 0x6c     0x36 */
 208                 _MSCAN_RESERVED_(28, 2);        /* + 0x6e          */
 209                 u16 dsr5_4;                     /* + 0x70     0x38 */
 210                 _MSCAN_RESERVED_(29, 2);        /* + 0x72          */
 211                 u16 dsr7_6;                     /* + 0x74     0x3a */
 212                 _MSCAN_RESERVED_(30, 2);        /* + 0x76          */
 213                 u8 dlr;                         /* + 0x78     0x3c */
 214                 u8 tbpr;                        /* + 0x79     0x3d */
 215                 _MSCAN_RESERVED_(31, 2);        /* + 0x7a          */
 216                 u16 time;                       /* + 0x7c     0x3e */
 217         } tx;
 218         _MSCAN_RESERVED_(32, 2);                /* + 0x7e          */
 219 } __packed;
 220
 221 #undef _MSCAN_RESERVED_
 222 #define MSCAN_REGION    sizeof(struct mscan)
 223
 224 #define MSCAN_NORMAL_MODE       0
 225 #define MSCAN_SLEEP_MODE        MSCAN_SLPRQ
 226 #define MSCAN_INIT_MODE         (MSCAN_INITRQ | MSCAN_SLPRQ)
 227 #define MSCAN_POWEROFF_MODE     (MSCAN_CSWAI | MSCAN_SLPRQ)
 228 #define MSCAN_SET_MODE_RETRIES  255
 229 #define MSCAN_ECHO_SKB_MAX      3
 230 #define MSCAN_RX_INTS_ENABLE    (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \
 231                                  MSCAN_RSTATE1 | MSCAN_RSTATE0 | \
 232                                  MSCAN_TSTATE1 | MSCAN_TSTATE0)
 233
 234 /* MSCAN type variants */
 235 enum {
 236         MSCAN_TYPE_MPC5200,
 237         MSCAN_TYPE_MPC5121
 238 };
 239
 240 #define BTR0_BRP_MASK           0x3f
 241 #define BTR0_SJW_SHIFT          6
 242 #define BTR0_SJW_MASK           (0x3 << BTR0_SJW_SHIFT)
 243
 244 #define BTR1_TSEG1_MASK         0xf
 245 #define BTR1_TSEG2_SHIFT        4
 246 #define BTR1_TSEG2_MASK         (0x7 << BTR1_TSEG2_SHIFT)
 247 #define BTR1_SAM_SHIFT          7
 248
 249 #define BTR0_SET_BRP(brp)       (((brp) - 1) & BTR0_BRP_MASK)
 250 #define BTR0_SET_SJW(sjw)       ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
 251                                  BTR0_SJW_MASK)
 252
 253 #define BTR1_SET_TSEG1(tseg1)   (((tseg1) - 1) &  BTR1_TSEG1_MASK)
 254 #define BTR1_SET_TSEG2(tseg2)   ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
 255                                  BTR1_TSEG2_MASK)
 256 #define BTR1_SET_SAM(sam)       ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
 257
 258 #define F_RX_PROGRESS   0
 259 #define F_TX_PROGRESS   1
 260 #define F_TX_WAIT_ALL   2
 261
 262 #define TX_QUEUE_SIZE   3
 263
 264 struct tx_queue_entry {
 265         struct list_head list;
 266         u8 mask;
 267         u8 id;
 268 };
 269
 270 struct mscan_priv {
 271         struct can_priv can;    /* must be the first member */
 272         unsigned int type;      /* MSCAN type variants */
 273         unsigned long flags;
 274         void __iomem *reg_base; /* ioremap'ed address to registers */
 275         struct clk *clk_ipg;    /* clock for registers */
 276         struct clk *clk_can;    /* clock for bitrates */
 277         u8 shadow_statflg;
 278         u8 shadow_canrier;
 279         u8 cur_pri;
 280         u8 prev_buf_id;
 281         u8 tx_active;
 282
 283         struct list_head tx_head;
 284         struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
 285         struct napi_struct napi;
 286 };
 287
 288 struct net_device *alloc_mscandev(void);
 289 int register_mscandev(struct net_device *dev, int mscan_clksrc);
 290 void unregister_mscandev(struct net_device *dev);
 291
 292 #endif /* __MSCAN_H__ */