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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / can / peak_canfd / peak_pciefd_main.c
blob0df1cdfa683577059f73e36af2142ac40c6586f1
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com>
3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com>
4 *
5 * Derived from the PCAN project file driver/src/pcan_pci.c:
6 *
7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/netdevice.h>
14 #include <linux/delay.h>
15 #include <linux/pci.h>
16 #include <linux/io.h>
17 #include <linux/can.h>
18 #include <linux/can/dev.h>
19
20 #include "peak_canfd_user.h"
21
22 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
23 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards");
24 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCIe/M.2 FD CAN cards");
25 MODULE_LICENSE("GPL v2");
26
27 #define PCIEFD_DRV_NAME "peak_pciefd"
28
29 #define PEAK_PCI_VENDOR_ID 0x001c /* The PCI device and vendor IDs */
30 #define PEAK_PCIEFD_ID 0x0013 /* for PCIe slot cards */
31 #define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */
32 #define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */
33 #define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */
34 #define PCAN_PCIEFD_OEM_ID 0x0019 /* for PCIe slot OEM cards */
35 #define PCAN_M2_ID 0x001a /* for M2 slot cards */
36
37 /* PEAK PCIe board access description */
38 #define PCIEFD_BAR0_SIZE (64 * 1024)
39 #define PCIEFD_RX_DMA_SIZE (4 * 1024)
40 #define PCIEFD_TX_DMA_SIZE (4 * 1024)
41
42 #define PCIEFD_TX_PAGE_SIZE (2 * 1024)
43
44 /* System Control Registers */
45 #define PCIEFD_REG_SYS_CTL_SET 0x0000 /* set bits */
46 #define PCIEFD_REG_SYS_CTL_CLR 0x0004 /* clear bits */
47
48 /* Version info registers */
49 #define PCIEFD_REG_SYS_VER1 0x0040 /* version reg #1 */
50 #define PCIEFD_REG_SYS_VER2 0x0044 /* version reg #2 */
51
52 #define PCIEFD_FW_VERSION(x, y, z) (((u32)(x) << 24) | \
53 ((u32)(y) << 16) | \
54 ((u32)(z) << 8))
55
56 /* System Control Registers Bits */
57 #define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */
58 #define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */
59
60 /* CAN-FD channel addresses */
61 #define PCIEFD_CANX_OFF(c) (((c) + 1) * 0x1000)
62
63 #define PCIEFD_ECHO_SKB_MAX PCANFD_ECHO_SKB_DEF
64
65 /* CAN-FD channel registers */
66 #define PCIEFD_REG_CAN_MISC 0x0000 /* Misc. control */
67 #define PCIEFD_REG_CAN_CLK_SEL 0x0008 /* Clock selector */
68 #define PCIEFD_REG_CAN_CMD_PORT_L 0x0010 /* 64-bits command port */
69 #define PCIEFD_REG_CAN_CMD_PORT_H 0x0014
70 #define PCIEFD_REG_CAN_TX_REQ_ACC 0x0020 /* Tx request accumulator */
71 #define PCIEFD_REG_CAN_TX_CTL_SET 0x0030 /* Tx control set register */
72 #define PCIEFD_REG_CAN_TX_CTL_CLR 0x0038 /* Tx control clear register */
73 #define PCIEFD_REG_CAN_TX_DMA_ADDR_L 0x0040 /* 64-bits addr for Tx DMA */
74 #define PCIEFD_REG_CAN_TX_DMA_ADDR_H 0x0044
75 #define PCIEFD_REG_CAN_RX_CTL_SET 0x0050 /* Rx control set register */
76 #define PCIEFD_REG_CAN_RX_CTL_CLR 0x0058 /* Rx control clear register */
77 #define PCIEFD_REG_CAN_RX_CTL_WRT 0x0060 /* Rx control write register */
78 #define PCIEFD_REG_CAN_RX_CTL_ACK 0x0068 /* Rx control ACK register */
79 #define PCIEFD_REG_CAN_RX_DMA_ADDR_L 0x0070 /* 64-bits addr for Rx DMA */
80 #define PCIEFD_REG_CAN_RX_DMA_ADDR_H 0x0074
81
82 /* CAN-FD channel misc register bits */
83 #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */
84
85 /* CAN-FD channel Clock SELector Source & DIVider */
86 #define CANFD_CLK_SEL_DIV_MASK 0x00000007
87 #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */
88 #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */
89 #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */
90 #define CANFD_CLK_SEL_DIV_24MHZ 0x00000003 /* SRC=240MHz only */
91 #define CANFD_CLK_SEL_DIV_20MHZ 0x00000004 /* SRC=240MHz only */
92
93 #define CANFD_CLK_SEL_SRC_MASK 0x00000008 /* 0=80MHz, 1=240MHz */
94 #define CANFD_CLK_SEL_SRC_240MHZ 0x00000008
95 #define CANFD_CLK_SEL_SRC_80MHZ (~CANFD_CLK_SEL_SRC_240MHZ & \
96 CANFD_CLK_SEL_SRC_MASK)
97
98 #define CANFD_CLK_SEL_20MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
99 CANFD_CLK_SEL_DIV_20MHZ)
100 #define CANFD_CLK_SEL_24MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
101 CANFD_CLK_SEL_DIV_24MHZ)
102 #define CANFD_CLK_SEL_30MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
103 CANFD_CLK_SEL_DIV_30MHZ)
104 #define CANFD_CLK_SEL_40MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
105 CANFD_CLK_SEL_DIV_40MHZ)
106 #define CANFD_CLK_SEL_60MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
107 CANFD_CLK_SEL_DIV_60MHZ)
108 #define CANFD_CLK_SEL_80MHZ (CANFD_CLK_SEL_SRC_80MHZ)
109
110 /* CAN-FD channel Rx/Tx control register bits */
111 #define CANFD_CTL_UNC_BIT 0x00010000 /* Uncached DMA mem */
112 #define CANFD_CTL_RST_BIT 0x00020000 /* reset DMA action */
113 #define CANFD_CTL_IEN_BIT 0x00040000 /* IRQ enable */
114
115 /* Rx IRQ Count and Time Limits */
116 #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */
117 #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */
118
119 /* Tx anticipation window (link logical address should be aligned on 2K
120 * boundary)
121 */
122 #define PCIEFD_TX_PAGE_COUNT (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE)
123
124 #define CANFD_MSG_LNK_TX 0x1001 /* Tx msgs link */
125
126 /* 32-bits IRQ status fields, heading Rx DMA area */
127 static inline int pciefd_irq_tag(u32 irq_status)
128 {
129 return irq_status & 0x0000000f;
130 }
131
132 static inline int pciefd_irq_rx_cnt(u32 irq_status)
133 {
134 return (irq_status & 0x000007f0) >> 4;
135 }
136
137 static inline int pciefd_irq_is_lnk(u32 irq_status)
138 {
139 return irq_status & 0x00010000;
140 }
141
142 /* Rx record */
143 struct pciefd_rx_dma {
144 __le32 irq_status;
145 __le32 sys_time_low;
146 __le32 sys_time_high;
147 struct pucan_rx_msg msg[];
148 } __packed __aligned(4);
149
150 /* Tx Link record */
151 struct pciefd_tx_link {
152 __le16 size;
153 __le16 type;
154 __le32 laddr_lo;
155 __le32 laddr_hi;
156 } __packed __aligned(4);
157
158 /* Tx page descriptor */
159 struct pciefd_page {
160 void *vbase; /* page virtual address */
161 dma_addr_t lbase; /* page logical address */
162 u32 offset;
163 u32 size;
164 };
165
166 /* CAN-FD channel object */
167 struct pciefd_board;
168 struct pciefd_can {
169 struct peak_canfd_priv ucan; /* must be the first member */
170 void __iomem *reg_base; /* channel config base addr */
171 struct pciefd_board *board; /* reverse link */
172
173 struct pucan_command pucan_cmd; /* command buffer */
174
175 dma_addr_t rx_dma_laddr; /* DMA virtual and logical addr */
176 void *rx_dma_vaddr; /* for Rx and Tx areas */
177 dma_addr_t tx_dma_laddr;
178 void *tx_dma_vaddr;
179
180 struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT];
181 u16 tx_pages_free; /* free Tx pages counter */
182 u16 tx_page_index; /* current page used for Tx */
183 spinlock_t tx_lock;
184
185 u32 irq_status;
186 u32 irq_tag; /* next irq tag */
187 };
188
189 /* PEAK-PCIe FD board object */
190 struct pciefd_board {
191 void __iomem *reg_base;
192 struct pci_dev *pci_dev;
193 int can_count;
194 spinlock_t cmd_lock; /* 64-bits cmds must be atomic */
195 struct pciefd_can *can[]; /* array of network devices */
196 };
197
198 /* supported device ids. */
199 static const struct pci_device_id peak_pciefd_tbl[] = {
200 {PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
201 {PEAK_PCI_VENDOR_ID, PCAN_CPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
202 {PEAK_PCI_VENDOR_ID, PCAN_PCIE104FD_ID, PCI_ANY_ID, PCI_ANY_ID,},
203 {PEAK_PCI_VENDOR_ID, PCAN_MINIPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
204 {PEAK_PCI_VENDOR_ID, PCAN_PCIEFD_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,},
205 {PEAK_PCI_VENDOR_ID, PCAN_M2_ID, PCI_ANY_ID, PCI_ANY_ID,},
206 {0,}
207 };
208
209 MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl);
210
211 /* read a 32 bits value from a SYS block register */
212 static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg)
213 {
214 return readl(priv->reg_base + reg);
215 }
216
217 /* write a 32 bits value into a SYS block register */
218 static inline void pciefd_sys_writereg(const struct pciefd_board *priv,
219 u32 val, u16 reg)
220 {
221 writel(val, priv->reg_base + reg);
222 }
223
224 /* read a 32 bits value from CAN-FD block register */
225 static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg)
226 {
227 return readl(priv->reg_base + reg);
228 }
229
230 /* write a 32 bits value into a CAN-FD block register */
231 static inline void pciefd_can_writereg(const struct pciefd_can *priv,
232 u32 val, u16 reg)
233 {
234 writel(val, priv->reg_base + reg);
235 }
236
237 /* give a channel logical Rx DMA address to the board */
238 static void pciefd_can_setup_rx_dma(struct pciefd_can *priv)
239 {
240 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
241 const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32);
242 #else
243 const u32 dma_addr_h = 0;
244 #endif
245
246 /* (DMA must be reset for Rx) */
247 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET);
248
249 /* write the logical address of the Rx DMA area for this channel */
250 pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr,
251 PCIEFD_REG_CAN_RX_DMA_ADDR_L);
252 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
253
254 /* also indicates that Rx DMA is cacheable */
255 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR);
256 }
257
258 /* clear channel logical Rx DMA address from the board */
259 static void pciefd_can_clear_rx_dma(struct pciefd_can *priv)
260 {
261 /* DMA must be reset for Rx */
262 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET);
263
264 /* clear the logical address of the Rx DMA area for this channel */
265 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L);
266 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
267 }
268
269 /* give a channel logical Tx DMA address to the board */
270 static void pciefd_can_setup_tx_dma(struct pciefd_can *priv)
271 {
272 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
273 const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32);
274 #else
275 const u32 dma_addr_h = 0;
276 #endif
277
278 /* (DMA must be reset for Tx) */
279 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET);
280
281 /* write the logical address of the Tx DMA area for this channel */
282 pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr,
283 PCIEFD_REG_CAN_TX_DMA_ADDR_L);
284 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
285
286 /* also indicates that Tx DMA is cacheable */
287 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR);
288 }
289
290 /* clear channel logical Tx DMA address from the board */
291 static void pciefd_can_clear_tx_dma(struct pciefd_can *priv)
292 {
293 /* DMA must be reset for Tx */
294 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET);
295
296 /* clear the logical address of the Tx DMA area for this channel */
297 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L);
298 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
299 }
300
301 static void pciefd_can_ack_rx_dma(struct pciefd_can *priv)
302 {
303 /* read value of current IRQ tag and inc it for next one */
304 priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr);
305 priv->irq_tag++;
306 priv->irq_tag &= 0xf;
307
308 /* write the next IRQ tag for this CAN */
309 pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK);
310 }
311
312 /* IRQ handler */
313 static irqreturn_t pciefd_irq_handler(int irq, void *arg)
314 {
315 struct pciefd_can *priv = arg;
316 struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr;
317
318 /* INTA mode only to sync with PCIe transaction */
319 if (!pci_dev_msi_enabled(priv->board->pci_dev))
320 (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1);
321
322 /* read IRQ status from the first 32-bits of the Rx DMA area */
323 priv->irq_status = le32_to_cpu(rx_dma->irq_status);
324
325 /* check if this (shared) IRQ is for this CAN */
326 if (pciefd_irq_tag(priv->irq_status) != priv->irq_tag)
327 return IRQ_NONE;
328
329 /* handle rx messages (if any) */
330 peak_canfd_handle_msgs_list(&priv->ucan,
331 rx_dma->msg,
332 pciefd_irq_rx_cnt(priv->irq_status));
333
334 /* handle tx link interrupt (if any) */
335 if (pciefd_irq_is_lnk(priv->irq_status)) {
336 unsigned long flags;
337
338 spin_lock_irqsave(&priv->tx_lock, flags);
339 priv->tx_pages_free++;
340 spin_unlock_irqrestore(&priv->tx_lock, flags);
341
342 /* wake producer up (only if enough room in echo_skb array) */
343 spin_lock_irqsave(&priv->ucan.echo_lock, flags);
344 if (!priv->ucan.can.echo_skb[priv->ucan.echo_idx])
345 netif_wake_queue(priv->ucan.ndev);
346
347 spin_unlock_irqrestore(&priv->ucan.echo_lock, flags);
348 }
349
350 /* re-enable Rx DMA transfer for this CAN */
351 pciefd_can_ack_rx_dma(priv);
352
353 return IRQ_HANDLED;
354 }
355
356 static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan)
357 {
358 struct pciefd_can *priv = (struct pciefd_can *)ucan;
359 int i;
360
361 /* initialize the Tx pages descriptors */
362 priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1;
363 priv->tx_page_index = 0;
364
365 priv->tx_pages[0].vbase = priv->tx_dma_vaddr;
366 priv->tx_pages[0].lbase = priv->tx_dma_laddr;
367
368 for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) {
369 priv->tx_pages[i].offset = 0;
370 priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE -
371 sizeof(struct pciefd_tx_link);
372 if (i) {
373 priv->tx_pages[i].vbase =
374 priv->tx_pages[i - 1].vbase +
375 PCIEFD_TX_PAGE_SIZE;
376 priv->tx_pages[i].lbase =
377 priv->tx_pages[i - 1].lbase +
378 PCIEFD_TX_PAGE_SIZE;
379 }
380 }
381
382 /* setup Tx DMA addresses into IP core */
383 pciefd_can_setup_tx_dma(priv);
384
385 /* start (TX_RST=0) Tx Path */
386 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR);
387
388 return 0;
389 }
390
391 /* board specific CANFD command pre-processing */
392 static int pciefd_pre_cmd(struct peak_canfd_priv *ucan)
393 {
394 struct pciefd_can *priv = (struct pciefd_can *)ucan;
395 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd);
396 int err;
397
398 /* pre-process command */
399 switch (cmd) {
400 case PUCAN_CMD_NORMAL_MODE:
401 case PUCAN_CMD_LISTEN_ONLY_MODE:
402
403 if (ucan->can.state == CAN_STATE_BUS_OFF)
404 break;
405
406 /* going into operational mode: setup IRQ handler */
407 err = request_irq(priv->ucan.ndev->irq,
408 pciefd_irq_handler,
409 IRQF_SHARED,
410 PCIEFD_DRV_NAME,
411 priv);
412 if (err)
413 return err;
414
415 /* setup Rx DMA address */
416 pciefd_can_setup_rx_dma(priv);
417
418 /* setup max count of msgs per IRQ */
419 pciefd_can_writereg(priv, (CANFD_CTL_IRQ_TL_DEF) << 8 |
420 CANFD_CTL_IRQ_CL_DEF,
421 PCIEFD_REG_CAN_RX_CTL_WRT);
422
423 /* clear DMA RST for Rx (Rx start) */
424 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
425 PCIEFD_REG_CAN_RX_CTL_CLR);
426
427 /* reset timestamps */
428 pciefd_can_writereg(priv, !CANFD_MISC_TS_RST,
429 PCIEFD_REG_CAN_MISC);
430
431 /* do an initial ACK */
432 pciefd_can_ack_rx_dma(priv);
433
434 /* enable IRQ for this CAN after having set next irq_tag */
435 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
436 PCIEFD_REG_CAN_RX_CTL_SET);
437
438 /* Tx path will be setup as soon as RX_BARRIER is received */
439 break;
440 default:
441 break;
442 }
443
444 return 0;
445 }
446
447 /* write a command */
448 static int pciefd_write_cmd(struct peak_canfd_priv *ucan)
449 {
450 struct pciefd_can *priv = (struct pciefd_can *)ucan;
451 unsigned long flags;
452
453 /* 64-bits command is atomic */
454 spin_lock_irqsave(&priv->board->cmd_lock, flags);
455
456 pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer,
457 PCIEFD_REG_CAN_CMD_PORT_L);
458 pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4),
459 PCIEFD_REG_CAN_CMD_PORT_H);
460
461 spin_unlock_irqrestore(&priv->board->cmd_lock, flags);
462
463 return 0;
464 }
465
466 /* board specific CANFD command post-processing */
467 static int pciefd_post_cmd(struct peak_canfd_priv *ucan)
468 {
469 struct pciefd_can *priv = (struct pciefd_can *)ucan;
470 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd);
471
472 switch (cmd) {
473 case PUCAN_CMD_RESET_MODE:
474
475 if (ucan->can.state == CAN_STATE_STOPPED)
476 break;
477
478 /* controller now in reset mode: */
479
480 /* disable IRQ for this CAN */
481 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
482 PCIEFD_REG_CAN_RX_CTL_CLR);
483
484 /* stop and reset DMA addresses in Tx/Rx engines */
485 pciefd_can_clear_tx_dma(priv);
486 pciefd_can_clear_rx_dma(priv);
487
488 /* wait for above commands to complete (read cycle) */
489 (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1);
490
491 free_irq(priv->ucan.ndev->irq, priv);
492
493 ucan->can.state = CAN_STATE_STOPPED;
494
495 break;
496 }
497
498 return 0;
499 }
500
501 static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size,
502 int *room_left)
503 {
504 struct pciefd_can *priv = (struct pciefd_can *)ucan;
505 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index;
506 unsigned long flags;
507 void *msg;
508
509 spin_lock_irqsave(&priv->tx_lock, flags);
510
511 if (page->offset + msg_size > page->size) {
512 struct pciefd_tx_link *lk;
513
514 /* not enough space in this page: try another one */
515 if (!priv->tx_pages_free) {
516 spin_unlock_irqrestore(&priv->tx_lock, flags);
517
518 /* Tx overflow */
519 return NULL;
520 }
521
522 priv->tx_pages_free--;
523
524 /* keep address of the very last free slot of current page */
525 lk = page->vbase + page->offset;
526
527 /* next, move on a new free page */
528 priv->tx_page_index = (priv->tx_page_index + 1) %
529 PCIEFD_TX_PAGE_COUNT;
530 page = priv->tx_pages + priv->tx_page_index;
531
532 /* put link record to this new page at the end of prev one */
533 lk->size = cpu_to_le16(sizeof(*lk));
534 lk->type = cpu_to_le16(CANFD_MSG_LNK_TX);
535 lk->laddr_lo = cpu_to_le32(page->lbase);
536
537 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
538 lk->laddr_hi = cpu_to_le32(page->lbase >> 32);
539 #else
540 lk->laddr_hi = 0;
541 #endif
542 /* next msgs will be put from the begininng of this new page */
543 page->offset = 0;
544 }
545
546 *room_left = priv->tx_pages_free * page->size;
547
548 spin_unlock_irqrestore(&priv->tx_lock, flags);
549
550 msg = page->vbase + page->offset;
551
552 /* give back room left in the tx ring */
553 *room_left += page->size - (page->offset + msg_size);
554
555 return msg;
556 }
557
558 static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan,
559 struct pucan_tx_msg *msg)
560 {
561 struct pciefd_can *priv = (struct pciefd_can *)ucan;
562 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index;
563
564 /* this slot is now reserved for writing the frame */
565 page->offset += le16_to_cpu(msg->size);
566
567 /* tell the board a frame has been written in Tx DMA area */
568 pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC);
569
570 return 0;
571 }
572
573 /* probe for CAN-FD channel #pciefd_board->can_count */
574 static int pciefd_can_probe(struct pciefd_board *pciefd)
575 {
576 struct net_device *ndev;
577 struct pciefd_can *priv;
578 u32 clk;
579 int err;
580
581 /* allocate the candev object with default isize of echo skbs ring */
582 ndev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count,
583 PCIEFD_ECHO_SKB_MAX);
584 if (!ndev) {
585 dev_err(&pciefd->pci_dev->dev,
586 "failed to alloc candev object\n");
587 goto failure;
588 }
589
590 priv = netdev_priv(ndev);
591
592 /* fill-in candev private object: */
593
594 /* setup PCIe-FD own callbacks */
595 priv->ucan.pre_cmd = pciefd_pre_cmd;
596 priv->ucan.write_cmd = pciefd_write_cmd;
597 priv->ucan.post_cmd = pciefd_post_cmd;
598 priv->ucan.enable_tx_path = pciefd_enable_tx_path;
599 priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg;
600 priv->ucan.write_tx_msg = pciefd_write_tx_msg;
601
602 /* setup PCIe-FD own command buffer */
603 priv->ucan.cmd_buffer = &priv->pucan_cmd;
604 priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd);
605
606 priv->board = pciefd;
607
608 /* CAN config regs block address */
609 priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index);
610
611 /* allocate non-cacheable DMA'able 4KB memory area for Rx */
612 priv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,
613 PCIEFD_RX_DMA_SIZE,
614 &priv->rx_dma_laddr,
615 GFP_KERNEL);
616 if (!priv->rx_dma_vaddr) {
617 dev_err(&pciefd->pci_dev->dev,
618 "Rx dmam_alloc_coherent(%u) failure\n",
619 PCIEFD_RX_DMA_SIZE);
620 goto err_free_candev;
621 }
622
623 /* allocate non-cacheable DMA'able 4KB memory area for Tx */
624 priv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,
625 PCIEFD_TX_DMA_SIZE,
626 &priv->tx_dma_laddr,
627 GFP_KERNEL);
628 if (!priv->tx_dma_vaddr) {
629 dev_err(&pciefd->pci_dev->dev,
630 "Tx dmam_alloc_coherent(%u) failure\n",
631 PCIEFD_TX_DMA_SIZE);
632 goto err_free_candev;
633 }
634
635 /* CAN clock in RST mode */
636 pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC);
637
638 /* read current clock value */
639 clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL);
640 switch (clk) {
641 case CANFD_CLK_SEL_20MHZ:
642 priv->ucan.can.clock.freq = 20 * 1000 * 1000;
643 break;
644 case CANFD_CLK_SEL_24MHZ:
645 priv->ucan.can.clock.freq = 24 * 1000 * 1000;
646 break;
647 case CANFD_CLK_SEL_30MHZ:
648 priv->ucan.can.clock.freq = 30 * 1000 * 1000;
649 break;
650 case CANFD_CLK_SEL_40MHZ:
651 priv->ucan.can.clock.freq = 40 * 1000 * 1000;
652 break;
653 case CANFD_CLK_SEL_60MHZ:
654 priv->ucan.can.clock.freq = 60 * 1000 * 1000;
655 break;
656 default:
657 pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ,
658 PCIEFD_REG_CAN_CLK_SEL);
659
660 fallthrough;
661 case CANFD_CLK_SEL_80MHZ:
662 priv->ucan.can.clock.freq = 80 * 1000 * 1000;
663 break;
664 }
665
666 ndev->irq = pciefd->pci_dev->irq;
667
668 SET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev);
669
670 err = register_candev(ndev);
671 if (err) {
672 dev_err(&pciefd->pci_dev->dev,
673 "couldn't register CAN device: %d\n", err);
674 goto err_free_candev;
675 }
676
677 spin_lock_init(&priv->tx_lock);
678
679 /* save the object address in the board structure */
680 pciefd->can[pciefd->can_count] = priv;
681
682 dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n",
683 ndev->name, priv->reg_base, ndev->irq);
684
685 return 0;
686
687 err_free_candev:
688 free_candev(ndev);
689
690 failure:
691 return -ENOMEM;
692 }
693
694 /* remove a CAN-FD channel by releasing all of its resources */
695 static void pciefd_can_remove(struct pciefd_can *priv)
696 {
697 /* unregister (close) the can device to go back to RST mode first */
698 unregister_candev(priv->ucan.ndev);
699
700 /* finally, free the candev object */
701 free_candev(priv->ucan.ndev);
702 }
703
704 /* remove all CAN-FD channels by releasing their own resources */
705 static void pciefd_can_remove_all(struct pciefd_board *pciefd)
706 {
707 while (pciefd->can_count > 0)
708 pciefd_can_remove(pciefd->can[--pciefd->can_count]);
709 }
710
711 /* probe for the entire device */
712 static int peak_pciefd_probe(struct pci_dev *pdev,
713 const struct pci_device_id *ent)
714 {
715 struct pciefd_board *pciefd;
716 int err, can_count;
717 u16 sub_sys_id;
718 u8 hw_ver_major;
719 u8 hw_ver_minor;
720 u8 hw_ver_sub;
721 u32 v2;
722
723 err = pci_enable_device(pdev);
724 if (err)
725 return err;
726 err = pci_request_regions(pdev, PCIEFD_DRV_NAME);
727 if (err)
728 goto err_disable_pci;
729
730 /* the number of channels depends on sub-system id */
731 err = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sub_sys_id);
732 if (err)
733 goto err_release_regions;
734
735 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n",
736 pdev->vendor, pdev->device, sub_sys_id);
737
738 if (sub_sys_id >= 0x0012)
739 can_count = 4;
740 else if (sub_sys_id >= 0x0010)
741 can_count = 3;
742 else if (sub_sys_id >= 0x0004)
743 can_count = 2;
744 else
745 can_count = 1;
746
747 /* allocate board structure object */
748 pciefd = devm_kzalloc(&pdev->dev, struct_size(pciefd, can, can_count),
749 GFP_KERNEL);
750 if (!pciefd) {
751 err = -ENOMEM;
752 goto err_release_regions;
753 }
754
755 /* initialize the board structure */
756 pciefd->pci_dev = pdev;
757 spin_lock_init(&pciefd->cmd_lock);
758
759 /* save the PCI BAR0 virtual address for further system regs access */
760 pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE);
761 if (!pciefd->reg_base) {
762 dev_err(&pdev->dev, "failed to map PCI resource #0\n");
763 err = -ENOMEM;
764 goto err_release_regions;
765 }
766
767 /* read the firmware version number */
768 v2 = pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER2);
769
770 hw_ver_major = (v2 & 0x0000f000) >> 12;
771 hw_ver_minor = (v2 & 0x00000f00) >> 8;
772 hw_ver_sub = (v2 & 0x000000f0) >> 4;
773
774 dev_info(&pdev->dev,
775 "%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n", can_count,
776 hw_ver_major, hw_ver_minor, hw_ver_sub);
777
778 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
779 /* FW < v3.3.0 DMA logic doesn't handle correctly the mix of 32-bit and
780 * 64-bit logical addresses: this workaround forces usage of 32-bit
781 * DMA addresses only when such a fw is detected.
782 */
783 if (PCIEFD_FW_VERSION(hw_ver_major, hw_ver_minor, hw_ver_sub) <
784 PCIEFD_FW_VERSION(3, 3, 0)) {
785 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
786 if (err)
787 dev_warn(&pdev->dev,
788 "warning: can't set DMA mask %llxh (err %d)\n",
789 DMA_BIT_MASK(32), err);
790 }
791 #endif
792
793 /* stop system clock */
794 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN,
795 PCIEFD_REG_SYS_CTL_CLR);
796
797 pci_set_master(pdev);
798
799 /* create now the corresponding channels objects */
800 while (pciefd->can_count < can_count) {
801 err = pciefd_can_probe(pciefd);
802 if (err)
803 goto err_free_canfd;
804
805 pciefd->can_count++;
806 }
807
808 /* set system timestamps counter in RST mode */
809 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST,
810 PCIEFD_REG_SYS_CTL_SET);
811
812 /* wait a bit (read cycle) */
813 (void)pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER1);
814
815 /* free all clocks */
816 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST,
817 PCIEFD_REG_SYS_CTL_CLR);
818
819 /* start system clock */
820 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN,
821 PCIEFD_REG_SYS_CTL_SET);
822
823 /* remember the board structure address in the device user data */
824 pci_set_drvdata(pdev, pciefd);
825
826 return 0;
827
828 err_free_canfd:
829 pciefd_can_remove_all(pciefd);
830
831 pci_iounmap(pdev, pciefd->reg_base);
832
833 err_release_regions:
834 pci_release_regions(pdev);
835
836 err_disable_pci:
837 pci_disable_device(pdev);
838
839 /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while
840 * the probe() function must return a negative errno in case of failure
841 * (err is unchanged if negative)
842 */
843 return pcibios_err_to_errno(err);
844 }
845
846 /* free the board structure object, as well as its resources: */
847 static void peak_pciefd_remove(struct pci_dev *pdev)
848 {
849 struct pciefd_board *pciefd = pci_get_drvdata(pdev);
850
851 /* release CAN-FD channels resources */
852 pciefd_can_remove_all(pciefd);
853
854 pci_iounmap(pdev, pciefd->reg_base);
855
856 pci_release_regions(pdev);
857 pci_disable_device(pdev);
858 }
859
860 static struct pci_driver peak_pciefd_driver = {
861 .name = PCIEFD_DRV_NAME,
862 .id_table = peak_pciefd_tbl,
863 .probe = peak_pciefd_probe,
864 .remove = peak_pciefd_remove,
865 };
866
867 module_pci_driver(peak_pciefd_driver);
Linux with added FPC-III support