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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / dsa / lantiq_gswip.c
blob662e68a0e7e61d3629b70a96cfd603e26be2d2d8
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs
4 *
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8 *
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
11 *
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
18 *
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
26 */
27
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/etherdevice.h>
31 #include <linux/firmware.h>
32 #include <linux/if_bridge.h>
33 #include <linux/if_vlan.h>
34 #include <linux/iopoll.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/module.h>
37 #include <linux/of_mdio.h>
38 #include <linux/of_net.h>
39 #include <linux/of_platform.h>
40 #include <linux/phy.h>
41 #include <linux/phylink.h>
42 #include <linux/platform_device.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
45 #include <net/dsa.h>
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
47
48 #include "lantiq_pce.h"
49
50 /* GSWIP MDIO Registers */
51 #define GSWIP_MDIO_GLOB 0x00
52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15)
53 #define GSWIP_MDIO_CTRL 0x08
54 #define GSWIP_MDIO_CTRL_BUSY BIT(12)
55 #define GSWIP_MDIO_CTRL_RD BIT(11)
56 #define GSWIP_MDIO_CTRL_WR BIT(10)
57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
60 #define GSWIP_MDIO_READ 0x09
61 #define GSWIP_MDIO_WRITE 0x0A
62 #define GSWIP_MDIO_MDC_CFG0 0x0B
63 #define GSWIP_MDIO_MDC_CFG1 0x0C
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000
66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000
69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000
72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800
73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000
74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200
77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
88 GSWIP_MDIO_PHY_FCONRX_MASK | \
89 GSWIP_MDIO_PHY_FCONTX_MASK | \
90 GSWIP_MDIO_PHY_LINK_MASK | \
91 GSWIP_MDIO_PHY_SPEED_MASK | \
92 GSWIP_MDIO_PHY_FDUP_MASK)
93
94 /* GSWIP MII Registers */
95 #define GSWIP_MII_CFGp(p) (0x2 * (p))
96 #define GSWIP_MII_CFG_EN BIT(14)
97 #define GSWIP_MII_CFG_LDCLKDIS BIT(12)
98 #define GSWIP_MII_CFG_MODE_MIIP 0x0
99 #define GSWIP_MII_CFG_MODE_MIIM 0x1
100 #define GSWIP_MII_CFG_MODE_RMIIP 0x2
101 #define GSWIP_MII_CFG_MODE_RMIIM 0x3
102 #define GSWIP_MII_CFG_MODE_RGMII 0x4
103 #define GSWIP_MII_CFG_MODE_MASK 0xf
104 #define GSWIP_MII_CFG_RATE_M2P5 0x00
105 #define GSWIP_MII_CFG_RATE_M25 0x10
106 #define GSWIP_MII_CFG_RATE_M125 0x20
107 #define GSWIP_MII_CFG_RATE_M50 0x30
108 #define GSWIP_MII_CFG_RATE_AUTO 0x40
109 #define GSWIP_MII_CFG_RATE_MASK 0x70
110 #define GSWIP_MII_PCDU0 0x01
111 #define GSWIP_MII_PCDU1 0x03
112 #define GSWIP_MII_PCDU5 0x05
113 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
114 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
115
116 /* GSWIP Core Registers */
117 #define GSWIP_SWRES 0x000
118 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
119 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
120 #define GSWIP_VERSION 0x013
121 #define GSWIP_VERSION_REV_SHIFT 0
122 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
123 #define GSWIP_VERSION_MOD_SHIFT 8
124 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
125 #define GSWIP_VERSION_2_0 0x100
126 #define GSWIP_VERSION_2_1 0x021
127 #define GSWIP_VERSION_2_2 0x122
128 #define GSWIP_VERSION_2_2_ETC 0x022
129
130 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
131 #define GSWIP_BM_RAM_ADDR 0x044
132 #define GSWIP_BM_RAM_CTRL 0x045
133 #define GSWIP_BM_RAM_CTRL_BAS BIT(15)
134 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
135 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
136 #define GSWIP_BM_QUEUE_GCTRL 0x04A
137 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
138 /* buffer management Port Configuration Register */
139 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
140 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
141 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
142 /* buffer management Port Control Register */
143 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
144 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
145 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
146
147 /* PCE */
148 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
149 #define GSWIP_PCE_TBL_MASK 0x448
150 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
151 #define GSWIP_PCE_TBL_ADDR 0x44E
152 #define GSWIP_PCE_TBL_CTRL 0x44F
153 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
154 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
155 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
156 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
157 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
158 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
159 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
160 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
161 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
162 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
163 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
164 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
165 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
166 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
167 #define GSWIP_PCE_GCTRL_0 0x456
168 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
169 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
170 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
171 #define GSWIP_PCE_GCTRL_1 0x457
172 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
173 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
174 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
175 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
176 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
177 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
178 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
179 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
180 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
181 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
182 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
183 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
184 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
185 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
186 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
187 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
188 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
189 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
190 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
191
192 #define GSWIP_MAC_FLEN 0x8C5
193 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
194 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
195
196 /* Ethernet Switch Fetch DMA Port Control Register */
197 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
198 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
199 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
200 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
201 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
202 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
203 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
204 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
205 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
206
207 /* Ethernet Switch Store DMA Port Control Register */
208 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
209 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
210 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
211 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */
212
213 #define GSWIP_TABLE_ACTIVE_VLAN 0x01
214 #define GSWIP_TABLE_VLAN_MAPPING 0x02
215 #define GSWIP_TABLE_MAC_BRIDGE 0x0b
216 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
217
218 #define XRX200_GPHY_FW_ALIGN (16 * 1024)
219
220 struct gswip_hw_info {
221 int max_ports;
222 int cpu_port;
223 };
224
225 struct xway_gphy_match_data {
226 char *fe_firmware_name;
227 char *ge_firmware_name;
228 };
229
230 struct gswip_gphy_fw {
231 struct clk *clk_gate;
232 struct reset_control *reset;
233 u32 fw_addr_offset;
234 char *fw_name;
235 };
236
237 struct gswip_vlan {
238 struct net_device *bridge;
239 u16 vid;
240 u8 fid;
241 };
242
243 struct gswip_priv {
244 __iomem void *gswip;
245 __iomem void *mdio;
246 __iomem void *mii;
247 const struct gswip_hw_info *hw_info;
248 const struct xway_gphy_match_data *gphy_fw_name_cfg;
249 struct dsa_switch *ds;
250 struct device *dev;
251 struct regmap *rcu_regmap;
252 struct gswip_vlan vlans[64];
253 int num_gphy_fw;
254 struct gswip_gphy_fw *gphy_fw;
255 u32 port_vlan_filter;
256 };
257
258 struct gswip_pce_table_entry {
259 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
260 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
261 u16 key[8];
262 u16 val[5];
263 u16 mask;
264 u8 gmap;
265 bool type;
266 bool valid;
267 bool key_mode;
268 };
269
270 struct gswip_rmon_cnt_desc {
271 unsigned int size;
272 unsigned int offset;
273 const char *name;
274 };
275
276 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
277
278 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
279 /** Receive Packet Count (only packets that are accepted and not discarded). */
280 MIB_DESC(1, 0x1F, "RxGoodPkts"),
281 MIB_DESC(1, 0x23, "RxUnicastPkts"),
282 MIB_DESC(1, 0x22, "RxMulticastPkts"),
283 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
284 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
285 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
286 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
287 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
288 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
289 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
290 MIB_DESC(1, 0x12, "Rx64BytePkts"),
291 MIB_DESC(1, 0x13, "Rx127BytePkts"),
292 MIB_DESC(1, 0x14, "Rx255BytePkts"),
293 MIB_DESC(1, 0x15, "Rx511BytePkts"),
294 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
295 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
296 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
297 MIB_DESC(1, 0x18, "RxDroppedPkts"),
298 MIB_DESC(1, 0x19, "RxFilteredPkts"),
299 MIB_DESC(2, 0x24, "RxGoodBytes"),
300 MIB_DESC(2, 0x26, "RxBadBytes"),
301 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
302 MIB_DESC(1, 0x0C, "TxGoodPkts"),
303 MIB_DESC(1, 0x06, "TxUnicastPkts"),
304 MIB_DESC(1, 0x07, "TxMulticastPkts"),
305 MIB_DESC(1, 0x00, "Tx64BytePkts"),
306 MIB_DESC(1, 0x01, "Tx127BytePkts"),
307 MIB_DESC(1, 0x02, "Tx255BytePkts"),
308 MIB_DESC(1, 0x03, "Tx511BytePkts"),
309 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
310 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
311 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
312 MIB_DESC(1, 0x08, "TxSingleCollCount"),
313 MIB_DESC(1, 0x09, "TxMultCollCount"),
314 MIB_DESC(1, 0x0A, "TxLateCollCount"),
315 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
316 MIB_DESC(1, 0x0D, "TxPauseCount"),
317 MIB_DESC(1, 0x10, "TxDroppedPkts"),
318 MIB_DESC(2, 0x0E, "TxGoodBytes"),
319 };
320
321 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
322 {
323 return __raw_readl(priv->gswip + (offset * 4));
324 }
325
326 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
327 {
328 __raw_writel(val, priv->gswip + (offset * 4));
329 }
330
331 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
332 u32 offset)
333 {
334 u32 val = gswip_switch_r(priv, offset);
335
336 val &= ~(clear);
337 val |= set;
338 gswip_switch_w(priv, val, offset);
339 }
340
341 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
342 u32 cleared)
343 {
344 u32 val;
345
346 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
347 (val & cleared) == 0, 20, 50000);
348 }
349
350 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
351 {
352 return __raw_readl(priv->mdio + (offset * 4));
353 }
354
355 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
356 {
357 __raw_writel(val, priv->mdio + (offset * 4));
358 }
359
360 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
361 u32 offset)
362 {
363 u32 val = gswip_mdio_r(priv, offset);
364
365 val &= ~(clear);
366 val |= set;
367 gswip_mdio_w(priv, val, offset);
368 }
369
370 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
371 {
372 return __raw_readl(priv->mii + (offset * 4));
373 }
374
375 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
376 {
377 __raw_writel(val, priv->mii + (offset * 4));
378 }
379
380 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
381 u32 offset)
382 {
383 u32 val = gswip_mii_r(priv, offset);
384
385 val &= ~(clear);
386 val |= set;
387 gswip_mii_w(priv, val, offset);
388 }
389
390 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
391 int port)
392 {
393 /* There's no MII_CFG register for the CPU port */
394 if (!dsa_is_cpu_port(priv->ds, port))
395 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
396 }
397
398 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
399 int port)
400 {
401 switch (port) {
402 case 0:
403 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
404 break;
405 case 1:
406 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
407 break;
408 case 5:
409 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
410 break;
411 }
412 }
413
414 static int gswip_mdio_poll(struct gswip_priv *priv)
415 {
416 int cnt = 100;
417
418 while (likely(cnt--)) {
419 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
420
421 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
422 return 0;
423 usleep_range(20, 40);
424 }
425
426 return -ETIMEDOUT;
427 }
428
429 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
430 {
431 struct gswip_priv *priv = bus->priv;
432 int err;
433
434 err = gswip_mdio_poll(priv);
435 if (err) {
436 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
437 return err;
438 }
439
440 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
441 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
442 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
443 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
444 GSWIP_MDIO_CTRL);
445
446 return 0;
447 }
448
449 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
450 {
451 struct gswip_priv *priv = bus->priv;
452 int err;
453
454 err = gswip_mdio_poll(priv);
455 if (err) {
456 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
457 return err;
458 }
459
460 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
461 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
462 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
463 GSWIP_MDIO_CTRL);
464
465 err = gswip_mdio_poll(priv);
466 if (err) {
467 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
468 return err;
469 }
470
471 return gswip_mdio_r(priv, GSWIP_MDIO_READ);
472 }
473
474 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
475 {
476 struct dsa_switch *ds = priv->ds;
477
478 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev);
479 if (!ds->slave_mii_bus)
480 return -ENOMEM;
481
482 ds->slave_mii_bus->priv = priv;
483 ds->slave_mii_bus->read = gswip_mdio_rd;
484 ds->slave_mii_bus->write = gswip_mdio_wr;
485 ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
486 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
487 dev_name(priv->dev));
488 ds->slave_mii_bus->parent = priv->dev;
489 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
490
491 return of_mdiobus_register(ds->slave_mii_bus, mdio_np);
492 }
493
494 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
495 struct gswip_pce_table_entry *tbl)
496 {
497 int i;
498 int err;
499 u16 crtl;
500 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
501 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
502
503 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
504 GSWIP_PCE_TBL_CTRL_BAS);
505 if (err)
506 return err;
507
508 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
509 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
510 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
511 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
512 GSWIP_PCE_TBL_CTRL);
513
514 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
515 GSWIP_PCE_TBL_CTRL_BAS);
516 if (err)
517 return err;
518
519 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
520 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
521
522 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
523 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
524
525 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
526
527 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
528
529 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
530 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
531 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
532
533 return 0;
534 }
535
536 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
537 struct gswip_pce_table_entry *tbl)
538 {
539 int i;
540 int err;
541 u16 crtl;
542 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
543 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
544
545 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
546 GSWIP_PCE_TBL_CTRL_BAS);
547 if (err)
548 return err;
549
550 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
551 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
552 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
553 tbl->table | addr_mode,
554 GSWIP_PCE_TBL_CTRL);
555
556 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
557 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
558
559 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
560 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
561
562 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
563 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
564 tbl->table | addr_mode,
565 GSWIP_PCE_TBL_CTRL);
566
567 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
568
569 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
570 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
571 GSWIP_PCE_TBL_CTRL_GMAP_MASK);
572 if (tbl->type)
573 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
574 if (tbl->valid)
575 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
576 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
577 crtl |= GSWIP_PCE_TBL_CTRL_BAS;
578 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
579
580 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
581 GSWIP_PCE_TBL_CTRL_BAS);
582 }
583
584 /* Add the LAN port into a bridge with the CPU port by
585 * default. This prevents automatic forwarding of
586 * packages between the LAN ports when no explicit
587 * bridge is configured.
588 */
589 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
590 {
591 struct gswip_pce_table_entry vlan_active = {0,};
592 struct gswip_pce_table_entry vlan_mapping = {0,};
593 unsigned int cpu_port = priv->hw_info->cpu_port;
594 unsigned int max_ports = priv->hw_info->max_ports;
595 int err;
596
597 if (port >= max_ports) {
598 dev_err(priv->dev, "single port for %i supported\n", port);
599 return -EIO;
600 }
601
602 vlan_active.index = port + 1;
603 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
604 vlan_active.key[0] = 0; /* vid */
605 vlan_active.val[0] = port + 1 /* fid */;
606 vlan_active.valid = add;
607 err = gswip_pce_table_entry_write(priv, &vlan_active);
608 if (err) {
609 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
610 return err;
611 }
612
613 if (!add)
614 return 0;
615
616 vlan_mapping.index = port + 1;
617 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
618 vlan_mapping.val[0] = 0 /* vid */;
619 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
620 vlan_mapping.val[2] = 0;
621 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
622 if (err) {
623 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
624 return err;
625 }
626
627 return 0;
628 }
629
630 static int gswip_port_enable(struct dsa_switch *ds, int port,
631 struct phy_device *phydev)
632 {
633 struct gswip_priv *priv = ds->priv;
634 int err;
635
636 if (!dsa_is_user_port(ds, port))
637 return 0;
638
639 if (!dsa_is_cpu_port(ds, port)) {
640 err = gswip_add_single_port_br(priv, port, true);
641 if (err)
642 return err;
643 }
644
645 /* RMON Counter Enable for port */
646 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
647
648 /* enable port fetch/store dma & VLAN Modification */
649 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
650 GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
651 GSWIP_FDMA_PCTRLp(port));
652 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
653 GSWIP_SDMA_PCTRLp(port));
654
655 if (!dsa_is_cpu_port(ds, port)) {
656 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO |
657 GSWIP_MDIO_PHY_SPEED_AUTO |
658 GSWIP_MDIO_PHY_FDUP_AUTO |
659 GSWIP_MDIO_PHY_FCONTX_AUTO |
660 GSWIP_MDIO_PHY_FCONRX_AUTO |
661 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK);
662
663 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port));
664 /* Activate MDIO auto polling */
665 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0);
666 }
667
668 return 0;
669 }
670
671 static void gswip_port_disable(struct dsa_switch *ds, int port)
672 {
673 struct gswip_priv *priv = ds->priv;
674
675 if (!dsa_is_user_port(ds, port))
676 return;
677
678 if (!dsa_is_cpu_port(ds, port)) {
679 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN,
680 GSWIP_MDIO_PHY_LINK_MASK,
681 GSWIP_MDIO_PHYp(port));
682 /* Deactivate MDIO auto polling */
683 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0);
684 }
685
686 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
687 GSWIP_FDMA_PCTRLp(port));
688 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
689 GSWIP_SDMA_PCTRLp(port));
690 }
691
692 static int gswip_pce_load_microcode(struct gswip_priv *priv)
693 {
694 int i;
695 int err;
696
697 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
698 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
699 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
700 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
701
702 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
703 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
704 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
705 GSWIP_PCE_TBL_VAL(0));
706 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
707 GSWIP_PCE_TBL_VAL(1));
708 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
709 GSWIP_PCE_TBL_VAL(2));
710 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
711 GSWIP_PCE_TBL_VAL(3));
712
713 /* start the table access: */
714 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
715 GSWIP_PCE_TBL_CTRL);
716 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
717 GSWIP_PCE_TBL_CTRL_BAS);
718 if (err)
719 return err;
720 }
721
722 /* tell the switch that the microcode is loaded */
723 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
724 GSWIP_PCE_GCTRL_0);
725
726 return 0;
727 }
728
729 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
730 bool vlan_filtering,
731 struct switchdev_trans *trans)
732 {
733 struct gswip_priv *priv = ds->priv;
734
735 /* Do not allow changing the VLAN filtering options while in bridge */
736 if (switchdev_trans_ph_prepare(trans)) {
737 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
738
739 if (!bridge)
740 return 0;
741
742 if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering)
743 return -EIO;
744
745 return 0;
746 }
747
748 if (vlan_filtering) {
749 /* Use port based VLAN tag */
750 gswip_switch_mask(priv,
751 GSWIP_PCE_VCTRL_VSR,
752 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
753 GSWIP_PCE_VCTRL_VEMR,
754 GSWIP_PCE_VCTRL(port));
755 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
756 GSWIP_PCE_PCTRL_0p(port));
757 } else {
758 /* Use port based VLAN tag */
759 gswip_switch_mask(priv,
760 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
761 GSWIP_PCE_VCTRL_VEMR,
762 GSWIP_PCE_VCTRL_VSR,
763 GSWIP_PCE_VCTRL(port));
764 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
765 GSWIP_PCE_PCTRL_0p(port));
766 }
767
768 return 0;
769 }
770
771 static int gswip_setup(struct dsa_switch *ds)
772 {
773 struct gswip_priv *priv = ds->priv;
774 unsigned int cpu_port = priv->hw_info->cpu_port;
775 int i;
776 int err;
777
778 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
779 usleep_range(5000, 10000);
780 gswip_switch_w(priv, 0, GSWIP_SWRES);
781
782 /* disable port fetch/store dma on all ports */
783 for (i = 0; i < priv->hw_info->max_ports; i++) {
784 struct switchdev_trans trans;
785
786 /* Skip the prepare phase, this shouldn't return an error
787 * during setup.
788 */
789 trans.ph_prepare = false;
790
791 gswip_port_disable(ds, i);
792 gswip_port_vlan_filtering(ds, i, false, &trans);
793 }
794
795 /* enable Switch */
796 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
797
798 err = gswip_pce_load_microcode(priv);
799 if (err) {
800 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
801 return err;
802 }
803
804 /* Default unknown Broadcast/Multicast/Unicast port maps */
805 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
806 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
807 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
808
809 /* disable PHY auto polling */
810 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
811 /* Configure the MDIO Clock 2.5 MHz */
812 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
813
814 /* Disable the xMII link */
815 for (i = 0; i < priv->hw_info->max_ports; i++)
816 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i);
817
818 /* enable special tag insertion on cpu port */
819 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
820 GSWIP_FDMA_PCTRLp(cpu_port));
821
822 /* accept special tag in ingress direction */
823 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
824 GSWIP_PCE_PCTRL_0p(cpu_port));
825
826 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
827 GSWIP_MAC_CTRL_2p(cpu_port));
828 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN);
829 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
830 GSWIP_BM_QUEUE_GCTRL);
831
832 /* VLAN aware Switching */
833 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
834
835 /* Flush MAC Table */
836 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
837
838 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
839 GSWIP_PCE_GCTRL_0_MTFL);
840 if (err) {
841 dev_err(priv->dev, "MAC flushing didn't finish\n");
842 return err;
843 }
844
845 gswip_port_enable(ds, cpu_port, NULL);
846 return 0;
847 }
848
849 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
850 int port,
851 enum dsa_tag_protocol mp)
852 {
853 return DSA_TAG_PROTO_GSWIP;
854 }
855
856 static int gswip_vlan_active_create(struct gswip_priv *priv,
857 struct net_device *bridge,
858 int fid, u16 vid)
859 {
860 struct gswip_pce_table_entry vlan_active = {0,};
861 unsigned int max_ports = priv->hw_info->max_ports;
862 int idx = -1;
863 int err;
864 int i;
865
866 /* Look for a free slot */
867 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
868 if (!priv->vlans[i].bridge) {
869 idx = i;
870 break;
871 }
872 }
873
874 if (idx == -1)
875 return -ENOSPC;
876
877 if (fid == -1)
878 fid = idx;
879
880 vlan_active.index = idx;
881 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
882 vlan_active.key[0] = vid;
883 vlan_active.val[0] = fid;
884 vlan_active.valid = true;
885
886 err = gswip_pce_table_entry_write(priv, &vlan_active);
887 if (err) {
888 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
889 return err;
890 }
891
892 priv->vlans[idx].bridge = bridge;
893 priv->vlans[idx].vid = vid;
894 priv->vlans[idx].fid = fid;
895
896 return idx;
897 }
898
899 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
900 {
901 struct gswip_pce_table_entry vlan_active = {0,};
902 int err;
903
904 vlan_active.index = idx;
905 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
906 vlan_active.valid = false;
907 err = gswip_pce_table_entry_write(priv, &vlan_active);
908 if (err)
909 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
910 priv->vlans[idx].bridge = NULL;
911
912 return err;
913 }
914
915 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
916 struct net_device *bridge, int port)
917 {
918 struct gswip_pce_table_entry vlan_mapping = {0,};
919 unsigned int max_ports = priv->hw_info->max_ports;
920 unsigned int cpu_port = priv->hw_info->cpu_port;
921 bool active_vlan_created = false;
922 int idx = -1;
923 int i;
924 int err;
925
926 /* Check if there is already a page for this bridge */
927 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
928 if (priv->vlans[i].bridge == bridge) {
929 idx = i;
930 break;
931 }
932 }
933
934 /* If this bridge is not programmed yet, add a Active VLAN table
935 * entry in a free slot and prepare the VLAN mapping table entry.
936 */
937 if (idx == -1) {
938 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
939 if (idx < 0)
940 return idx;
941 active_vlan_created = true;
942
943 vlan_mapping.index = idx;
944 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
945 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
946 vlan_mapping.val[0] = 0;
947 } else {
948 /* Read the existing VLAN mapping entry from the switch */
949 vlan_mapping.index = idx;
950 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
951 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
952 if (err) {
953 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
954 err);
955 return err;
956 }
957 }
958
959 /* Update the VLAN mapping entry and write it to the switch */
960 vlan_mapping.val[1] |= BIT(cpu_port);
961 vlan_mapping.val[1] |= BIT(port);
962 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
963 if (err) {
964 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
965 /* In case an Active VLAN was creaetd delete it again */
966 if (active_vlan_created)
967 gswip_vlan_active_remove(priv, idx);
968 return err;
969 }
970
971 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
972 return 0;
973 }
974
975 static int gswip_vlan_add_aware(struct gswip_priv *priv,
976 struct net_device *bridge, int port,
977 u16 vid, bool untagged,
978 bool pvid)
979 {
980 struct gswip_pce_table_entry vlan_mapping = {0,};
981 unsigned int max_ports = priv->hw_info->max_ports;
982 unsigned int cpu_port = priv->hw_info->cpu_port;
983 bool active_vlan_created = false;
984 int idx = -1;
985 int fid = -1;
986 int i;
987 int err;
988
989 /* Check if there is already a page for this bridge */
990 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
991 if (priv->vlans[i].bridge == bridge) {
992 if (fid != -1 && fid != priv->vlans[i].fid)
993 dev_err(priv->dev, "one bridge with multiple flow ids\n");
994 fid = priv->vlans[i].fid;
995 if (priv->vlans[i].vid == vid) {
996 idx = i;
997 break;
998 }
999 }
1000 }
1001
1002 /* If this bridge is not programmed yet, add a Active VLAN table
1003 * entry in a free slot and prepare the VLAN mapping table entry.
1004 */
1005 if (idx == -1) {
1006 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1007 if (idx < 0)
1008 return idx;
1009 active_vlan_created = true;
1010
1011 vlan_mapping.index = idx;
1012 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1013 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1014 vlan_mapping.val[0] = vid;
1015 } else {
1016 /* Read the existing VLAN mapping entry from the switch */
1017 vlan_mapping.index = idx;
1018 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1019 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1020 if (err) {
1021 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1022 err);
1023 return err;
1024 }
1025 }
1026
1027 vlan_mapping.val[0] = vid;
1028 /* Update the VLAN mapping entry and write it to the switch */
1029 vlan_mapping.val[1] |= BIT(cpu_port);
1030 vlan_mapping.val[2] |= BIT(cpu_port);
1031 vlan_mapping.val[1] |= BIT(port);
1032 if (untagged)
1033 vlan_mapping.val[2] &= ~BIT(port);
1034 else
1035 vlan_mapping.val[2] |= BIT(port);
1036 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1037 if (err) {
1038 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1039 /* In case an Active VLAN was creaetd delete it again */
1040 if (active_vlan_created)
1041 gswip_vlan_active_remove(priv, idx);
1042 return err;
1043 }
1044
1045 if (pvid)
1046 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1047
1048 return 0;
1049 }
1050
1051 static int gswip_vlan_remove(struct gswip_priv *priv,
1052 struct net_device *bridge, int port,
1053 u16 vid, bool pvid, bool vlan_aware)
1054 {
1055 struct gswip_pce_table_entry vlan_mapping = {0,};
1056 unsigned int max_ports = priv->hw_info->max_ports;
1057 unsigned int cpu_port = priv->hw_info->cpu_port;
1058 int idx = -1;
1059 int i;
1060 int err;
1061
1062 /* Check if there is already a page for this bridge */
1063 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1064 if (priv->vlans[i].bridge == bridge &&
1065 (!vlan_aware || priv->vlans[i].vid == vid)) {
1066 idx = i;
1067 break;
1068 }
1069 }
1070
1071 if (idx == -1) {
1072 dev_err(priv->dev, "bridge to leave does not exists\n");
1073 return -ENOENT;
1074 }
1075
1076 vlan_mapping.index = idx;
1077 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1078 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1079 if (err) {
1080 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1081 return err;
1082 }
1083
1084 vlan_mapping.val[1] &= ~BIT(port);
1085 vlan_mapping.val[2] &= ~BIT(port);
1086 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1087 if (err) {
1088 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1089 return err;
1090 }
1091
1092 /* In case all ports are removed from the bridge, remove the VLAN */
1093 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1094 err = gswip_vlan_active_remove(priv, idx);
1095 if (err) {
1096 dev_err(priv->dev, "failed to write active VLAN: %d\n",
1097 err);
1098 return err;
1099 }
1100 }
1101
1102 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1103 if (pvid)
1104 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1105
1106 return 0;
1107 }
1108
1109 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1110 struct net_device *bridge)
1111 {
1112 struct gswip_priv *priv = ds->priv;
1113 int err;
1114
1115 /* When the bridge uses VLAN filtering we have to configure VLAN
1116 * specific bridges. No bridge is configured here.
1117 */
1118 if (!br_vlan_enabled(bridge)) {
1119 err = gswip_vlan_add_unaware(priv, bridge, port);
1120 if (err)
1121 return err;
1122 priv->port_vlan_filter &= ~BIT(port);
1123 } else {
1124 priv->port_vlan_filter |= BIT(port);
1125 }
1126 return gswip_add_single_port_br(priv, port, false);
1127 }
1128
1129 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1130 struct net_device *bridge)
1131 {
1132 struct gswip_priv *priv = ds->priv;
1133
1134 gswip_add_single_port_br(priv, port, true);
1135
1136 /* When the bridge uses VLAN filtering we have to configure VLAN
1137 * specific bridges. No bridge is configured here.
1138 */
1139 if (!br_vlan_enabled(bridge))
1140 gswip_vlan_remove(priv, bridge, port, 0, true, false);
1141 }
1142
1143 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1144 const struct switchdev_obj_port_vlan *vlan)
1145 {
1146 struct gswip_priv *priv = ds->priv;
1147 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1148 unsigned int max_ports = priv->hw_info->max_ports;
1149 u16 vid;
1150 int i;
1151 int pos = max_ports;
1152
1153 /* We only support VLAN filtering on bridges */
1154 if (!dsa_is_cpu_port(ds, port) && !bridge)
1155 return -EOPNOTSUPP;
1156
1157 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1158 int idx = -1;
1159
1160 /* Check if there is already a page for this VLAN */
1161 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1162 if (priv->vlans[i].bridge == bridge &&
1163 priv->vlans[i].vid == vid) {
1164 idx = i;
1165 break;
1166 }
1167 }
1168
1169 /* If this VLAN is not programmed yet, we have to reserve
1170 * one entry in the VLAN table. Make sure we start at the
1171 * next position round.
1172 */
1173 if (idx == -1) {
1174 /* Look for a free slot */
1175 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1176 if (!priv->vlans[pos].bridge) {
1177 idx = pos;
1178 pos++;
1179 break;
1180 }
1181 }
1182
1183 if (idx == -1)
1184 return -ENOSPC;
1185 }
1186 }
1187
1188 return 0;
1189 }
1190
1191 static void gswip_port_vlan_add(struct dsa_switch *ds, int port,
1192 const struct switchdev_obj_port_vlan *vlan)
1193 {
1194 struct gswip_priv *priv = ds->priv;
1195 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1196 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1197 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1198 u16 vid;
1199
1200 /* We have to receive all packets on the CPU port and should not
1201 * do any VLAN filtering here. This is also called with bridge
1202 * NULL and then we do not know for which bridge to configure
1203 * this.
1204 */
1205 if (dsa_is_cpu_port(ds, port))
1206 return;
1207
1208 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1209 gswip_vlan_add_aware(priv, bridge, port, vid, untagged, pvid);
1210 }
1211
1212 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1213 const struct switchdev_obj_port_vlan *vlan)
1214 {
1215 struct gswip_priv *priv = ds->priv;
1216 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1217 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1218 u16 vid;
1219 int err;
1220
1221 /* We have to receive all packets on the CPU port and should not
1222 * do any VLAN filtering here. This is also called with bridge
1223 * NULL and then we do not know for which bridge to configure
1224 * this.
1225 */
1226 if (dsa_is_cpu_port(ds, port))
1227 return 0;
1228
1229 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1230 err = gswip_vlan_remove(priv, bridge, port, vid, pvid, true);
1231 if (err)
1232 return err;
1233 }
1234
1235 return 0;
1236 }
1237
1238 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1239 {
1240 struct gswip_priv *priv = ds->priv;
1241 struct gswip_pce_table_entry mac_bridge = {0,};
1242 int i;
1243 int err;
1244
1245 for (i = 0; i < 2048; i++) {
1246 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1247 mac_bridge.index = i;
1248
1249 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1250 if (err) {
1251 dev_err(priv->dev, "failed to read mac bridge: %d\n",
1252 err);
1253 return;
1254 }
1255
1256 if (!mac_bridge.valid)
1257 continue;
1258
1259 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1260 continue;
1261
1262 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1263 continue;
1264
1265 mac_bridge.valid = false;
1266 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1267 if (err) {
1268 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1269 err);
1270 return;
1271 }
1272 }
1273 }
1274
1275 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1276 {
1277 struct gswip_priv *priv = ds->priv;
1278 u32 stp_state;
1279
1280 switch (state) {
1281 case BR_STATE_DISABLED:
1282 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1283 GSWIP_SDMA_PCTRLp(port));
1284 return;
1285 case BR_STATE_BLOCKING:
1286 case BR_STATE_LISTENING:
1287 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1288 break;
1289 case BR_STATE_LEARNING:
1290 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1291 break;
1292 case BR_STATE_FORWARDING:
1293 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1294 break;
1295 default:
1296 dev_err(priv->dev, "invalid STP state: %d\n", state);
1297 return;
1298 }
1299
1300 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1301 GSWIP_SDMA_PCTRLp(port));
1302 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1303 GSWIP_PCE_PCTRL_0p(port));
1304 }
1305
1306 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1307 const unsigned char *addr, u16 vid, bool add)
1308 {
1309 struct gswip_priv *priv = ds->priv;
1310 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1311 struct gswip_pce_table_entry mac_bridge = {0,};
1312 unsigned int cpu_port = priv->hw_info->cpu_port;
1313 int fid = -1;
1314 int i;
1315 int err;
1316
1317 if (!bridge)
1318 return -EINVAL;
1319
1320 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1321 if (priv->vlans[i].bridge == bridge) {
1322 fid = priv->vlans[i].fid;
1323 break;
1324 }
1325 }
1326
1327 if (fid == -1) {
1328 dev_err(priv->dev, "Port not part of a bridge\n");
1329 return -EINVAL;
1330 }
1331
1332 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1333 mac_bridge.key_mode = true;
1334 mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1335 mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1336 mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1337 mac_bridge.key[3] = fid;
1338 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1339 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1340 mac_bridge.valid = add;
1341
1342 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1343 if (err)
1344 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1345
1346 return err;
1347 }
1348
1349 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1350 const unsigned char *addr, u16 vid)
1351 {
1352 return gswip_port_fdb(ds, port, addr, vid, true);
1353 }
1354
1355 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1356 const unsigned char *addr, u16 vid)
1357 {
1358 return gswip_port_fdb(ds, port, addr, vid, false);
1359 }
1360
1361 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1362 dsa_fdb_dump_cb_t *cb, void *data)
1363 {
1364 struct gswip_priv *priv = ds->priv;
1365 struct gswip_pce_table_entry mac_bridge = {0,};
1366 unsigned char addr[6];
1367 int i;
1368 int err;
1369
1370 for (i = 0; i < 2048; i++) {
1371 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1372 mac_bridge.index = i;
1373
1374 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1375 if (err) {
1376 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1377 err);
1378 return err;
1379 }
1380
1381 if (!mac_bridge.valid)
1382 continue;
1383
1384 addr[5] = mac_bridge.key[0] & 0xff;
1385 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1386 addr[3] = mac_bridge.key[1] & 0xff;
1387 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1388 addr[1] = mac_bridge.key[2] & 0xff;
1389 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1390 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1391 if (mac_bridge.val[0] & BIT(port))
1392 cb(addr, 0, true, data);
1393 } else {
1394 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port)
1395 cb(addr, 0, false, data);
1396 }
1397 }
1398 return 0;
1399 }
1400
1401 static void gswip_phylink_validate(struct dsa_switch *ds, int port,
1402 unsigned long *supported,
1403 struct phylink_link_state *state)
1404 {
1405 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1406
1407 switch (port) {
1408 case 0:
1409 case 1:
1410 if (!phy_interface_mode_is_rgmii(state->interface) &&
1411 state->interface != PHY_INTERFACE_MODE_MII &&
1412 state->interface != PHY_INTERFACE_MODE_REVMII &&
1413 state->interface != PHY_INTERFACE_MODE_RMII)
1414 goto unsupported;
1415 break;
1416 case 2:
1417 case 3:
1418 case 4:
1419 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1420 goto unsupported;
1421 break;
1422 case 5:
1423 if (!phy_interface_mode_is_rgmii(state->interface) &&
1424 state->interface != PHY_INTERFACE_MODE_INTERNAL)
1425 goto unsupported;
1426 break;
1427 default:
1428 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1429 dev_err(ds->dev, "Unsupported port: %i\n", port);
1430 return;
1431 }
1432
1433 /* Allow all the expected bits */
1434 phylink_set(mask, Autoneg);
1435 phylink_set_port_modes(mask);
1436 phylink_set(mask, Pause);
1437 phylink_set(mask, Asym_Pause);
1438
1439 /* With the exclusion of MII, Reverse MII and Reduced MII, we
1440 * support Gigabit, including Half duplex
1441 */
1442 if (state->interface != PHY_INTERFACE_MODE_MII &&
1443 state->interface != PHY_INTERFACE_MODE_REVMII &&
1444 state->interface != PHY_INTERFACE_MODE_RMII) {
1445 phylink_set(mask, 1000baseT_Full);
1446 phylink_set(mask, 1000baseT_Half);
1447 }
1448
1449 phylink_set(mask, 10baseT_Half);
1450 phylink_set(mask, 10baseT_Full);
1451 phylink_set(mask, 100baseT_Half);
1452 phylink_set(mask, 100baseT_Full);
1453
1454 bitmap_and(supported, supported, mask,
1455 __ETHTOOL_LINK_MODE_MASK_NBITS);
1456 bitmap_and(state->advertising, state->advertising, mask,
1457 __ETHTOOL_LINK_MODE_MASK_NBITS);
1458 return;
1459
1460 unsupported:
1461 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1462 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1463 phy_modes(state->interface), port);
1464 return;
1465 }
1466
1467 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1468 unsigned int mode,
1469 const struct phylink_link_state *state)
1470 {
1471 struct gswip_priv *priv = ds->priv;
1472 u32 miicfg = 0;
1473
1474 miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1475
1476 switch (state->interface) {
1477 case PHY_INTERFACE_MODE_MII:
1478 case PHY_INTERFACE_MODE_INTERNAL:
1479 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1480 break;
1481 case PHY_INTERFACE_MODE_REVMII:
1482 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1483 break;
1484 case PHY_INTERFACE_MODE_RMII:
1485 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1486 break;
1487 case PHY_INTERFACE_MODE_RGMII:
1488 case PHY_INTERFACE_MODE_RGMII_ID:
1489 case PHY_INTERFACE_MODE_RGMII_RXID:
1490 case PHY_INTERFACE_MODE_RGMII_TXID:
1491 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1492 break;
1493 default:
1494 dev_err(ds->dev,
1495 "Unsupported interface: %d\n", state->interface);
1496 return;
1497 }
1498 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port);
1499
1500 switch (state->interface) {
1501 case PHY_INTERFACE_MODE_RGMII_ID:
1502 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1503 GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1504 break;
1505 case PHY_INTERFACE_MODE_RGMII_RXID:
1506 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1507 break;
1508 case PHY_INTERFACE_MODE_RGMII_TXID:
1509 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1510 break;
1511 default:
1512 break;
1513 }
1514 }
1515
1516 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1517 unsigned int mode,
1518 phy_interface_t interface)
1519 {
1520 struct gswip_priv *priv = ds->priv;
1521
1522 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1523 }
1524
1525 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1526 unsigned int mode,
1527 phy_interface_t interface,
1528 struct phy_device *phydev,
1529 int speed, int duplex,
1530 bool tx_pause, bool rx_pause)
1531 {
1532 struct gswip_priv *priv = ds->priv;
1533
1534 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1535 }
1536
1537 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1538 uint8_t *data)
1539 {
1540 int i;
1541
1542 if (stringset != ETH_SS_STATS)
1543 return;
1544
1545 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1546 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1547 ETH_GSTRING_LEN);
1548 }
1549
1550 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1551 u32 index)
1552 {
1553 u32 result;
1554 int err;
1555
1556 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1557 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1558 GSWIP_BM_RAM_CTRL_OPMOD,
1559 table | GSWIP_BM_RAM_CTRL_BAS,
1560 GSWIP_BM_RAM_CTRL);
1561
1562 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1563 GSWIP_BM_RAM_CTRL_BAS);
1564 if (err) {
1565 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1566 table, index);
1567 return 0;
1568 }
1569
1570 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1571 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1572
1573 return result;
1574 }
1575
1576 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1577 uint64_t *data)
1578 {
1579 struct gswip_priv *priv = ds->priv;
1580 const struct gswip_rmon_cnt_desc *rmon_cnt;
1581 int i;
1582 u64 high;
1583
1584 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1585 rmon_cnt = &gswip_rmon_cnt[i];
1586
1587 data[i] = gswip_bcm_ram_entry_read(priv, port,
1588 rmon_cnt->offset);
1589 if (rmon_cnt->size == 2) {
1590 high = gswip_bcm_ram_entry_read(priv, port,
1591 rmon_cnt->offset + 1);
1592 data[i] |= high << 32;
1593 }
1594 }
1595 }
1596
1597 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1598 {
1599 if (sset != ETH_SS_STATS)
1600 return 0;
1601
1602 return ARRAY_SIZE(gswip_rmon_cnt);
1603 }
1604
1605 static const struct dsa_switch_ops gswip_switch_ops = {
1606 .get_tag_protocol = gswip_get_tag_protocol,
1607 .setup = gswip_setup,
1608 .port_enable = gswip_port_enable,
1609 .port_disable = gswip_port_disable,
1610 .port_bridge_join = gswip_port_bridge_join,
1611 .port_bridge_leave = gswip_port_bridge_leave,
1612 .port_fast_age = gswip_port_fast_age,
1613 .port_vlan_filtering = gswip_port_vlan_filtering,
1614 .port_vlan_prepare = gswip_port_vlan_prepare,
1615 .port_vlan_add = gswip_port_vlan_add,
1616 .port_vlan_del = gswip_port_vlan_del,
1617 .port_stp_state_set = gswip_port_stp_state_set,
1618 .port_fdb_add = gswip_port_fdb_add,
1619 .port_fdb_del = gswip_port_fdb_del,
1620 .port_fdb_dump = gswip_port_fdb_dump,
1621 .phylink_validate = gswip_phylink_validate,
1622 .phylink_mac_config = gswip_phylink_mac_config,
1623 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1624 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1625 .get_strings = gswip_get_strings,
1626 .get_ethtool_stats = gswip_get_ethtool_stats,
1627 .get_sset_count = gswip_get_sset_count,
1628 };
1629
1630 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1631 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1632 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1633 };
1634
1635 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1636 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1637 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1638 };
1639
1640 static const struct xway_gphy_match_data xrx300_gphy_data = {
1641 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1642 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1643 };
1644
1645 static const struct of_device_id xway_gphy_match[] = {
1646 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1647 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1648 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1649 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1650 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1651 {},
1652 };
1653
1654 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1655 {
1656 struct device *dev = priv->dev;
1657 const struct firmware *fw;
1658 void *fw_addr;
1659 dma_addr_t dma_addr;
1660 dma_addr_t dev_addr;
1661 size_t size;
1662 int ret;
1663
1664 ret = clk_prepare_enable(gphy_fw->clk_gate);
1665 if (ret)
1666 return ret;
1667
1668 reset_control_assert(gphy_fw->reset);
1669
1670 ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1671 if (ret) {
1672 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1673 gphy_fw->fw_name, ret);
1674 return ret;
1675 }
1676
1677 /* GPHY cores need the firmware code in a persistent and contiguous
1678 * memory area with a 16 kB boundary aligned start address.
1679 */
1680 size = fw->size + XRX200_GPHY_FW_ALIGN;
1681
1682 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1683 if (fw_addr) {
1684 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1685 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1686 memcpy(fw_addr, fw->data, fw->size);
1687 } else {
1688 dev_err(dev, "failed to alloc firmware memory\n");
1689 release_firmware(fw);
1690 return -ENOMEM;
1691 }
1692
1693 release_firmware(fw);
1694
1695 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1696 if (ret)
1697 return ret;
1698
1699 reset_control_deassert(gphy_fw->reset);
1700
1701 return ret;
1702 }
1703
1704 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1705 struct gswip_gphy_fw *gphy_fw,
1706 struct device_node *gphy_fw_np, int i)
1707 {
1708 struct device *dev = priv->dev;
1709 u32 gphy_mode;
1710 int ret;
1711 char gphyname[10];
1712
1713 snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1714
1715 gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1716 if (IS_ERR(gphy_fw->clk_gate)) {
1717 dev_err(dev, "Failed to lookup gate clock\n");
1718 return PTR_ERR(gphy_fw->clk_gate);
1719 }
1720
1721 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1722 if (ret)
1723 return ret;
1724
1725 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1726 /* Default to GE mode */
1727 if (ret)
1728 gphy_mode = GPHY_MODE_GE;
1729
1730 switch (gphy_mode) {
1731 case GPHY_MODE_FE:
1732 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1733 break;
1734 case GPHY_MODE_GE:
1735 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1736 break;
1737 default:
1738 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1739 return -EINVAL;
1740 }
1741
1742 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1743 if (IS_ERR(gphy_fw->reset)) {
1744 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
1745 dev_err(dev, "Failed to lookup gphy reset\n");
1746 return PTR_ERR(gphy_fw->reset);
1747 }
1748
1749 return gswip_gphy_fw_load(priv, gphy_fw);
1750 }
1751
1752 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1753 struct gswip_gphy_fw *gphy_fw)
1754 {
1755 int ret;
1756
1757 /* check if the device was fully probed */
1758 if (!gphy_fw->fw_name)
1759 return;
1760
1761 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
1762 if (ret)
1763 dev_err(priv->dev, "can not reset GPHY FW pointer");
1764
1765 clk_disable_unprepare(gphy_fw->clk_gate);
1766
1767 reset_control_put(gphy_fw->reset);
1768 }
1769
1770 static int gswip_gphy_fw_list(struct gswip_priv *priv,
1771 struct device_node *gphy_fw_list_np, u32 version)
1772 {
1773 struct device *dev = priv->dev;
1774 struct device_node *gphy_fw_np;
1775 const struct of_device_id *match;
1776 int err;
1777 int i = 0;
1778
1779 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
1780 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
1781 * needs a different GPHY firmware.
1782 */
1783 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
1784 switch (version) {
1785 case GSWIP_VERSION_2_0:
1786 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
1787 break;
1788 case GSWIP_VERSION_2_1:
1789 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
1790 break;
1791 default:
1792 dev_err(dev, "unknown GSWIP version: 0x%x", version);
1793 return -ENOENT;
1794 }
1795 }
1796
1797 match = of_match_node(xway_gphy_match, gphy_fw_list_np);
1798 if (match && match->data)
1799 priv->gphy_fw_name_cfg = match->data;
1800
1801 if (!priv->gphy_fw_name_cfg) {
1802 dev_err(dev, "GPHY compatible type not supported");
1803 return -ENOENT;
1804 }
1805
1806 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
1807 if (!priv->num_gphy_fw)
1808 return -ENOENT;
1809
1810 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
1811 "lantiq,rcu");
1812 if (IS_ERR(priv->rcu_regmap))
1813 return PTR_ERR(priv->rcu_regmap);
1814
1815 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
1816 sizeof(*priv->gphy_fw),
1817 GFP_KERNEL | __GFP_ZERO);
1818 if (!priv->gphy_fw)
1819 return -ENOMEM;
1820
1821 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
1822 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
1823 gphy_fw_np, i);
1824 if (err)
1825 goto remove_gphy;
1826 i++;
1827 }
1828
1829 /* The standalone PHY11G requires 300ms to be fully
1830 * initialized and ready for any MDIO communication after being
1831 * taken out of reset. For the SoC-internal GPHY variant there
1832 * is no (known) documentation for the minimum time after a
1833 * reset. Use the same value as for the standalone variant as
1834 * some users have reported internal PHYs not being detected
1835 * without any delay.
1836 */
1837 msleep(300);
1838
1839 return 0;
1840
1841 remove_gphy:
1842 for (i = 0; i < priv->num_gphy_fw; i++)
1843 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1844 return err;
1845 }
1846
1847 static int gswip_probe(struct platform_device *pdev)
1848 {
1849 struct gswip_priv *priv;
1850 struct device_node *mdio_np, *gphy_fw_np;
1851 struct device *dev = &pdev->dev;
1852 int err;
1853 int i;
1854 u32 version;
1855
1856 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1857 if (!priv)
1858 return -ENOMEM;
1859
1860 priv->gswip = devm_platform_ioremap_resource(pdev, 0);
1861 if (IS_ERR(priv->gswip))
1862 return PTR_ERR(priv->gswip);
1863
1864 priv->mdio = devm_platform_ioremap_resource(pdev, 1);
1865 if (IS_ERR(priv->mdio))
1866 return PTR_ERR(priv->mdio);
1867
1868 priv->mii = devm_platform_ioremap_resource(pdev, 2);
1869 if (IS_ERR(priv->mii))
1870 return PTR_ERR(priv->mii);
1871
1872 priv->hw_info = of_device_get_match_data(dev);
1873 if (!priv->hw_info)
1874 return -EINVAL;
1875
1876 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
1877 if (!priv->ds)
1878 return -ENOMEM;
1879
1880 priv->ds->dev = dev;
1881 priv->ds->num_ports = priv->hw_info->max_ports;
1882 priv->ds->priv = priv;
1883 priv->ds->ops = &gswip_switch_ops;
1884 priv->dev = dev;
1885 version = gswip_switch_r(priv, GSWIP_VERSION);
1886
1887 /* bring up the mdio bus */
1888 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
1889 if (gphy_fw_np) {
1890 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
1891 of_node_put(gphy_fw_np);
1892 if (err) {
1893 dev_err(dev, "gphy fw probe failed\n");
1894 return err;
1895 }
1896 }
1897
1898 /* bring up the mdio bus */
1899 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
1900 if (mdio_np) {
1901 err = gswip_mdio(priv, mdio_np);
1902 if (err) {
1903 dev_err(dev, "mdio probe failed\n");
1904 goto put_mdio_node;
1905 }
1906 }
1907
1908 err = dsa_register_switch(priv->ds);
1909 if (err) {
1910 dev_err(dev, "dsa switch register failed: %i\n", err);
1911 goto mdio_bus;
1912 }
1913 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
1914 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
1915 priv->hw_info->cpu_port);
1916 err = -EINVAL;
1917 goto disable_switch;
1918 }
1919
1920 platform_set_drvdata(pdev, priv);
1921
1922 dev_info(dev, "probed GSWIP version %lx mod %lx\n",
1923 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
1924 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
1925 return 0;
1926
1927 disable_switch:
1928 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
1929 dsa_unregister_switch(priv->ds);
1930 mdio_bus:
1931 if (mdio_np)
1932 mdiobus_unregister(priv->ds->slave_mii_bus);
1933 put_mdio_node:
1934 of_node_put(mdio_np);
1935 for (i = 0; i < priv->num_gphy_fw; i++)
1936 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1937 return err;
1938 }
1939
1940 static int gswip_remove(struct platform_device *pdev)
1941 {
1942 struct gswip_priv *priv = platform_get_drvdata(pdev);
1943 int i;
1944
1945 /* disable the switch */
1946 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
1947
1948 dsa_unregister_switch(priv->ds);
1949
1950 if (priv->ds->slave_mii_bus) {
1951 mdiobus_unregister(priv->ds->slave_mii_bus);
1952 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
1953 }
1954
1955 for (i = 0; i < priv->num_gphy_fw; i++)
1956 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1957
1958 return 0;
1959 }
1960
1961 static const struct gswip_hw_info gswip_xrx200 = {
1962 .max_ports = 7,
1963 .cpu_port = 6,
1964 };
1965
1966 static const struct of_device_id gswip_of_match[] = {
1967 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
1968 {},
1969 };
1970 MODULE_DEVICE_TABLE(of, gswip_of_match);
1971
1972 static struct platform_driver gswip_driver = {
1973 .probe = gswip_probe,
1974 .remove = gswip_remove,
1975 .driver = {
1976 .name = "gswip",
1977 .of_match_table = gswip_of_match,
1978 },
1979 };
1980
1981 module_platform_driver(gswip_driver);
1982
1983 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
1984 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
1985 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
1986 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
1987 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
1988 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
1989 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1990 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
1991 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support