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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / dsa / mt7530.c
bloba67cac15a724aadc0c2e1d53802930a0a4306ad5
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 */
6 #include <linux/etherdevice.h>
7 #include <linux/if_bridge.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/of_mdio.h>
14 #include <linux/of_net.h>
15 #include <linux/of_platform.h>
16 #include <linux/phylink.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/gpio/consumer.h>
21 #include <net/dsa.h>
22
23 #include "mt7530.h"
24
25 /* String, offset, and register size in bytes if different from 4 bytes */
26 static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x6c, "RxMulticast"),
49 MIB_DESC(1, 0x70, "RxBroadcast"),
50 MIB_DESC(1, 0x74, "RxAlignErr"),
51 MIB_DESC(1, 0x78, "RxCrcErr"),
52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
53 MIB_DESC(1, 0x80, "RxFragErr"),
54 MIB_DESC(1, 0x84, "RxOverSzErr"),
55 MIB_DESC(1, 0x88, "RxJabberErr"),
56 MIB_DESC(1, 0x8c, "RxPause"),
57 MIB_DESC(1, 0x90, "RxPktSz64"),
58 MIB_DESC(1, 0x94, "RxPktSz65To127"),
59 MIB_DESC(1, 0x98, "RxPktSz128To255"),
60 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
63 MIB_DESC(2, 0xa8, "RxBytes"),
64 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
65 MIB_DESC(1, 0xb4, "RxIngressDrop"),
66 MIB_DESC(1, 0xb8, "RxArlDrop"),
67 };
68
69 static int
70 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
71 {
72 struct mii_bus *bus = priv->bus;
73 int value, ret;
74
75 /* Write the desired MMD Devad */
76 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
77 if (ret < 0)
78 goto err;
79
80 /* Write the desired MMD register address */
81 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
82 if (ret < 0)
83 goto err;
84
85 /* Select the Function : DATA with no post increment */
86 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
87 if (ret < 0)
88 goto err;
89
90 /* Read the content of the MMD's selected register */
91 value = bus->read(bus, 0, MII_MMD_DATA);
92
93 return value;
94 err:
95 dev_err(&bus->dev, "failed to read mmd register\n");
96
97 return ret;
98 }
99
100 static int
101 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
102 int devad, u32 data)
103 {
104 struct mii_bus *bus = priv->bus;
105 int ret;
106
107 /* Write the desired MMD Devad */
108 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
109 if (ret < 0)
110 goto err;
111
112 /* Write the desired MMD register address */
113 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
114 if (ret < 0)
115 goto err;
116
117 /* Select the Function : DATA with no post increment */
118 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
119 if (ret < 0)
120 goto err;
121
122 /* Write the data into MMD's selected register */
123 ret = bus->write(bus, 0, MII_MMD_DATA, data);
124 err:
125 if (ret < 0)
126 dev_err(&bus->dev,
127 "failed to write mmd register\n");
128 return ret;
129 }
130
131 static void
132 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
133 {
134 struct mii_bus *bus = priv->bus;
135
136 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
137
138 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
139
140 mutex_unlock(&bus->mdio_lock);
141 }
142
143 static void
144 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
145 {
146 struct mii_bus *bus = priv->bus;
147 u32 val;
148
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
152 val &= ~mask;
153 val |= set;
154 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
155
156 mutex_unlock(&bus->mdio_lock);
157 }
158
159 static void
160 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
161 {
162 core_rmw(priv, reg, 0, val);
163 }
164
165 static void
166 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
167 {
168 core_rmw(priv, reg, val, 0);
169 }
170
171 static int
172 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
173 {
174 struct mii_bus *bus = priv->bus;
175 u16 page, r, lo, hi;
176 int ret;
177
178 page = (reg >> 6) & 0x3ff;
179 r = (reg >> 2) & 0xf;
180 lo = val & 0xffff;
181 hi = val >> 16;
182
183 /* MT7530 uses 31 as the pseudo port */
184 ret = bus->write(bus, 0x1f, 0x1f, page);
185 if (ret < 0)
186 goto err;
187
188 ret = bus->write(bus, 0x1f, r, lo);
189 if (ret < 0)
190 goto err;
191
192 ret = bus->write(bus, 0x1f, 0x10, hi);
193 err:
194 if (ret < 0)
195 dev_err(&bus->dev,
196 "failed to write mt7530 register\n");
197 return ret;
198 }
199
200 static u32
201 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
202 {
203 struct mii_bus *bus = priv->bus;
204 u16 page, r, lo, hi;
205 int ret;
206
207 page = (reg >> 6) & 0x3ff;
208 r = (reg >> 2) & 0xf;
209
210 /* MT7530 uses 31 as the pseudo port */
211 ret = bus->write(bus, 0x1f, 0x1f, page);
212 if (ret < 0) {
213 dev_err(&bus->dev,
214 "failed to read mt7530 register\n");
215 return ret;
216 }
217
218 lo = bus->read(bus, 0x1f, r);
219 hi = bus->read(bus, 0x1f, 0x10);
220
221 return (hi << 16) | (lo & 0xffff);
222 }
223
224 static void
225 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
226 {
227 struct mii_bus *bus = priv->bus;
228
229 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
230
231 mt7530_mii_write(priv, reg, val);
232
233 mutex_unlock(&bus->mdio_lock);
234 }
235
236 static u32
237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p)
238 {
239 return mt7530_mii_read(p->priv, p->reg);
240 }
241
242 static u32
243 _mt7530_read(struct mt7530_dummy_poll *p)
244 {
245 struct mii_bus *bus = p->priv->bus;
246 u32 val;
247
248 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
249
250 val = mt7530_mii_read(p->priv, p->reg);
251
252 mutex_unlock(&bus->mdio_lock);
253
254 return val;
255 }
256
257 static u32
258 mt7530_read(struct mt7530_priv *priv, u32 reg)
259 {
260 struct mt7530_dummy_poll p;
261
262 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
263 return _mt7530_read(&p);
264 }
265
266 static void
267 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
268 u32 mask, u32 set)
269 {
270 struct mii_bus *bus = priv->bus;
271 u32 val;
272
273 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
274
275 val = mt7530_mii_read(priv, reg);
276 val &= ~mask;
277 val |= set;
278 mt7530_mii_write(priv, reg, val);
279
280 mutex_unlock(&bus->mdio_lock);
281 }
282
283 static void
284 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
285 {
286 mt7530_rmw(priv, reg, 0, val);
287 }
288
289 static void
290 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
291 {
292 mt7530_rmw(priv, reg, val, 0);
293 }
294
295 static int
296 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
297 {
298 u32 val;
299 int ret;
300 struct mt7530_dummy_poll p;
301
302 /* Set the command operating upon the MAC address entries */
303 val = ATC_BUSY | ATC_MAT(0) | cmd;
304 mt7530_write(priv, MT7530_ATC, val);
305
306 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
307 ret = readx_poll_timeout(_mt7530_read, &p, val,
308 !(val & ATC_BUSY), 20, 20000);
309 if (ret < 0) {
310 dev_err(priv->dev, "reset timeout\n");
311 return ret;
312 }
313
314 /* Additional sanity for read command if the specified
315 * entry is invalid
316 */
317 val = mt7530_read(priv, MT7530_ATC);
318 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
319 return -EINVAL;
320
321 if (rsp)
322 *rsp = val;
323
324 return 0;
325 }
326
327 static void
328 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
329 {
330 u32 reg[3];
331 int i;
332
333 /* Read from ARL table into an array */
334 for (i = 0; i < 3; i++) {
335 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
336
337 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
338 __func__, __LINE__, i, reg[i]);
339 }
340
341 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
342 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
343 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
344 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
345 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
346 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
347 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
348 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
349 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
350 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
351 }
352
353 static void
354 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
355 u8 port_mask, const u8 *mac,
356 u8 aging, u8 type)
357 {
358 u32 reg[3] = { 0 };
359 int i;
360
361 reg[1] |= vid & CVID_MASK;
362 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
363 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
364 /* STATIC_ENT indicate that entry is static wouldn't
365 * be aged out and STATIC_EMP specified as erasing an
366 * entry
367 */
368 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
369 reg[1] |= mac[5] << MAC_BYTE_5;
370 reg[1] |= mac[4] << MAC_BYTE_4;
371 reg[0] |= mac[3] << MAC_BYTE_3;
372 reg[0] |= mac[2] << MAC_BYTE_2;
373 reg[0] |= mac[1] << MAC_BYTE_1;
374 reg[0] |= mac[0] << MAC_BYTE_0;
375
376 /* Write array into the ARL table */
377 for (i = 0; i < 3; i++)
378 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
379 }
380
381 /* Setup TX circuit including relevant PAD and driving */
382 static int
383 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
384 {
385 struct mt7530_priv *priv = ds->priv;
386 u32 ncpo1, ssc_delta, trgint, i, xtal;
387
388 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
389
390 if (xtal == HWTRAP_XTAL_20MHZ) {
391 dev_err(priv->dev,
392 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
393 __func__);
394 return -EINVAL;
395 }
396
397 switch (interface) {
398 case PHY_INTERFACE_MODE_RGMII:
399 trgint = 0;
400 /* PLL frequency: 125MHz */
401 ncpo1 = 0x0c80;
402 break;
403 case PHY_INTERFACE_MODE_TRGMII:
404 trgint = 1;
405 if (priv->id == ID_MT7621) {
406 /* PLL frequency: 150MHz: 1.2GBit */
407 if (xtal == HWTRAP_XTAL_40MHZ)
408 ncpo1 = 0x0780;
409 if (xtal == HWTRAP_XTAL_25MHZ)
410 ncpo1 = 0x0a00;
411 } else { /* PLL frequency: 250MHz: 2.0Gbit */
412 if (xtal == HWTRAP_XTAL_40MHZ)
413 ncpo1 = 0x0c80;
414 if (xtal == HWTRAP_XTAL_25MHZ)
415 ncpo1 = 0x1400;
416 }
417 break;
418 default:
419 dev_err(priv->dev, "xMII interface %d not supported\n",
420 interface);
421 return -EINVAL;
422 }
423
424 if (xtal == HWTRAP_XTAL_25MHZ)
425 ssc_delta = 0x57;
426 else
427 ssc_delta = 0x87;
428
429 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
430 P6_INTF_MODE(trgint));
431
432 /* Lower Tx Driving for TRGMII path */
433 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
434 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
435 TD_DM_DRVP(8) | TD_DM_DRVN(8));
436
437 /* Setup core clock for MT7530 */
438 if (!trgint) {
439 /* Disable MT7530 core clock */
440 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
441
442 /* Disable PLL, since phy_device has not yet been created
443 * provided for phy_[read,write]_mmd_indirect is called, we
444 * provide our own core_write_mmd_indirect to complete this
445 * function.
446 */
447 core_write_mmd_indirect(priv,
448 CORE_GSWPLL_GRP1,
449 MDIO_MMD_VEND2,
450 0);
451
452 /* Set core clock into 500Mhz */
453 core_write(priv, CORE_GSWPLL_GRP2,
454 RG_GSWPLL_POSDIV_500M(1) |
455 RG_GSWPLL_FBKDIV_500M(25));
456
457 /* Enable PLL */
458 core_write(priv, CORE_GSWPLL_GRP1,
459 RG_GSWPLL_EN_PRE |
460 RG_GSWPLL_POSDIV_200M(2) |
461 RG_GSWPLL_FBKDIV_200M(32));
462
463 /* Enable MT7530 core clock */
464 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
465 }
466
467 /* Setup the MT7530 TRGMII Tx Clock */
468 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
473 core_write(priv, CORE_PLL_GROUP4,
474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
475 RG_SYSPLL_BIAS_LPF_EN);
476 core_write(priv, CORE_PLL_GROUP2,
477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
478 RG_SYSPLL_POSDIV(1));
479 core_write(priv, CORE_PLL_GROUP7,
480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
482 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
483 REG_GSWCK_EN | REG_TRGMIICK_EN);
484
485 if (!trgint)
486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
487 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
488 RD_TAP_MASK, RD_TAP(16));
489 return 0;
490 }
491
492 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
493 {
494 u32 val;
495
496 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
497
498 return (val & PAD_DUAL_SGMII_EN) != 0;
499 }
500
501 static int
502 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
503 {
504 struct mt7530_priv *priv = ds->priv;
505 u32 top_sig;
506 u32 hwstrap;
507 u32 xtal;
508 u32 val;
509
510 if (mt7531_dual_sgmii_supported(priv))
511 return 0;
512
513 val = mt7530_read(priv, MT7531_CREV);
514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
515 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
516 if ((val & CHIP_REV_M) > 0)
517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
518 HWTRAP_XTAL_FSEL_25MHZ;
519 else
520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
521
522 /* Step 1 : Disable MT7531 COREPLL */
523 val = mt7530_read(priv, MT7531_PLLGP_EN);
524 val &= ~EN_COREPLL;
525 mt7530_write(priv, MT7531_PLLGP_EN, val);
526
527 /* Step 2: switch to XTAL output */
528 val = mt7530_read(priv, MT7531_PLLGP_EN);
529 val |= SW_CLKSW;
530 mt7530_write(priv, MT7531_PLLGP_EN, val);
531
532 val = mt7530_read(priv, MT7531_PLLGP_CR0);
533 val &= ~RG_COREPLL_EN;
534 mt7530_write(priv, MT7531_PLLGP_CR0, val);
535
536 /* Step 3: disable PLLGP and enable program PLLGP */
537 val = mt7530_read(priv, MT7531_PLLGP_EN);
538 val |= SW_PLLGP;
539 mt7530_write(priv, MT7531_PLLGP_EN, val);
540
541 /* Step 4: program COREPLL output frequency to 500MHz */
542 val = mt7530_read(priv, MT7531_PLLGP_CR0);
543 val &= ~RG_COREPLL_POSDIV_M;
544 val |= 2 << RG_COREPLL_POSDIV_S;
545 mt7530_write(priv, MT7531_PLLGP_CR0, val);
546 usleep_range(25, 35);
547
548 switch (xtal) {
549 case HWTRAP_XTAL_FSEL_25MHZ:
550 val = mt7530_read(priv, MT7531_PLLGP_CR0);
551 val &= ~RG_COREPLL_SDM_PCW_M;
552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
553 mt7530_write(priv, MT7531_PLLGP_CR0, val);
554 break;
555 case HWTRAP_XTAL_FSEL_40MHZ:
556 val = mt7530_read(priv, MT7531_PLLGP_CR0);
557 val &= ~RG_COREPLL_SDM_PCW_M;
558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
559 mt7530_write(priv, MT7531_PLLGP_CR0, val);
560 break;
561 }
562
563 /* Set feedback divide ratio update signal to high */
564 val = mt7530_read(priv, MT7531_PLLGP_CR0);
565 val |= RG_COREPLL_SDM_PCW_CHG;
566 mt7530_write(priv, MT7531_PLLGP_CR0, val);
567 /* Wait for at least 16 XTAL clocks */
568 usleep_range(10, 20);
569
570 /* Step 5: set feedback divide ratio update signal to low */
571 val = mt7530_read(priv, MT7531_PLLGP_CR0);
572 val &= ~RG_COREPLL_SDM_PCW_CHG;
573 mt7530_write(priv, MT7531_PLLGP_CR0, val);
574
575 /* Enable 325M clock for SGMII */
576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
577
578 /* Enable 250SSC clock for RGMII */
579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
580
581 /* Step 6: Enable MT7531 PLL */
582 val = mt7530_read(priv, MT7531_PLLGP_CR0);
583 val |= RG_COREPLL_EN;
584 mt7530_write(priv, MT7531_PLLGP_CR0, val);
585
586 val = mt7530_read(priv, MT7531_PLLGP_EN);
587 val |= EN_COREPLL;
588 mt7530_write(priv, MT7531_PLLGP_EN, val);
589 usleep_range(25, 35);
590
591 return 0;
592 }
593
594 static void
595 mt7530_mib_reset(struct dsa_switch *ds)
596 {
597 struct mt7530_priv *priv = ds->priv;
598
599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
601 }
602
603 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
604 {
605 struct mt7530_priv *priv = ds->priv;
606
607 return mdiobus_read_nested(priv->bus, port, regnum);
608 }
609
610 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
611 u16 val)
612 {
613 struct mt7530_priv *priv = ds->priv;
614
615 return mdiobus_write_nested(priv->bus, port, regnum, val);
616 }
617
618 static int
619 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
620 int regnum)
621 {
622 struct mii_bus *bus = priv->bus;
623 struct mt7530_dummy_poll p;
624 u32 reg, val;
625 int ret;
626
627 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
628
629 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
630
631 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
632 !(val & MT7531_PHY_ACS_ST), 20, 100000);
633 if (ret < 0) {
634 dev_err(priv->dev, "poll timeout\n");
635 goto out;
636 }
637
638 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
639 MT7531_MDIO_DEV_ADDR(devad) | regnum;
640 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
641
642 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
643 !(val & MT7531_PHY_ACS_ST), 20, 100000);
644 if (ret < 0) {
645 dev_err(priv->dev, "poll timeout\n");
646 goto out;
647 }
648
649 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
650 MT7531_MDIO_DEV_ADDR(devad);
651 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
652
653 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
654 !(val & MT7531_PHY_ACS_ST), 20, 100000);
655 if (ret < 0) {
656 dev_err(priv->dev, "poll timeout\n");
657 goto out;
658 }
659
660 ret = val & MT7531_MDIO_RW_DATA_MASK;
661 out:
662 mutex_unlock(&bus->mdio_lock);
663
664 return ret;
665 }
666
667 static int
668 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
669 int regnum, u32 data)
670 {
671 struct mii_bus *bus = priv->bus;
672 struct mt7530_dummy_poll p;
673 u32 val, reg;
674 int ret;
675
676 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
677
678 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
679
680 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
681 !(val & MT7531_PHY_ACS_ST), 20, 100000);
682 if (ret < 0) {
683 dev_err(priv->dev, "poll timeout\n");
684 goto out;
685 }
686
687 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
688 MT7531_MDIO_DEV_ADDR(devad) | regnum;
689 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
690
691 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
692 !(val & MT7531_PHY_ACS_ST), 20, 100000);
693 if (ret < 0) {
694 dev_err(priv->dev, "poll timeout\n");
695 goto out;
696 }
697
698 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
699 MT7531_MDIO_DEV_ADDR(devad) | data;
700 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
701
702 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
703 !(val & MT7531_PHY_ACS_ST), 20, 100000);
704 if (ret < 0) {
705 dev_err(priv->dev, "poll timeout\n");
706 goto out;
707 }
708
709 out:
710 mutex_unlock(&bus->mdio_lock);
711
712 return ret;
713 }
714
715 static int
716 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
717 {
718 struct mii_bus *bus = priv->bus;
719 struct mt7530_dummy_poll p;
720 int ret;
721 u32 val;
722
723 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
724
725 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
726
727 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
728 !(val & MT7531_PHY_ACS_ST), 20, 100000);
729 if (ret < 0) {
730 dev_err(priv->dev, "poll timeout\n");
731 goto out;
732 }
733
734 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
735 MT7531_MDIO_REG_ADDR(regnum);
736
737 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
738
739 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
740 !(val & MT7531_PHY_ACS_ST), 20, 100000);
741 if (ret < 0) {
742 dev_err(priv->dev, "poll timeout\n");
743 goto out;
744 }
745
746 ret = val & MT7531_MDIO_RW_DATA_MASK;
747 out:
748 mutex_unlock(&bus->mdio_lock);
749
750 return ret;
751 }
752
753 static int
754 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
755 u16 data)
756 {
757 struct mii_bus *bus = priv->bus;
758 struct mt7530_dummy_poll p;
759 int ret;
760 u32 reg;
761
762 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
763
764 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
765
766 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
767 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
768 if (ret < 0) {
769 dev_err(priv->dev, "poll timeout\n");
770 goto out;
771 }
772
773 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
774 MT7531_MDIO_REG_ADDR(regnum) | data;
775
776 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
777
778 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
779 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
780 if (ret < 0) {
781 dev_err(priv->dev, "poll timeout\n");
782 goto out;
783 }
784
785 out:
786 mutex_unlock(&bus->mdio_lock);
787
788 return ret;
789 }
790
791 static int
792 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
793 {
794 struct mt7530_priv *priv = ds->priv;
795 int devad;
796 int ret;
797
798 if (regnum & MII_ADDR_C45) {
799 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
800 ret = mt7531_ind_c45_phy_read(priv, port, devad,
801 regnum & MII_REGADDR_C45_MASK);
802 } else {
803 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
804 }
805
806 return ret;
807 }
808
809 static int
810 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
811 u16 data)
812 {
813 struct mt7530_priv *priv = ds->priv;
814 int devad;
815 int ret;
816
817 if (regnum & MII_ADDR_C45) {
818 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
819 ret = mt7531_ind_c45_phy_write(priv, port, devad,
820 regnum & MII_REGADDR_C45_MASK,
821 data);
822 } else {
823 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
824 }
825
826 return ret;
827 }
828
829 static void
830 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
831 uint8_t *data)
832 {
833 int i;
834
835 if (stringset != ETH_SS_STATS)
836 return;
837
838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
839 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
840 ETH_GSTRING_LEN);
841 }
842
843 static void
844 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
845 uint64_t *data)
846 {
847 struct mt7530_priv *priv = ds->priv;
848 const struct mt7530_mib_desc *mib;
849 u32 reg, i;
850 u64 hi;
851
852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
853 mib = &mt7530_mib[i];
854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
855
856 data[i] = mt7530_read(priv, reg);
857 if (mib->size == 2) {
858 hi = mt7530_read(priv, reg + 4);
859 data[i] |= hi << 32;
860 }
861 }
862 }
863
864 static int
865 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
866 {
867 if (sset != ETH_SS_STATS)
868 return 0;
869
870 return ARRAY_SIZE(mt7530_mib);
871 }
872
873 static int
874 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
875 {
876 struct mt7530_priv *priv = ds->priv;
877 unsigned int secs = msecs / 1000;
878 unsigned int tmp_age_count;
879 unsigned int error = -1;
880 unsigned int age_count;
881 unsigned int age_unit;
882
883 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
884 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
885 return -ERANGE;
886
887 /* iterate through all possible age_count to find the closest pair */
888 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
890
891 if (tmp_age_unit <= AGE_UNIT_MAX) {
892 unsigned int tmp_error = secs -
893 (tmp_age_count + 1) * (tmp_age_unit + 1);
894
895 /* found a closer pair */
896 if (error > tmp_error) {
897 error = tmp_error;
898 age_count = tmp_age_count;
899 age_unit = tmp_age_unit;
900 }
901
902 /* found the exact match, so break the loop */
903 if (!error)
904 break;
905 }
906 }
907
908 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
909
910 return 0;
911 }
912
913 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
914 {
915 struct mt7530_priv *priv = ds->priv;
916 u8 tx_delay = 0;
917 int val;
918
919 mutex_lock(&priv->reg_mutex);
920
921 val = mt7530_read(priv, MT7530_MHWTRAP);
922
923 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
924 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
925
926 switch (priv->p5_intf_sel) {
927 case P5_INTF_SEL_PHY_P0:
928 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
929 val |= MHWTRAP_PHY0_SEL;
930 fallthrough;
931 case P5_INTF_SEL_PHY_P4:
932 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
933 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
934
935 /* Setup the MAC by default for the cpu port */
936 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
937 break;
938 case P5_INTF_SEL_GMAC5:
939 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
940 val &= ~MHWTRAP_P5_DIS;
941 break;
942 case P5_DISABLED:
943 interface = PHY_INTERFACE_MODE_NA;
944 break;
945 default:
946 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
947 priv->p5_intf_sel);
948 goto unlock_exit;
949 }
950
951 /* Setup RGMII settings */
952 if (phy_interface_mode_is_rgmii(interface)) {
953 val |= MHWTRAP_P5_RGMII_MODE;
954
955 /* P5 RGMII RX Clock Control: delay setting for 1000M */
956 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
957
958 /* Don't set delay in DSA mode */
959 if (!dsa_is_dsa_port(priv->ds, 5) &&
960 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
961 interface == PHY_INTERFACE_MODE_RGMII_ID))
962 tx_delay = 4; /* n * 0.5 ns */
963
964 /* P5 RGMII TX Clock Control: delay x */
965 mt7530_write(priv, MT7530_P5RGMIITXCR,
966 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
967
968 /* reduce P5 RGMII Tx driving, 8mA */
969 mt7530_write(priv, MT7530_IO_DRV_CR,
970 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
971 }
972
973 mt7530_write(priv, MT7530_MHWTRAP, val);
974
975 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
976 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
977
978 priv->p5_interface = interface;
979
980 unlock_exit:
981 mutex_unlock(&priv->reg_mutex);
982 }
983
984 static int
985 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
986 {
987 struct mt7530_priv *priv = ds->priv;
988 int ret;
989
990 /* Setup max capability of CPU port at first */
991 if (priv->info->cpu_port_config) {
992 ret = priv->info->cpu_port_config(ds, port);
993 if (ret)
994 return ret;
995 }
996
997 /* Enable Mediatek header mode on the cpu port */
998 mt7530_write(priv, MT7530_PVC_P(port),
999 PORT_SPEC_TAG);
1000
1001 /* Unknown multicast frame forwarding to the cpu port */
1002 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
1003
1004 /* Set CPU port number */
1005 if (priv->id == ID_MT7621)
1006 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1007
1008 /* CPU port gets connected to all user ports of
1009 * the switch.
1010 */
1011 mt7530_write(priv, MT7530_PCR_P(port),
1012 PCR_MATRIX(dsa_user_ports(priv->ds)));
1013
1014 return 0;
1015 }
1016
1017 static int
1018 mt7530_port_enable(struct dsa_switch *ds, int port,
1019 struct phy_device *phy)
1020 {
1021 struct mt7530_priv *priv = ds->priv;
1022
1023 if (!dsa_is_user_port(ds, port))
1024 return 0;
1025
1026 mutex_lock(&priv->reg_mutex);
1027
1028 /* Allow the user port gets connected to the cpu port and also
1029 * restore the port matrix if the port is the member of a certain
1030 * bridge.
1031 */
1032 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1033 priv->ports[port].enable = true;
1034 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1035 priv->ports[port].pm);
1036 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1037
1038 mutex_unlock(&priv->reg_mutex);
1039
1040 return 0;
1041 }
1042
1043 static void
1044 mt7530_port_disable(struct dsa_switch *ds, int port)
1045 {
1046 struct mt7530_priv *priv = ds->priv;
1047
1048 if (!dsa_is_user_port(ds, port))
1049 return;
1050
1051 mutex_lock(&priv->reg_mutex);
1052
1053 /* Clear up all port matrix which could be restored in the next
1054 * enablement for the port.
1055 */
1056 priv->ports[port].enable = false;
1057 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1058 PCR_MATRIX_CLR);
1059 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1060
1061 mutex_unlock(&priv->reg_mutex);
1062 }
1063
1064 static int
1065 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1066 {
1067 struct mt7530_priv *priv = ds->priv;
1068 struct mii_bus *bus = priv->bus;
1069 int length;
1070 u32 val;
1071
1072 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1073 * largest MTU of the slave ports. Because the switch only has a global
1074 * RX length register, only allowing CPU port here is enough.
1075 */
1076 if (!dsa_is_cpu_port(ds, port))
1077 return 0;
1078
1079 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1080
1081 val = mt7530_mii_read(priv, MT7530_GMACCR);
1082 val &= ~MAX_RX_PKT_LEN_MASK;
1083
1084 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1085 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1086 if (length <= 1522) {
1087 val |= MAX_RX_PKT_LEN_1522;
1088 } else if (length <= 1536) {
1089 val |= MAX_RX_PKT_LEN_1536;
1090 } else if (length <= 1552) {
1091 val |= MAX_RX_PKT_LEN_1552;
1092 } else {
1093 val &= ~MAX_RX_JUMBO_MASK;
1094 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1095 val |= MAX_RX_PKT_LEN_JUMBO;
1096 }
1097
1098 mt7530_mii_write(priv, MT7530_GMACCR, val);
1099
1100 mutex_unlock(&bus->mdio_lock);
1101
1102 return 0;
1103 }
1104
1105 static int
1106 mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1107 {
1108 return MT7530_MAX_MTU;
1109 }
1110
1111 static void
1112 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1113 {
1114 struct mt7530_priv *priv = ds->priv;
1115 u32 stp_state;
1116
1117 switch (state) {
1118 case BR_STATE_DISABLED:
1119 stp_state = MT7530_STP_DISABLED;
1120 break;
1121 case BR_STATE_BLOCKING:
1122 stp_state = MT7530_STP_BLOCKING;
1123 break;
1124 case BR_STATE_LISTENING:
1125 stp_state = MT7530_STP_LISTENING;
1126 break;
1127 case BR_STATE_LEARNING:
1128 stp_state = MT7530_STP_LEARNING;
1129 break;
1130 case BR_STATE_FORWARDING:
1131 default:
1132 stp_state = MT7530_STP_FORWARDING;
1133 break;
1134 }
1135
1136 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1137 }
1138
1139 static int
1140 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1141 struct net_device *bridge)
1142 {
1143 struct mt7530_priv *priv = ds->priv;
1144 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1145 int i;
1146
1147 mutex_lock(&priv->reg_mutex);
1148
1149 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1150 /* Add this port to the port matrix of the other ports in the
1151 * same bridge. If the port is disabled, port matrix is kept
1152 * and not being setup until the port becomes enabled.
1153 */
1154 if (dsa_is_user_port(ds, i) && i != port) {
1155 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1156 continue;
1157 if (priv->ports[i].enable)
1158 mt7530_set(priv, MT7530_PCR_P(i),
1159 PCR_MATRIX(BIT(port)));
1160 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1161
1162 port_bitmap |= BIT(i);
1163 }
1164 }
1165
1166 /* Add the all other ports to this port matrix. */
1167 if (priv->ports[port].enable)
1168 mt7530_rmw(priv, MT7530_PCR_P(port),
1169 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1170 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1171
1172 mutex_unlock(&priv->reg_mutex);
1173
1174 return 0;
1175 }
1176
1177 static void
1178 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1179 {
1180 struct mt7530_priv *priv = ds->priv;
1181 bool all_user_ports_removed = true;
1182 int i;
1183
1184 /* When a port is removed from the bridge, the port would be set up
1185 * back to the default as is at initial boot which is a VLAN-unaware
1186 * port.
1187 */
1188 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1189 MT7530_PORT_MATRIX_MODE);
1190 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1191 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1192 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1193
1194 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1195 if (dsa_is_user_port(ds, i) &&
1196 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1197 all_user_ports_removed = false;
1198 break;
1199 }
1200 }
1201
1202 /* CPU port also does the same thing until all user ports belonging to
1203 * the CPU port get out of VLAN filtering mode.
1204 */
1205 if (all_user_ports_removed) {
1206 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1207 PCR_MATRIX(dsa_user_ports(priv->ds)));
1208 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1209 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1210 }
1211 }
1212
1213 static void
1214 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1215 {
1216 struct mt7530_priv *priv = ds->priv;
1217
1218 /* The real fabric path would be decided on the membership in the
1219 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
1220 * means potential VLAN can be consisting of certain subset of all
1221 * ports.
1222 */
1223 mt7530_rmw(priv, MT7530_PCR_P(port),
1224 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
1225
1226 /* Trapped into security mode allows packet forwarding through VLAN
1227 * table lookup. CPU port is set to fallback mode to let untagged
1228 * frames pass through.
1229 */
1230 if (dsa_is_cpu_port(ds, port))
1231 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1232 MT7530_PORT_FALLBACK_MODE);
1233 else
1234 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1235 MT7530_PORT_SECURITY_MODE);
1236
1237 /* Set the port as a user port which is to be able to recognize VID
1238 * from incoming packets before fetching entry within the VLAN table.
1239 */
1240 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1241 VLAN_ATTR(MT7530_VLAN_USER) |
1242 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1243 }
1244
1245 static void
1246 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1247 struct net_device *bridge)
1248 {
1249 struct mt7530_priv *priv = ds->priv;
1250 int i;
1251
1252 mutex_lock(&priv->reg_mutex);
1253
1254 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1255 /* Remove this port from the port matrix of the other ports
1256 * in the same bridge. If the port is disabled, port matrix
1257 * is kept and not being setup until the port becomes enabled.
1258 * And the other port's port matrix cannot be broken when the
1259 * other port is still a VLAN-aware port.
1260 */
1261 if (dsa_is_user_port(ds, i) && i != port &&
1262 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1263 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1264 continue;
1265 if (priv->ports[i].enable)
1266 mt7530_clear(priv, MT7530_PCR_P(i),
1267 PCR_MATRIX(BIT(port)));
1268 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1269 }
1270 }
1271
1272 /* Set the cpu port to be the only one in the port matrix of
1273 * this port.
1274 */
1275 if (priv->ports[port].enable)
1276 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1277 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1278 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1279
1280 mutex_unlock(&priv->reg_mutex);
1281 }
1282
1283 static int
1284 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1285 const unsigned char *addr, u16 vid)
1286 {
1287 struct mt7530_priv *priv = ds->priv;
1288 int ret;
1289 u8 port_mask = BIT(port);
1290
1291 mutex_lock(&priv->reg_mutex);
1292 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1293 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1294 mutex_unlock(&priv->reg_mutex);
1295
1296 return ret;
1297 }
1298
1299 static int
1300 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1301 const unsigned char *addr, u16 vid)
1302 {
1303 struct mt7530_priv *priv = ds->priv;
1304 int ret;
1305 u8 port_mask = BIT(port);
1306
1307 mutex_lock(&priv->reg_mutex);
1308 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
1309 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1310 mutex_unlock(&priv->reg_mutex);
1311
1312 return ret;
1313 }
1314
1315 static int
1316 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1317 dsa_fdb_dump_cb_t *cb, void *data)
1318 {
1319 struct mt7530_priv *priv = ds->priv;
1320 struct mt7530_fdb _fdb = { 0 };
1321 int cnt = MT7530_NUM_FDB_RECORDS;
1322 int ret = 0;
1323 u32 rsp = 0;
1324
1325 mutex_lock(&priv->reg_mutex);
1326
1327 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1328 if (ret < 0)
1329 goto err;
1330
1331 do {
1332 if (rsp & ATC_SRCH_HIT) {
1333 mt7530_fdb_read(priv, &_fdb);
1334 if (_fdb.port_mask & BIT(port)) {
1335 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1336 data);
1337 if (ret < 0)
1338 break;
1339 }
1340 }
1341 } while (--cnt &&
1342 !(rsp & ATC_SRCH_END) &&
1343 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1344 err:
1345 mutex_unlock(&priv->reg_mutex);
1346
1347 return 0;
1348 }
1349
1350 static int
1351 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1352 {
1353 struct mt7530_dummy_poll p;
1354 u32 val;
1355 int ret;
1356
1357 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1358 mt7530_write(priv, MT7530_VTCR, val);
1359
1360 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1361 ret = readx_poll_timeout(_mt7530_read, &p, val,
1362 !(val & VTCR_BUSY), 20, 20000);
1363 if (ret < 0) {
1364 dev_err(priv->dev, "poll timeout\n");
1365 return ret;
1366 }
1367
1368 val = mt7530_read(priv, MT7530_VTCR);
1369 if (val & VTCR_INVALID) {
1370 dev_err(priv->dev, "read VTCR invalid\n");
1371 return -EINVAL;
1372 }
1373
1374 return 0;
1375 }
1376
1377 static int
1378 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1379 bool vlan_filtering,
1380 struct switchdev_trans *trans)
1381 {
1382 if (switchdev_trans_ph_prepare(trans))
1383 return 0;
1384
1385 if (vlan_filtering) {
1386 /* The port is being kept as VLAN-unaware port when bridge is
1387 * set up with vlan_filtering not being set, Otherwise, the
1388 * port and the corresponding CPU port is required the setup
1389 * for becoming a VLAN-aware port.
1390 */
1391 mt7530_port_set_vlan_aware(ds, port);
1392 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1393 } else {
1394 mt7530_port_set_vlan_unaware(ds, port);
1395 }
1396
1397 return 0;
1398 }
1399
1400 static int
1401 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1402 const struct switchdev_obj_port_vlan *vlan)
1403 {
1404 /* nothing needed */
1405
1406 return 0;
1407 }
1408
1409 static void
1410 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1411 struct mt7530_hw_vlan_entry *entry)
1412 {
1413 u8 new_members;
1414 u32 val;
1415
1416 new_members = entry->old_members | BIT(entry->port) |
1417 BIT(MT7530_CPU_PORT);
1418
1419 /* Validate the entry with independent learning, create egress tag per
1420 * VLAN and joining the port as one of the port members.
1421 */
1422 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1423 mt7530_write(priv, MT7530_VAWD1, val);
1424
1425 /* Decide whether adding tag or not for those outgoing packets from the
1426 * port inside the VLAN.
1427 */
1428 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1429 MT7530_VLAN_EGRESS_TAG;
1430 mt7530_rmw(priv, MT7530_VAWD2,
1431 ETAG_CTRL_P_MASK(entry->port),
1432 ETAG_CTRL_P(entry->port, val));
1433
1434 /* CPU port is always taken as a tagged port for serving more than one
1435 * VLANs across and also being applied with egress type stack mode for
1436 * that VLAN tags would be appended after hardware special tag used as
1437 * DSA tag.
1438 */
1439 mt7530_rmw(priv, MT7530_VAWD2,
1440 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1441 ETAG_CTRL_P(MT7530_CPU_PORT,
1442 MT7530_VLAN_EGRESS_STACK));
1443 }
1444
1445 static void
1446 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1447 struct mt7530_hw_vlan_entry *entry)
1448 {
1449 u8 new_members;
1450 u32 val;
1451
1452 new_members = entry->old_members & ~BIT(entry->port);
1453
1454 val = mt7530_read(priv, MT7530_VAWD1);
1455 if (!(val & VLAN_VALID)) {
1456 dev_err(priv->dev,
1457 "Cannot be deleted due to invalid entry\n");
1458 return;
1459 }
1460
1461 /* If certain member apart from CPU port is still alive in the VLAN,
1462 * the entry would be kept valid. Otherwise, the entry is got to be
1463 * disabled.
1464 */
1465 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1466 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1467 VLAN_VALID;
1468 mt7530_write(priv, MT7530_VAWD1, val);
1469 } else {
1470 mt7530_write(priv, MT7530_VAWD1, 0);
1471 mt7530_write(priv, MT7530_VAWD2, 0);
1472 }
1473 }
1474
1475 static void
1476 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1477 struct mt7530_hw_vlan_entry *entry,
1478 mt7530_vlan_op vlan_op)
1479 {
1480 u32 val;
1481
1482 /* Fetch entry */
1483 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1484
1485 val = mt7530_read(priv, MT7530_VAWD1);
1486
1487 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1488
1489 /* Manipulate entry */
1490 vlan_op(priv, entry);
1491
1492 /* Flush result to hardware */
1493 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1494 }
1495
1496 static void
1497 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1498 const struct switchdev_obj_port_vlan *vlan)
1499 {
1500 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1501 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1502 struct mt7530_hw_vlan_entry new_entry;
1503 struct mt7530_priv *priv = ds->priv;
1504 u16 vid;
1505
1506 mutex_lock(&priv->reg_mutex);
1507
1508 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1509 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1510 mt7530_hw_vlan_update(priv, vid, &new_entry,
1511 mt7530_hw_vlan_add);
1512 }
1513
1514 if (pvid) {
1515 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1516 G0_PORT_VID(vlan->vid_end));
1517 priv->ports[port].pvid = vlan->vid_end;
1518 }
1519
1520 mutex_unlock(&priv->reg_mutex);
1521 }
1522
1523 static int
1524 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1525 const struct switchdev_obj_port_vlan *vlan)
1526 {
1527 struct mt7530_hw_vlan_entry target_entry;
1528 struct mt7530_priv *priv = ds->priv;
1529 u16 vid, pvid;
1530
1531 mutex_lock(&priv->reg_mutex);
1532
1533 pvid = priv->ports[port].pvid;
1534 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1535 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1536 mt7530_hw_vlan_update(priv, vid, &target_entry,
1537 mt7530_hw_vlan_del);
1538
1539 /* PVID is being restored to the default whenever the PVID port
1540 * is being removed from the VLAN.
1541 */
1542 if (pvid == vid)
1543 pvid = G0_PORT_VID_DEF;
1544 }
1545
1546 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1547 priv->ports[port].pvid = pvid;
1548
1549 mutex_unlock(&priv->reg_mutex);
1550
1551 return 0;
1552 }
1553
1554 static int mt753x_mirror_port_get(unsigned int id, u32 val)
1555 {
1556 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1557 MIRROR_PORT(val);
1558 }
1559
1560 static int mt753x_mirror_port_set(unsigned int id, u32 val)
1561 {
1562 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1563 MIRROR_PORT(val);
1564 }
1565
1566 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1567 struct dsa_mall_mirror_tc_entry *mirror,
1568 bool ingress)
1569 {
1570 struct mt7530_priv *priv = ds->priv;
1571 int monitor_port;
1572 u32 val;
1573
1574 /* Check for existent entry */
1575 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1576 return -EEXIST;
1577
1578 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1579
1580 /* MT7530 only supports one monitor port */
1581 monitor_port = mt753x_mirror_port_get(priv->id, val);
1582 if (val & MT753X_MIRROR_EN(priv->id) &&
1583 monitor_port != mirror->to_local_port)
1584 return -EEXIST;
1585
1586 val |= MT753X_MIRROR_EN(priv->id);
1587 val &= ~MT753X_MIRROR_MASK(priv->id);
1588 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1589 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1590
1591 val = mt7530_read(priv, MT7530_PCR_P(port));
1592 if (ingress) {
1593 val |= PORT_RX_MIR;
1594 priv->mirror_rx |= BIT(port);
1595 } else {
1596 val |= PORT_TX_MIR;
1597 priv->mirror_tx |= BIT(port);
1598 }
1599 mt7530_write(priv, MT7530_PCR_P(port), val);
1600
1601 return 0;
1602 }
1603
1604 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1605 struct dsa_mall_mirror_tc_entry *mirror)
1606 {
1607 struct mt7530_priv *priv = ds->priv;
1608 u32 val;
1609
1610 val = mt7530_read(priv, MT7530_PCR_P(port));
1611 if (mirror->ingress) {
1612 val &= ~PORT_RX_MIR;
1613 priv->mirror_rx &= ~BIT(port);
1614 } else {
1615 val &= ~PORT_TX_MIR;
1616 priv->mirror_tx &= ~BIT(port);
1617 }
1618 mt7530_write(priv, MT7530_PCR_P(port), val);
1619
1620 if (!priv->mirror_rx && !priv->mirror_tx) {
1621 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1622 val &= ~MT753X_MIRROR_EN(priv->id);
1623 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1624 }
1625 }
1626
1627 static enum dsa_tag_protocol
1628 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1629 enum dsa_tag_protocol mp)
1630 {
1631 struct mt7530_priv *priv = ds->priv;
1632
1633 if (port != MT7530_CPU_PORT) {
1634 dev_warn(priv->dev,
1635 "port not matched with tagging CPU port\n");
1636 return DSA_TAG_PROTO_NONE;
1637 } else {
1638 return DSA_TAG_PROTO_MTK;
1639 }
1640 }
1641
1642 static int
1643 mt7530_setup(struct dsa_switch *ds)
1644 {
1645 struct mt7530_priv *priv = ds->priv;
1646 struct device_node *phy_node;
1647 struct device_node *mac_np;
1648 struct mt7530_dummy_poll p;
1649 phy_interface_t interface;
1650 struct device_node *dn;
1651 u32 id, val;
1652 int ret, i;
1653
1654 /* The parent node of master netdev which holds the common system
1655 * controller also is the container for two GMACs nodes representing
1656 * as two netdev instances.
1657 */
1658 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
1659 ds->configure_vlan_while_not_filtering = true;
1660 ds->mtu_enforcement_ingress = true;
1661
1662 if (priv->id == ID_MT7530) {
1663 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1664 ret = regulator_enable(priv->core_pwr);
1665 if (ret < 0) {
1666 dev_err(priv->dev,
1667 "Failed to enable core power: %d\n", ret);
1668 return ret;
1669 }
1670
1671 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1672 ret = regulator_enable(priv->io_pwr);
1673 if (ret < 0) {
1674 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1675 ret);
1676 return ret;
1677 }
1678 }
1679
1680 /* Reset whole chip through gpio pin or memory-mapped registers for
1681 * different type of hardware
1682 */
1683 if (priv->mcm) {
1684 reset_control_assert(priv->rstc);
1685 usleep_range(1000, 1100);
1686 reset_control_deassert(priv->rstc);
1687 } else {
1688 gpiod_set_value_cansleep(priv->reset, 0);
1689 usleep_range(1000, 1100);
1690 gpiod_set_value_cansleep(priv->reset, 1);
1691 }
1692
1693 /* Waiting for MT7530 got to stable */
1694 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1695 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1696 20, 1000000);
1697 if (ret < 0) {
1698 dev_err(priv->dev, "reset timeout\n");
1699 return ret;
1700 }
1701
1702 id = mt7530_read(priv, MT7530_CREV);
1703 id >>= CHIP_NAME_SHIFT;
1704 if (id != MT7530_ID) {
1705 dev_err(priv->dev, "chip %x can't be supported\n", id);
1706 return -ENODEV;
1707 }
1708
1709 /* Reset the switch through internal reset */
1710 mt7530_write(priv, MT7530_SYS_CTRL,
1711 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1712 SYS_CTRL_REG_RST);
1713
1714 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1715 val = mt7530_read(priv, MT7530_MHWTRAP);
1716 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1717 val |= MHWTRAP_MANUAL;
1718 mt7530_write(priv, MT7530_MHWTRAP, val);
1719
1720 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1721
1722 /* Enable and reset MIB counters */
1723 mt7530_mib_reset(ds);
1724
1725 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1726 /* Disable forwarding by default on all ports */
1727 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1728 PCR_MATRIX_CLR);
1729
1730 if (dsa_is_cpu_port(ds, i)) {
1731 ret = mt753x_cpu_port_enable(ds, i);
1732 if (ret)
1733 return ret;
1734 } else
1735 mt7530_port_disable(ds, i);
1736
1737 /* Enable consistent egress tag */
1738 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1739 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1740 }
1741
1742 /* Setup port 5 */
1743 priv->p5_intf_sel = P5_DISABLED;
1744 interface = PHY_INTERFACE_MODE_NA;
1745
1746 if (!dsa_is_unused_port(ds, 5)) {
1747 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1748 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1749 if (ret && ret != -ENODEV)
1750 return ret;
1751 } else {
1752 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1753 for_each_child_of_node(dn, mac_np) {
1754 if (!of_device_is_compatible(mac_np,
1755 "mediatek,eth-mac"))
1756 continue;
1757
1758 ret = of_property_read_u32(mac_np, "reg", &id);
1759 if (ret < 0 || id != 1)
1760 continue;
1761
1762 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1763 if (!phy_node)
1764 continue;
1765
1766 if (phy_node->parent == priv->dev->of_node->parent) {
1767 ret = of_get_phy_mode(mac_np, &interface);
1768 if (ret && ret != -ENODEV) {
1769 of_node_put(mac_np);
1770 return ret;
1771 }
1772 id = of_mdio_parse_addr(ds->dev, phy_node);
1773 if (id == 0)
1774 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1775 if (id == 4)
1776 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1777 }
1778 of_node_put(mac_np);
1779 of_node_put(phy_node);
1780 break;
1781 }
1782 }
1783
1784 mt7530_setup_port5(ds, interface);
1785
1786 /* Flush the FDB table */
1787 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1788 if (ret < 0)
1789 return ret;
1790
1791 return 0;
1792 }
1793
1794 static int
1795 mt7531_setup(struct dsa_switch *ds)
1796 {
1797 struct mt7530_priv *priv = ds->priv;
1798 struct mt7530_dummy_poll p;
1799 u32 val, id;
1800 int ret, i;
1801
1802 /* Reset whole chip through gpio pin or memory-mapped registers for
1803 * different type of hardware
1804 */
1805 if (priv->mcm) {
1806 reset_control_assert(priv->rstc);
1807 usleep_range(1000, 1100);
1808 reset_control_deassert(priv->rstc);
1809 } else {
1810 gpiod_set_value_cansleep(priv->reset, 0);
1811 usleep_range(1000, 1100);
1812 gpiod_set_value_cansleep(priv->reset, 1);
1813 }
1814
1815 /* Waiting for MT7530 got to stable */
1816 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1817 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1818 20, 1000000);
1819 if (ret < 0) {
1820 dev_err(priv->dev, "reset timeout\n");
1821 return ret;
1822 }
1823
1824 id = mt7530_read(priv, MT7531_CREV);
1825 id >>= CHIP_NAME_SHIFT;
1826
1827 if (id != MT7531_ID) {
1828 dev_err(priv->dev, "chip %x can't be supported\n", id);
1829 return -ENODEV;
1830 }
1831
1832 /* Reset the switch through internal reset */
1833 mt7530_write(priv, MT7530_SYS_CTRL,
1834 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1835 SYS_CTRL_REG_RST);
1836
1837 if (mt7531_dual_sgmii_supported(priv)) {
1838 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
1839
1840 /* Let ds->slave_mii_bus be able to access external phy. */
1841 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
1842 MT7531_EXT_P_MDC_11);
1843 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
1844 MT7531_EXT_P_MDIO_12);
1845 } else {
1846 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1847 }
1848 dev_dbg(ds->dev, "P5 support %s interface\n",
1849 p5_intf_modes(priv->p5_intf_sel));
1850
1851 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
1852 MT7531_GPIO0_INTERRUPT);
1853
1854 /* Let phylink decide the interface later. */
1855 priv->p5_interface = PHY_INTERFACE_MODE_NA;
1856 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1857
1858 /* Enable PHY core PLL, since phy_device has not yet been created
1859 * provided for phy_[read,write]_mmd_indirect is called, we provide
1860 * our own mt7531_ind_mmd_phy_[read,write] to complete this
1861 * function.
1862 */
1863 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
1864 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
1865 val |= MT7531_PHY_PLL_BYPASS_MODE;
1866 val &= ~MT7531_PHY_PLL_OFF;
1867 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
1868 CORE_PLL_GROUP4, val);
1869
1870 /* BPDU to CPU port */
1871 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
1872 BIT(MT7530_CPU_PORT));
1873 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
1874 MT753X_BPDU_CPU_ONLY);
1875
1876 /* Enable and reset MIB counters */
1877 mt7530_mib_reset(ds);
1878
1879 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1880 /* Disable forwarding by default on all ports */
1881 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1882 PCR_MATRIX_CLR);
1883
1884 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
1885
1886 if (dsa_is_cpu_port(ds, i)) {
1887 ret = mt753x_cpu_port_enable(ds, i);
1888 if (ret)
1889 return ret;
1890 } else
1891 mt7530_port_disable(ds, i);
1892
1893 /* Enable consistent egress tag */
1894 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1895 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1896 }
1897
1898 ds->configure_vlan_while_not_filtering = true;
1899 ds->mtu_enforcement_ingress = true;
1900
1901 /* Flush the FDB table */
1902 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1903 if (ret < 0)
1904 return ret;
1905
1906 return 0;
1907 }
1908
1909 static bool
1910 mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
1911 const struct phylink_link_state *state)
1912 {
1913 struct mt7530_priv *priv = ds->priv;
1914
1915 switch (port) {
1916 case 0 ... 4: /* Internal phy */
1917 if (state->interface != PHY_INTERFACE_MODE_GMII)
1918 return false;
1919 break;
1920 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1921 if (!phy_interface_mode_is_rgmii(state->interface) &&
1922 state->interface != PHY_INTERFACE_MODE_MII &&
1923 state->interface != PHY_INTERFACE_MODE_GMII)
1924 return false;
1925 break;
1926 case 6: /* 1st cpu port */
1927 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1928 state->interface != PHY_INTERFACE_MODE_TRGMII)
1929 return false;
1930 break;
1931 default:
1932 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1933 port);
1934 return false;
1935 }
1936
1937 return true;
1938 }
1939
1940 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
1941 {
1942 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
1943 }
1944
1945 static bool
1946 mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
1947 const struct phylink_link_state *state)
1948 {
1949 struct mt7530_priv *priv = ds->priv;
1950
1951 switch (port) {
1952 case 0 ... 4: /* Internal phy */
1953 if (state->interface != PHY_INTERFACE_MODE_GMII)
1954 return false;
1955 break;
1956 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
1957 if (mt7531_is_rgmii_port(priv, port))
1958 return phy_interface_mode_is_rgmii(state->interface);
1959 fallthrough;
1960 case 6: /* 1st cpu port supports sgmii/8023z only */
1961 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
1962 !phy_interface_mode_is_8023z(state->interface))
1963 return false;
1964 break;
1965 default:
1966 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1967 port);
1968 return false;
1969 }
1970
1971 return true;
1972 }
1973
1974 static bool
1975 mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
1976 const struct phylink_link_state *state)
1977 {
1978 struct mt7530_priv *priv = ds->priv;
1979
1980 return priv->info->phy_mode_supported(ds, port, state);
1981 }
1982
1983 static int
1984 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
1985 {
1986 struct mt7530_priv *priv = ds->priv;
1987
1988 return priv->info->pad_setup(ds, state->interface);
1989 }
1990
1991 static int
1992 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1993 phy_interface_t interface)
1994 {
1995 struct mt7530_priv *priv = ds->priv;
1996
1997 /* Only need to setup port5. */
1998 if (port != 5)
1999 return 0;
2000
2001 mt7530_setup_port5(priv->ds, interface);
2002
2003 return 0;
2004 }
2005
2006 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2007 phy_interface_t interface,
2008 struct phy_device *phydev)
2009 {
2010 u32 val;
2011
2012 if (!mt7531_is_rgmii_port(priv, port)) {
2013 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2014 port);
2015 return -EINVAL;
2016 }
2017
2018 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2019 val |= GP_CLK_EN;
2020 val &= ~GP_MODE_MASK;
2021 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2022 val &= ~CLK_SKEW_IN_MASK;
2023 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2024 val &= ~CLK_SKEW_OUT_MASK;
2025 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2026 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2027
2028 /* Do not adjust rgmii delay when vendor phy driver presents. */
2029 if (!phydev || phy_driver_is_genphy(phydev)) {
2030 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2031 switch (interface) {
2032 case PHY_INTERFACE_MODE_RGMII:
2033 val |= TXCLK_NO_REVERSE;
2034 val |= RXCLK_NO_DELAY;
2035 break;
2036 case PHY_INTERFACE_MODE_RGMII_RXID:
2037 val |= TXCLK_NO_REVERSE;
2038 break;
2039 case PHY_INTERFACE_MODE_RGMII_TXID:
2040 val |= RXCLK_NO_DELAY;
2041 break;
2042 case PHY_INTERFACE_MODE_RGMII_ID:
2043 break;
2044 default:
2045 return -EINVAL;
2046 }
2047 }
2048 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2049
2050 return 0;
2051 }
2052
2053 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2054 unsigned long *supported)
2055 {
2056 /* Port5 supports ethier RGMII or SGMII.
2057 * Port6 supports SGMII only.
2058 */
2059 switch (port) {
2060 case 5:
2061 if (mt7531_is_rgmii_port(priv, port))
2062 break;
2063 fallthrough;
2064 case 6:
2065 phylink_set(supported, 1000baseX_Full);
2066 phylink_set(supported, 2500baseX_Full);
2067 phylink_set(supported, 2500baseT_Full);
2068 }
2069 }
2070
2071 static void
2072 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2073 unsigned int mode, phy_interface_t interface,
2074 int speed, int duplex)
2075 {
2076 struct mt7530_priv *priv = ds->priv;
2077 unsigned int val;
2078
2079 /* For adjusting speed and duplex of SGMII force mode. */
2080 if (interface != PHY_INTERFACE_MODE_SGMII ||
2081 phylink_autoneg_inband(mode))
2082 return;
2083
2084 /* SGMII force mode setting */
2085 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2086 val &= ~MT7531_SGMII_IF_MODE_MASK;
2087
2088 switch (speed) {
2089 case SPEED_10:
2090 val |= MT7531_SGMII_FORCE_SPEED_10;
2091 break;
2092 case SPEED_100:
2093 val |= MT7531_SGMII_FORCE_SPEED_100;
2094 break;
2095 case SPEED_1000:
2096 val |= MT7531_SGMII_FORCE_SPEED_1000;
2097 break;
2098 }
2099
2100 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2101 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2102 */
2103 if ((speed == SPEED_10 || speed == SPEED_100) &&
2104 duplex != DUPLEX_FULL)
2105 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2106
2107 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2108 }
2109
2110 static bool mt753x_is_mac_port(u32 port)
2111 {
2112 return (port == 5 || port == 6);
2113 }
2114
2115 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2116 phy_interface_t interface)
2117 {
2118 u32 val;
2119
2120 if (!mt753x_is_mac_port(port))
2121 return -EINVAL;
2122
2123 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2124 MT7531_SGMII_PHYA_PWD);
2125
2126 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2127 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2128 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2129 * encoding.
2130 */
2131 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2132 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2133 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2134
2135 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2136
2137 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2138 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2139 */
2140 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2141 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2142 MT7531_SGMII_FORCE_SPEED_1000);
2143
2144 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2145
2146 return 0;
2147 }
2148
2149 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2150 phy_interface_t interface)
2151 {
2152 if (!mt753x_is_mac_port(port))
2153 return -EINVAL;
2154
2155 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2156 MT7531_SGMII_PHYA_PWD);
2157
2158 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2159 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2160
2161 mt7530_set(priv, MT7531_SGMII_MODE(port),
2162 MT7531_SGMII_REMOTE_FAULT_DIS |
2163 MT7531_SGMII_SPEED_DUPLEX_AN);
2164
2165 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2166 MT7531_SGMII_TX_CONFIG_MASK, 1);
2167
2168 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2169
2170 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2171
2172 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2173
2174 return 0;
2175 }
2176
2177 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2178 {
2179 struct mt7530_priv *priv = ds->priv;
2180 u32 val;
2181
2182 /* Only restart AN when AN is enabled */
2183 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2184 if (val & MT7531_SGMII_AN_ENABLE) {
2185 val |= MT7531_SGMII_AN_RESTART;
2186 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2187 }
2188 }
2189
2190 static int
2191 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2192 phy_interface_t interface)
2193 {
2194 struct mt7530_priv *priv = ds->priv;
2195 struct phy_device *phydev;
2196 struct dsa_port *dp;
2197
2198 if (!mt753x_is_mac_port(port)) {
2199 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2200 return -EINVAL;
2201 }
2202
2203 switch (interface) {
2204 case PHY_INTERFACE_MODE_RGMII:
2205 case PHY_INTERFACE_MODE_RGMII_ID:
2206 case PHY_INTERFACE_MODE_RGMII_RXID:
2207 case PHY_INTERFACE_MODE_RGMII_TXID:
2208 dp = dsa_to_port(ds, port);
2209 phydev = dp->slave->phydev;
2210 return mt7531_rgmii_setup(priv, port, interface, phydev);
2211 case PHY_INTERFACE_MODE_SGMII:
2212 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2213 case PHY_INTERFACE_MODE_NA:
2214 case PHY_INTERFACE_MODE_1000BASEX:
2215 case PHY_INTERFACE_MODE_2500BASEX:
2216 if (phylink_autoneg_inband(mode))
2217 return -EINVAL;
2218
2219 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2220 default:
2221 return -EINVAL;
2222 }
2223
2224 return -EINVAL;
2225 }
2226
2227 static int
2228 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2229 const struct phylink_link_state *state)
2230 {
2231 struct mt7530_priv *priv = ds->priv;
2232
2233 return priv->info->mac_port_config(ds, port, mode, state->interface);
2234 }
2235
2236 static void
2237 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2238 const struct phylink_link_state *state)
2239 {
2240 struct mt7530_priv *priv = ds->priv;
2241 u32 mcr_cur, mcr_new;
2242
2243 if (!mt753x_phy_mode_supported(ds, port, state))
2244 goto unsupported;
2245
2246 switch (port) {
2247 case 0 ... 4: /* Internal phy */
2248 if (state->interface != PHY_INTERFACE_MODE_GMII)
2249 goto unsupported;
2250 break;
2251 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2252 if (priv->p5_interface == state->interface)
2253 break;
2254
2255 if (mt753x_mac_config(ds, port, mode, state) < 0)
2256 goto unsupported;
2257
2258 if (priv->p5_intf_sel != P5_DISABLED)
2259 priv->p5_interface = state->interface;
2260 break;
2261 case 6: /* 1st cpu port */
2262 if (priv->p6_interface == state->interface)
2263 break;
2264
2265 mt753x_pad_setup(ds, state);
2266
2267 if (mt753x_mac_config(ds, port, mode, state) < 0)
2268 goto unsupported;
2269
2270 priv->p6_interface = state->interface;
2271 break;
2272 default:
2273 unsupported:
2274 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2275 __func__, phy_modes(state->interface), port);
2276 return;
2277 }
2278
2279 if (phylink_autoneg_inband(mode) &&
2280 state->interface != PHY_INTERFACE_MODE_SGMII) {
2281 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2282 __func__);
2283 return;
2284 }
2285
2286 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2287 mcr_new = mcr_cur;
2288 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
2289 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
2290 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
2291
2292 /* Are we connected to external phy */
2293 if (port == 5 && dsa_is_user_port(ds, 5))
2294 mcr_new |= PMCR_EXT_PHY;
2295
2296 if (mcr_new != mcr_cur)
2297 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2298 }
2299
2300 static void
2301 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2302 {
2303 struct mt7530_priv *priv = ds->priv;
2304
2305 if (!priv->info->mac_pcs_an_restart)
2306 return;
2307
2308 priv->info->mac_pcs_an_restart(ds, port);
2309 }
2310
2311 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2312 unsigned int mode,
2313 phy_interface_t interface)
2314 {
2315 struct mt7530_priv *priv = ds->priv;
2316
2317 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2318 }
2319
2320 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2321 unsigned int mode, phy_interface_t interface,
2322 int speed, int duplex)
2323 {
2324 struct mt7530_priv *priv = ds->priv;
2325
2326 if (!priv->info->mac_pcs_link_up)
2327 return;
2328
2329 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2330 }
2331
2332 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2333 unsigned int mode,
2334 phy_interface_t interface,
2335 struct phy_device *phydev,
2336 int speed, int duplex,
2337 bool tx_pause, bool rx_pause)
2338 {
2339 struct mt7530_priv *priv = ds->priv;
2340 u32 mcr;
2341
2342 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2343
2344 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2345
2346 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2347 * variants.
2348 */
2349 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2350 (phy_interface_mode_is_8023z(interface))) {
2351 speed = SPEED_1000;
2352 duplex = DUPLEX_FULL;
2353 }
2354
2355 switch (speed) {
2356 case SPEED_1000:
2357 mcr |= PMCR_FORCE_SPEED_1000;
2358 break;
2359 case SPEED_100:
2360 mcr |= PMCR_FORCE_SPEED_100;
2361 break;
2362 }
2363 if (duplex == DUPLEX_FULL) {
2364 mcr |= PMCR_FORCE_FDX;
2365 if (tx_pause)
2366 mcr |= PMCR_TX_FC_EN;
2367 if (rx_pause)
2368 mcr |= PMCR_RX_FC_EN;
2369 }
2370
2371 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2372 }
2373
2374 static int
2375 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2376 {
2377 struct mt7530_priv *priv = ds->priv;
2378 phy_interface_t interface;
2379 int speed;
2380 int ret;
2381
2382 switch (port) {
2383 case 5:
2384 if (mt7531_is_rgmii_port(priv, port))
2385 interface = PHY_INTERFACE_MODE_RGMII;
2386 else
2387 interface = PHY_INTERFACE_MODE_2500BASEX;
2388
2389 priv->p5_interface = interface;
2390 break;
2391 case 6:
2392 interface = PHY_INTERFACE_MODE_2500BASEX;
2393
2394 mt7531_pad_setup(ds, interface);
2395
2396 priv->p6_interface = interface;
2397 break;
2398 default:
2399 return -EINVAL;
2400 }
2401
2402 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2403 speed = SPEED_2500;
2404 else
2405 speed = SPEED_1000;
2406
2407 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2408 if (ret)
2409 return ret;
2410 mt7530_write(priv, MT7530_PMCR_P(port),
2411 PMCR_CPU_PORT_SETTING(priv->id));
2412 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2413 speed, DUPLEX_FULL, true, true);
2414
2415 return 0;
2416 }
2417
2418 static void
2419 mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2420 unsigned long *supported)
2421 {
2422 if (port == 5)
2423 phylink_set(supported, 1000baseX_Full);
2424 }
2425
2426 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2427 unsigned long *supported)
2428 {
2429 struct mt7530_priv *priv = ds->priv;
2430
2431 mt7531_sgmii_validate(priv, port, supported);
2432 }
2433
2434 static void
2435 mt753x_phylink_validate(struct dsa_switch *ds, int port,
2436 unsigned long *supported,
2437 struct phylink_link_state *state)
2438 {
2439 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2440 struct mt7530_priv *priv = ds->priv;
2441
2442 if (state->interface != PHY_INTERFACE_MODE_NA &&
2443 !mt753x_phy_mode_supported(ds, port, state)) {
2444 linkmode_zero(supported);
2445 return;
2446 }
2447
2448 phylink_set_port_modes(mask);
2449
2450 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2451 !phy_interface_mode_is_8023z(state->interface)) {
2452 phylink_set(mask, 10baseT_Half);
2453 phylink_set(mask, 10baseT_Full);
2454 phylink_set(mask, 100baseT_Half);
2455 phylink_set(mask, 100baseT_Full);
2456 phylink_set(mask, Autoneg);
2457 }
2458
2459 /* This switch only supports 1G full-duplex. */
2460 if (state->interface != PHY_INTERFACE_MODE_MII)
2461 phylink_set(mask, 1000baseT_Full);
2462
2463 priv->info->mac_port_validate(ds, port, mask);
2464
2465 phylink_set(mask, Pause);
2466 phylink_set(mask, Asym_Pause);
2467
2468 linkmode_and(supported, supported, mask);
2469 linkmode_and(state->advertising, state->advertising, mask);
2470
2471 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2472 * to advertise both, only report advertising at 2500BaseX.
2473 */
2474 phylink_helper_basex_speed(state);
2475 }
2476
2477 static int
2478 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2479 struct phylink_link_state *state)
2480 {
2481 struct mt7530_priv *priv = ds->priv;
2482 u32 pmsr;
2483
2484 if (port < 0 || port >= MT7530_NUM_PORTS)
2485 return -EINVAL;
2486
2487 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2488
2489 state->link = (pmsr & PMSR_LINK);
2490 state->an_complete = state->link;
2491 state->duplex = !!(pmsr & PMSR_DPX);
2492
2493 switch (pmsr & PMSR_SPEED_MASK) {
2494 case PMSR_SPEED_10:
2495 state->speed = SPEED_10;
2496 break;
2497 case PMSR_SPEED_100:
2498 state->speed = SPEED_100;
2499 break;
2500 case PMSR_SPEED_1000:
2501 state->speed = SPEED_1000;
2502 break;
2503 default:
2504 state->speed = SPEED_UNKNOWN;
2505 break;
2506 }
2507
2508 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2509 if (pmsr & PMSR_RX_FC)
2510 state->pause |= MLO_PAUSE_RX;
2511 if (pmsr & PMSR_TX_FC)
2512 state->pause |= MLO_PAUSE_TX;
2513
2514 return 1;
2515 }
2516
2517 static int
2518 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2519 struct phylink_link_state *state)
2520 {
2521 u32 status, val;
2522 u16 config_reg;
2523
2524 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2525 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2526 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2527 (status & MT7531_SGMII_AN_ENABLE)) {
2528 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2529 config_reg = val >> 16;
2530
2531 switch (config_reg & LPA_SGMII_SPD_MASK) {
2532 case LPA_SGMII_1000:
2533 state->speed = SPEED_1000;
2534 break;
2535 case LPA_SGMII_100:
2536 state->speed = SPEED_100;
2537 break;
2538 case LPA_SGMII_10:
2539 state->speed = SPEED_10;
2540 break;
2541 default:
2542 dev_err(priv->dev, "invalid sgmii PHY speed\n");
2543 state->link = false;
2544 return -EINVAL;
2545 }
2546
2547 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2548 state->duplex = DUPLEX_FULL;
2549 else
2550 state->duplex = DUPLEX_HALF;
2551 }
2552
2553 return 0;
2554 }
2555
2556 static int
2557 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2558 struct phylink_link_state *state)
2559 {
2560 struct mt7530_priv *priv = ds->priv;
2561
2562 if (state->interface == PHY_INTERFACE_MODE_SGMII)
2563 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2564
2565 return -EOPNOTSUPP;
2566 }
2567
2568 static int
2569 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2570 struct phylink_link_state *state)
2571 {
2572 struct mt7530_priv *priv = ds->priv;
2573
2574 return priv->info->mac_port_get_state(ds, port, state);
2575 }
2576
2577 static int
2578 mt753x_setup(struct dsa_switch *ds)
2579 {
2580 struct mt7530_priv *priv = ds->priv;
2581
2582 return priv->info->sw_setup(ds);
2583 }
2584
2585 static int
2586 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
2587 {
2588 struct mt7530_priv *priv = ds->priv;
2589
2590 return priv->info->phy_read(ds, port, regnum);
2591 }
2592
2593 static int
2594 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2595 {
2596 struct mt7530_priv *priv = ds->priv;
2597
2598 return priv->info->phy_write(ds, port, regnum, val);
2599 }
2600
2601 static const struct dsa_switch_ops mt7530_switch_ops = {
2602 .get_tag_protocol = mtk_get_tag_protocol,
2603 .setup = mt753x_setup,
2604 .get_strings = mt7530_get_strings,
2605 .phy_read = mt753x_phy_read,
2606 .phy_write = mt753x_phy_write,
2607 .get_ethtool_stats = mt7530_get_ethtool_stats,
2608 .get_sset_count = mt7530_get_sset_count,
2609 .set_ageing_time = mt7530_set_ageing_time,
2610 .port_enable = mt7530_port_enable,
2611 .port_disable = mt7530_port_disable,
2612 .port_change_mtu = mt7530_port_change_mtu,
2613 .port_max_mtu = mt7530_port_max_mtu,
2614 .port_stp_state_set = mt7530_stp_state_set,
2615 .port_bridge_join = mt7530_port_bridge_join,
2616 .port_bridge_leave = mt7530_port_bridge_leave,
2617 .port_fdb_add = mt7530_port_fdb_add,
2618 .port_fdb_del = mt7530_port_fdb_del,
2619 .port_fdb_dump = mt7530_port_fdb_dump,
2620 .port_vlan_filtering = mt7530_port_vlan_filtering,
2621 .port_vlan_prepare = mt7530_port_vlan_prepare,
2622 .port_vlan_add = mt7530_port_vlan_add,
2623 .port_vlan_del = mt7530_port_vlan_del,
2624 .port_mirror_add = mt753x_port_mirror_add,
2625 .port_mirror_del = mt753x_port_mirror_del,
2626 .phylink_validate = mt753x_phylink_validate,
2627 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
2628 .phylink_mac_config = mt753x_phylink_mac_config,
2629 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
2630 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
2631 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
2632 };
2633
2634 static const struct mt753x_info mt753x_table[] = {
2635 [ID_MT7621] = {
2636 .id = ID_MT7621,
2637 .sw_setup = mt7530_setup,
2638 .phy_read = mt7530_phy_read,
2639 .phy_write = mt7530_phy_write,
2640 .pad_setup = mt7530_pad_clk_setup,
2641 .phy_mode_supported = mt7530_phy_mode_supported,
2642 .mac_port_validate = mt7530_mac_port_validate,
2643 .mac_port_get_state = mt7530_phylink_mac_link_state,
2644 .mac_port_config = mt7530_mac_config,
2645 },
2646 [ID_MT7530] = {
2647 .id = ID_MT7530,
2648 .sw_setup = mt7530_setup,
2649 .phy_read = mt7530_phy_read,
2650 .phy_write = mt7530_phy_write,
2651 .pad_setup = mt7530_pad_clk_setup,
2652 .phy_mode_supported = mt7530_phy_mode_supported,
2653 .mac_port_validate = mt7530_mac_port_validate,
2654 .mac_port_get_state = mt7530_phylink_mac_link_state,
2655 .mac_port_config = mt7530_mac_config,
2656 },
2657 [ID_MT7531] = {
2658 .id = ID_MT7531,
2659 .sw_setup = mt7531_setup,
2660 .phy_read = mt7531_ind_phy_read,
2661 .phy_write = mt7531_ind_phy_write,
2662 .pad_setup = mt7531_pad_setup,
2663 .cpu_port_config = mt7531_cpu_port_config,
2664 .phy_mode_supported = mt7531_phy_mode_supported,
2665 .mac_port_validate = mt7531_mac_port_validate,
2666 .mac_port_get_state = mt7531_phylink_mac_link_state,
2667 .mac_port_config = mt7531_mac_config,
2668 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
2669 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
2670 },
2671 };
2672
2673 static const struct of_device_id mt7530_of_match[] = {
2674 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
2675 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
2676 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
2677 { /* sentinel */ },
2678 };
2679 MODULE_DEVICE_TABLE(of, mt7530_of_match);
2680
2681 static int
2682 mt7530_probe(struct mdio_device *mdiodev)
2683 {
2684 struct mt7530_priv *priv;
2685 struct device_node *dn;
2686
2687 dn = mdiodev->dev.of_node;
2688
2689 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2690 if (!priv)
2691 return -ENOMEM;
2692
2693 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2694 if (!priv->ds)
2695 return -ENOMEM;
2696
2697 priv->ds->dev = &mdiodev->dev;
2698 priv->ds->num_ports = DSA_MAX_PORTS;
2699
2700 /* Use medatek,mcm property to distinguish hardware type that would
2701 * casues a little bit differences on power-on sequence.
2702 */
2703 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
2704 if (priv->mcm) {
2705 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
2706
2707 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
2708 if (IS_ERR(priv->rstc)) {
2709 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2710 return PTR_ERR(priv->rstc);
2711 }
2712 }
2713
2714 /* Get the hardware identifier from the devicetree node.
2715 * We will need it for some of the clock and regulator setup.
2716 */
2717 priv->info = of_device_get_match_data(&mdiodev->dev);
2718 if (!priv->info)
2719 return -EINVAL;
2720
2721 /* Sanity check if these required device operations are filled
2722 * properly.
2723 */
2724 if (!priv->info->sw_setup || !priv->info->pad_setup ||
2725 !priv->info->phy_read || !priv->info->phy_write ||
2726 !priv->info->phy_mode_supported ||
2727 !priv->info->mac_port_validate ||
2728 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
2729 return -EINVAL;
2730
2731 priv->id = priv->info->id;
2732
2733 if (priv->id == ID_MT7530) {
2734 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
2735 if (IS_ERR(priv->core_pwr))
2736 return PTR_ERR(priv->core_pwr);
2737
2738 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
2739 if (IS_ERR(priv->io_pwr))
2740 return PTR_ERR(priv->io_pwr);
2741 }
2742
2743 /* Not MCM that indicates switch works as the remote standalone
2744 * integrated circuit so the GPIO pin would be used to complete
2745 * the reset, otherwise memory-mapped register accessing used
2746 * through syscon provides in the case of MCM.
2747 */
2748 if (!priv->mcm) {
2749 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
2750 GPIOD_OUT_LOW);
2751 if (IS_ERR(priv->reset)) {
2752 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2753 return PTR_ERR(priv->reset);
2754 }
2755 }
2756
2757 priv->bus = mdiodev->bus;
2758 priv->dev = &mdiodev->dev;
2759 priv->ds->priv = priv;
2760 priv->ds->ops = &mt7530_switch_ops;
2761 mutex_init(&priv->reg_mutex);
2762 dev_set_drvdata(&mdiodev->dev, priv);
2763
2764 return dsa_register_switch(priv->ds);
2765 }
2766
2767 static void
2768 mt7530_remove(struct mdio_device *mdiodev)
2769 {
2770 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
2771 int ret = 0;
2772
2773 ret = regulator_disable(priv->core_pwr);
2774 if (ret < 0)
2775 dev_err(priv->dev,
2776 "Failed to disable core power: %d\n", ret);
2777
2778 ret = regulator_disable(priv->io_pwr);
2779 if (ret < 0)
2780 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
2781 ret);
2782
2783 dsa_unregister_switch(priv->ds);
2784 mutex_destroy(&priv->reg_mutex);
2785 }
2786
2787 static struct mdio_driver mt7530_mdio_driver = {
2788 .probe = mt7530_probe,
2789 .remove = mt7530_remove,
2790 .mdiodrv.driver = {
2791 .name = "mt7530",
2792 .of_match_table = mt7530_of_match,
2793 },
2794 };
2795
2796 mdio_module_driver(mt7530_mdio_driver);
2797
2798 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
2799 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
2800 MODULE_LICENSE("GPL");
Linux with added FPC-III support