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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / dsa / qca / ar9331.c
blob4d49c5f2b79056a8abfb711612ddb94a54fa8712
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
3 /*
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
7 * | | | +------+
8 * | | +--| |
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
10 * | | | | +------+
11 * | | | +--| |
12 * | MAC2-|----RMII--------| PHY1 |-o P1
13 * | | | | +------+
14 * | | | +--| |
15 * | MAC3-|----RMII--------| PHY2 |-o P2
16 * | | | | +------+
17 * | | | +--| |
18 * | MAC4-|----RMII--------| PHY3 |-o P3
19 * | | | | +------+
20 * | | | +--| |
21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4
22 * | | | | +------+
23 * +----------------------+ | \--CFG_SW_PHY_SWAP
24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP
25 * \---MDIO0--NC
26 *
27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on
28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be
29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled.
30 *
31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this
33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5
34 * bundle.
35 *
36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
37 *
38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register
39 * set and not related to switch internal registers.
40 */
41
42 #include <linux/bitfield.h>
43 #include <linux/module.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_mdio.h>
46 #include <linux/regmap.h>
47 #include <linux/reset.h>
48 #include <net/dsa.h>
49
50 #define AR9331_SW_NAME "ar9331_switch"
51 #define AR9331_SW_PORTS 6
52
53 /* dummy reg to change page */
54 #define AR9331_SW_REG_PAGE 0x40000
55
56 /* Global Interrupt */
57 #define AR9331_SW_REG_GINT 0x10
58 #define AR9331_SW_REG_GINT_MASK 0x14
59 #define AR9331_SW_GINT_PHY_INT BIT(2)
60
61 #define AR9331_SW_REG_FLOOD_MASK 0x2c
62 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26)
63
64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30
65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
66
67 #define AR9331_SW_REG_MDIO_CTRL 0x98
68 #define AR9331_SW_MDIO_CTRL_BUSY BIT(31)
69 #define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30)
70 #define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27)
71 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)
72 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)
73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
74
75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
76
77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
78 * If not set, mac can be config by software.
79 */
80 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12)
81
82 /* LINK_EN - If set, MAC is configured from PHY link status.
83 * If not set, MAC should be configured by software.
84 */
85 #define AR9331_SW_PORT_STATUS_LINK_EN BIT(9)
86 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6)
87 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5)
88 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4)
89 #define AR9331_SW_PORT_STATUS_RXMAC BIT(3)
90 #define AR9331_SW_PORT_STATUS_TXMAC BIT(2)
91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
92 #define AR9331_SW_PORT_STATUS_SPEED_1000 2
93 #define AR9331_SW_PORT_STATUS_SPEED_100 1
94 #define AR9331_SW_PORT_STATUS_SPEED_10 0
95
96 #define AR9331_SW_PORT_STATUS_MAC_MASK \
97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
98
99 #define AR9331_SW_PORT_STATUS_LINK_MASK \
100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
102 AR9331_SW_PORT_STATUS_SPEED_M)
103
104 /* Phy bypass mode
105 * ------------------------------------------------------------------------
106 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
107 *
108 * real | start | OP | PhyAddr | Reg Addr | TA |
109 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA |
110 *
111 *
112 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
113 * real | Data |
114 * atheros| Data |
115 *
116 * ------------------------------------------------------------------------
117 * Page address mode
118 * ------------------------------------------------------------------------
119 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
120 * real | start | OP | PhyAddr | Reg Addr | TA |
121 * atheros| start | OP | 2'b11 | 8'b0 | TA |
122 *
123 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
124 * real | Data |
125 * atheros| | Page [9:0] |
126 */
127 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be
128 * written to bits[9:0] of mdio data register.
129 */
130 #define AR9331_SW_ADDR_PAGE GENMASK(18, 9)
131
132 /* ------------------------------------------------------------------------
133 * Normal register access mode
134 * ------------------------------------------------------------------------
135 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
136 * real | start | OP | PhyAddr | Reg Addr | TA |
137 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA |
138 *
139 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
140 * real | Data |
141 * atheros| Data |
142 * ------------------------------------------------------------------------
143 */
144 #define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)
145 #define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)
146
147 #define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)
148 #define AR9331_SW_MDIO_PHY_MODE_PAGE 3
149 #define AR9331_SW_MDIO_PHY_MODE_REG 2
150 #define AR9331_SW_MDIO_PHY_MODE_BYPASS 0
151 #define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)
152
153 /* Empirical determined values */
154 #define AR9331_SW_MDIO_POLL_SLEEP_US 1
155 #define AR9331_SW_MDIO_POLL_TIMEOUT_US 20
156
157 struct ar9331_sw_priv {
158 struct device *dev;
159 struct dsa_switch ds;
160 struct dsa_switch_ops ops;
161 struct irq_domain *irqdomain;
162 u32 irq_mask;
163 struct mutex lock_irq;
164 struct mii_bus *mbus; /* mdio master */
165 struct mii_bus *sbus; /* mdio slave */
166 struct regmap *regmap;
167 struct reset_control *sw_reset;
168 };
169
170 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
171 * If some kind of optimization is used, the request should be repeated.
172 */
173 static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
174 {
175 int ret;
176
177 ret = reset_control_assert(priv->sw_reset);
178 if (ret)
179 goto error;
180
181 /* AR9331 doc do not provide any information about proper reset
182 * sequence. The AR8136 (the closes switch to the AR9331) doc says:
183 * reset duration should be greater than 10ms. So, let's use this value
184 * for now.
185 */
186 usleep_range(10000, 15000);
187 ret = reset_control_deassert(priv->sw_reset);
188 if (ret)
189 goto error;
190 /* There is no information on how long should we wait after reset.
191 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load
192 * status. AR9331 has no EEPROM support.
193 * For now, do not wait. In case AR8136 will be needed, the after
194 * reset delay can be added as well.
195 */
196
197 return 0;
198 error:
199 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
200 return ret;
201 }
202
203 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
204 u16 data)
205 {
206 struct ar9331_sw_priv *priv = mbus->priv;
207 struct regmap *regmap = priv->regmap;
208 u32 val;
209 int ret;
210
211 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
212 AR9331_SW_MDIO_CTRL_BUSY |
213 AR9331_SW_MDIO_CTRL_MASTER_EN |
214 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
215 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
216 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
217 if (ret)
218 goto error;
219
220 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
221 !(val & AR9331_SW_MDIO_CTRL_BUSY),
222 AR9331_SW_MDIO_POLL_SLEEP_US,
223 AR9331_SW_MDIO_POLL_TIMEOUT_US);
224 if (ret)
225 goto error;
226
227 return 0;
228 error:
229 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
230 return ret;
231 }
232
233 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
234 {
235 struct ar9331_sw_priv *priv = mbus->priv;
236 struct regmap *regmap = priv->regmap;
237 u32 val;
238 int ret;
239
240 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
241 AR9331_SW_MDIO_CTRL_BUSY |
242 AR9331_SW_MDIO_CTRL_MASTER_EN |
243 AR9331_SW_MDIO_CTRL_CMD_READ |
244 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
245 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
246 if (ret)
247 goto error;
248
249 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
250 !(val & AR9331_SW_MDIO_CTRL_BUSY),
251 AR9331_SW_MDIO_POLL_SLEEP_US,
252 AR9331_SW_MDIO_POLL_TIMEOUT_US);
253 if (ret)
254 goto error;
255
256 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
257 if (ret)
258 goto error;
259
260 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
261
262 error:
263 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
264 return ret;
265 }
266
267 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
268 {
269 struct device *dev = priv->dev;
270 struct mii_bus *mbus;
271 struct device_node *np, *mnp;
272 int ret;
273
274 np = dev->of_node;
275
276 mbus = devm_mdiobus_alloc(dev);
277 if (!mbus)
278 return -ENOMEM;
279
280 mbus->name = np->full_name;
281 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
282
283 mbus->read = ar9331_sw_mbus_read;
284 mbus->write = ar9331_sw_mbus_write;
285 mbus->priv = priv;
286 mbus->parent = dev;
287
288 mnp = of_get_child_by_name(np, "mdio");
289 if (!mnp)
290 return -ENODEV;
291
292 ret = of_mdiobus_register(mbus, mnp);
293 of_node_put(mnp);
294 if (ret)
295 return ret;
296
297 priv->mbus = mbus;
298
299 return 0;
300 }
301
302 static int ar9331_sw_setup(struct dsa_switch *ds)
303 {
304 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
305 struct regmap *regmap = priv->regmap;
306 int ret;
307
308 ret = ar9331_sw_reset(priv);
309 if (ret)
310 return ret;
311
312 /* Reset will set proper defaults. CPU - Port0 will be enabled and
313 * configured. All other ports (ports 1 - 5) are disabled
314 */
315 ret = ar9331_sw_mbus_init(priv);
316 if (ret)
317 return ret;
318
319 /* Do not drop broadcast frames */
320 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
321 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
322 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
323 if (ret)
324 goto error;
325
326 /* Set max frame size to the maximum supported value */
327 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
328 AR9331_SW_GLOBAL_CTRL_MFS_M,
329 AR9331_SW_GLOBAL_CTRL_MFS_M);
330 if (ret)
331 goto error;
332
333 return 0;
334 error:
335 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
336 return ret;
337 }
338
339 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
340 {
341 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
342 struct regmap *regmap = priv->regmap;
343 int ret;
344
345 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
346 if (ret)
347 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
348 }
349
350 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
351 int port,
352 enum dsa_tag_protocol m)
353 {
354 return DSA_TAG_PROTO_AR9331;
355 }
356
357 static void ar9331_sw_phylink_validate(struct dsa_switch *ds, int port,
358 unsigned long *supported,
359 struct phylink_link_state *state)
360 {
361 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
362
363 switch (port) {
364 case 0:
365 if (state->interface != PHY_INTERFACE_MODE_GMII)
366 goto unsupported;
367
368 phylink_set(mask, 1000baseT_Full);
369 phylink_set(mask, 1000baseT_Half);
370 break;
371 case 1:
372 case 2:
373 case 3:
374 case 4:
375 case 5:
376 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
377 goto unsupported;
378 break;
379 default:
380 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
381 dev_err(ds->dev, "Unsupported port: %i\n", port);
382 return;
383 }
384
385 phylink_set_port_modes(mask);
386 phylink_set(mask, Pause);
387 phylink_set(mask, Asym_Pause);
388
389 phylink_set(mask, 10baseT_Half);
390 phylink_set(mask, 10baseT_Full);
391 phylink_set(mask, 100baseT_Half);
392 phylink_set(mask, 100baseT_Full);
393
394 bitmap_and(supported, supported, mask,
395 __ETHTOOL_LINK_MODE_MASK_NBITS);
396 bitmap_and(state->advertising, state->advertising, mask,
397 __ETHTOOL_LINK_MODE_MASK_NBITS);
398
399 return;
400
401 unsupported:
402 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
403 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n",
404 state->interface, port);
405 }
406
407 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
408 unsigned int mode,
409 const struct phylink_link_state *state)
410 {
411 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
412 struct regmap *regmap = priv->regmap;
413 int ret;
414
415 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
416 AR9331_SW_PORT_STATUS_LINK_EN |
417 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
418 if (ret)
419 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
420 }
421
422 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
423 unsigned int mode,
424 phy_interface_t interface)
425 {
426 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
427 struct regmap *regmap = priv->regmap;
428 int ret;
429
430 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
431 AR9331_SW_PORT_STATUS_MAC_MASK, 0);
432 if (ret)
433 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
434 }
435
436 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
437 unsigned int mode,
438 phy_interface_t interface,
439 struct phy_device *phydev,
440 int speed, int duplex,
441 bool tx_pause, bool rx_pause)
442 {
443 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
444 struct regmap *regmap = priv->regmap;
445 u32 val;
446 int ret;
447
448 val = AR9331_SW_PORT_STATUS_MAC_MASK;
449 switch (speed) {
450 case SPEED_1000:
451 val |= AR9331_SW_PORT_STATUS_SPEED_1000;
452 break;
453 case SPEED_100:
454 val |= AR9331_SW_PORT_STATUS_SPEED_100;
455 break;
456 case SPEED_10:
457 val |= AR9331_SW_PORT_STATUS_SPEED_10;
458 break;
459 default:
460 return;
461 }
462
463 if (duplex)
464 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
465
466 if (tx_pause)
467 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
468
469 if (rx_pause)
470 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
471
472 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
473 AR9331_SW_PORT_STATUS_MAC_MASK |
474 AR9331_SW_PORT_STATUS_LINK_MASK,
475 val);
476 if (ret)
477 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
478 }
479
480 static const struct dsa_switch_ops ar9331_sw_ops = {
481 .get_tag_protocol = ar9331_sw_get_tag_protocol,
482 .setup = ar9331_sw_setup,
483 .port_disable = ar9331_sw_port_disable,
484 .phylink_validate = ar9331_sw_phylink_validate,
485 .phylink_mac_config = ar9331_sw_phylink_mac_config,
486 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down,
487 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up,
488 };
489
490 static irqreturn_t ar9331_sw_irq(int irq, void *data)
491 {
492 struct ar9331_sw_priv *priv = data;
493 struct regmap *regmap = priv->regmap;
494 u32 stat;
495 int ret;
496
497 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
498 if (ret) {
499 dev_err(priv->dev, "can't read interrupt status\n");
500 return IRQ_NONE;
501 }
502
503 if (!stat)
504 return IRQ_NONE;
505
506 if (stat & AR9331_SW_GINT_PHY_INT) {
507 int child_irq;
508
509 child_irq = irq_find_mapping(priv->irqdomain, 0);
510 handle_nested_irq(child_irq);
511 }
512
513 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
514 if (ret) {
515 dev_err(priv->dev, "can't write interrupt status\n");
516 return IRQ_NONE;
517 }
518
519 return IRQ_HANDLED;
520 }
521
522 static void ar9331_sw_mask_irq(struct irq_data *d)
523 {
524 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
525
526 priv->irq_mask = 0;
527 }
528
529 static void ar9331_sw_unmask_irq(struct irq_data *d)
530 {
531 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
532
533 priv->irq_mask = AR9331_SW_GINT_PHY_INT;
534 }
535
536 static void ar9331_sw_irq_bus_lock(struct irq_data *d)
537 {
538 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
539
540 mutex_lock(&priv->lock_irq);
541 }
542
543 static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
544 {
545 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
546 struct regmap *regmap = priv->regmap;
547 int ret;
548
549 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
550 AR9331_SW_GINT_PHY_INT, priv->irq_mask);
551 if (ret)
552 dev_err(priv->dev, "failed to change IRQ mask\n");
553
554 mutex_unlock(&priv->lock_irq);
555 }
556
557 static struct irq_chip ar9331_sw_irq_chip = {
558 .name = AR9331_SW_NAME,
559 .irq_mask = ar9331_sw_mask_irq,
560 .irq_unmask = ar9331_sw_unmask_irq,
561 .irq_bus_lock = ar9331_sw_irq_bus_lock,
562 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
563 };
564
565 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
566 irq_hw_number_t hwirq)
567 {
568 irq_set_chip_data(irq, domain->host_data);
569 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
570 irq_set_nested_thread(irq, 1);
571 irq_set_noprobe(irq);
572
573 return 0;
574 }
575
576 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
577 {
578 irq_set_nested_thread(irq, 0);
579 irq_set_chip_and_handler(irq, NULL, NULL);
580 irq_set_chip_data(irq, NULL);
581 }
582
583 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
584 .map = ar9331_sw_irq_map,
585 .unmap = ar9331_sw_irq_unmap,
586 .xlate = irq_domain_xlate_onecell,
587 };
588
589 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
590 {
591 struct device_node *np = priv->dev->of_node;
592 struct device *dev = priv->dev;
593 int ret, irq;
594
595 irq = of_irq_get(np, 0);
596 if (irq <= 0) {
597 dev_err(dev, "failed to get parent IRQ\n");
598 return irq ? irq : -EINVAL;
599 }
600
601 mutex_init(&priv->lock_irq);
602 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
603 IRQF_ONESHOT, AR9331_SW_NAME, priv);
604 if (ret) {
605 dev_err(dev, "unable to request irq: %d\n", ret);
606 return ret;
607 }
608
609 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
610 priv);
611 if (!priv->irqdomain) {
612 dev_err(dev, "failed to create IRQ domain\n");
613 return -EINVAL;
614 }
615
616 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
617
618 return 0;
619 }
620
621 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
622 {
623 u8 r, p;
624
625 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
626 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
627 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
628
629 return mdiobus_write(sbus, p, r, val);
630 }
631
632 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
633 {
634 u8 r, p;
635
636 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
637 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
638 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
639
640 return mdiobus_read(sbus, p, r);
641 }
642
643 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
644 void *val_buf, size_t val_len)
645 {
646 struct ar9331_sw_priv *priv = ctx;
647 struct mii_bus *sbus = priv->sbus;
648 u32 reg = *(u32 *)reg_buf;
649 int ret;
650
651 if (reg == AR9331_SW_REG_PAGE) {
652 /* We cannot read the page selector register from hardware and
653 * we cache its value in regmap. Return all bits set here,
654 * that regmap will always write the page on first use.
655 */
656 *(u32 *)val_buf = GENMASK(9, 0);
657 return 0;
658 }
659
660 ret = __ar9331_mdio_read(sbus, reg);
661 if (ret < 0)
662 goto error;
663
664 *(u32 *)val_buf = ret;
665 ret = __ar9331_mdio_read(sbus, reg + 2);
666 if (ret < 0)
667 goto error;
668
669 *(u32 *)val_buf |= ret << 16;
670
671 return 0;
672 error:
673 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
674 return ret;
675 }
676
677 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
678 {
679 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
680 struct mii_bus *sbus = priv->sbus;
681 int ret;
682
683 if (reg == AR9331_SW_REG_PAGE) {
684 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
685 0, val);
686 if (ret < 0)
687 goto error;
688
689 return 0;
690 }
691
692 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
693 if (ret < 0)
694 goto error;
695
696 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
697 val >> 16);
698 if (ret < 0)
699 goto error;
700
701 return 0;
702 error:
703 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
704 return ret;
705 }
706
707 static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
708 {
709 u32 reg = *(u32 *)data;
710 u32 val = *((u32 *)data + 1);
711
712 return ar9331_mdio_write(context, reg, val);
713 }
714
715 static const struct regmap_range ar9331_valid_regs[] = {
716 regmap_reg_range(0x0, 0x0),
717 regmap_reg_range(0x10, 0x14),
718 regmap_reg_range(0x20, 0x24),
719 regmap_reg_range(0x2c, 0x30),
720 regmap_reg_range(0x40, 0x44),
721 regmap_reg_range(0x50, 0x78),
722 regmap_reg_range(0x80, 0x98),
723
724 regmap_reg_range(0x100, 0x120),
725 regmap_reg_range(0x200, 0x220),
726 regmap_reg_range(0x300, 0x320),
727 regmap_reg_range(0x400, 0x420),
728 regmap_reg_range(0x500, 0x520),
729 regmap_reg_range(0x600, 0x620),
730
731 regmap_reg_range(0x20000, 0x200a4),
732 regmap_reg_range(0x20100, 0x201a4),
733 regmap_reg_range(0x20200, 0x202a4),
734 regmap_reg_range(0x20300, 0x203a4),
735 regmap_reg_range(0x20400, 0x204a4),
736 regmap_reg_range(0x20500, 0x205a4),
737
738 /* dummy page selector reg */
739 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
740 };
741
742 static const struct regmap_range ar9331_nonvolatile_regs[] = {
743 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
744 };
745
746 static const struct regmap_range_cfg ar9331_regmap_range[] = {
747 {
748 .selector_reg = AR9331_SW_REG_PAGE,
749 .selector_mask = GENMASK(9, 0),
750 .selector_shift = 0,
751
752 .window_start = 0,
753 .window_len = 512,
754
755 .range_min = 0,
756 .range_max = AR9331_SW_REG_PAGE - 4,
757 },
758 };
759
760 static const struct regmap_access_table ar9331_register_set = {
761 .yes_ranges = ar9331_valid_regs,
762 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
763 };
764
765 static const struct regmap_access_table ar9331_volatile_set = {
766 .no_ranges = ar9331_nonvolatile_regs,
767 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
768 };
769
770 static const struct regmap_config ar9331_mdio_regmap_config = {
771 .reg_bits = 32,
772 .val_bits = 32,
773 .reg_stride = 4,
774 .max_register = AR9331_SW_REG_PAGE,
775
776 .ranges = ar9331_regmap_range,
777 .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
778
779 .volatile_table = &ar9331_volatile_set,
780 .wr_table = &ar9331_register_set,
781 .rd_table = &ar9331_register_set,
782
783 .cache_type = REGCACHE_RBTREE,
784 };
785
786 static struct regmap_bus ar9331_sw_bus = {
787 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
788 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
789 .read = ar9331_mdio_read,
790 .write = ar9331_sw_bus_write,
791 .max_raw_read = 4,
792 .max_raw_write = 4,
793 };
794
795 static int ar9331_sw_probe(struct mdio_device *mdiodev)
796 {
797 struct ar9331_sw_priv *priv;
798 struct dsa_switch *ds;
799 int ret;
800
801 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
802 if (!priv)
803 return -ENOMEM;
804
805 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
806 &ar9331_mdio_regmap_config);
807 if (IS_ERR(priv->regmap)) {
808 ret = PTR_ERR(priv->regmap);
809 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
810 return ret;
811 }
812
813 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
814 if (IS_ERR(priv->sw_reset)) {
815 dev_err(&mdiodev->dev, "missing switch reset\n");
816 return PTR_ERR(priv->sw_reset);
817 }
818
819 priv->sbus = mdiodev->bus;
820 priv->dev = &mdiodev->dev;
821
822 ret = ar9331_sw_irq_init(priv);
823 if (ret)
824 return ret;
825
826 ds = &priv->ds;
827 ds->dev = &mdiodev->dev;
828 ds->num_ports = AR9331_SW_PORTS;
829 ds->priv = priv;
830 priv->ops = ar9331_sw_ops;
831 ds->ops = &priv->ops;
832 dev_set_drvdata(&mdiodev->dev, priv);
833
834 ret = dsa_register_switch(ds);
835 if (ret)
836 goto err_remove_irq;
837
838 return 0;
839
840 err_remove_irq:
841 irq_domain_remove(priv->irqdomain);
842
843 return ret;
844 }
845
846 static void ar9331_sw_remove(struct mdio_device *mdiodev)
847 {
848 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
849
850 irq_domain_remove(priv->irqdomain);
851 mdiobus_unregister(priv->mbus);
852 dsa_unregister_switch(&priv->ds);
853
854 reset_control_assert(priv->sw_reset);
855 }
856
857 static const struct of_device_id ar9331_sw_of_match[] = {
858 { .compatible = "qca,ar9331-switch" },
859 { },
860 };
861
862 static struct mdio_driver ar9331_sw_mdio_driver = {
863 .probe = ar9331_sw_probe,
864 .remove = ar9331_sw_remove,
865 .mdiodrv.driver = {
866 .name = AR9331_SW_NAME,
867 .of_match_table = ar9331_sw_of_match,
868 },
869 };
870
871 mdio_module_driver(ar9331_sw_mdio_driver);
872
873 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
874 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
875 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support