drivers/net/dsa/sja1105/sja1105.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5 #ifndef _SJA1105_H
   6 #define _SJA1105_H
   7
   8 #include <linux/ptp_clock_kernel.h>
   9 #include <linux/timecounter.h>
  10 #include <linux/dsa/sja1105.h>
  11 #include <linux/dsa/8021q.h>
  12 #include <net/dsa.h>
  13 #include <linux/mutex.h>
  14 #include "sja1105_static_config.h"
  15
  16 #define SJA1105_NUM_PORTS               5
  17 #define SJA1105_NUM_TC                  8
  18 #define SJA1105ET_FDB_BIN_SIZE          4
  19 /* The hardware value is in multiples of 10 ms.
  20  * The passed parameter is in multiples of 1 ms.
  21  */
  22 #define SJA1105_AGEING_TIME_MS(ms)      ((ms) / 10)
  23 #define SJA1105_NUM_L2_POLICERS         45
  24
  25 typedef enum {
  26         SPI_READ = 0,
  27         SPI_WRITE = 1,
  28 } sja1105_spi_rw_mode_t;
  29
  30 #include "sja1105_tas.h"
  31 #include "sja1105_ptp.h"
  32
  33 /* Keeps the different addresses between E/T and P/Q/R/S */
  34 struct sja1105_regs {
  35         u64 device_id;
  36         u64 prod_id;
  37         u64 status;
  38         u64 port_control;
  39         u64 rgu;
  40         u64 vl_status;
  41         u64 config;
  42         u64 sgmii;
  43         u64 rmii_pll1;
  44         u64 ptppinst;
  45         u64 ptppindur;
  46         u64 ptp_control;
  47         u64 ptpclkval;
  48         u64 ptpclkrate;
  49         u64 ptpclkcorp;
  50         u64 ptpsyncts;
  51         u64 ptpschtm;
  52         u64 ptpegr_ts[SJA1105_NUM_PORTS];
  53         u64 pad_mii_tx[SJA1105_NUM_PORTS];
  54         u64 pad_mii_rx[SJA1105_NUM_PORTS];
  55         u64 pad_mii_id[SJA1105_NUM_PORTS];
  56         u64 cgu_idiv[SJA1105_NUM_PORTS];
  57         u64 mii_tx_clk[SJA1105_NUM_PORTS];
  58         u64 mii_rx_clk[SJA1105_NUM_PORTS];
  59         u64 mii_ext_tx_clk[SJA1105_NUM_PORTS];
  60         u64 mii_ext_rx_clk[SJA1105_NUM_PORTS];
  61         u64 rgmii_tx_clk[SJA1105_NUM_PORTS];
  62         u64 rmii_ref_clk[SJA1105_NUM_PORTS];
  63         u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS];
  64         u64 mac[SJA1105_NUM_PORTS];
  65         u64 mac_hl1[SJA1105_NUM_PORTS];
  66         u64 mac_hl2[SJA1105_NUM_PORTS];
  67         u64 ether_stats[SJA1105_NUM_PORTS];
  68         u64 qlevel[SJA1105_NUM_PORTS];
  69 };
  70
  71 struct sja1105_info {
  72         u64 device_id;
  73         /* Needed for distinction between P and R, and between Q and S
  74          * (since the parts with/without SGMII share the same
  75          * switch core and device_id)
  76          */
  77         u64 part_no;
  78         /* E/T and P/Q/R/S have partial timestamps of different sizes.
  79          * They must be reconstructed on both families anyway to get the full
  80          * 64-bit values back.
  81          */
  82         int ptp_ts_bits;
  83         /* Also SPI commands are of different sizes to retrieve
  84          * the egress timestamps.
  85          */
  86         int ptpegr_ts_bytes;
  87         int num_cbs_shapers;
  88         const struct sja1105_dynamic_table_ops *dyn_ops;
  89         const struct sja1105_table_ops *static_ops;
  90         const struct sja1105_regs *regs;
  91         /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag
  92          * from double-tagged frames. E/T will pop it only when it's equal to
  93          * TPID from the General Parameters Table, while P/Q/R/S will only
  94          * pop it when it's equal to TPID2.
  95          */
  96         u16 qinq_tpid;
  97         int (*reset_cmd)(struct dsa_switch *ds);
  98         int (*setup_rgmii_delay)(const void *ctx, int port);
  99         /* Prototypes from include/net/dsa.h */
 100         int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
 101                            const unsigned char *addr, u16 vid);
 102         int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
 103                            const unsigned char *addr, u16 vid);
 104         void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
 105                                 enum packing_op op);
 106         const char *name;
 107 };
 108
 109 enum sja1105_key_type {
 110         SJA1105_KEY_BCAST,
 111         SJA1105_KEY_TC,
 112         SJA1105_KEY_VLAN_UNAWARE_VL,
 113         SJA1105_KEY_VLAN_AWARE_VL,
 114 };
 115
 116 struct sja1105_key {
 117         enum sja1105_key_type type;
 118
 119         union {
 120                 /* SJA1105_KEY_TC */
 121                 struct {
 122                         int pcp;
 123                 } tc;
 124
 125                 /* SJA1105_KEY_VLAN_UNAWARE_VL */
 126                 /* SJA1105_KEY_VLAN_AWARE_VL */
 127                 struct {
 128                         u64 dmac;
 129                         u16 vid;
 130                         u16 pcp;
 131                 } vl;
 132         };
 133 };
 134
 135 enum sja1105_rule_type {
 136         SJA1105_RULE_BCAST_POLICER,
 137         SJA1105_RULE_TC_POLICER,
 138         SJA1105_RULE_VL,
 139 };
 140
 141 enum sja1105_vl_type {
 142         SJA1105_VL_NONCRITICAL,
 143         SJA1105_VL_RATE_CONSTRAINED,
 144         SJA1105_VL_TIME_TRIGGERED,
 145 };
 146
 147 struct sja1105_rule {
 148         struct list_head list;
 149         unsigned long cookie;
 150         unsigned long port_mask;
 151         struct sja1105_key key;
 152         enum sja1105_rule_type type;
 153
 154         /* Action */
 155         union {
 156                 /* SJA1105_RULE_BCAST_POLICER */
 157                 struct {
 158                         int sharindx;
 159                 } bcast_pol;
 160
 161                 /* SJA1105_RULE_TC_POLICER */
 162                 struct {
 163                         int sharindx;
 164                 } tc_pol;
 165
 166                 /* SJA1105_RULE_VL */
 167                 struct {
 168                         enum sja1105_vl_type type;
 169                         unsigned long destports;
 170                         int sharindx;
 171                         int maxlen;
 172                         int ipv;
 173                         u64 base_time;
 174                         u64 cycle_time;
 175                         int num_entries;
 176                         struct action_gate_entry *entries;
 177                         struct flow_stats stats;
 178                 } vl;
 179         };
 180 };
 181
 182 struct sja1105_flow_block {
 183         struct list_head rules;
 184         bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
 185         int num_virtual_links;
 186 };
 187
 188 struct sja1105_bridge_vlan {
 189         struct list_head list;
 190         int port;
 191         u16 vid;
 192         bool pvid;
 193         bool untagged;
 194 };
 195
 196 enum sja1105_vlan_state {
 197         SJA1105_VLAN_UNAWARE,
 198         SJA1105_VLAN_BEST_EFFORT,
 199         SJA1105_VLAN_FILTERING_FULL,
 200 };
 201
 202 struct sja1105_private {
 203         struct sja1105_static_config static_config;
 204         bool rgmii_rx_delay[SJA1105_NUM_PORTS];
 205         bool rgmii_tx_delay[SJA1105_NUM_PORTS];
 206         bool best_effort_vlan_filtering;
 207         const struct sja1105_info *info;
 208         struct gpio_desc *reset_gpio;
 209         struct spi_device *spidev;
 210         struct dsa_switch *ds;
 211         struct list_head dsa_8021q_vlans;
 212         struct list_head bridge_vlans;
 213         struct sja1105_flow_block flow_block;
 214         struct sja1105_port ports[SJA1105_NUM_PORTS];
 215         /* Serializes transmission of management frames so that
 216          * the switch doesn't confuse them with one another.
 217          */
 218         struct mutex mgmt_lock;
 219         struct dsa_8021q_context *dsa_8021q_ctx;
 220         enum sja1105_vlan_state vlan_state;
 221         struct devlink_region **regions;
 222         struct sja1105_cbs_entry *cbs;
 223         struct sja1105_tagger_data tagger_data;
 224         struct sja1105_ptp_data ptp_data;
 225         struct sja1105_tas_data tas_data;
 226 };
 227
 228 #include "sja1105_dynamic_config.h"
 229
 230 struct sja1105_spi_message {
 231         u64 access;
 232         u64 read_count;
 233         u64 address;
 234 };
 235
 236 /* From sja1105_main.c */
 237 enum sja1105_reset_reason {
 238         SJA1105_VLAN_FILTERING = 0,
 239         SJA1105_RX_HWTSTAMPING,
 240         SJA1105_AGEING_TIME,
 241         SJA1105_SCHEDULING,
 242         SJA1105_BEST_EFFORT_POLICING,
 243         SJA1105_VIRTUAL_LINKS,
 244 };
 245
 246 int sja1105_static_config_reload(struct sja1105_private *priv,
 247                                  enum sja1105_reset_reason reason);
 248 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
 249                            struct switchdev_trans *trans);
 250 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
 251
 252 /* From sja1105_devlink.c */
 253 int sja1105_devlink_setup(struct dsa_switch *ds);
 254 void sja1105_devlink_teardown(struct dsa_switch *ds);
 255 int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id,
 256                               struct devlink_param_gset_ctx *ctx);
 257 int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id,
 258                               struct devlink_param_gset_ctx *ctx);
 259 int sja1105_devlink_info_get(struct dsa_switch *ds,
 260                              struct devlink_info_req *req,
 261                              struct netlink_ext_ack *extack);
 262
 263 /* From sja1105_spi.c */
 264 int sja1105_xfer_buf(const struct sja1105_private *priv,
 265                      sja1105_spi_rw_mode_t rw, u64 reg_addr,
 266                      u8 *buf, size_t len);
 267 int sja1105_xfer_u32(const struct sja1105_private *priv,
 268                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
 269                      struct ptp_system_timestamp *ptp_sts);
 270 int sja1105_xfer_u64(const struct sja1105_private *priv,
 271                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
 272                      struct ptp_system_timestamp *ptp_sts);
 273 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
 274                                          void *config_buf, int buf_len);
 275 int sja1105_static_config_upload(struct sja1105_private *priv);
 276 int sja1105_inhibit_tx(const struct sja1105_private *priv,
 277                        unsigned long port_bitmap, bool tx_inhibited);
 278
 279 extern const struct sja1105_info sja1105e_info;
 280 extern const struct sja1105_info sja1105t_info;
 281 extern const struct sja1105_info sja1105p_info;
 282 extern const struct sja1105_info sja1105q_info;
 283 extern const struct sja1105_info sja1105r_info;
 284 extern const struct sja1105_info sja1105s_info;
 285
 286 /* From sja1105_clocking.c */
 287
 288 typedef enum {
 289         XMII_MAC = 0,
 290         XMII_PHY = 1,
 291 } sja1105_mii_role_t;
 292
 293 typedef enum {
 294         XMII_MODE_MII           = 0,
 295         XMII_MODE_RMII          = 1,
 296         XMII_MODE_RGMII         = 2,
 297         XMII_MODE_SGMII         = 3,
 298 } sja1105_phy_interface_t;
 299
 300 typedef enum {
 301         SJA1105_SPEED_10MBPS    = 3,
 302         SJA1105_SPEED_100MBPS   = 2,
 303         SJA1105_SPEED_1000MBPS  = 1,
 304         SJA1105_SPEED_AUTO      = 0,
 305 } sja1105_speed_t;
 306
 307 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
 308 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
 309 int sja1105_clocking_setup(struct sja1105_private *priv);
 310
 311 /* From sja1105_ethtool.c */
 312 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
 313 void sja1105_get_strings(struct dsa_switch *ds, int port,
 314                          u32 stringset, u8 *data);
 315 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
 316
 317 /* From sja1105_dynamic_config.c */
 318 int sja1105_dynamic_config_read(struct sja1105_private *priv,
 319                                 enum sja1105_blk_idx blk_idx,
 320                                 int index, void *entry);
 321 int sja1105_dynamic_config_write(struct sja1105_private *priv,
 322                                  enum sja1105_blk_idx blk_idx,
 323                                  int index, void *entry, bool keep);
 324
 325 enum sja1105_iotag {
 326         SJA1105_C_TAG = 0, /* Inner VLAN header */
 327         SJA1105_S_TAG = 1, /* Outer VLAN header */
 328 };
 329
 330 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
 331 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
 332                       const unsigned char *addr, u16 vid);
 333 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
 334                       const unsigned char *addr, u16 vid);
 335 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
 336                         const unsigned char *addr, u16 vid);
 337 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
 338                         const unsigned char *addr, u16 vid);
 339
 340 /* From sja1105_flower.c */
 341 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
 342                            struct flow_cls_offload *cls, bool ingress);
 343 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
 344                            struct flow_cls_offload *cls, bool ingress);
 345 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
 346                              struct flow_cls_offload *cls, bool ingress);
 347 void sja1105_flower_setup(struct dsa_switch *ds);
 348 void sja1105_flower_teardown(struct dsa_switch *ds);
 349 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
 350                                        unsigned long cookie);
 351
 352 #endif