drivers/net/dsa/sja1105/sja1105_clocking.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright (c) 2016-2018, NXP Semiconductors
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5 #include <linux/packing.h>
   6 #include "sja1105.h"
   7
   8 #define SJA1105_SIZE_CGU_CMD    4
   9
  10 /* Common structure for CFG_PAD_MIIx_RX and CFG_PAD_MIIx_TX */
  11 struct sja1105_cfg_pad_mii {
  12         u64 d32_os;
  13         u64 d32_ih;
  14         u64 d32_ipud;
  15         u64 d10_ih;
  16         u64 d10_os;
  17         u64 d10_ipud;
  18         u64 ctrl_os;
  19         u64 ctrl_ih;
  20         u64 ctrl_ipud;
  21         u64 clk_os;
  22         u64 clk_ih;
  23         u64 clk_ipud;
  24 };
  25
  26 struct sja1105_cfg_pad_mii_id {
  27         u64 rxc_stable_ovr;
  28         u64 rxc_delay;
  29         u64 rxc_bypass;
  30         u64 rxc_pd;
  31         u64 txc_stable_ovr;
  32         u64 txc_delay;
  33         u64 txc_bypass;
  34         u64 txc_pd;
  35 };
  36
  37 /* UM10944 Table 82.
  38  * IDIV_0_C to IDIV_4_C control registers
  39  * (addr. 10000Bh to 10000Fh)
  40  */
  41 struct sja1105_cgu_idiv {
  42         u64 clksrc;
  43         u64 autoblock;
  44         u64 idiv;
  45         u64 pd;
  46 };
  47
  48 /* PLL_1_C control register
  49  *
  50  * SJA1105 E/T: UM10944 Table 81 (address 10000Ah)
  51  * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah)
  52  */
  53 struct sja1105_cgu_pll_ctrl {
  54         u64 pllclksrc;
  55         u64 msel;
  56         u64 autoblock;
  57         u64 psel;
  58         u64 direct;
  59         u64 fbsel;
  60         u64 bypass;
  61         u64 pd;
  62 };
  63
  64 enum {
  65         CLKSRC_MII0_TX_CLK      = 0x00,
  66         CLKSRC_MII0_RX_CLK      = 0x01,
  67         CLKSRC_MII1_TX_CLK      = 0x02,
  68         CLKSRC_MII1_RX_CLK      = 0x03,
  69         CLKSRC_MII2_TX_CLK      = 0x04,
  70         CLKSRC_MII2_RX_CLK      = 0x05,
  71         CLKSRC_MII3_TX_CLK      = 0x06,
  72         CLKSRC_MII3_RX_CLK      = 0x07,
  73         CLKSRC_MII4_TX_CLK      = 0x08,
  74         CLKSRC_MII4_RX_CLK      = 0x09,
  75         CLKSRC_PLL0             = 0x0B,
  76         CLKSRC_PLL1             = 0x0E,
  77         CLKSRC_IDIV0            = 0x11,
  78         CLKSRC_IDIV1            = 0x12,
  79         CLKSRC_IDIV2            = 0x13,
  80         CLKSRC_IDIV3            = 0x14,
  81         CLKSRC_IDIV4            = 0x15,
  82 };
  83
  84 /* UM10944 Table 83.
  85  * MIIx clock control registers 1 to 30
  86  * (addresses 100013h to 100035h)
  87  */
  88 struct sja1105_cgu_mii_ctrl {
  89         u64 clksrc;
  90         u64 autoblock;
  91         u64 pd;
  92 };
  93
  94 static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv,
  95                                      enum packing_op op)
  96 {
  97         const int size = 4;
  98
  99         sja1105_packing(buf, &idiv->clksrc,    28, 24, size, op);
 100         sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op);
 101         sja1105_packing(buf, &idiv->idiv,       5,  2, size, op);
 102         sja1105_packing(buf, &idiv->pd,         0,  0, size, op);
 103 }
 104
 105 static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
 106                                    bool enabled, int factor)
 107 {
 108         const struct sja1105_regs *regs = priv->info->regs;
 109         struct device *dev = priv->ds->dev;
 110         struct sja1105_cgu_idiv idiv;
 111         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 112
 113         if (enabled && factor != 1 && factor != 10) {
 114                 dev_err(dev, "idiv factor must be 1 or 10\n");
 115                 return -ERANGE;
 116         }
 117
 118         /* Payload for packed_buf */
 119         idiv.clksrc    = 0x0A;            /* 25MHz */
 120         idiv.autoblock = 1;               /* Block clk automatically */
 121         idiv.idiv      = factor - 1;      /* Divide by 1 or 10 */
 122         idiv.pd        = enabled ? 0 : 1; /* Power down? */
 123         sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK);
 124
 125         return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port],
 126                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 127 }
 128
 129 static void
 130 sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd,
 131                                 enum packing_op op)
 132 {
 133         const int size = 4;
 134
 135         sja1105_packing(buf, &cmd->clksrc,    28, 24, size, op);
 136         sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
 137         sja1105_packing(buf, &cmd->pd,         0,  0, size, op);
 138 }
 139
 140 static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
 141                                          int port, sja1105_mii_role_t role)
 142 {
 143         const struct sja1105_regs *regs = priv->info->regs;
 144         struct sja1105_cgu_mii_ctrl mii_tx_clk;
 145         const int mac_clk_sources[] = {
 146                 CLKSRC_MII0_TX_CLK,
 147                 CLKSRC_MII1_TX_CLK,
 148                 CLKSRC_MII2_TX_CLK,
 149                 CLKSRC_MII3_TX_CLK,
 150                 CLKSRC_MII4_TX_CLK,
 151         };
 152         const int phy_clk_sources[] = {
 153                 CLKSRC_IDIV0,
 154                 CLKSRC_IDIV1,
 155                 CLKSRC_IDIV2,
 156                 CLKSRC_IDIV3,
 157                 CLKSRC_IDIV4,
 158         };
 159         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 160         int clksrc;
 161
 162         if (role == XMII_MAC)
 163                 clksrc = mac_clk_sources[port];
 164         else
 165                 clksrc = phy_clk_sources[port];
 166
 167         /* Payload for packed_buf */
 168         mii_tx_clk.clksrc    = clksrc;
 169         mii_tx_clk.autoblock = 1;  /* Autoblock clk while changing clksrc */
 170         mii_tx_clk.pd        = 0;  /* Power Down off => enabled */
 171         sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK);
 172
 173         return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port],
 174                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 175 }
 176
 177 static int
 178 sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
 179 {
 180         const struct sja1105_regs *regs = priv->info->regs;
 181         struct sja1105_cgu_mii_ctrl mii_rx_clk;
 182         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 183         const int clk_sources[] = {
 184                 CLKSRC_MII0_RX_CLK,
 185                 CLKSRC_MII1_RX_CLK,
 186                 CLKSRC_MII2_RX_CLK,
 187                 CLKSRC_MII3_RX_CLK,
 188                 CLKSRC_MII4_RX_CLK,
 189         };
 190
 191         /* Payload for packed_buf */
 192         mii_rx_clk.clksrc    = clk_sources[port];
 193         mii_rx_clk.autoblock = 1;  /* Autoblock clk while changing clksrc */
 194         mii_rx_clk.pd        = 0;  /* Power Down off => enabled */
 195         sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK);
 196
 197         return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port],
 198                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 199 }
 200
 201 static int
 202 sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
 203 {
 204         const struct sja1105_regs *regs = priv->info->regs;
 205         struct sja1105_cgu_mii_ctrl mii_ext_tx_clk;
 206         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 207         const int clk_sources[] = {
 208                 CLKSRC_IDIV0,
 209                 CLKSRC_IDIV1,
 210                 CLKSRC_IDIV2,
 211                 CLKSRC_IDIV3,
 212                 CLKSRC_IDIV4,
 213         };
 214
 215         /* Payload for packed_buf */
 216         mii_ext_tx_clk.clksrc    = clk_sources[port];
 217         mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
 218         mii_ext_tx_clk.pd        = 0; /* Power Down off => enabled */
 219         sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK);
 220
 221         return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port],
 222                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 223 }
 224
 225 static int
 226 sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
 227 {
 228         const struct sja1105_regs *regs = priv->info->regs;
 229         struct sja1105_cgu_mii_ctrl mii_ext_rx_clk;
 230         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 231         const int clk_sources[] = {
 232                 CLKSRC_IDIV0,
 233                 CLKSRC_IDIV1,
 234                 CLKSRC_IDIV2,
 235                 CLKSRC_IDIV3,
 236                 CLKSRC_IDIV4,
 237         };
 238
 239         /* Payload for packed_buf */
 240         mii_ext_rx_clk.clksrc    = clk_sources[port];
 241         mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
 242         mii_ext_rx_clk.pd        = 0; /* Power Down off => enabled */
 243         sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK);
 244
 245         return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port],
 246                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 247 }
 248
 249 static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port,
 250                                       sja1105_mii_role_t role)
 251 {
 252         struct device *dev = priv->ds->dev;
 253         int rc;
 254
 255         dev_dbg(dev, "Configuring MII-%s clocking\n",
 256                 (role == XMII_MAC) ? "MAC" : "PHY");
 257         /* If role is MAC, disable IDIV
 258          * If role is PHY, enable IDIV and configure for 1/1 divider
 259          */
 260         rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1);
 261         if (rc < 0)
 262                 return rc;
 263
 264         /* Configure CLKSRC of MII_TX_CLK_n
 265          *   * If role is MAC, select TX_CLK_n
 266          *   * If role is PHY, select IDIV_n
 267          */
 268         rc = sja1105_cgu_mii_tx_clk_config(priv, port, role);
 269         if (rc < 0)
 270                 return rc;
 271
 272         /* Configure CLKSRC of MII_RX_CLK_n
 273          * Select RX_CLK_n
 274          */
 275         rc = sja1105_cgu_mii_rx_clk_config(priv, port);
 276         if (rc < 0)
 277                 return rc;
 278
 279         if (role == XMII_PHY) {
 280                 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */
 281
 282                 /* Configure CLKSRC of EXT_TX_CLK_n
 283                  * Select IDIV_n
 284                  */
 285                 rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port);
 286                 if (rc < 0)
 287                         return rc;
 288
 289                 /* Configure CLKSRC of EXT_RX_CLK_n
 290                  * Select IDIV_n
 291                  */
 292                 rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port);
 293                 if (rc < 0)
 294                         return rc;
 295         }
 296         return 0;
 297 }
 298
 299 static void
 300 sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd,
 301                                 enum packing_op op)
 302 {
 303         const int size = 4;
 304
 305         sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op);
 306         sja1105_packing(buf, &cmd->msel,      23, 16, size, op);
 307         sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
 308         sja1105_packing(buf, &cmd->psel,       9,  8, size, op);
 309         sja1105_packing(buf, &cmd->direct,     7,  7, size, op);
 310         sja1105_packing(buf, &cmd->fbsel,      6,  6, size, op);
 311         sja1105_packing(buf, &cmd->bypass,     1,  1, size, op);
 312         sja1105_packing(buf, &cmd->pd,         0,  0, size, op);
 313 }
 314
 315 static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
 316                                            int port, sja1105_speed_t speed)
 317 {
 318         const struct sja1105_regs *regs = priv->info->regs;
 319         struct sja1105_cgu_mii_ctrl txc;
 320         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 321         int clksrc;
 322
 323         if (speed == SJA1105_SPEED_1000MBPS) {
 324                 clksrc = CLKSRC_PLL0;
 325         } else {
 326                 int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2,
 327                                      CLKSRC_IDIV3, CLKSRC_IDIV4};
 328                 clksrc = clk_sources[port];
 329         }
 330
 331         /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */
 332         txc.clksrc = clksrc;
 333         /* Autoblock clk while changing clksrc */
 334         txc.autoblock = 1;
 335         /* Power Down off => enabled */
 336         txc.pd = 0;
 337         sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK);
 338
 339         return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port],
 340                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 341 }
 342
 343 /* AGU */
 344 static void
 345 sja1105_cfg_pad_mii_packing(void *buf, struct sja1105_cfg_pad_mii *cmd,
 346                             enum packing_op op)
 347 {
 348         const int size = 4;
 349
 350         sja1105_packing(buf, &cmd->d32_os,   28, 27, size, op);
 351         sja1105_packing(buf, &cmd->d32_ih,   26, 26, size, op);
 352         sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op);
 353         sja1105_packing(buf, &cmd->d10_os,   20, 19, size, op);
 354         sja1105_packing(buf, &cmd->d10_ih,   18, 18, size, op);
 355         sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op);
 356         sja1105_packing(buf, &cmd->ctrl_os,  12, 11, size, op);
 357         sja1105_packing(buf, &cmd->ctrl_ih,  10, 10, size, op);
 358         sja1105_packing(buf, &cmd->ctrl_ipud, 9,  8, size, op);
 359         sja1105_packing(buf, &cmd->clk_os,    4,  3, size, op);
 360         sja1105_packing(buf, &cmd->clk_ih,    2,  2, size, op);
 361         sja1105_packing(buf, &cmd->clk_ipud,  1,  0, size, op);
 362 }
 363
 364 static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
 365                                            int port)
 366 {
 367         const struct sja1105_regs *regs = priv->info->regs;
 368         struct sja1105_cfg_pad_mii pad_mii_tx = {0};
 369         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 370
 371         /* Payload */
 372         pad_mii_tx.d32_os    = 3; /* TXD[3:2] output stage: */
 373                                   /*          high noise/high speed */
 374         pad_mii_tx.d10_os    = 3; /* TXD[1:0] output stage: */
 375                                   /*          high noise/high speed */
 376         pad_mii_tx.d32_ipud  = 2; /* TXD[3:2] input stage: */
 377                                   /*          plain input (default) */
 378         pad_mii_tx.d10_ipud  = 2; /* TXD[1:0] input stage: */
 379                                   /*          plain input (default) */
 380         pad_mii_tx.ctrl_os   = 3; /* TX_CTL / TX_ER output stage */
 381         pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */
 382         pad_mii_tx.clk_os    = 3; /* TX_CLK output stage */
 383         pad_mii_tx.clk_ih    = 0; /* TX_CLK input hysteresis (default) */
 384         pad_mii_tx.clk_ipud  = 2; /* TX_CLK input stage (default) */
 385         sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_tx, PACK);
 386
 387         return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port],
 388                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 389 }
 390
 391 static int sja1105_cfg_pad_rx_config(struct sja1105_private *priv, int port)
 392 {
 393         const struct sja1105_regs *regs = priv->info->regs;
 394         struct sja1105_cfg_pad_mii pad_mii_rx = {0};
 395         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 396
 397         /* Payload */
 398         pad_mii_rx.d32_ih    = 0; /* RXD[3:2] input stage hysteresis: */
 399                                   /*          non-Schmitt (default) */
 400         pad_mii_rx.d32_ipud  = 2; /* RXD[3:2] input weak pull-up/down */
 401                                   /*          plain input (default) */
 402         pad_mii_rx.d10_ih    = 0; /* RXD[1:0] input stage hysteresis: */
 403                                   /*          non-Schmitt (default) */
 404         pad_mii_rx.d10_ipud  = 2; /* RXD[1:0] input weak pull-up/down */
 405                                   /*          plain input (default) */
 406         pad_mii_rx.ctrl_ih   = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */
 407                                   /* input stage hysteresis: */
 408                                   /* non-Schmitt (default) */
 409         pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */
 410                                   /* input stage weak pull-up/down: */
 411                                   /* pull-down */
 412         pad_mii_rx.clk_os    = 2; /* RX_CLK/RXC output stage: */
 413                                   /* medium noise/fast speed (default) */
 414         pad_mii_rx.clk_ih    = 0; /* RX_CLK/RXC input hysteresis: */
 415                                   /* non-Schmitt (default) */
 416         pad_mii_rx.clk_ipud  = 2; /* RX_CLK/RXC input pull-up/down: */
 417                                   /* plain input (default) */
 418         sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_rx, PACK);
 419
 420         return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port],
 421                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 422 }
 423
 424 static void
 425 sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
 426                                enum packing_op op)
 427 {
 428         const int size = SJA1105_SIZE_CGU_CMD;
 429
 430         sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op);
 431         sja1105_packing(buf, &cmd->rxc_delay,      14, 10, size, op);
 432         sja1105_packing(buf, &cmd->rxc_bypass,      9,  9, size, op);
 433         sja1105_packing(buf, &cmd->rxc_pd,          8,  8, size, op);
 434         sja1105_packing(buf, &cmd->txc_stable_ovr,  7,  7, size, op);
 435         sja1105_packing(buf, &cmd->txc_delay,       6,  2, size, op);
 436         sja1105_packing(buf, &cmd->txc_bypass,      1,  1, size, op);
 437         sja1105_packing(buf, &cmd->txc_pd,          0,  0, size, op);
 438 }
 439
 440 /* Valid range in degrees is an integer between 73.8 and 101.7 */
 441 static u64 sja1105_rgmii_delay(u64 phase)
 442 {
 443         /* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9.
 444          * To avoid floating point operations we'll multiply by 10
 445          * and get 1 decimal point precision.
 446          */
 447         phase *= 10;
 448         return (phase - 738) / 9;
 449 }
 450
 451 /* The RGMII delay setup procedure is 2-step and gets called upon each
 452  * .phylink_mac_config. Both are strategic.
 453  * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
 454  * with recovering from a frequency change of the link partner's RGMII clock.
 455  * The easiest way to recover from this is to temporarily power down the TDL,
 456  * as it will re-lock at the new frequency afterwards.
 457  */
 458 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
 459 {
 460         const struct sja1105_private *priv = ctx;
 461         const struct sja1105_regs *regs = priv->info->regs;
 462         struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
 463         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 464         int rc;
 465
 466         if (priv->rgmii_rx_delay[port])
 467                 pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
 468         if (priv->rgmii_tx_delay[port])
 469                 pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
 470
 471         /* Stage 1: Turn the RGMII delay lines off. */
 472         pad_mii_id.rxc_bypass = 1;
 473         pad_mii_id.rxc_pd = 1;
 474         pad_mii_id.txc_bypass = 1;
 475         pad_mii_id.txc_pd = 1;
 476         sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
 477
 478         rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
 479                               packed_buf, SJA1105_SIZE_CGU_CMD);
 480         if (rc < 0)
 481                 return rc;
 482
 483         /* Stage 2: Turn the RGMII delay lines on. */
 484         if (priv->rgmii_rx_delay[port]) {
 485                 pad_mii_id.rxc_bypass = 0;
 486                 pad_mii_id.rxc_pd = 0;
 487         }
 488         if (priv->rgmii_tx_delay[port]) {
 489                 pad_mii_id.txc_bypass = 0;
 490                 pad_mii_id.txc_pd = 0;
 491         }
 492         sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
 493
 494         return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
 495                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 496 }
 497
 498 static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port,
 499                                         sja1105_mii_role_t role)
 500 {
 501         struct device *dev = priv->ds->dev;
 502         struct sja1105_mac_config_entry *mac;
 503         sja1105_speed_t speed;
 504         int rc;
 505
 506         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
 507         speed = mac[port].speed;
 508
 509         dev_dbg(dev, "Configuring port %d RGMII at speed %dMbps\n",
 510                 port, speed);
 511
 512         switch (speed) {
 513         case SJA1105_SPEED_1000MBPS:
 514                 /* 1000Mbps, IDIV disabled (125 MHz) */
 515                 rc = sja1105_cgu_idiv_config(priv, port, false, 1);
 516                 break;
 517         case SJA1105_SPEED_100MBPS:
 518                 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */
 519                 rc = sja1105_cgu_idiv_config(priv, port, true, 1);
 520                 break;
 521         case SJA1105_SPEED_10MBPS:
 522                 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */
 523                 rc = sja1105_cgu_idiv_config(priv, port, true, 10);
 524                 break;
 525         case SJA1105_SPEED_AUTO:
 526                 /* Skip CGU configuration if there is no speed available
 527                  * (e.g. link is not established yet)
 528                  */
 529                 dev_dbg(dev, "Speed not available, skipping CGU config\n");
 530                 return 0;
 531         default:
 532                 rc = -EINVAL;
 533         }
 534
 535         if (rc < 0) {
 536                 dev_err(dev, "Failed to configure idiv\n");
 537                 return rc;
 538         }
 539         rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed);
 540         if (rc < 0) {
 541                 dev_err(dev, "Failed to configure RGMII Tx clock\n");
 542                 return rc;
 543         }
 544         rc = sja1105_rgmii_cfg_pad_tx_config(priv, port);
 545         if (rc < 0) {
 546                 dev_err(dev, "Failed to configure Tx pad registers\n");
 547                 return rc;
 548         }
 549         if (!priv->info->setup_rgmii_delay)
 550                 return 0;
 551         /* The role has no hardware effect for RGMII. However we use it as
 552          * a proxy for this interface being a MAC-to-MAC connection, with
 553          * the RGMII internal delays needing to be applied by us.
 554          */
 555         if (role == XMII_MAC)
 556                 return 0;
 557
 558         return priv->info->setup_rgmii_delay(priv, port);
 559 }
 560
 561 static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
 562                                            int port)
 563 {
 564         const struct sja1105_regs *regs = priv->info->regs;
 565         struct sja1105_cgu_mii_ctrl ref_clk;
 566         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 567         const int clk_sources[] = {
 568                 CLKSRC_MII0_TX_CLK,
 569                 CLKSRC_MII1_TX_CLK,
 570                 CLKSRC_MII2_TX_CLK,
 571                 CLKSRC_MII3_TX_CLK,
 572                 CLKSRC_MII4_TX_CLK,
 573         };
 574
 575         /* Payload for packed_buf */
 576         ref_clk.clksrc    = clk_sources[port];
 577         ref_clk.autoblock = 1;      /* Autoblock clk while changing clksrc */
 578         ref_clk.pd        = 0;      /* Power Down off => enabled */
 579         sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);
 580
 581         return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port],
 582                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 583 }
 584
 585 static int
 586 sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
 587 {
 588         const struct sja1105_regs *regs = priv->info->regs;
 589         struct sja1105_cgu_mii_ctrl ext_tx_clk;
 590         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 591
 592         /* Payload for packed_buf */
 593         ext_tx_clk.clksrc    = CLKSRC_PLL1;
 594         ext_tx_clk.autoblock = 1;   /* Autoblock clk while changing clksrc */
 595         ext_tx_clk.pd        = 0;   /* Power Down off => enabled */
 596         sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK);
 597
 598         return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port],
 599                                 packed_buf, SJA1105_SIZE_CGU_CMD);
 600 }
 601
 602 static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
 603 {
 604         const struct sja1105_regs *regs = priv->info->regs;
 605         u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
 606         struct sja1105_cgu_pll_ctrl pll = {0};
 607         struct device *dev = priv->ds->dev;
 608         int rc;
 609
 610         /* PLL1 must be enabled and output 50 Mhz.
 611          * This is done by writing first 0x0A010941 to
 612          * the PLL_1_C register and then deasserting
 613          * power down (PD) 0x0A010940.
 614          */
 615
 616         /* Step 1: PLL1 setup for 50Mhz */
 617         pll.pllclksrc = 0xA;
 618         pll.msel      = 0x1;
 619         pll.autoblock = 0x1;
 620         pll.psel      = 0x1;
 621         pll.direct    = 0x0;
 622         pll.fbsel     = 0x1;
 623         pll.bypass    = 0x0;
 624         pll.pd        = 0x1;
 625
 626         sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
 627         rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
 628                               SJA1105_SIZE_CGU_CMD);
 629         if (rc < 0) {
 630                 dev_err(dev, "failed to configure PLL1 for 50MHz\n");
 631                 return rc;
 632         }
 633
 634         /* Step 2: Enable PLL1 */
 635         pll.pd = 0x0;
 636
 637         sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
 638         rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
 639                               SJA1105_SIZE_CGU_CMD);
 640         if (rc < 0) {
 641                 dev_err(dev, "failed to enable PLL1\n");
 642                 return rc;
 643         }
 644         return rc;
 645 }
 646
 647 static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port,
 648                                        sja1105_mii_role_t role)
 649 {
 650         struct device *dev = priv->ds->dev;
 651         int rc;
 652
 653         dev_dbg(dev, "Configuring RMII-%s clocking\n",
 654                 (role == XMII_MAC) ? "MAC" : "PHY");
 655         /* AH1601.pdf chapter 2.5.1. Sources */
 656         if (role == XMII_MAC) {
 657                 /* Configure and enable PLL1 for 50Mhz output */
 658                 rc = sja1105_cgu_rmii_pll_config(priv);
 659                 if (rc < 0)
 660                         return rc;
 661         }
 662         /* Disable IDIV for this port */
 663         rc = sja1105_cgu_idiv_config(priv, port, false, 1);
 664         if (rc < 0)
 665                 return rc;
 666         /* Source to sink mappings */
 667         rc = sja1105_cgu_rmii_ref_clk_config(priv, port);
 668         if (rc < 0)
 669                 return rc;
 670         if (role == XMII_MAC) {
 671                 rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port);
 672                 if (rc < 0)
 673                         return rc;
 674         }
 675         return 0;
 676 }
 677
 678 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port)
 679 {
 680         struct sja1105_xmii_params_entry *mii;
 681         struct device *dev = priv->ds->dev;
 682         sja1105_phy_interface_t phy_mode;
 683         sja1105_mii_role_t role;
 684         int rc;
 685
 686         mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
 687
 688         /* RGMII etc */
 689         phy_mode = mii->xmii_mode[port];
 690         /* MAC or PHY, for applicable types (not RGMII) */
 691         role = mii->phy_mac[port];
 692
 693         switch (phy_mode) {
 694         case XMII_MODE_MII:
 695                 rc = sja1105_mii_clocking_setup(priv, port, role);
 696                 break;
 697         case XMII_MODE_RMII:
 698                 rc = sja1105_rmii_clocking_setup(priv, port, role);
 699                 break;
 700         case XMII_MODE_RGMII:
 701                 rc = sja1105_rgmii_clocking_setup(priv, port, role);
 702                 break;
 703         case XMII_MODE_SGMII:
 704                 /* Nothing to do in the CGU for SGMII */
 705                 rc = 0;
 706                 break;
 707         default:
 708                 dev_err(dev, "Invalid interface mode specified: %d\n",
 709                         phy_mode);
 710                 return -EINVAL;
 711         }
 712         if (rc) {
 713                 dev_err(dev, "Clocking setup for port %d failed: %d\n",
 714                         port, rc);
 715                 return rc;
 716         }
 717
 718         /* Internally pull down the RX_DV/CRS_DV/RX_CTL and RX_ER inputs */
 719         return sja1105_cfg_pad_rx_config(priv, port);
 720 }
 721
 722 int sja1105_clocking_setup(struct sja1105_private *priv)
 723 {
 724         int port, rc;
 725
 726         for (port = 0; port < SJA1105_NUM_PORTS; port++) {
 727                 rc = sja1105_clocking_setup_port(priv, port);
 728                 if (rc < 0)
 729                         return rc;
 730         }
 731         return 0;
 732 }