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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / amd / pcnet32.c
blob187b0b9a6e1df6ab3ea7ecfe05b96fa731e225ad
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #define DRV_NAME "pcnet32"
27 #define DRV_RELDATE "21.Apr.2008"
28 #define PFX DRV_NAME ": "
29
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/sched.h>
33 #include <linux/string.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/crc32.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_ether.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
51 #include <linux/io.h>
52 #include <linux/uaccess.h>
53
54 #include <asm/dma.h>
55 #include <asm/irq.h>
56
57 /*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60 static const struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
70
71 { } /* terminate list */
72 };
73
74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
75
76 static int cards_found;
77
78 /*
79 * VLB I/O addresses
80 */
81 static unsigned int pcnet32_portlist[] =
82 { 0x300, 0x320, 0x340, 0x360, 0 };
83
84 static int pcnet32_debug;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
87
88 static struct net_device *pcnet32_dev;
89
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
92
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
97
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
102
103 #define PCNET32_DMA_MASK 0xffffffff
104
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108 /*
109 * table to translate option values from tulip
110 * to internal options
111 */
112 static const unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
130 };
131
132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Loopback test (offline)"
134 };
135
136 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
137
138 #define PCNET32_NUM_REGS 136
139
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options[MAX_UNITS];
142 static int full_duplex[MAX_UNITS];
143 static int homepna[MAX_UNITS];
144
145 /*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
155 /*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
165 #endif
166
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
169
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
172
173 #define PKT_BUF_SKB 1544
174 /* actual buffer length after being aligned */
175 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
176 /* chip wants twos complement of the (aligned) buffer length */
177 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
178
179 /* Offsets from base I/O address. */
180 #define PCNET32_WIO_RDP 0x10
181 #define PCNET32_WIO_RAP 0x12
182 #define PCNET32_WIO_RESET 0x14
183 #define PCNET32_WIO_BDP 0x16
184
185 #define PCNET32_DWIO_RDP 0x10
186 #define PCNET32_DWIO_RAP 0x14
187 #define PCNET32_DWIO_RESET 0x18
188 #define PCNET32_DWIO_BDP 0x1C
189
190 #define PCNET32_TOTAL_SIZE 0x20
191
192 #define CSR0 0
193 #define CSR0_INIT 0x1
194 #define CSR0_START 0x2
195 #define CSR0_STOP 0x4
196 #define CSR0_TXPOLL 0x8
197 #define CSR0_INTEN 0x40
198 #define CSR0_IDON 0x0100
199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200 #define PCNET32_INIT_LOW 1
201 #define PCNET32_INIT_HIGH 2
202 #define CSR3 3
203 #define CSR4 4
204 #define CSR5 5
205 #define CSR5_SUSPEND 0x0001
206 #define CSR15 15
207 #define PCNET32_MC_FILTER 8
208
209 #define PCNET32_79C970A 0x2621
210
211 /* The PCNET32 Rx and Tx ring descriptors. */
212 struct pcnet32_rx_head {
213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
218 };
219
220 struct pcnet32_tx_head {
221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
226 };
227
228 /* The PCNET32 32-Bit initialization block, described in databook. */
229 struct pcnet32_init_block {
230 __le16 mode;
231 __le16 tlen_rlen;
232 u8 phys_addr[6];
233 __le16 reserved;
234 __le32 filter[2];
235 /* Receive and transmit ring base, along with extra bits. */
236 __le32 rx_ring;
237 __le32 tx_ring;
238 };
239
240 /* PCnet32 access functions */
241 struct pcnet32_access {
242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
249 };
250
251 /*
252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using dma_alloc_coherent().
254 */
255 struct pcnet32_private {
256 struct pcnet32_init_block *init_block;
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by dma_alloc_coherent */
262 struct pci_dev *pci_dev;
263 const char *name;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 const struct pcnet32_access *a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
283 struct net_device *dev;
284 struct napi_struct napi;
285 char tx_full;
286 char phycount; /* number of phys found */
287 int options;
288 unsigned int shared_irq:1, /* shared irq possible */
289 dxsuflo:1, /* disable transmit stop on uflo */
290 mii:1, /* mii port available */
291 autoneg:1, /* autoneg enabled */
292 port_tp:1, /* port set to TP */
293 fdx:1; /* full duplex enabled */
294 struct net_device *next;
295 struct mii_if_info mii_if;
296 struct timer_list watchdog_timer;
297 u32 msg_enable; /* debug message level */
298
299 /* each bit indicates an available PHY */
300 u32 phymask;
301 unsigned short chip_version; /* which variant this is */
302
303 /* saved registers during ethtool blink */
304 u16 save_regs[4];
305 };
306
307 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
308 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
309 static int pcnet32_open(struct net_device *);
310 static int pcnet32_init_ring(struct net_device *);
311 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
312 struct net_device *);
313 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue);
314 static irqreturn_t pcnet32_interrupt(int, void *);
315 static int pcnet32_close(struct net_device *);
316 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
317 static void pcnet32_load_multicast(struct net_device *dev);
318 static void pcnet32_set_multicast_list(struct net_device *);
319 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
320 static void pcnet32_watchdog(struct timer_list *);
321 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
322 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
323 int val);
324 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
325 static void pcnet32_ethtool_test(struct net_device *dev,
326 struct ethtool_test *eth_test, u64 * data);
327 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
328 static int pcnet32_get_regs_len(struct net_device *dev);
329 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
330 void *ptr);
331 static void pcnet32_purge_tx_ring(struct net_device *dev);
332 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
333 static void pcnet32_free_ring(struct net_device *dev);
334 static void pcnet32_check_media(struct net_device *dev, int verbose);
335
336 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
337 {
338 outw(index, addr + PCNET32_WIO_RAP);
339 return inw(addr + PCNET32_WIO_RDP);
340 }
341
342 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
343 {
344 outw(index, addr + PCNET32_WIO_RAP);
345 outw(val, addr + PCNET32_WIO_RDP);
346 }
347
348 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
349 {
350 outw(index, addr + PCNET32_WIO_RAP);
351 return inw(addr + PCNET32_WIO_BDP);
352 }
353
354 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
355 {
356 outw(index, addr + PCNET32_WIO_RAP);
357 outw(val, addr + PCNET32_WIO_BDP);
358 }
359
360 static u16 pcnet32_wio_read_rap(unsigned long addr)
361 {
362 return inw(addr + PCNET32_WIO_RAP);
363 }
364
365 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
366 {
367 outw(val, addr + PCNET32_WIO_RAP);
368 }
369
370 static void pcnet32_wio_reset(unsigned long addr)
371 {
372 inw(addr + PCNET32_WIO_RESET);
373 }
374
375 static int pcnet32_wio_check(unsigned long addr)
376 {
377 outw(88, addr + PCNET32_WIO_RAP);
378 return inw(addr + PCNET32_WIO_RAP) == 88;
379 }
380
381 static const struct pcnet32_access pcnet32_wio = {
382 .read_csr = pcnet32_wio_read_csr,
383 .write_csr = pcnet32_wio_write_csr,
384 .read_bcr = pcnet32_wio_read_bcr,
385 .write_bcr = pcnet32_wio_write_bcr,
386 .read_rap = pcnet32_wio_read_rap,
387 .write_rap = pcnet32_wio_write_rap,
388 .reset = pcnet32_wio_reset
389 };
390
391 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
392 {
393 outl(index, addr + PCNET32_DWIO_RAP);
394 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
395 }
396
397 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
398 {
399 outl(index, addr + PCNET32_DWIO_RAP);
400 outl(val, addr + PCNET32_DWIO_RDP);
401 }
402
403 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
404 {
405 outl(index, addr + PCNET32_DWIO_RAP);
406 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
407 }
408
409 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
410 {
411 outl(index, addr + PCNET32_DWIO_RAP);
412 outl(val, addr + PCNET32_DWIO_BDP);
413 }
414
415 static u16 pcnet32_dwio_read_rap(unsigned long addr)
416 {
417 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
418 }
419
420 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
421 {
422 outl(val, addr + PCNET32_DWIO_RAP);
423 }
424
425 static void pcnet32_dwio_reset(unsigned long addr)
426 {
427 inl(addr + PCNET32_DWIO_RESET);
428 }
429
430 static int pcnet32_dwio_check(unsigned long addr)
431 {
432 outl(88, addr + PCNET32_DWIO_RAP);
433 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
434 }
435
436 static const struct pcnet32_access pcnet32_dwio = {
437 .read_csr = pcnet32_dwio_read_csr,
438 .write_csr = pcnet32_dwio_write_csr,
439 .read_bcr = pcnet32_dwio_read_bcr,
440 .write_bcr = pcnet32_dwio_write_bcr,
441 .read_rap = pcnet32_dwio_read_rap,
442 .write_rap = pcnet32_dwio_write_rap,
443 .reset = pcnet32_dwio_reset
444 };
445
446 static void pcnet32_netif_stop(struct net_device *dev)
447 {
448 struct pcnet32_private *lp = netdev_priv(dev);
449
450 netif_trans_update(dev); /* prevent tx timeout */
451 napi_disable(&lp->napi);
452 netif_tx_disable(dev);
453 }
454
455 static void pcnet32_netif_start(struct net_device *dev)
456 {
457 struct pcnet32_private *lp = netdev_priv(dev);
458 ulong ioaddr = dev->base_addr;
459 u16 val;
460
461 netif_wake_queue(dev);
462 val = lp->a->read_csr(ioaddr, CSR3);
463 val &= 0x00ff;
464 lp->a->write_csr(ioaddr, CSR3, val);
465 napi_enable(&lp->napi);
466 }
467
468 /*
469 * Allocate space for the new sized tx ring.
470 * Free old resources
471 * Save new resources.
472 * Any failure keeps old resources.
473 * Must be called with lp->lock held.
474 */
475 static void pcnet32_realloc_tx_ring(struct net_device *dev,
476 struct pcnet32_private *lp,
477 unsigned int size)
478 {
479 dma_addr_t new_ring_dma_addr;
480 dma_addr_t *new_dma_addr_list;
481 struct pcnet32_tx_head *new_tx_ring;
482 struct sk_buff **new_skb_list;
483 unsigned int entries = BIT(size);
484
485 pcnet32_purge_tx_ring(dev);
486
487 new_tx_ring =
488 dma_alloc_coherent(&lp->pci_dev->dev,
489 sizeof(struct pcnet32_tx_head) * entries,
490 &new_ring_dma_addr, GFP_ATOMIC);
491 if (new_tx_ring == NULL)
492 return;
493
494 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
495 if (!new_dma_addr_list)
496 goto free_new_tx_ring;
497
498 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
499 if (!new_skb_list)
500 goto free_new_lists;
501
502 kfree(lp->tx_skbuff);
503 kfree(lp->tx_dma_addr);
504 dma_free_coherent(&lp->pci_dev->dev,
505 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
506 lp->tx_ring, lp->tx_ring_dma_addr);
507
508 lp->tx_ring_size = entries;
509 lp->tx_mod_mask = lp->tx_ring_size - 1;
510 lp->tx_len_bits = (size << 12);
511 lp->tx_ring = new_tx_ring;
512 lp->tx_ring_dma_addr = new_ring_dma_addr;
513 lp->tx_dma_addr = new_dma_addr_list;
514 lp->tx_skbuff = new_skb_list;
515 return;
516
517 free_new_lists:
518 kfree(new_dma_addr_list);
519 free_new_tx_ring:
520 dma_free_coherent(&lp->pci_dev->dev,
521 sizeof(struct pcnet32_tx_head) * entries,
522 new_tx_ring, new_ring_dma_addr);
523 }
524
525 /*
526 * Allocate space for the new sized rx ring.
527 * Re-use old receive buffers.
528 * alloc extra buffers
529 * free unneeded buffers
530 * free unneeded buffers
531 * Save new resources.
532 * Any failure keeps old resources.
533 * Must be called with lp->lock held.
534 */
535 static void pcnet32_realloc_rx_ring(struct net_device *dev,
536 struct pcnet32_private *lp,
537 unsigned int size)
538 {
539 dma_addr_t new_ring_dma_addr;
540 dma_addr_t *new_dma_addr_list;
541 struct pcnet32_rx_head *new_rx_ring;
542 struct sk_buff **new_skb_list;
543 int new, overlap;
544 unsigned int entries = BIT(size);
545
546 new_rx_ring =
547 dma_alloc_coherent(&lp->pci_dev->dev,
548 sizeof(struct pcnet32_rx_head) * entries,
549 &new_ring_dma_addr, GFP_ATOMIC);
550 if (new_rx_ring == NULL)
551 return;
552
553 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
554 if (!new_dma_addr_list)
555 goto free_new_rx_ring;
556
557 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
558 if (!new_skb_list)
559 goto free_new_lists;
560
561 /* first copy the current receive buffers */
562 overlap = min(entries, lp->rx_ring_size);
563 for (new = 0; new < overlap; new++) {
564 new_rx_ring[new] = lp->rx_ring[new];
565 new_dma_addr_list[new] = lp->rx_dma_addr[new];
566 new_skb_list[new] = lp->rx_skbuff[new];
567 }
568 /* now allocate any new buffers needed */
569 for (; new < entries; new++) {
570 struct sk_buff *rx_skbuff;
571 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
572 rx_skbuff = new_skb_list[new];
573 if (!rx_skbuff) {
574 /* keep the original lists and buffers */
575 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
576 __func__);
577 goto free_all_new;
578 }
579 skb_reserve(rx_skbuff, NET_IP_ALIGN);
580
581 new_dma_addr_list[new] =
582 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,
583 PKT_BUF_SIZE, DMA_FROM_DEVICE);
584 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new])) {
585 netif_err(lp, drv, dev, "%s dma mapping failed\n",
586 __func__);
587 dev_kfree_skb(new_skb_list[new]);
588 goto free_all_new;
589 }
590 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
591 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
592 new_rx_ring[new].status = cpu_to_le16(0x8000);
593 }
594 /* and free any unneeded buffers */
595 for (; new < lp->rx_ring_size; new++) {
596 if (lp->rx_skbuff[new]) {
597 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[new]))
598 dma_unmap_single(&lp->pci_dev->dev,
599 lp->rx_dma_addr[new],
600 PKT_BUF_SIZE,
601 DMA_FROM_DEVICE);
602 dev_kfree_skb(lp->rx_skbuff[new]);
603 }
604 }
605
606 kfree(lp->rx_skbuff);
607 kfree(lp->rx_dma_addr);
608 dma_free_coherent(&lp->pci_dev->dev,
609 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
610 lp->rx_ring, lp->rx_ring_dma_addr);
611
612 lp->rx_ring_size = entries;
613 lp->rx_mod_mask = lp->rx_ring_size - 1;
614 lp->rx_len_bits = (size << 4);
615 lp->rx_ring = new_rx_ring;
616 lp->rx_ring_dma_addr = new_ring_dma_addr;
617 lp->rx_dma_addr = new_dma_addr_list;
618 lp->rx_skbuff = new_skb_list;
619 return;
620
621 free_all_new:
622 while (--new >= lp->rx_ring_size) {
623 if (new_skb_list[new]) {
624 if (!dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new]))
625 dma_unmap_single(&lp->pci_dev->dev,
626 new_dma_addr_list[new],
627 PKT_BUF_SIZE,
628 DMA_FROM_DEVICE);
629 dev_kfree_skb(new_skb_list[new]);
630 }
631 }
632 kfree(new_skb_list);
633 free_new_lists:
634 kfree(new_dma_addr_list);
635 free_new_rx_ring:
636 dma_free_coherent(&lp->pci_dev->dev,
637 sizeof(struct pcnet32_rx_head) * entries,
638 new_rx_ring, new_ring_dma_addr);
639 }
640
641 static void pcnet32_purge_rx_ring(struct net_device *dev)
642 {
643 struct pcnet32_private *lp = netdev_priv(dev);
644 int i;
645
646 /* free all allocated skbuffs */
647 for (i = 0; i < lp->rx_ring_size; i++) {
648 lp->rx_ring[i].status = 0; /* CPU owns buffer */
649 wmb(); /* Make sure adapter sees owner change */
650 if (lp->rx_skbuff[i]) {
651 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i]))
652 dma_unmap_single(&lp->pci_dev->dev,
653 lp->rx_dma_addr[i],
654 PKT_BUF_SIZE,
655 DMA_FROM_DEVICE);
656 dev_kfree_skb_any(lp->rx_skbuff[i]);
657 }
658 lp->rx_skbuff[i] = NULL;
659 lp->rx_dma_addr[i] = 0;
660 }
661 }
662
663 #ifdef CONFIG_NET_POLL_CONTROLLER
664 static void pcnet32_poll_controller(struct net_device *dev)
665 {
666 disable_irq(dev->irq);
667 pcnet32_interrupt(0, dev);
668 enable_irq(dev->irq);
669 }
670 #endif
671
672 /*
673 * lp->lock must be held.
674 */
675 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
676 int can_sleep)
677 {
678 int csr5;
679 struct pcnet32_private *lp = netdev_priv(dev);
680 const struct pcnet32_access *a = lp->a;
681 ulong ioaddr = dev->base_addr;
682 int ticks;
683
684 /* really old chips have to be stopped. */
685 if (lp->chip_version < PCNET32_79C970A)
686 return 0;
687
688 /* set SUSPEND (SPND) - CSR5 bit 0 */
689 csr5 = a->read_csr(ioaddr, CSR5);
690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
691
692 /* poll waiting for bit to be set */
693 ticks = 0;
694 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
695 spin_unlock_irqrestore(&lp->lock, *flags);
696 if (can_sleep)
697 msleep(1);
698 else
699 mdelay(1);
700 spin_lock_irqsave(&lp->lock, *flags);
701 ticks++;
702 if (ticks > 200) {
703 netif_printk(lp, hw, KERN_DEBUG, dev,
704 "Error getting into suspend!\n");
705 return 0;
706 }
707 }
708 return 1;
709 }
710
711 static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr)
712 {
713 int csr5 = lp->a->read_csr(ioaddr, CSR5);
714 /* clear SUSPEND (SPND) - CSR5 bit 0 */
715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
716 }
717
718 static int pcnet32_get_link_ksettings(struct net_device *dev,
719 struct ethtool_link_ksettings *cmd)
720 {
721 struct pcnet32_private *lp = netdev_priv(dev);
722 unsigned long flags;
723
724 spin_lock_irqsave(&lp->lock, flags);
725 if (lp->mii) {
726 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
727 } else if (lp->chip_version == PCNET32_79C970A) {
728 if (lp->autoneg) {
729 cmd->base.autoneg = AUTONEG_ENABLE;
730 if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0)
731 cmd->base.port = PORT_AUI;
732 else
733 cmd->base.port = PORT_TP;
734 } else {
735 cmd->base.autoneg = AUTONEG_DISABLE;
736 cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI;
737 }
738 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF;
739 cmd->base.speed = SPEED_10;
740 ethtool_convert_legacy_u32_to_link_mode(
741 cmd->link_modes.supported,
742 SUPPORTED_TP | SUPPORTED_AUI);
743 }
744 spin_unlock_irqrestore(&lp->lock, flags);
745 return 0;
746 }
747
748 static int pcnet32_set_link_ksettings(struct net_device *dev,
749 const struct ethtool_link_ksettings *cmd)
750 {
751 struct pcnet32_private *lp = netdev_priv(dev);
752 ulong ioaddr = dev->base_addr;
753 unsigned long flags;
754 int r = -EOPNOTSUPP;
755 int suspended, bcr2, bcr9, csr15;
756
757 spin_lock_irqsave(&lp->lock, flags);
758 if (lp->mii) {
759 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
760 } else if (lp->chip_version == PCNET32_79C970A) {
761 suspended = pcnet32_suspend(dev, &flags, 0);
762 if (!suspended)
763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
764
765 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
766 bcr2 = lp->a->read_bcr(ioaddr, 2);
767 if (cmd->base.autoneg == AUTONEG_ENABLE) {
768 lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002);
769 } else {
770 lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002);
771
772 lp->port_tp = cmd->base.port == PORT_TP;
773 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;
774 if (cmd->base.port == PORT_TP)
775 csr15 |= 0x0080;
776 lp->a->write_csr(ioaddr, CSR15, csr15);
777 lp->init_block->mode = cpu_to_le16(csr15);
778
779 lp->fdx = cmd->base.duplex == DUPLEX_FULL;
780 bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003;
781 if (cmd->base.duplex == DUPLEX_FULL)
782 bcr9 |= 0x0003;
783 lp->a->write_bcr(ioaddr, 9, bcr9);
784 }
785 if (suspended)
786 pcnet32_clr_suspend(lp, ioaddr);
787 else if (netif_running(dev))
788 pcnet32_restart(dev, CSR0_NORMAL);
789 r = 0;
790 }
791 spin_unlock_irqrestore(&lp->lock, flags);
792 return r;
793 }
794
795 static void pcnet32_get_drvinfo(struct net_device *dev,
796 struct ethtool_drvinfo *info)
797 {
798 struct pcnet32_private *lp = netdev_priv(dev);
799
800 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
801 if (lp->pci_dev)
802 strlcpy(info->bus_info, pci_name(lp->pci_dev),
803 sizeof(info->bus_info));
804 else
805 snprintf(info->bus_info, sizeof(info->bus_info),
806 "VLB 0x%lx", dev->base_addr);
807 }
808
809 static u32 pcnet32_get_link(struct net_device *dev)
810 {
811 struct pcnet32_private *lp = netdev_priv(dev);
812 unsigned long flags;
813 int r;
814
815 spin_lock_irqsave(&lp->lock, flags);
816 if (lp->mii) {
817 r = mii_link_ok(&lp->mii_if);
818 } else if (lp->chip_version == PCNET32_79C970A) {
819 ulong ioaddr = dev->base_addr; /* card base I/O address */
820 /* only read link if port is set to TP */
821 if (!lp->autoneg && lp->port_tp)
822 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
823 else /* link always up for AUI port or port auto select */
824 r = 1;
825 } else if (lp->chip_version > PCNET32_79C970A) {
826 ulong ioaddr = dev->base_addr; /* card base I/O address */
827 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
828 } else { /* can not detect link on really old chips */
829 r = 1;
830 }
831 spin_unlock_irqrestore(&lp->lock, flags);
832
833 return r;
834 }
835
836 static u32 pcnet32_get_msglevel(struct net_device *dev)
837 {
838 struct pcnet32_private *lp = netdev_priv(dev);
839 return lp->msg_enable;
840 }
841
842 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
843 {
844 struct pcnet32_private *lp = netdev_priv(dev);
845 lp->msg_enable = value;
846 }
847
848 static int pcnet32_nway_reset(struct net_device *dev)
849 {
850 struct pcnet32_private *lp = netdev_priv(dev);
851 unsigned long flags;
852 int r = -EOPNOTSUPP;
853
854 if (lp->mii) {
855 spin_lock_irqsave(&lp->lock, flags);
856 r = mii_nway_restart(&lp->mii_if);
857 spin_unlock_irqrestore(&lp->lock, flags);
858 }
859 return r;
860 }
861
862 static void pcnet32_get_ringparam(struct net_device *dev,
863 struct ethtool_ringparam *ering)
864 {
865 struct pcnet32_private *lp = netdev_priv(dev);
866
867 ering->tx_max_pending = TX_MAX_RING_SIZE;
868 ering->tx_pending = lp->tx_ring_size;
869 ering->rx_max_pending = RX_MAX_RING_SIZE;
870 ering->rx_pending = lp->rx_ring_size;
871 }
872
873 static int pcnet32_set_ringparam(struct net_device *dev,
874 struct ethtool_ringparam *ering)
875 {
876 struct pcnet32_private *lp = netdev_priv(dev);
877 unsigned long flags;
878 unsigned int size;
879 ulong ioaddr = dev->base_addr;
880 int i;
881
882 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
883 return -EINVAL;
884
885 if (netif_running(dev))
886 pcnet32_netif_stop(dev);
887
888 spin_lock_irqsave(&lp->lock, flags);
889 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
890
891 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
892
893 /* set the minimum ring size to 4, to allow the loopback test to work
894 * unchanged.
895 */
896 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
897 if (size <= (1 << i))
898 break;
899 }
900 if ((1 << i) != lp->tx_ring_size)
901 pcnet32_realloc_tx_ring(dev, lp, i);
902
903 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
904 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
905 if (size <= (1 << i))
906 break;
907 }
908 if ((1 << i) != lp->rx_ring_size)
909 pcnet32_realloc_rx_ring(dev, lp, i);
910
911 lp->napi.weight = lp->rx_ring_size / 2;
912
913 if (netif_running(dev)) {
914 pcnet32_netif_start(dev);
915 pcnet32_restart(dev, CSR0_NORMAL);
916 }
917
918 spin_unlock_irqrestore(&lp->lock, flags);
919
920 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
921 lp->rx_ring_size, lp->tx_ring_size);
922
923 return 0;
924 }
925
926 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
927 u8 *data)
928 {
929 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
930 }
931
932 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
933 {
934 switch (sset) {
935 case ETH_SS_TEST:
936 return PCNET32_TEST_LEN;
937 default:
938 return -EOPNOTSUPP;
939 }
940 }
941
942 static void pcnet32_ethtool_test(struct net_device *dev,
943 struct ethtool_test *test, u64 * data)
944 {
945 struct pcnet32_private *lp = netdev_priv(dev);
946 int rc;
947
948 if (test->flags == ETH_TEST_FL_OFFLINE) {
949 rc = pcnet32_loopback_test(dev, data);
950 if (rc) {
951 netif_printk(lp, hw, KERN_DEBUG, dev,
952 "Loopback test failed\n");
953 test->flags |= ETH_TEST_FL_FAILED;
954 } else
955 netif_printk(lp, hw, KERN_DEBUG, dev,
956 "Loopback test passed\n");
957 } else
958 netif_printk(lp, hw, KERN_DEBUG, dev,
959 "No tests to run (specify 'Offline' on ethtool)\n");
960 } /* end pcnet32_ethtool_test */
961
962 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
963 {
964 struct pcnet32_private *lp = netdev_priv(dev);
965 const struct pcnet32_access *a = lp->a; /* access to registers */
966 ulong ioaddr = dev->base_addr; /* card base I/O address */
967 struct sk_buff *skb; /* sk buff */
968 int x, i; /* counters */
969 int numbuffs = 4; /* number of TX/RX buffers and descs */
970 u16 status = 0x8300; /* TX ring status */
971 __le16 teststatus; /* test of ring status */
972 int rc; /* return code */
973 int size; /* size of packets */
974 unsigned char *packet; /* source packet data */
975 static const int data_len = 60; /* length of source packets */
976 unsigned long flags;
977 unsigned long ticks;
978
979 rc = 1; /* default to fail */
980
981 if (netif_running(dev))
982 pcnet32_netif_stop(dev);
983
984 spin_lock_irqsave(&lp->lock, flags);
985 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
986
987 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
988
989 /* Reset the PCNET32 */
990 lp->a->reset(ioaddr);
991 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
992
993 /* switch pcnet32 to 32bit mode */
994 lp->a->write_bcr(ioaddr, 20, 2);
995
996 /* purge & init rings but don't actually restart */
997 pcnet32_restart(dev, 0x0000);
998
999 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
1000
1001 /* Initialize Transmit buffers. */
1002 size = data_len + 15;
1003 for (x = 0; x < numbuffs; x++) {
1004 skb = netdev_alloc_skb(dev, size);
1005 if (!skb) {
1006 netif_printk(lp, hw, KERN_DEBUG, dev,
1007 "Cannot allocate skb at line: %d!\n",
1008 __LINE__);
1009 goto clean_up;
1010 }
1011 packet = skb->data;
1012 skb_put(skb, size); /* create space for data */
1013 lp->tx_skbuff[x] = skb;
1014 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
1015 lp->tx_ring[x].misc = 0;
1016
1017 /* put DA and SA into the skb */
1018 for (i = 0; i < 6; i++)
1019 *packet++ = dev->dev_addr[i];
1020 for (i = 0; i < 6; i++)
1021 *packet++ = dev->dev_addr[i];
1022 /* type */
1023 *packet++ = 0x08;
1024 *packet++ = 0x06;
1025 /* packet number */
1026 *packet++ = x;
1027 /* fill packet with data */
1028 for (i = 0; i < data_len; i++)
1029 *packet++ = i;
1030
1031 lp->tx_dma_addr[x] =
1032 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
1033 DMA_TO_DEVICE);
1034 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[x])) {
1035 netif_printk(lp, hw, KERN_DEBUG, dev,
1036 "DMA mapping error at line: %d!\n",
1037 __LINE__);
1038 goto clean_up;
1039 }
1040 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
1041 wmb(); /* Make sure owner changes after all others are visible */
1042 lp->tx_ring[x].status = cpu_to_le16(status);
1043 }
1044
1045 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
1046 a->write_bcr(ioaddr, 32, x | 0x0002);
1047
1048 /* set int loopback in CSR15 */
1049 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1050 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1051
1052 teststatus = cpu_to_le16(0x8000);
1053 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
1054
1055 /* Check status of descriptors */
1056 for (x = 0; x < numbuffs; x++) {
1057 ticks = 0;
1058 rmb();
1059 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061 msleep(1);
1062 spin_lock_irqsave(&lp->lock, flags);
1063 rmb();
1064 ticks++;
1065 }
1066 if (ticks == 200) {
1067 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
1068 break;
1069 }
1070 }
1071
1072 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
1073 wmb();
1074 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1075 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
1076
1077 for (x = 0; x < numbuffs; x++) {
1078 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
1079 skb = lp->rx_skbuff[x];
1080 for (i = 0; i < size; i++)
1081 pr_cont(" %02x", *(skb->data + i));
1082 pr_cont("\n");
1083 }
1084 }
1085
1086 x = 0;
1087 rc = 0;
1088 while (x < numbuffs && !rc) {
1089 skb = lp->rx_skbuff[x];
1090 packet = lp->tx_skbuff[x]->data;
1091 for (i = 0; i < size; i++) {
1092 if (*(skb->data + i) != packet[i]) {
1093 netif_printk(lp, hw, KERN_DEBUG, dev,
1094 "Error in compare! %2x - %02x %02x\n",
1095 i, *(skb->data + i), packet[i]);
1096 rc = 1;
1097 break;
1098 }
1099 }
1100 x++;
1101 }
1102
1103 clean_up:
1104 *data1 = rc;
1105 pcnet32_purge_tx_ring(dev);
1106
1107 x = a->read_csr(ioaddr, CSR15);
1108 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1109
1110 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1111 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1112
1113 if (netif_running(dev)) {
1114 pcnet32_netif_start(dev);
1115 pcnet32_restart(dev, CSR0_NORMAL);
1116 } else {
1117 pcnet32_purge_rx_ring(dev);
1118 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1119 }
1120 spin_unlock_irqrestore(&lp->lock, flags);
1121
1122 return rc;
1123 } /* end pcnet32_loopback_test */
1124
1125 static int pcnet32_set_phys_id(struct net_device *dev,
1126 enum ethtool_phys_id_state state)
1127 {
1128 struct pcnet32_private *lp = netdev_priv(dev);
1129 const struct pcnet32_access *a = lp->a;
1130 ulong ioaddr = dev->base_addr;
1131 unsigned long flags;
1132 int i;
1133
1134 switch (state) {
1135 case ETHTOOL_ID_ACTIVE:
1136 /* Save the current value of the bcrs */
1137 spin_lock_irqsave(&lp->lock, flags);
1138 for (i = 4; i < 8; i++)
1139 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1140 spin_unlock_irqrestore(&lp->lock, flags);
1141 return 2; /* cycle on/off twice per second */
1142
1143 case ETHTOOL_ID_ON:
1144 case ETHTOOL_ID_OFF:
1145 /* Blink the led */
1146 spin_lock_irqsave(&lp->lock, flags);
1147 for (i = 4; i < 8; i++)
1148 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1149 spin_unlock_irqrestore(&lp->lock, flags);
1150 break;
1151
1152 case ETHTOOL_ID_INACTIVE:
1153 /* Restore the original value of the bcrs */
1154 spin_lock_irqsave(&lp->lock, flags);
1155 for (i = 4; i < 8; i++)
1156 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1157 spin_unlock_irqrestore(&lp->lock, flags);
1158 }
1159 return 0;
1160 }
1161
1162 /*
1163 * process one receive descriptor entry
1164 */
1165
1166 static void pcnet32_rx_entry(struct net_device *dev,
1167 struct pcnet32_private *lp,
1168 struct pcnet32_rx_head *rxp,
1169 int entry)
1170 {
1171 int status = (short)le16_to_cpu(rxp->status) >> 8;
1172 int rx_in_place = 0;
1173 struct sk_buff *skb;
1174 short pkt_len;
1175
1176 if (status != 0x03) { /* There was an error. */
1177 /*
1178 * There is a tricky error noted by John Murphy,
1179 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1180 * buffers it's possible for a jabber packet to use two
1181 * buffers, with only the last correctly noting the error.
1182 */
1183 if (status & 0x01) /* Only count a general error at the */
1184 dev->stats.rx_errors++; /* end of a packet. */
1185 if (status & 0x20)
1186 dev->stats.rx_frame_errors++;
1187 if (status & 0x10)
1188 dev->stats.rx_over_errors++;
1189 if (status & 0x08)
1190 dev->stats.rx_crc_errors++;
1191 if (status & 0x04)
1192 dev->stats.rx_fifo_errors++;
1193 return;
1194 }
1195
1196 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1197
1198 /* Discard oversize frames. */
1199 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1200 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1201 pkt_len);
1202 dev->stats.rx_errors++;
1203 return;
1204 }
1205 if (pkt_len < 60) {
1206 netif_err(lp, rx_err, dev, "Runt packet!\n");
1207 dev->stats.rx_errors++;
1208 return;
1209 }
1210
1211 if (pkt_len > rx_copybreak) {
1212 struct sk_buff *newskb;
1213 dma_addr_t new_dma_addr;
1214
1215 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1216 /*
1217 * map the new buffer, if mapping fails, drop the packet and
1218 * reuse the old buffer
1219 */
1220 if (newskb) {
1221 skb_reserve(newskb, NET_IP_ALIGN);
1222 new_dma_addr = dma_map_single(&lp->pci_dev->dev,
1223 newskb->data,
1224 PKT_BUF_SIZE,
1225 DMA_FROM_DEVICE);
1226 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr)) {
1227 netif_err(lp, rx_err, dev,
1228 "DMA mapping error.\n");
1229 dev_kfree_skb(newskb);
1230 skb = NULL;
1231 } else {
1232 skb = lp->rx_skbuff[entry];
1233 dma_unmap_single(&lp->pci_dev->dev,
1234 lp->rx_dma_addr[entry],
1235 PKT_BUF_SIZE,
1236 DMA_FROM_DEVICE);
1237 skb_put(skb, pkt_len);
1238 lp->rx_skbuff[entry] = newskb;
1239 lp->rx_dma_addr[entry] = new_dma_addr;
1240 rxp->base = cpu_to_le32(new_dma_addr);
1241 rx_in_place = 1;
1242 }
1243 } else
1244 skb = NULL;
1245 } else
1246 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1247
1248 if (skb == NULL) {
1249 dev->stats.rx_dropped++;
1250 return;
1251 }
1252 if (!rx_in_place) {
1253 skb_reserve(skb, NET_IP_ALIGN);
1254 skb_put(skb, pkt_len); /* Make room */
1255 dma_sync_single_for_cpu(&lp->pci_dev->dev,
1256 lp->rx_dma_addr[entry], pkt_len,
1257 DMA_FROM_DEVICE);
1258 skb_copy_to_linear_data(skb,
1259 (unsigned char *)(lp->rx_skbuff[entry]->data),
1260 pkt_len);
1261 dma_sync_single_for_device(&lp->pci_dev->dev,
1262 lp->rx_dma_addr[entry], pkt_len,
1263 DMA_FROM_DEVICE);
1264 }
1265 dev->stats.rx_bytes += skb->len;
1266 skb->protocol = eth_type_trans(skb, dev);
1267 netif_receive_skb(skb);
1268 dev->stats.rx_packets++;
1269 }
1270
1271 static int pcnet32_rx(struct net_device *dev, int budget)
1272 {
1273 struct pcnet32_private *lp = netdev_priv(dev);
1274 int entry = lp->cur_rx & lp->rx_mod_mask;
1275 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1276 int npackets = 0;
1277
1278 /* If we own the next entry, it's a new packet. Send it up. */
1279 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1280 pcnet32_rx_entry(dev, lp, rxp, entry);
1281 npackets += 1;
1282 /*
1283 * The docs say that the buffer length isn't touched, but Andrew
1284 * Boyd of QNX reports that some revs of the 79C965 clear it.
1285 */
1286 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1287 wmb(); /* Make sure owner changes after others are visible */
1288 rxp->status = cpu_to_le16(0x8000);
1289 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1290 rxp = &lp->rx_ring[entry];
1291 }
1292
1293 return npackets;
1294 }
1295
1296 static int pcnet32_tx(struct net_device *dev)
1297 {
1298 struct pcnet32_private *lp = netdev_priv(dev);
1299 unsigned int dirty_tx = lp->dirty_tx;
1300 int delta;
1301 int must_restart = 0;
1302
1303 while (dirty_tx != lp->cur_tx) {
1304 int entry = dirty_tx & lp->tx_mod_mask;
1305 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1306
1307 if (status < 0)
1308 break; /* It still hasn't been Txed */
1309
1310 lp->tx_ring[entry].base = 0;
1311
1312 if (status & 0x4000) {
1313 /* There was a major error, log it. */
1314 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1315 dev->stats.tx_errors++;
1316 netif_err(lp, tx_err, dev,
1317 "Tx error status=%04x err_status=%08x\n",
1318 status, err_status);
1319 if (err_status & 0x04000000)
1320 dev->stats.tx_aborted_errors++;
1321 if (err_status & 0x08000000)
1322 dev->stats.tx_carrier_errors++;
1323 if (err_status & 0x10000000)
1324 dev->stats.tx_window_errors++;
1325 #ifndef DO_DXSUFLO
1326 if (err_status & 0x40000000) {
1327 dev->stats.tx_fifo_errors++;
1328 /* Ackk! On FIFO errors the Tx unit is turned off! */
1329 /* Remove this verbosity later! */
1330 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1331 must_restart = 1;
1332 }
1333 #else
1334 if (err_status & 0x40000000) {
1335 dev->stats.tx_fifo_errors++;
1336 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1337 /* Ackk! On FIFO errors the Tx unit is turned off! */
1338 /* Remove this verbosity later! */
1339 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1340 must_restart = 1;
1341 }
1342 }
1343 #endif
1344 } else {
1345 if (status & 0x1800)
1346 dev->stats.collisions++;
1347 dev->stats.tx_packets++;
1348 }
1349
1350 /* We must free the original skb */
1351 if (lp->tx_skbuff[entry]) {
1352 dma_unmap_single(&lp->pci_dev->dev,
1353 lp->tx_dma_addr[entry],
1354 lp->tx_skbuff[entry]->len,
1355 DMA_TO_DEVICE);
1356 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1357 lp->tx_skbuff[entry] = NULL;
1358 lp->tx_dma_addr[entry] = 0;
1359 }
1360 dirty_tx++;
1361 }
1362
1363 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1364 if (delta > lp->tx_ring_size) {
1365 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1366 dirty_tx, lp->cur_tx, lp->tx_full);
1367 dirty_tx += lp->tx_ring_size;
1368 delta -= lp->tx_ring_size;
1369 }
1370
1371 if (lp->tx_full &&
1372 netif_queue_stopped(dev) &&
1373 delta < lp->tx_ring_size - 2) {
1374 /* The ring is no longer full, clear tbusy. */
1375 lp->tx_full = 0;
1376 netif_wake_queue(dev);
1377 }
1378 lp->dirty_tx = dirty_tx;
1379
1380 return must_restart;
1381 }
1382
1383 static int pcnet32_poll(struct napi_struct *napi, int budget)
1384 {
1385 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1386 struct net_device *dev = lp->dev;
1387 unsigned long ioaddr = dev->base_addr;
1388 unsigned long flags;
1389 int work_done;
1390 u16 val;
1391
1392 work_done = pcnet32_rx(dev, budget);
1393
1394 spin_lock_irqsave(&lp->lock, flags);
1395 if (pcnet32_tx(dev)) {
1396 /* reset the chip to clear the error condition, then restart */
1397 lp->a->reset(ioaddr);
1398 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1399 pcnet32_restart(dev, CSR0_START);
1400 netif_wake_queue(dev);
1401 }
1402
1403 if (work_done < budget && napi_complete_done(napi, work_done)) {
1404 /* clear interrupt masks */
1405 val = lp->a->read_csr(ioaddr, CSR3);
1406 val &= 0x00ff;
1407 lp->a->write_csr(ioaddr, CSR3, val);
1408
1409 /* Set interrupt enable. */
1410 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1411 }
1412
1413 spin_unlock_irqrestore(&lp->lock, flags);
1414 return work_done;
1415 }
1416
1417 #define PCNET32_REGS_PER_PHY 32
1418 #define PCNET32_MAX_PHYS 32
1419 static int pcnet32_get_regs_len(struct net_device *dev)
1420 {
1421 struct pcnet32_private *lp = netdev_priv(dev);
1422 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1423
1424 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1425 }
1426
1427 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1428 void *ptr)
1429 {
1430 int i, csr0;
1431 u16 *buff = ptr;
1432 struct pcnet32_private *lp = netdev_priv(dev);
1433 const struct pcnet32_access *a = lp->a;
1434 ulong ioaddr = dev->base_addr;
1435 unsigned long flags;
1436
1437 spin_lock_irqsave(&lp->lock, flags);
1438
1439 csr0 = a->read_csr(ioaddr, CSR0);
1440 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1441 pcnet32_suspend(dev, &flags, 1);
1442
1443 /* read address PROM */
1444 for (i = 0; i < 16; i += 2)
1445 *buff++ = inw(ioaddr + i);
1446
1447 /* read control and status registers */
1448 for (i = 0; i < 90; i++)
1449 *buff++ = a->read_csr(ioaddr, i);
1450
1451 *buff++ = a->read_csr(ioaddr, 112);
1452 *buff++ = a->read_csr(ioaddr, 114);
1453
1454 /* read bus configuration registers */
1455 for (i = 0; i < 30; i++)
1456 *buff++ = a->read_bcr(ioaddr, i);
1457
1458 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1459
1460 for (i = 31; i < 36; i++)
1461 *buff++ = a->read_bcr(ioaddr, i);
1462
1463 /* read mii phy registers */
1464 if (lp->mii) {
1465 int j;
1466 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1467 if (lp->phymask & (1 << j)) {
1468 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1469 lp->a->write_bcr(ioaddr, 33,
1470 (j << 5) | i);
1471 *buff++ = lp->a->read_bcr(ioaddr, 34);
1472 }
1473 }
1474 }
1475 }
1476
1477 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1478 pcnet32_clr_suspend(lp, ioaddr);
1479
1480 spin_unlock_irqrestore(&lp->lock, flags);
1481 }
1482
1483 static const struct ethtool_ops pcnet32_ethtool_ops = {
1484 .get_drvinfo = pcnet32_get_drvinfo,
1485 .get_msglevel = pcnet32_get_msglevel,
1486 .set_msglevel = pcnet32_set_msglevel,
1487 .nway_reset = pcnet32_nway_reset,
1488 .get_link = pcnet32_get_link,
1489 .get_ringparam = pcnet32_get_ringparam,
1490 .set_ringparam = pcnet32_set_ringparam,
1491 .get_strings = pcnet32_get_strings,
1492 .self_test = pcnet32_ethtool_test,
1493 .set_phys_id = pcnet32_set_phys_id,
1494 .get_regs_len = pcnet32_get_regs_len,
1495 .get_regs = pcnet32_get_regs,
1496 .get_sset_count = pcnet32_get_sset_count,
1497 .get_link_ksettings = pcnet32_get_link_ksettings,
1498 .set_link_ksettings = pcnet32_set_link_ksettings,
1499 };
1500
1501 /* only probes for non-PCI devices, the rest are handled by
1502 * pci_register_driver via pcnet32_probe_pci */
1503
1504 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1505 {
1506 unsigned int *port, ioaddr;
1507
1508 /* search for PCnet32 VLB cards at known addresses */
1509 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1510 if (request_region
1511 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1512 /* check if there is really a pcnet chip on that ioaddr */
1513 if ((inb(ioaddr + 14) == 0x57) &&
1514 (inb(ioaddr + 15) == 0x57)) {
1515 pcnet32_probe1(ioaddr, 0, NULL);
1516 } else {
1517 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1518 }
1519 }
1520 }
1521 }
1522
1523 static int
1524 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1525 {
1526 unsigned long ioaddr;
1527 int err;
1528
1529 err = pci_enable_device(pdev);
1530 if (err < 0) {
1531 if (pcnet32_debug & NETIF_MSG_PROBE)
1532 pr_err("failed to enable device -- err=%d\n", err);
1533 return err;
1534 }
1535 pci_set_master(pdev);
1536
1537 ioaddr = pci_resource_start(pdev, 0);
1538 if (!ioaddr) {
1539 if (pcnet32_debug & NETIF_MSG_PROBE)
1540 pr_err("card has no PCI IO resources, aborting\n");
1541 err = -ENODEV;
1542 goto err_disable_dev;
1543 }
1544
1545 err = dma_set_mask(&pdev->dev, PCNET32_DMA_MASK);
1546 if (err) {
1547 if (pcnet32_debug & NETIF_MSG_PROBE)
1548 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1549 goto err_disable_dev;
1550 }
1551 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1552 if (pcnet32_debug & NETIF_MSG_PROBE)
1553 pr_err("io address range already allocated\n");
1554 err = -EBUSY;
1555 goto err_disable_dev;
1556 }
1557
1558 err = pcnet32_probe1(ioaddr, 1, pdev);
1559
1560 err_disable_dev:
1561 if (err < 0)
1562 pci_disable_device(pdev);
1563
1564 return err;
1565 }
1566
1567 static const struct net_device_ops pcnet32_netdev_ops = {
1568 .ndo_open = pcnet32_open,
1569 .ndo_stop = pcnet32_close,
1570 .ndo_start_xmit = pcnet32_start_xmit,
1571 .ndo_tx_timeout = pcnet32_tx_timeout,
1572 .ndo_get_stats = pcnet32_get_stats,
1573 .ndo_set_rx_mode = pcnet32_set_multicast_list,
1574 .ndo_do_ioctl = pcnet32_ioctl,
1575 .ndo_set_mac_address = eth_mac_addr,
1576 .ndo_validate_addr = eth_validate_addr,
1577 #ifdef CONFIG_NET_POLL_CONTROLLER
1578 .ndo_poll_controller = pcnet32_poll_controller,
1579 #endif
1580 };
1581
1582 /* pcnet32_probe1
1583 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1584 * pdev will be NULL when called from pcnet32_probe_vlbus.
1585 */
1586 static int
1587 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1588 {
1589 struct pcnet32_private *lp;
1590 int i, media;
1591 int fdx, mii, fset, dxsuflo, sram;
1592 int chip_version;
1593 char *chipname;
1594 struct net_device *dev;
1595 const struct pcnet32_access *a = NULL;
1596 u8 promaddr[ETH_ALEN];
1597 int ret = -ENODEV;
1598
1599 /* reset the chip */
1600 pcnet32_wio_reset(ioaddr);
1601
1602 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1603 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1604 a = &pcnet32_wio;
1605 } else {
1606 pcnet32_dwio_reset(ioaddr);
1607 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1608 pcnet32_dwio_check(ioaddr)) {
1609 a = &pcnet32_dwio;
1610 } else {
1611 if (pcnet32_debug & NETIF_MSG_PROBE)
1612 pr_err("No access methods\n");
1613 goto err_release_region;
1614 }
1615 }
1616
1617 chip_version =
1618 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1619 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1620 pr_info(" PCnet chip version is %#x\n", chip_version);
1621 if ((chip_version & 0xfff) != 0x003) {
1622 if (pcnet32_debug & NETIF_MSG_PROBE)
1623 pr_info("Unsupported chip version\n");
1624 goto err_release_region;
1625 }
1626
1627 /* initialize variables */
1628 fdx = mii = fset = dxsuflo = sram = 0;
1629 chip_version = (chip_version >> 12) & 0xffff;
1630
1631 switch (chip_version) {
1632 case 0x2420:
1633 chipname = "PCnet/PCI 79C970"; /* PCI */
1634 break;
1635 case 0x2430:
1636 if (shared)
1637 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1638 else
1639 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1640 break;
1641 case 0x2621:
1642 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1643 fdx = 1;
1644 break;
1645 case 0x2623:
1646 chipname = "PCnet/FAST 79C971"; /* PCI */
1647 fdx = 1;
1648 mii = 1;
1649 fset = 1;
1650 break;
1651 case 0x2624:
1652 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1653 fdx = 1;
1654 mii = 1;
1655 fset = 1;
1656 break;
1657 case 0x2625:
1658 chipname = "PCnet/FAST III 79C973"; /* PCI */
1659 fdx = 1;
1660 mii = 1;
1661 sram = 1;
1662 break;
1663 case 0x2626:
1664 chipname = "PCnet/Home 79C978"; /* PCI */
1665 fdx = 1;
1666 /*
1667 * This is based on specs published at www.amd.com. This section
1668 * assumes that a card with a 79C978 wants to go into standard
1669 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1670 * and the module option homepna=1 can select this instead.
1671 */
1672 media = a->read_bcr(ioaddr, 49);
1673 media &= ~3; /* default to 10Mb ethernet */
1674 if (cards_found < MAX_UNITS && homepna[cards_found])
1675 media |= 1; /* switch to home wiring mode */
1676 if (pcnet32_debug & NETIF_MSG_PROBE)
1677 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1678 (media & 1) ? "1" : "10");
1679 a->write_bcr(ioaddr, 49, media);
1680 break;
1681 case 0x2627:
1682 chipname = "PCnet/FAST III 79C975"; /* PCI */
1683 fdx = 1;
1684 mii = 1;
1685 sram = 1;
1686 break;
1687 case 0x2628:
1688 chipname = "PCnet/PRO 79C976";
1689 fdx = 1;
1690 mii = 1;
1691 break;
1692 default:
1693 if (pcnet32_debug & NETIF_MSG_PROBE)
1694 pr_info("PCnet version %#x, no PCnet32 chip\n",
1695 chip_version);
1696 goto err_release_region;
1697 }
1698
1699 /*
1700 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1701 * starting until the packet is loaded. Strike one for reliability, lose
1702 * one for latency - although on PCI this isn't a big loss. Older chips
1703 * have FIFO's smaller than a packet, so you can't do this.
1704 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1705 */
1706
1707 if (fset) {
1708 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1709 a->write_csr(ioaddr, 80,
1710 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1711 dxsuflo = 1;
1712 }
1713
1714 /*
1715 * The Am79C973/Am79C975 controllers come with 12K of SRAM
1716 * which we can use for the Tx/Rx buffers but most importantly,
1717 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1718 * Tx fifo underflows.
1719 */
1720 if (sram) {
1721 /*
1722 * The SRAM is being configured in two steps. First we
1723 * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1724 * to the datasheet, each bit corresponds to a 512-byte
1725 * page so we can have at most 24 pages. The SRAM_SIZE
1726 * holds the value of the upper 8 bits of the 16-bit SRAM size.
1727 * The low 8-bits start at 0x00 and end at 0xff. So the
1728 * address range is from 0x0000 up to 0x17ff. Therefore,
1729 * the SRAM_SIZE is set to 0x17. The next step is to set
1730 * the BCR26:SRAM_BND midway through so the Tx and Rx
1731 * buffers can share the SRAM equally.
1732 */
1733 a->write_bcr(ioaddr, 25, 0x17);
1734 a->write_bcr(ioaddr, 26, 0xc);
1735 /* And finally enable the NOUFLO bit */
1736 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1737 }
1738
1739 dev = alloc_etherdev(sizeof(*lp));
1740 if (!dev) {
1741 ret = -ENOMEM;
1742 goto err_release_region;
1743 }
1744
1745 if (pdev)
1746 SET_NETDEV_DEV(dev, &pdev->dev);
1747
1748 if (pcnet32_debug & NETIF_MSG_PROBE)
1749 pr_info("%s at %#3lx,", chipname, ioaddr);
1750
1751 /* In most chips, after a chip reset, the ethernet address is read from the
1752 * station address PROM at the base address and programmed into the
1753 * "Physical Address Registers" CSR12-14.
1754 * As a precautionary measure, we read the PROM values and complain if
1755 * they disagree with the CSRs. If they miscompare, and the PROM addr
1756 * is valid, then the PROM addr is used.
1757 */
1758 for (i = 0; i < 3; i++) {
1759 unsigned int val;
1760 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1761 /* There may be endianness issues here. */
1762 dev->dev_addr[2 * i] = val & 0x0ff;
1763 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1764 }
1765
1766 /* read PROM address and compare with CSR address */
1767 for (i = 0; i < ETH_ALEN; i++)
1768 promaddr[i] = inb(ioaddr + i);
1769
1770 if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1771 !is_valid_ether_addr(dev->dev_addr)) {
1772 if (is_valid_ether_addr(promaddr)) {
1773 if (pcnet32_debug & NETIF_MSG_PROBE) {
1774 pr_cont(" warning: CSR address invalid,\n");
1775 pr_info(" using instead PROM address of");
1776 }
1777 memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1778 }
1779 }
1780
1781 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1782 if (!is_valid_ether_addr(dev->dev_addr))
1783 eth_zero_addr(dev->dev_addr);
1784
1785 if (pcnet32_debug & NETIF_MSG_PROBE) {
1786 pr_cont(" %pM", dev->dev_addr);
1787
1788 /* Version 0x2623 and 0x2624 */
1789 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1790 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1791 pr_info(" tx_start_pt(0x%04x):", i);
1792 switch (i >> 10) {
1793 case 0:
1794 pr_cont(" 20 bytes,");
1795 break;
1796 case 1:
1797 pr_cont(" 64 bytes,");
1798 break;
1799 case 2:
1800 pr_cont(" 128 bytes,");
1801 break;
1802 case 3:
1803 pr_cont("~220 bytes,");
1804 break;
1805 }
1806 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1807 pr_cont(" BCR18(%x):", i & 0xffff);
1808 if (i & (1 << 5))
1809 pr_cont("BurstWrEn ");
1810 if (i & (1 << 6))
1811 pr_cont("BurstRdEn ");
1812 if (i & (1 << 7))
1813 pr_cont("DWordIO ");
1814 if (i & (1 << 11))
1815 pr_cont("NoUFlow ");
1816 i = a->read_bcr(ioaddr, 25);
1817 pr_info(" SRAMSIZE=0x%04x,", i << 8);
1818 i = a->read_bcr(ioaddr, 26);
1819 pr_cont(" SRAM_BND=0x%04x,", i << 8);
1820 i = a->read_bcr(ioaddr, 27);
1821 if (i & (1 << 14))
1822 pr_cont("LowLatRx");
1823 }
1824 }
1825
1826 dev->base_addr = ioaddr;
1827 lp = netdev_priv(dev);
1828 /* dma_alloc_coherent returns page-aligned memory, so we do not have to check the alignment */
1829 lp->init_block = dma_alloc_coherent(&pdev->dev,
1830 sizeof(*lp->init_block),
1831 &lp->init_dma_addr, GFP_KERNEL);
1832 if (!lp->init_block) {
1833 if (pcnet32_debug & NETIF_MSG_PROBE)
1834 pr_err("Coherent memory allocation failed\n");
1835 ret = -ENOMEM;
1836 goto err_free_netdev;
1837 }
1838 lp->pci_dev = pdev;
1839
1840 lp->dev = dev;
1841
1842 spin_lock_init(&lp->lock);
1843
1844 lp->name = chipname;
1845 lp->shared_irq = shared;
1846 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1847 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1848 lp->tx_mod_mask = lp->tx_ring_size - 1;
1849 lp->rx_mod_mask = lp->rx_ring_size - 1;
1850 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1851 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1852 lp->mii_if.full_duplex = fdx;
1853 lp->mii_if.phy_id_mask = 0x1f;
1854 lp->mii_if.reg_num_mask = 0x1f;
1855 lp->dxsuflo = dxsuflo;
1856 lp->mii = mii;
1857 lp->chip_version = chip_version;
1858 lp->msg_enable = pcnet32_debug;
1859 if ((cards_found >= MAX_UNITS) ||
1860 (options[cards_found] >= sizeof(options_mapping)))
1861 lp->options = PCNET32_PORT_ASEL;
1862 else
1863 lp->options = options_mapping[options[cards_found]];
1864 /* force default port to TP on 79C970A so link detection can work */
1865 if (lp->chip_version == PCNET32_79C970A)
1866 lp->options = PCNET32_PORT_10BT;
1867 lp->mii_if.dev = dev;
1868 lp->mii_if.mdio_read = mdio_read;
1869 lp->mii_if.mdio_write = mdio_write;
1870
1871 /* napi.weight is used in both the napi and non-napi cases */
1872 lp->napi.weight = lp->rx_ring_size / 2;
1873
1874 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1875
1876 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1877 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1878 lp->options |= PCNET32_PORT_FD;
1879
1880 lp->a = a;
1881
1882 /* prior to register_netdev, dev->name is not yet correct */
1883 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1884 ret = -ENOMEM;
1885 goto err_free_ring;
1886 }
1887 /* detect special T1/E1 WAN card by checking for MAC address */
1888 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1889 dev->dev_addr[2] == 0x75)
1890 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1891
1892 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1893 lp->init_block->tlen_rlen =
1894 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1895 for (i = 0; i < 6; i++)
1896 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1897 lp->init_block->filter[0] = 0x00000000;
1898 lp->init_block->filter[1] = 0x00000000;
1899 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1900 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1901
1902 /* switch pcnet32 to 32bit mode */
1903 a->write_bcr(ioaddr, 20, 2);
1904
1905 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1906 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1907
1908 if (pdev) { /* use the IRQ provided by PCI */
1909 dev->irq = pdev->irq;
1910 if (pcnet32_debug & NETIF_MSG_PROBE)
1911 pr_cont(" assigned IRQ %d\n", dev->irq);
1912 } else {
1913 unsigned long irq_mask = probe_irq_on();
1914
1915 /*
1916 * To auto-IRQ we enable the initialization-done and DMA error
1917 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1918 * boards will work.
1919 */
1920 /* Trigger an initialization just for the interrupt. */
1921 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1922 mdelay(1);
1923
1924 dev->irq = probe_irq_off(irq_mask);
1925 if (!dev->irq) {
1926 if (pcnet32_debug & NETIF_MSG_PROBE)
1927 pr_cont(", failed to detect IRQ line\n");
1928 ret = -ENODEV;
1929 goto err_free_ring;
1930 }
1931 if (pcnet32_debug & NETIF_MSG_PROBE)
1932 pr_cont(", probed IRQ %d\n", dev->irq);
1933 }
1934
1935 /* Set the mii phy_id so that we can query the link state */
1936 if (lp->mii) {
1937 /* lp->phycount and lp->phymask are set to 0 by memset above */
1938
1939 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1940 /* scan for PHYs */
1941 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1942 unsigned short id1, id2;
1943
1944 id1 = mdio_read(dev, i, MII_PHYSID1);
1945 if (id1 == 0xffff)
1946 continue;
1947 id2 = mdio_read(dev, i, MII_PHYSID2);
1948 if (id2 == 0xffff)
1949 continue;
1950 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1951 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1952 lp->phycount++;
1953 lp->phymask |= (1 << i);
1954 lp->mii_if.phy_id = i;
1955 if (pcnet32_debug & NETIF_MSG_PROBE)
1956 pr_info("Found PHY %04x:%04x at address %d\n",
1957 id1, id2, i);
1958 }
1959 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1960 if (lp->phycount > 1)
1961 lp->options |= PCNET32_PORT_MII;
1962 }
1963
1964 timer_setup(&lp->watchdog_timer, pcnet32_watchdog, 0);
1965
1966 /* The PCNET32-specific entries in the device structure. */
1967 dev->netdev_ops = &pcnet32_netdev_ops;
1968 dev->ethtool_ops = &pcnet32_ethtool_ops;
1969 dev->watchdog_timeo = (5 * HZ);
1970
1971 /* Fill in the generic fields of the device structure. */
1972 if (register_netdev(dev))
1973 goto err_free_ring;
1974
1975 if (pdev) {
1976 pci_set_drvdata(pdev, dev);
1977 } else {
1978 lp->next = pcnet32_dev;
1979 pcnet32_dev = dev;
1980 }
1981
1982 if (pcnet32_debug & NETIF_MSG_PROBE)
1983 pr_info("%s: registered as %s\n", dev->name, lp->name);
1984 cards_found++;
1985
1986 /* enable LED writes */
1987 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1988
1989 return 0;
1990
1991 err_free_ring:
1992 pcnet32_free_ring(dev);
1993 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
1994 lp->init_block, lp->init_dma_addr);
1995 err_free_netdev:
1996 free_netdev(dev);
1997 err_release_region:
1998 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1999 return ret;
2000 }
2001
2002 /* if any allocation fails, caller must also call pcnet32_free_ring */
2003 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
2004 {
2005 struct pcnet32_private *lp = netdev_priv(dev);
2006
2007 lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
2008 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
2009 &lp->tx_ring_dma_addr, GFP_KERNEL);
2010 if (lp->tx_ring == NULL) {
2011 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");
2012 return -ENOMEM;
2013 }
2014
2015 lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
2016 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
2017 &lp->rx_ring_dma_addr, GFP_KERNEL);
2018 if (lp->rx_ring == NULL) {
2019 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");
2020 return -ENOMEM;
2021 }
2022
2023 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2024 GFP_KERNEL);
2025 if (!lp->tx_dma_addr)
2026 return -ENOMEM;
2027
2028 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2029 GFP_KERNEL);
2030 if (!lp->rx_dma_addr)
2031 return -ENOMEM;
2032
2033 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2034 GFP_KERNEL);
2035 if (!lp->tx_skbuff)
2036 return -ENOMEM;
2037
2038 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2039 GFP_KERNEL);
2040 if (!lp->rx_skbuff)
2041 return -ENOMEM;
2042
2043 return 0;
2044 }
2045
2046 static void pcnet32_free_ring(struct net_device *dev)
2047 {
2048 struct pcnet32_private *lp = netdev_priv(dev);
2049
2050 kfree(lp->tx_skbuff);
2051 lp->tx_skbuff = NULL;
2052
2053 kfree(lp->rx_skbuff);
2054 lp->rx_skbuff = NULL;
2055
2056 kfree(lp->tx_dma_addr);
2057 lp->tx_dma_addr = NULL;
2058
2059 kfree(lp->rx_dma_addr);
2060 lp->rx_dma_addr = NULL;
2061
2062 if (lp->tx_ring) {
2063 dma_free_coherent(&lp->pci_dev->dev,
2064 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
2065 lp->tx_ring, lp->tx_ring_dma_addr);
2066 lp->tx_ring = NULL;
2067 }
2068
2069 if (lp->rx_ring) {
2070 dma_free_coherent(&lp->pci_dev->dev,
2071 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
2072 lp->rx_ring, lp->rx_ring_dma_addr);
2073 lp->rx_ring = NULL;
2074 }
2075 }
2076
2077 static int pcnet32_open(struct net_device *dev)
2078 {
2079 struct pcnet32_private *lp = netdev_priv(dev);
2080 struct pci_dev *pdev = lp->pci_dev;
2081 unsigned long ioaddr = dev->base_addr;
2082 u16 val;
2083 int i;
2084 int rc;
2085 unsigned long flags;
2086
2087 if (request_irq(dev->irq, pcnet32_interrupt,
2088 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2089 (void *)dev)) {
2090 return -EAGAIN;
2091 }
2092
2093 spin_lock_irqsave(&lp->lock, flags);
2094 /* Check for a valid station address */
2095 if (!is_valid_ether_addr(dev->dev_addr)) {
2096 rc = -EINVAL;
2097 goto err_free_irq;
2098 }
2099
2100 /* Reset the PCNET32 */
2101 lp->a->reset(ioaddr);
2102
2103 /* switch pcnet32 to 32bit mode */
2104 lp->a->write_bcr(ioaddr, 20, 2);
2105
2106 netif_printk(lp, ifup, KERN_DEBUG, dev,
2107 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2108 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2109 (u32) (lp->rx_ring_dma_addr),
2110 (u32) (lp->init_dma_addr));
2111
2112 lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL);
2113 lp->port_tp = !!(lp->options & PCNET32_PORT_10BT);
2114 lp->fdx = !!(lp->options & PCNET32_PORT_FD);
2115
2116 /* set/reset autoselect bit */
2117 val = lp->a->read_bcr(ioaddr, 2) & ~2;
2118 if (lp->options & PCNET32_PORT_ASEL)
2119 val |= 2;
2120 lp->a->write_bcr(ioaddr, 2, val);
2121
2122 /* handle full duplex setting */
2123 if (lp->mii_if.full_duplex) {
2124 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2125 if (lp->options & PCNET32_PORT_FD) {
2126 val |= 1;
2127 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2128 val |= 2;
2129 } else if (lp->options & PCNET32_PORT_ASEL) {
2130 /* workaround of xSeries250, turn on for 79C975 only */
2131 if (lp->chip_version == 0x2627)
2132 val |= 3;
2133 }
2134 lp->a->write_bcr(ioaddr, 9, val);
2135 }
2136
2137 /* set/reset GPSI bit in test register */
2138 val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2139 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2140 val |= 0x10;
2141 lp->a->write_csr(ioaddr, 124, val);
2142
2143 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2144 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2145 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2146 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2147 if (lp->options & PCNET32_PORT_ASEL) {
2148 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2149 netif_printk(lp, link, KERN_DEBUG, dev,
2150 "Setting 100Mb-Full Duplex\n");
2151 }
2152 }
2153 if (lp->phycount < 2) {
2154 /*
2155 * 24 Jun 2004 according AMD, in order to change the PHY,
2156 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2157 * duplex, and/or enable auto negotiation, and clear DANAS
2158 */
2159 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2160 lp->a->write_bcr(ioaddr, 32,
2161 lp->a->read_bcr(ioaddr, 32) | 0x0080);
2162 /* disable Auto Negotiation, set 10Mpbs, HD */
2163 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2164 if (lp->options & PCNET32_PORT_FD)
2165 val |= 0x10;
2166 if (lp->options & PCNET32_PORT_100)
2167 val |= 0x08;
2168 lp->a->write_bcr(ioaddr, 32, val);
2169 } else {
2170 if (lp->options & PCNET32_PORT_ASEL) {
2171 lp->a->write_bcr(ioaddr, 32,
2172 lp->a->read_bcr(ioaddr,
2173 32) | 0x0080);
2174 /* enable auto negotiate, setup, disable fd */
2175 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2176 val |= 0x20;
2177 lp->a->write_bcr(ioaddr, 32, val);
2178 }
2179 }
2180 } else {
2181 int first_phy = -1;
2182 u16 bmcr;
2183 u32 bcr9;
2184 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2185
2186 /*
2187 * There is really no good other way to handle multiple PHYs
2188 * other than turning off all automatics
2189 */
2190 val = lp->a->read_bcr(ioaddr, 2);
2191 lp->a->write_bcr(ioaddr, 2, val & ~2);
2192 val = lp->a->read_bcr(ioaddr, 32);
2193 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2194
2195 if (!(lp->options & PCNET32_PORT_ASEL)) {
2196 /* setup ecmd */
2197 ecmd.port = PORT_MII;
2198 ecmd.transceiver = XCVR_INTERNAL;
2199 ecmd.autoneg = AUTONEG_DISABLE;
2200 ethtool_cmd_speed_set(&ecmd,
2201 (lp->options & PCNET32_PORT_100) ?
2202 SPEED_100 : SPEED_10);
2203 bcr9 = lp->a->read_bcr(ioaddr, 9);
2204
2205 if (lp->options & PCNET32_PORT_FD) {
2206 ecmd.duplex = DUPLEX_FULL;
2207 bcr9 |= (1 << 0);
2208 } else {
2209 ecmd.duplex = DUPLEX_HALF;
2210 bcr9 |= ~(1 << 0);
2211 }
2212 lp->a->write_bcr(ioaddr, 9, bcr9);
2213 }
2214
2215 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2216 if (lp->phymask & (1 << i)) {
2217 /* isolate all but the first PHY */
2218 bmcr = mdio_read(dev, i, MII_BMCR);
2219 if (first_phy == -1) {
2220 first_phy = i;
2221 mdio_write(dev, i, MII_BMCR,
2222 bmcr & ~BMCR_ISOLATE);
2223 } else {
2224 mdio_write(dev, i, MII_BMCR,
2225 bmcr | BMCR_ISOLATE);
2226 }
2227 /* use mii_ethtool_sset to setup PHY */
2228 lp->mii_if.phy_id = i;
2229 ecmd.phy_address = i;
2230 if (lp->options & PCNET32_PORT_ASEL) {
2231 mii_ethtool_gset(&lp->mii_if, &ecmd);
2232 ecmd.autoneg = AUTONEG_ENABLE;
2233 }
2234 mii_ethtool_sset(&lp->mii_if, &ecmd);
2235 }
2236 }
2237 lp->mii_if.phy_id = first_phy;
2238 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2239 }
2240
2241 #ifdef DO_DXSUFLO
2242 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2243 val = lp->a->read_csr(ioaddr, CSR3);
2244 val |= 0x40;
2245 lp->a->write_csr(ioaddr, CSR3, val);
2246 }
2247 #endif
2248
2249 lp->init_block->mode =
2250 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2251 pcnet32_load_multicast(dev);
2252
2253 if (pcnet32_init_ring(dev)) {
2254 rc = -ENOMEM;
2255 goto err_free_ring;
2256 }
2257
2258 napi_enable(&lp->napi);
2259
2260 /* Re-initialize the PCNET32, and start it when done. */
2261 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2262 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2263
2264 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2265 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2266
2267 netif_start_queue(dev);
2268
2269 if (lp->chip_version >= PCNET32_79C970A) {
2270 /* Print the link status and start the watchdog */
2271 pcnet32_check_media(dev, 1);
2272 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2273 }
2274
2275 i = 0;
2276 while (i++ < 100)
2277 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2278 break;
2279 /*
2280 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2281 * reports that doing so triggers a bug in the '974.
2282 */
2283 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2284
2285 netif_printk(lp, ifup, KERN_DEBUG, dev,
2286 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2287 i,
2288 (u32) (lp->init_dma_addr),
2289 lp->a->read_csr(ioaddr, CSR0));
2290
2291 spin_unlock_irqrestore(&lp->lock, flags);
2292
2293 return 0; /* Always succeed */
2294
2295 err_free_ring:
2296 /* free any allocated skbuffs */
2297 pcnet32_purge_rx_ring(dev);
2298
2299 /*
2300 * Switch back to 16bit mode to avoid problems with dumb
2301 * DOS packet driver after a warm reboot
2302 */
2303 lp->a->write_bcr(ioaddr, 20, 4);
2304
2305 err_free_irq:
2306 spin_unlock_irqrestore(&lp->lock, flags);
2307 free_irq(dev->irq, dev);
2308 return rc;
2309 }
2310
2311 /*
2312 * The LANCE has been halted for one reason or another (busmaster memory
2313 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2314 * etc.). Modern LANCE variants always reload their ring-buffer
2315 * configuration when restarted, so we must reinitialize our ring
2316 * context before restarting. As part of this reinitialization,
2317 * find all packets still on the Tx ring and pretend that they had been
2318 * sent (in effect, drop the packets on the floor) - the higher-level
2319 * protocols will time out and retransmit. It'd be better to shuffle
2320 * these skbs to a temp list and then actually re-Tx them after
2321 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2322 */
2323
2324 static void pcnet32_purge_tx_ring(struct net_device *dev)
2325 {
2326 struct pcnet32_private *lp = netdev_priv(dev);
2327 int i;
2328
2329 for (i = 0; i < lp->tx_ring_size; i++) {
2330 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2331 wmb(); /* Make sure adapter sees owner change */
2332 if (lp->tx_skbuff[i]) {
2333 if (!dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[i]))
2334 dma_unmap_single(&lp->pci_dev->dev,
2335 lp->tx_dma_addr[i],
2336 lp->tx_skbuff[i]->len,
2337 DMA_TO_DEVICE);
2338 dev_kfree_skb_any(lp->tx_skbuff[i]);
2339 }
2340 lp->tx_skbuff[i] = NULL;
2341 lp->tx_dma_addr[i] = 0;
2342 }
2343 }
2344
2345 /* Initialize the PCNET32 Rx and Tx rings. */
2346 static int pcnet32_init_ring(struct net_device *dev)
2347 {
2348 struct pcnet32_private *lp = netdev_priv(dev);
2349 int i;
2350
2351 lp->tx_full = 0;
2352 lp->cur_rx = lp->cur_tx = 0;
2353 lp->dirty_rx = lp->dirty_tx = 0;
2354
2355 for (i = 0; i < lp->rx_ring_size; i++) {
2356 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2357 if (rx_skbuff == NULL) {
2358 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2359 rx_skbuff = lp->rx_skbuff[i];
2360 if (!rx_skbuff) {
2361 /* there is not much we can do at this point */
2362 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2363 __func__);
2364 return -1;
2365 }
2366 skb_reserve(rx_skbuff, NET_IP_ALIGN);
2367 }
2368
2369 rmb();
2370 if (lp->rx_dma_addr[i] == 0) {
2371 lp->rx_dma_addr[i] =
2372 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,
2373 PKT_BUF_SIZE, DMA_FROM_DEVICE);
2374 if (dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i])) {
2375 /* there is not much we can do at this point */
2376 netif_err(lp, drv, dev,
2377 "%s pci dma mapping error\n",
2378 __func__);
2379 return -1;
2380 }
2381 }
2382 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2383 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2384 wmb(); /* Make sure owner changes after all others are visible */
2385 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2386 }
2387 /* The Tx buffer address is filled in as needed, but we do need to clear
2388 * the upper ownership bit. */
2389 for (i = 0; i < lp->tx_ring_size; i++) {
2390 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2391 wmb(); /* Make sure adapter sees owner change */
2392 lp->tx_ring[i].base = 0;
2393 lp->tx_dma_addr[i] = 0;
2394 }
2395
2396 lp->init_block->tlen_rlen =
2397 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2398 for (i = 0; i < 6; i++)
2399 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2400 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2401 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2402 wmb(); /* Make sure all changes are visible */
2403 return 0;
2404 }
2405
2406 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2407 * then flush the pending transmit operations, re-initialize the ring,
2408 * and tell the chip to initialize.
2409 */
2410 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2411 {
2412 struct pcnet32_private *lp = netdev_priv(dev);
2413 unsigned long ioaddr = dev->base_addr;
2414 int i;
2415
2416 /* wait for stop */
2417 for (i = 0; i < 100; i++)
2418 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2419 break;
2420
2421 if (i >= 100)
2422 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2423 __func__);
2424
2425 pcnet32_purge_tx_ring(dev);
2426 if (pcnet32_init_ring(dev))
2427 return;
2428
2429 /* ReInit Ring */
2430 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2431 i = 0;
2432 while (i++ < 1000)
2433 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2434 break;
2435
2436 lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2437 }
2438
2439 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue)
2440 {
2441 struct pcnet32_private *lp = netdev_priv(dev);
2442 unsigned long ioaddr = dev->base_addr, flags;
2443
2444 spin_lock_irqsave(&lp->lock, flags);
2445 /* Transmitter timeout, serious problems. */
2446 if (pcnet32_debug & NETIF_MSG_DRV)
2447 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2448 dev->name, lp->a->read_csr(ioaddr, CSR0));
2449 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2450 dev->stats.tx_errors++;
2451 if (netif_msg_tx_err(lp)) {
2452 int i;
2453 printk(KERN_DEBUG
2454 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2455 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2456 lp->cur_rx);
2457 for (i = 0; i < lp->rx_ring_size; i++)
2458 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2459 le32_to_cpu(lp->rx_ring[i].base),
2460 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2461 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2462 le16_to_cpu(lp->rx_ring[i].status));
2463 for (i = 0; i < lp->tx_ring_size; i++)
2464 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2465 le32_to_cpu(lp->tx_ring[i].base),
2466 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2467 le32_to_cpu(lp->tx_ring[i].misc),
2468 le16_to_cpu(lp->tx_ring[i].status));
2469 printk("\n");
2470 }
2471 pcnet32_restart(dev, CSR0_NORMAL);
2472
2473 netif_trans_update(dev); /* prevent tx timeout */
2474 netif_wake_queue(dev);
2475
2476 spin_unlock_irqrestore(&lp->lock, flags);
2477 }
2478
2479 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2480 struct net_device *dev)
2481 {
2482 struct pcnet32_private *lp = netdev_priv(dev);
2483 unsigned long ioaddr = dev->base_addr;
2484 u16 status;
2485 int entry;
2486 unsigned long flags;
2487
2488 spin_lock_irqsave(&lp->lock, flags);
2489
2490 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2491 "%s() called, csr0 %4.4x\n",
2492 __func__, lp->a->read_csr(ioaddr, CSR0));
2493
2494 /* Default status -- will not enable Successful-TxDone
2495 * interrupt when that option is available to us.
2496 */
2497 status = 0x8300;
2498
2499 /* Fill in a Tx ring entry */
2500
2501 /* Mask to ring buffer boundary. */
2502 entry = lp->cur_tx & lp->tx_mod_mask;
2503
2504 /* Caution: the write order is important here, set the status
2505 * with the "ownership" bits last. */
2506
2507 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2508
2509 lp->tx_ring[entry].misc = 0x00000000;
2510
2511 lp->tx_dma_addr[entry] =
2512 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
2513 DMA_TO_DEVICE);
2514 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[entry])) {
2515 dev_kfree_skb_any(skb);
2516 dev->stats.tx_dropped++;
2517 goto drop_packet;
2518 }
2519 lp->tx_skbuff[entry] = skb;
2520 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2521 wmb(); /* Make sure owner changes after all others are visible */
2522 lp->tx_ring[entry].status = cpu_to_le16(status);
2523
2524 lp->cur_tx++;
2525 dev->stats.tx_bytes += skb->len;
2526
2527 /* Trigger an immediate send poll. */
2528 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2529
2530 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2531 lp->tx_full = 1;
2532 netif_stop_queue(dev);
2533 }
2534 drop_packet:
2535 spin_unlock_irqrestore(&lp->lock, flags);
2536 return NETDEV_TX_OK;
2537 }
2538
2539 /* The PCNET32 interrupt handler. */
2540 static irqreturn_t
2541 pcnet32_interrupt(int irq, void *dev_id)
2542 {
2543 struct net_device *dev = dev_id;
2544 struct pcnet32_private *lp;
2545 unsigned long ioaddr;
2546 u16 csr0;
2547 int boguscnt = max_interrupt_work;
2548
2549 ioaddr = dev->base_addr;
2550 lp = netdev_priv(dev);
2551
2552 spin_lock(&lp->lock);
2553
2554 csr0 = lp->a->read_csr(ioaddr, CSR0);
2555 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2556 if (csr0 == 0xffff)
2557 break; /* PCMCIA remove happened */
2558 /* Acknowledge all of the current interrupt sources ASAP. */
2559 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2560
2561 netif_printk(lp, intr, KERN_DEBUG, dev,
2562 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
2563 csr0, lp->a->read_csr(ioaddr, CSR0));
2564
2565 /* Log misc errors. */
2566 if (csr0 & 0x4000)
2567 dev->stats.tx_errors++; /* Tx babble. */
2568 if (csr0 & 0x1000) {
2569 /*
2570 * This happens when our receive ring is full. This
2571 * shouldn't be a problem as we will see normal rx
2572 * interrupts for the frames in the receive ring. But
2573 * there are some PCI chipsets (I can reproduce this
2574 * on SP3G with Intel saturn chipset) which have
2575 * sometimes problems and will fill up the receive
2576 * ring with error descriptors. In this situation we
2577 * don't get a rx interrupt, but a missed frame
2578 * interrupt sooner or later.
2579 */
2580 dev->stats.rx_errors++; /* Missed a Rx frame. */
2581 }
2582 if (csr0 & 0x0800) {
2583 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2584 csr0);
2585 /* unlike for the lance, there is no restart needed */
2586 }
2587 if (napi_schedule_prep(&lp->napi)) {
2588 u16 val;
2589 /* set interrupt masks */
2590 val = lp->a->read_csr(ioaddr, CSR3);
2591 val |= 0x5f00;
2592 lp->a->write_csr(ioaddr, CSR3, val);
2593
2594 __napi_schedule(&lp->napi);
2595 break;
2596 }
2597 csr0 = lp->a->read_csr(ioaddr, CSR0);
2598 }
2599
2600 netif_printk(lp, intr, KERN_DEBUG, dev,
2601 "exiting interrupt, csr0=%#4.4x\n",
2602 lp->a->read_csr(ioaddr, CSR0));
2603
2604 spin_unlock(&lp->lock);
2605
2606 return IRQ_HANDLED;
2607 }
2608
2609 static int pcnet32_close(struct net_device *dev)
2610 {
2611 unsigned long ioaddr = dev->base_addr;
2612 struct pcnet32_private *lp = netdev_priv(dev);
2613 unsigned long flags;
2614
2615 del_timer_sync(&lp->watchdog_timer);
2616
2617 netif_stop_queue(dev);
2618 napi_disable(&lp->napi);
2619
2620 spin_lock_irqsave(&lp->lock, flags);
2621
2622 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2623
2624 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2625 "Shutting down ethercard, status was %2.2x\n",
2626 lp->a->read_csr(ioaddr, CSR0));
2627
2628 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2629 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2630
2631 /*
2632 * Switch back to 16bit mode to avoid problems with dumb
2633 * DOS packet driver after a warm reboot
2634 */
2635 lp->a->write_bcr(ioaddr, 20, 4);
2636
2637 spin_unlock_irqrestore(&lp->lock, flags);
2638
2639 free_irq(dev->irq, dev);
2640
2641 spin_lock_irqsave(&lp->lock, flags);
2642
2643 pcnet32_purge_rx_ring(dev);
2644 pcnet32_purge_tx_ring(dev);
2645
2646 spin_unlock_irqrestore(&lp->lock, flags);
2647
2648 return 0;
2649 }
2650
2651 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2652 {
2653 struct pcnet32_private *lp = netdev_priv(dev);
2654 unsigned long ioaddr = dev->base_addr;
2655 unsigned long flags;
2656
2657 spin_lock_irqsave(&lp->lock, flags);
2658 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2659 spin_unlock_irqrestore(&lp->lock, flags);
2660
2661 return &dev->stats;
2662 }
2663
2664 /* taken from the sunlance driver, which it took from the depca driver */
2665 static void pcnet32_load_multicast(struct net_device *dev)
2666 {
2667 struct pcnet32_private *lp = netdev_priv(dev);
2668 volatile struct pcnet32_init_block *ib = lp->init_block;
2669 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2670 struct netdev_hw_addr *ha;
2671 unsigned long ioaddr = dev->base_addr;
2672 int i;
2673 u32 crc;
2674
2675 /* set all multicast bits */
2676 if (dev->flags & IFF_ALLMULTI) {
2677 ib->filter[0] = cpu_to_le32(~0U);
2678 ib->filter[1] = cpu_to_le32(~0U);
2679 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2680 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2681 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2682 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2683 return;
2684 }
2685 /* clear the multicast filter */
2686 ib->filter[0] = 0;
2687 ib->filter[1] = 0;
2688
2689 /* Add addresses */
2690 netdev_for_each_mc_addr(ha, dev) {
2691 crc = ether_crc_le(6, ha->addr);
2692 crc = crc >> 26;
2693 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2694 }
2695 for (i = 0; i < 4; i++)
2696 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2697 le16_to_cpu(mcast_table[i]));
2698 }
2699
2700 /*
2701 * Set or clear the multicast filter for this adaptor.
2702 */
2703 static void pcnet32_set_multicast_list(struct net_device *dev)
2704 {
2705 unsigned long ioaddr = dev->base_addr, flags;
2706 struct pcnet32_private *lp = netdev_priv(dev);
2707 int csr15, suspended;
2708
2709 spin_lock_irqsave(&lp->lock, flags);
2710 suspended = pcnet32_suspend(dev, &flags, 0);
2711 csr15 = lp->a->read_csr(ioaddr, CSR15);
2712 if (dev->flags & IFF_PROMISC) {
2713 /* Log any net taps. */
2714 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2715 lp->init_block->mode =
2716 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2717 7);
2718 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2719 } else {
2720 lp->init_block->mode =
2721 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2722 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2723 pcnet32_load_multicast(dev);
2724 }
2725
2726 if (suspended) {
2727 pcnet32_clr_suspend(lp, ioaddr);
2728 } else {
2729 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2730 pcnet32_restart(dev, CSR0_NORMAL);
2731 netif_wake_queue(dev);
2732 }
2733
2734 spin_unlock_irqrestore(&lp->lock, flags);
2735 }
2736
2737 /* This routine assumes that the lp->lock is held */
2738 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2739 {
2740 struct pcnet32_private *lp = netdev_priv(dev);
2741 unsigned long ioaddr = dev->base_addr;
2742 u16 val_out;
2743
2744 if (!lp->mii)
2745 return 0;
2746
2747 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2748 val_out = lp->a->read_bcr(ioaddr, 34);
2749
2750 return val_out;
2751 }
2752
2753 /* This routine assumes that the lp->lock is held */
2754 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2755 {
2756 struct pcnet32_private *lp = netdev_priv(dev);
2757 unsigned long ioaddr = dev->base_addr;
2758
2759 if (!lp->mii)
2760 return;
2761
2762 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2763 lp->a->write_bcr(ioaddr, 34, val);
2764 }
2765
2766 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2767 {
2768 struct pcnet32_private *lp = netdev_priv(dev);
2769 int rc;
2770 unsigned long flags;
2771
2772 /* SIOC[GS]MIIxxx ioctls */
2773 if (lp->mii) {
2774 spin_lock_irqsave(&lp->lock, flags);
2775 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2776 spin_unlock_irqrestore(&lp->lock, flags);
2777 } else {
2778 rc = -EOPNOTSUPP;
2779 }
2780
2781 return rc;
2782 }
2783
2784 static int pcnet32_check_otherphy(struct net_device *dev)
2785 {
2786 struct pcnet32_private *lp = netdev_priv(dev);
2787 struct mii_if_info mii = lp->mii_if;
2788 u16 bmcr;
2789 int i;
2790
2791 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2792 if (i == lp->mii_if.phy_id)
2793 continue; /* skip active phy */
2794 if (lp->phymask & (1 << i)) {
2795 mii.phy_id = i;
2796 if (mii_link_ok(&mii)) {
2797 /* found PHY with active link */
2798 netif_info(lp, link, dev, "Using PHY number %d\n",
2799 i);
2800
2801 /* isolate inactive phy */
2802 bmcr =
2803 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2804 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2805 bmcr | BMCR_ISOLATE);
2806
2807 /* de-isolate new phy */
2808 bmcr = mdio_read(dev, i, MII_BMCR);
2809 mdio_write(dev, i, MII_BMCR,
2810 bmcr & ~BMCR_ISOLATE);
2811
2812 /* set new phy address */
2813 lp->mii_if.phy_id = i;
2814 return 1;
2815 }
2816 }
2817 }
2818 return 0;
2819 }
2820
2821 /*
2822 * Show the status of the media. Similar to mii_check_media however it
2823 * correctly shows the link speed for all (tested) pcnet32 variants.
2824 * Devices with no mii just report link state without speed.
2825 *
2826 * Caller is assumed to hold and release the lp->lock.
2827 */
2828
2829 static void pcnet32_check_media(struct net_device *dev, int verbose)
2830 {
2831 struct pcnet32_private *lp = netdev_priv(dev);
2832 int curr_link;
2833 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2834 u32 bcr9;
2835
2836 if (lp->mii) {
2837 curr_link = mii_link_ok(&lp->mii_if);
2838 } else if (lp->chip_version == PCNET32_79C970A) {
2839 ulong ioaddr = dev->base_addr; /* card base I/O address */
2840 /* only read link if port is set to TP */
2841 if (!lp->autoneg && lp->port_tp)
2842 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2843 else /* link always up for AUI port or port auto select */
2844 curr_link = 1;
2845 } else {
2846 ulong ioaddr = dev->base_addr; /* card base I/O address */
2847 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2848 }
2849 if (!curr_link) {
2850 if (prev_link || verbose) {
2851 netif_carrier_off(dev);
2852 netif_info(lp, link, dev, "link down\n");
2853 }
2854 if (lp->phycount > 1) {
2855 curr_link = pcnet32_check_otherphy(dev);
2856 prev_link = 0;
2857 }
2858 } else if (verbose || !prev_link) {
2859 netif_carrier_on(dev);
2860 if (lp->mii) {
2861 if (netif_msg_link(lp)) {
2862 struct ethtool_cmd ecmd = {
2863 .cmd = ETHTOOL_GSET };
2864 mii_ethtool_gset(&lp->mii_if, &ecmd);
2865 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2866 ethtool_cmd_speed(&ecmd),
2867 (ecmd.duplex == DUPLEX_FULL)
2868 ? "full" : "half");
2869 }
2870 bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2871 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2872 if (lp->mii_if.full_duplex)
2873 bcr9 |= (1 << 0);
2874 else
2875 bcr9 &= ~(1 << 0);
2876 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2877 }
2878 } else {
2879 netif_info(lp, link, dev, "link up\n");
2880 }
2881 }
2882 }
2883
2884 /*
2885 * Check for loss of link and link establishment.
2886 * Could possibly be changed to use mii_check_media instead.
2887 */
2888
2889 static void pcnet32_watchdog(struct timer_list *t)
2890 {
2891 struct pcnet32_private *lp = from_timer(lp, t, watchdog_timer);
2892 struct net_device *dev = lp->dev;
2893 unsigned long flags;
2894
2895 /* Print the link status if it has changed */
2896 spin_lock_irqsave(&lp->lock, flags);
2897 pcnet32_check_media(dev, 0);
2898 spin_unlock_irqrestore(&lp->lock, flags);
2899
2900 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2901 }
2902
2903 static int __maybe_unused pcnet32_pm_suspend(struct device *device_d)
2904 {
2905 struct net_device *dev = dev_get_drvdata(device_d);
2906
2907 if (netif_running(dev)) {
2908 netif_device_detach(dev);
2909 pcnet32_close(dev);
2910 }
2911
2912 return 0;
2913 }
2914
2915 static int __maybe_unused pcnet32_pm_resume(struct device *device_d)
2916 {
2917 struct net_device *dev = dev_get_drvdata(device_d);
2918
2919 if (netif_running(dev)) {
2920 pcnet32_open(dev);
2921 netif_device_attach(dev);
2922 }
2923
2924 return 0;
2925 }
2926
2927 static void pcnet32_remove_one(struct pci_dev *pdev)
2928 {
2929 struct net_device *dev = pci_get_drvdata(pdev);
2930
2931 if (dev) {
2932 struct pcnet32_private *lp = netdev_priv(dev);
2933
2934 unregister_netdev(dev);
2935 pcnet32_free_ring(dev);
2936 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2937 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
2938 lp->init_block, lp->init_dma_addr);
2939 free_netdev(dev);
2940 pci_disable_device(pdev);
2941 }
2942 }
2943
2944 static SIMPLE_DEV_PM_OPS(pcnet32_pm_ops, pcnet32_pm_suspend, pcnet32_pm_resume);
2945
2946 static struct pci_driver pcnet32_driver = {
2947 .name = DRV_NAME,
2948 .probe = pcnet32_probe_pci,
2949 .remove = pcnet32_remove_one,
2950 .id_table = pcnet32_pci_tbl,
2951 .driver = {
2952 .pm = &pcnet32_pm_ops,
2953 },
2954 };
2955
2956 /* An additional parameter that may be passed in... */
2957 static int debug = -1;
2958 static int tx_start_pt = -1;
2959 static int pcnet32_have_pci;
2960
2961 module_param(debug, int, 0);
2962 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2963 module_param(max_interrupt_work, int, 0);
2964 MODULE_PARM_DESC(max_interrupt_work,
2965 DRV_NAME " maximum events handled per interrupt");
2966 module_param(rx_copybreak, int, 0);
2967 MODULE_PARM_DESC(rx_copybreak,
2968 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2969 module_param(tx_start_pt, int, 0);
2970 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2971 module_param(pcnet32vlb, int, 0);
2972 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2973 module_param_array(options, int, NULL, 0);
2974 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2975 module_param_array(full_duplex, int, NULL, 0);
2976 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2977 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2978 module_param_array(homepna, int, NULL, 0);
2979 MODULE_PARM_DESC(homepna,
2980 DRV_NAME
2981 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2982
2983 MODULE_AUTHOR("Thomas Bogendoerfer");
2984 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2985 MODULE_LICENSE("GPL");
2986
2987 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2988
2989 static int __init pcnet32_init_module(void)
2990 {
2991 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2992
2993 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2994 tx_start = tx_start_pt;
2995
2996 /* find the PCI devices */
2997 if (!pci_register_driver(&pcnet32_driver))
2998 pcnet32_have_pci = 1;
2999
3000 /* should we find any remaining VLbus devices ? */
3001 if (pcnet32vlb)
3002 pcnet32_probe_vlbus(pcnet32_portlist);
3003
3004 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3005 pr_info("%d cards_found\n", cards_found);
3006
3007 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3008 }
3009
3010 static void __exit pcnet32_cleanup_module(void)
3011 {
3012 struct net_device *next_dev;
3013
3014 while (pcnet32_dev) {
3015 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3016 next_dev = lp->next;
3017 unregister_netdev(pcnet32_dev);
3018 pcnet32_free_ring(pcnet32_dev);
3019 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3020 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
3021 lp->init_block, lp->init_dma_addr);
3022 free_netdev(pcnet32_dev);
3023 pcnet32_dev = next_dev;
3024 }
3025
3026 if (pcnet32_have_pci)
3027 pci_unregister_driver(&pcnet32_driver);
3028 }
3029
3030 module_init(pcnet32_init_module);
3031 module_exit(pcnet32_cleanup_module);
3032
3033 /*
3034 * Local variables:
3035 * c-indent-level: 4
3036 * tab-width: 8
3037 * End:
3038 */
Linux with added FPC-III support