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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_hsi.h
blob2d3e962bdac34138b464e9811ddbc6e9fdb483ae
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2014-2018 Broadcom Limited
5 * Copyright (c) 2018-2020 Broadcom Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * DO NOT MODIFY!!! This file is automatically generated.
12 */
13
14 #ifndef _BNXT_HSI_H_
15 #define _BNXT_HSI_H_
16
17 /* hwrm_cmd_hdr (size:128b/16B) */
18 struct hwrm_cmd_hdr {
19 __le16 req_type;
20 __le16 cmpl_ring;
21 __le16 seq_id;
22 __le16 target_id;
23 __le64 resp_addr;
24 };
25
26 /* hwrm_resp_hdr (size:64b/8B) */
27 struct hwrm_resp_hdr {
28 __le16 error_code;
29 __le16 req_type;
30 __le16 seq_id;
31 __le16 resp_len;
32 };
33
34 #define CMD_DISCR_TLV_ENCAP 0x8000UL
35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
36
37
38 #define TLV_TYPE_HWRM_REQUEST 0x1UL
39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
53
54
55 /* tlv (size:64b/8B) */
56 struct tlv {
57 __le16 cmd_discr;
58 u8 reserved_8b;
59 u8 flags;
60 #define TLV_FLAGS_MORE 0x1UL
61 #define TLV_FLAGS_MORE_LAST 0x0UL
62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
63 #define TLV_FLAGS_REQUIRED 0x2UL
64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
67 __le16 tlv_type;
68 __le16 length;
69 };
70
71 /* input (size:128b/16B) */
72 struct input {
73 __le16 req_type;
74 __le16 cmpl_ring;
75 __le16 seq_id;
76 __le16 target_id;
77 __le64 resp_addr;
78 };
79
80 /* output (size:64b/8B) */
81 struct output {
82 __le16 error_code;
83 __le16 req_type;
84 __le16 seq_id;
85 __le16 resp_len;
86 };
87
88 /* hwrm_short_input (size:128b/16B) */
89 struct hwrm_short_input {
90 __le16 req_type;
91 __le16 signature;
92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
94 __le16 target_id;
95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
98 __le16 size;
99 __le64 req_addr;
100 };
101
102 /* cmd_nums (size:64b/8B) */
103 struct cmd_nums {
104 __le16 req_type;
105 #define HWRM_VER_GET 0x0UL
106 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL
107 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
108 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
109 #define HWRM_FUNC_VF_CFG 0xfUL
110 #define HWRM_RESERVED1 0x10UL
111 #define HWRM_FUNC_RESET 0x11UL
112 #define HWRM_FUNC_GETFID 0x12UL
113 #define HWRM_FUNC_VF_ALLOC 0x13UL
114 #define HWRM_FUNC_VF_FREE 0x14UL
115 #define HWRM_FUNC_QCAPS 0x15UL
116 #define HWRM_FUNC_QCFG 0x16UL
117 #define HWRM_FUNC_CFG 0x17UL
118 #define HWRM_FUNC_QSTATS 0x18UL
119 #define HWRM_FUNC_CLR_STATS 0x19UL
120 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
121 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
122 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
123 #define HWRM_FUNC_DRV_RGTR 0x1dUL
124 #define HWRM_FUNC_DRV_QVER 0x1eUL
125 #define HWRM_FUNC_BUF_RGTR 0x1fUL
126 #define HWRM_PORT_PHY_CFG 0x20UL
127 #define HWRM_PORT_MAC_CFG 0x21UL
128 #define HWRM_PORT_TS_QUERY 0x22UL
129 #define HWRM_PORT_QSTATS 0x23UL
130 #define HWRM_PORT_LPBK_QSTATS 0x24UL
131 #define HWRM_PORT_CLR_STATS 0x25UL
132 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
133 #define HWRM_PORT_PHY_QCFG 0x27UL
134 #define HWRM_PORT_MAC_QCFG 0x28UL
135 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
136 #define HWRM_PORT_PHY_QCAPS 0x2aUL
137 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
138 #define HWRM_PORT_PHY_I2C_READ 0x2cUL
139 #define HWRM_PORT_LED_CFG 0x2dUL
140 #define HWRM_PORT_LED_QCFG 0x2eUL
141 #define HWRM_PORT_LED_QCAPS 0x2fUL
142 #define HWRM_QUEUE_QPORTCFG 0x30UL
143 #define HWRM_QUEUE_QCFG 0x31UL
144 #define HWRM_QUEUE_CFG 0x32UL
145 #define HWRM_FUNC_VLAN_CFG 0x33UL
146 #define HWRM_FUNC_VLAN_QCFG 0x34UL
147 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
148 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
149 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
150 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
151 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
152 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
153 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
154 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
155 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
156 #define HWRM_VNIC_ALLOC 0x40UL
157 #define HWRM_VNIC_FREE 0x41UL
158 #define HWRM_VNIC_CFG 0x42UL
159 #define HWRM_VNIC_QCFG 0x43UL
160 #define HWRM_VNIC_TPA_CFG 0x44UL
161 #define HWRM_VNIC_TPA_QCFG 0x45UL
162 #define HWRM_VNIC_RSS_CFG 0x46UL
163 #define HWRM_VNIC_RSS_QCFG 0x47UL
164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL
165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
166 #define HWRM_VNIC_QCAPS 0x4aUL
167 #define HWRM_RING_ALLOC 0x50UL
168 #define HWRM_RING_FREE 0x51UL
169 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
170 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
171 #define HWRM_RING_AGGINT_QCAPS 0x54UL
172 #define HWRM_RING_SCHQ_ALLOC 0x55UL
173 #define HWRM_RING_SCHQ_CFG 0x56UL
174 #define HWRM_RING_SCHQ_FREE 0x57UL
175 #define HWRM_RING_RESET 0x5eUL
176 #define HWRM_RING_GRP_ALLOC 0x60UL
177 #define HWRM_RING_GRP_FREE 0x61UL
178 #define HWRM_RING_CFG 0x62UL
179 #define HWRM_RING_QCFG 0x63UL
180 #define HWRM_RESERVED5 0x64UL
181 #define HWRM_RESERVED6 0x65UL
182 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
183 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
184 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL
185 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL
186 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL
187 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
188 #define HWRM_CFA_L2_FILTER_FREE 0x91UL
189 #define HWRM_CFA_L2_FILTER_CFG 0x92UL
190 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
191 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
192 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
193 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
194 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
195 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
196 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
197 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
198 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
199 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
200 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
201 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
202 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
203 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
204 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
205 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
206 #define HWRM_STAT_CTX_ALLOC 0xb0UL
207 #define HWRM_STAT_CTX_FREE 0xb1UL
208 #define HWRM_STAT_CTX_QUERY 0xb2UL
209 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
210 #define HWRM_PORT_QSTATS_EXT 0xb4UL
211 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
212 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL
213 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
214 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
215 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL
216 #define HWRM_RESERVED7 0xbaUL
217 #define HWRM_PORT_TX_FIR_CFG 0xbbUL
218 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL
219 #define HWRM_PORT_ECN_QSTATS 0xbdUL
220 #define HWRM_FW_RESET 0xc0UL
221 #define HWRM_FW_QSTATUS 0xc1UL
222 #define HWRM_FW_HEALTH_CHECK 0xc2UL
223 #define HWRM_FW_SYNC 0xc3UL
224 #define HWRM_FW_STATE_QCAPS 0xc4UL
225 #define HWRM_FW_STATE_QUIESCE 0xc5UL
226 #define HWRM_FW_STATE_BACKUP 0xc6UL
227 #define HWRM_FW_STATE_RESTORE 0xc7UL
228 #define HWRM_FW_SET_TIME 0xc8UL
229 #define HWRM_FW_GET_TIME 0xc9UL
230 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
231 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
232 #define HWRM_FW_IPC_MAILBOX 0xccUL
233 #define HWRM_FW_ECN_CFG 0xcdUL
234 #define HWRM_FW_ECN_QCFG 0xceUL
235 #define HWRM_FW_SECURE_CFG 0xcfUL
236 #define HWRM_EXEC_FWD_RESP 0xd0UL
237 #define HWRM_REJECT_FWD_RESP 0xd1UL
238 #define HWRM_FWD_RESP 0xd2UL
239 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
240 #define HWRM_OEM_CMD 0xd4UL
241 #define HWRM_PORT_PRBS_TEST 0xd5UL
242 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
243 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
244 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL
245 #define HWRM_PORT_DSC_DUMP 0xd9UL
246 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
247 #define HWRM_REG_POWER_QUERY 0xe1UL
248 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
249 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL
250 #define HWRM_WOL_FILTER_ALLOC 0xf0UL
251 #define HWRM_WOL_FILTER_FREE 0xf1UL
252 #define HWRM_WOL_FILTER_QCFG 0xf2UL
253 #define HWRM_WOL_REASON_QCFG 0xf3UL
254 #define HWRM_CFA_METER_QCAPS 0xf4UL
255 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
256 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
257 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
258 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
259 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
260 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
261 #define HWRM_CFA_VFR_ALLOC 0xfdUL
262 #define HWRM_CFA_VFR_FREE 0xfeUL
263 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
264 #define HWRM_CFA_VF_PAIR_FREE 0x101UL
265 #define HWRM_CFA_VF_PAIR_INFO 0x102UL
266 #define HWRM_CFA_FLOW_ALLOC 0x103UL
267 #define HWRM_CFA_FLOW_FREE 0x104UL
268 #define HWRM_CFA_FLOW_FLUSH 0x105UL
269 #define HWRM_CFA_FLOW_STATS 0x106UL
270 #define HWRM_CFA_FLOW_INFO 0x107UL
271 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
272 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
273 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
274 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
275 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
276 #define HWRM_CFA_PAIR_ALLOC 0x10dUL
277 #define HWRM_CFA_PAIR_FREE 0x10eUL
278 #define HWRM_CFA_PAIR_INFO 0x10fUL
279 #define HWRM_FW_IPC_MSG 0x110UL
280 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
281 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
282 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
283 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
284 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
285 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
286 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL
287 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
288 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL
289 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
290 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL
291 #define HWRM_CFA_COUNTER_CFG 0x11cUL
292 #define HWRM_CFA_COUNTER_QCFG 0x11dUL
293 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL
294 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
295 #define HWRM_CFA_EEM_QCAPS 0x120UL
296 #define HWRM_CFA_EEM_CFG 0x121UL
297 #define HWRM_CFA_EEM_QCFG 0x122UL
298 #define HWRM_CFA_EEM_OP 0x123UL
299 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
300 #define HWRM_CFA_TFLIB 0x125UL
301 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
302 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
303 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
304 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
305 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
306 #define HWRM_ENGINE_CKV_FLUSH 0x133UL
307 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
308 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
309 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
310 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL
311 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
312 #define HWRM_ENGINE_QG_QUERY 0x13dUL
313 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
314 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
315 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
316 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
317 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
318 #define HWRM_ENGINE_QG_METER_BIND 0x143UL
319 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
320 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
321 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
322 #define HWRM_ENGINE_SG_QUERY 0x147UL
323 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
324 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
325 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
326 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
327 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
328 #define HWRM_ENGINE_STATS_CONFIG 0x155UL
329 #define HWRM_ENGINE_STATS_CLEAR 0x156UL
330 #define HWRM_ENGINE_STATS_QUERY 0x157UL
331 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL
332 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
333 #define HWRM_ENGINE_RQ_FREE 0x15fUL
334 #define HWRM_ENGINE_CQ_ALLOC 0x160UL
335 #define HWRM_ENGINE_CQ_FREE 0x161UL
336 #define HWRM_ENGINE_NQ_ALLOC 0x162UL
337 #define HWRM_ENGINE_NQ_FREE 0x163UL
338 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
339 #define HWRM_ENGINE_FUNC_QCFG 0x165UL
340 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
341 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
342 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
343 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
344 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
345 #define HWRM_FUNC_VF_BW_CFG 0x195UL
346 #define HWRM_FUNC_VF_BW_QCFG 0x196UL
347 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL
348 #define HWRM_FUNC_QSTATS_EXT 0x198UL
349 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL
350 #define HWRM_SELFTEST_QLIST 0x200UL
351 #define HWRM_SELFTEST_EXEC 0x201UL
352 #define HWRM_SELFTEST_IRQ 0x202UL
353 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
354 #define HWRM_PCIE_QSTATS 0x204UL
355 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL
356 #define HWRM_MFG_TIMERS_QUERY 0x206UL
357 #define HWRM_MFG_OTP_CFG 0x207UL
358 #define HWRM_MFG_OTP_QCFG 0x208UL
359 #define HWRM_MFG_HDMA_TEST 0x209UL
360 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL
361 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL
362 #define HWRM_TF 0x2bcUL
363 #define HWRM_TF_VERSION_GET 0x2bdUL
364 #define HWRM_TF_SESSION_OPEN 0x2c6UL
365 #define HWRM_TF_SESSION_ATTACH 0x2c7UL
366 #define HWRM_TF_SESSION_REGISTER 0x2c8UL
367 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL
368 #define HWRM_TF_SESSION_CLOSE 0x2caUL
369 #define HWRM_TF_SESSION_QCFG 0x2cbUL
370 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL
371 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL
372 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL
373 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL
374 #define HWRM_TF_TBL_TYPE_GET 0x2daUL
375 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL
376 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL
377 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL
378 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL
379 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL
380 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL
381 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL
382 #define HWRM_TF_EXT_EM_OP 0x2e7UL
383 #define HWRM_TF_EXT_EM_CFG 0x2e8UL
384 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL
385 #define HWRM_TF_EM_INSERT 0x2eaUL
386 #define HWRM_TF_EM_DELETE 0x2ebUL
387 #define HWRM_TF_TCAM_SET 0x2f8UL
388 #define HWRM_TF_TCAM_GET 0x2f9UL
389 #define HWRM_TF_TCAM_MOVE 0x2faUL
390 #define HWRM_TF_TCAM_FREE 0x2fbUL
391 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL
392 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL
393 #define HWRM_TF_IF_TBL_SET 0x2feUL
394 #define HWRM_TF_IF_TBL_GET 0x2ffUL
395 #define HWRM_SV 0x400UL
396 #define HWRM_DBG_READ_DIRECT 0xff10UL
397 #define HWRM_DBG_READ_INDIRECT 0xff11UL
398 #define HWRM_DBG_WRITE_DIRECT 0xff12UL
399 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
400 #define HWRM_DBG_DUMP 0xff14UL
401 #define HWRM_DBG_ERASE_NVM 0xff15UL
402 #define HWRM_DBG_CFG 0xff16UL
403 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
404 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
405 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
406 #define HWRM_DBG_FW_CLI 0xff1aUL
407 #define HWRM_DBG_I2C_CMD 0xff1bUL
408 #define HWRM_DBG_RING_INFO_GET 0xff1cUL
409 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL
410 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL
411 #define HWRM_DBG_DRV_TRACE 0xff1fUL
412 #define HWRM_DBG_QCAPS 0xff20UL
413 #define HWRM_DBG_QCFG 0xff21UL
414 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL
415 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL
416 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
417 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
418 #define HWRM_NVM_FLUSH 0xfff0UL
419 #define HWRM_NVM_GET_VARIABLE 0xfff1UL
420 #define HWRM_NVM_SET_VARIABLE 0xfff2UL
421 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
422 #define HWRM_NVM_MODIFY 0xfff4UL
423 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
424 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
425 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
426 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
427 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
428 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
429 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
430 #define HWRM_NVM_RAW_DUMP 0xfffcUL
431 #define HWRM_NVM_READ 0xfffdUL
432 #define HWRM_NVM_WRITE 0xfffeUL
433 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
434 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
435 __le16 unused_0[3];
436 };
437
438 /* ret_codes (size:64b/8B) */
439 struct ret_codes {
440 __le16 error_code;
441 #define HWRM_ERR_CODE_SUCCESS 0x0UL
442 #define HWRM_ERR_CODE_FAIL 0x1UL
443 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
444 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
445 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
446 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
447 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
448 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
449 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
450 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
451 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
452 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
453 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
454 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL
455 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL
456 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
457 #define HWRM_ERR_CODE_BUSY 0x10UL
458 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL
459 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
460 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
461 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
462 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
463 __le16 unused_0[3];
464 };
465
466 /* hwrm_err_output (size:128b/16B) */
467 struct hwrm_err_output {
468 __le16 error_code;
469 __le16 req_type;
470 __le16 seq_id;
471 __le16 resp_len;
472 __le32 opaque_0;
473 __le16 opaque_1;
474 u8 cmd_err;
475 u8 valid;
476 };
477 #define HWRM_NA_SIGNATURE ((__le32)(-1))
478 #define HWRM_MAX_REQ_LEN 128
479 #define HWRM_MAX_RESP_LEN 704
480 #define HW_HASH_INDEX_SIZE 0x80
481 #define HW_HASH_KEY_SIZE 40
482 #define HWRM_RESP_VALID_KEY 1
483 #define HWRM_TARGET_ID_BONO 0xFFF8
484 #define HWRM_TARGET_ID_KONG 0xFFF9
485 #define HWRM_TARGET_ID_APE 0xFFFA
486 #define HWRM_TARGET_ID_TOOLS 0xFFFD
487 #define HWRM_VERSION_MAJOR 1
488 #define HWRM_VERSION_MINOR 10
489 #define HWRM_VERSION_UPDATE 1
490 #define HWRM_VERSION_RSVD 68
491 #define HWRM_VERSION_STR "1.10.1.68"
492
493 /* hwrm_ver_get_input (size:192b/24B) */
494 struct hwrm_ver_get_input {
495 __le16 req_type;
496 __le16 cmpl_ring;
497 __le16 seq_id;
498 __le16 target_id;
499 __le64 resp_addr;
500 u8 hwrm_intf_maj;
501 u8 hwrm_intf_min;
502 u8 hwrm_intf_upd;
503 u8 unused_0[5];
504 };
505
506 /* hwrm_ver_get_output (size:1408b/176B) */
507 struct hwrm_ver_get_output {
508 __le16 error_code;
509 __le16 req_type;
510 __le16 seq_id;
511 __le16 resp_len;
512 u8 hwrm_intf_maj_8b;
513 u8 hwrm_intf_min_8b;
514 u8 hwrm_intf_upd_8b;
515 u8 hwrm_intf_rsvd_8b;
516 u8 hwrm_fw_maj_8b;
517 u8 hwrm_fw_min_8b;
518 u8 hwrm_fw_bld_8b;
519 u8 hwrm_fw_rsvd_8b;
520 u8 mgmt_fw_maj_8b;
521 u8 mgmt_fw_min_8b;
522 u8 mgmt_fw_bld_8b;
523 u8 mgmt_fw_rsvd_8b;
524 u8 netctrl_fw_maj_8b;
525 u8 netctrl_fw_min_8b;
526 u8 netctrl_fw_bld_8b;
527 u8 netctrl_fw_rsvd_8b;
528 __le32 dev_caps_cfg;
529 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
530 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
531 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
532 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
533 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
534 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
535 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
536 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
537 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
538 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
539 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
540 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
541 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
542 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL
543 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL
544 u8 roce_fw_maj_8b;
545 u8 roce_fw_min_8b;
546 u8 roce_fw_bld_8b;
547 u8 roce_fw_rsvd_8b;
548 char hwrm_fw_name[16];
549 char mgmt_fw_name[16];
550 char netctrl_fw_name[16];
551 char active_pkg_name[16];
552 char roce_fw_name[16];
553 __le16 chip_num;
554 u8 chip_rev;
555 u8 chip_metal;
556 u8 chip_bond_id;
557 u8 chip_platform_type;
558 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
559 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
560 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
561 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
562 __le16 max_req_win_len;
563 __le16 max_resp_len;
564 __le16 def_req_timeout;
565 u8 flags;
566 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
567 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
568 u8 unused_0[2];
569 u8 always_1;
570 __le16 hwrm_intf_major;
571 __le16 hwrm_intf_minor;
572 __le16 hwrm_intf_build;
573 __le16 hwrm_intf_patch;
574 __le16 hwrm_fw_major;
575 __le16 hwrm_fw_minor;
576 __le16 hwrm_fw_build;
577 __le16 hwrm_fw_patch;
578 __le16 mgmt_fw_major;
579 __le16 mgmt_fw_minor;
580 __le16 mgmt_fw_build;
581 __le16 mgmt_fw_patch;
582 __le16 netctrl_fw_major;
583 __le16 netctrl_fw_minor;
584 __le16 netctrl_fw_build;
585 __le16 netctrl_fw_patch;
586 __le16 roce_fw_major;
587 __le16 roce_fw_minor;
588 __le16 roce_fw_build;
589 __le16 roce_fw_patch;
590 __le16 max_ext_req_len;
591 u8 unused_1[5];
592 u8 valid;
593 };
594
595 /* eject_cmpl (size:128b/16B) */
596 struct eject_cmpl {
597 __le16 type;
598 #define EJECT_CMPL_TYPE_MASK 0x3fUL
599 #define EJECT_CMPL_TYPE_SFT 0
600 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
601 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
602 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
603 #define EJECT_CMPL_FLAGS_SFT 6
604 #define EJECT_CMPL_FLAGS_ERROR 0x40UL
605 __le16 len;
606 __le32 opaque;
607 __le16 v;
608 #define EJECT_CMPL_V 0x1UL
609 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
610 #define EJECT_CMPL_ERRORS_SFT 1
611 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
612 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
613 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
614 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
615 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
616 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
617 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
618 __le16 reserved16;
619 __le32 unused_2;
620 };
621
622 /* hwrm_cmpl (size:128b/16B) */
623 struct hwrm_cmpl {
624 __le16 type;
625 #define CMPL_TYPE_MASK 0x3fUL
626 #define CMPL_TYPE_SFT 0
627 #define CMPL_TYPE_HWRM_DONE 0x20UL
628 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
629 __le16 sequence_id;
630 __le32 unused_1;
631 __le32 v;
632 #define CMPL_V 0x1UL
633 __le32 unused_3;
634 };
635
636 /* hwrm_fwd_req_cmpl (size:128b/16B) */
637 struct hwrm_fwd_req_cmpl {
638 __le16 req_len_type;
639 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
640 #define FWD_REQ_CMPL_TYPE_SFT 0
641 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
642 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
643 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
644 #define FWD_REQ_CMPL_REQ_LEN_SFT 6
645 __le16 source_id;
646 __le32 unused0;
647 __le32 req_buf_addr_v[2];
648 #define FWD_REQ_CMPL_V 0x1UL
649 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
650 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
651 };
652
653 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
654 struct hwrm_fwd_resp_cmpl {
655 __le16 type;
656 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
657 #define FWD_RESP_CMPL_TYPE_SFT 0
658 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
659 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
660 __le16 source_id;
661 __le16 resp_len;
662 __le16 unused_1;
663 __le32 resp_buf_addr_v[2];
664 #define FWD_RESP_CMPL_V 0x1UL
665 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
666 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
667 };
668
669 /* hwrm_async_event_cmpl (size:128b/16B) */
670 struct hwrm_async_event_cmpl {
671 __le16 type;
672 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
673 #define ASYNC_EVENT_CMPL_TYPE_SFT 0
674 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
675 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
676 __le16 event_id;
677 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
678 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
679 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
680 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
681 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
682 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
683 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
684 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
685 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
686 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
687 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL
688 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
689 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
690 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
691 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
692 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
693 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
694 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
695 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
696 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
697 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
698 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
699 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
700 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
701 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
702 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
703 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
704 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
705 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
706 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL
707 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL
708 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL
709 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
710 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
711 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
712 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
713 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
714 __le32 event_data2;
715 u8 opaque_v;
716 #define ASYNC_EVENT_CMPL_V 0x1UL
717 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
718 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
719 u8 timestamp_lo;
720 __le16 timestamp_hi;
721 __le32 event_data1;
722 };
723
724 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
725 struct hwrm_async_event_cmpl_link_status_change {
726 __le16 type;
727 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
728 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
729 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
730 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
731 __le16 event_id;
732 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
733 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
734 __le32 event_data2;
735 u8 opaque_v;
736 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
737 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
738 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
739 u8 timestamp_lo;
740 __le16 timestamp_hi;
741 __le32 event_data1;
742 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
743 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
744 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
745 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
746 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
747 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
748 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
749 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
750 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
751 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
752 };
753
754 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
755 struct hwrm_async_event_cmpl_port_conn_not_allowed {
756 __le16 type;
757 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
758 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
759 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
760 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
761 __le16 event_id;
762 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
763 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
764 __le32 event_data2;
765 u8 opaque_v;
766 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
767 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
768 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
769 u8 timestamp_lo;
770 __le16 timestamp_hi;
771 __le32 event_data1;
772 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
773 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
774 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
775 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
776 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
777 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
778 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
779 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
780 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
781 };
782
783 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
784 struct hwrm_async_event_cmpl_link_speed_cfg_change {
785 __le16 type;
786 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
787 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
788 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
789 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
790 __le16 event_id;
791 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
792 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
793 __le32 event_data2;
794 u8 opaque_v;
795 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
796 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
797 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
798 u8 timestamp_lo;
799 __le16 timestamp_hi;
800 __le32 event_data1;
801 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
802 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
803 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
804 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
805 };
806
807 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
808 struct hwrm_async_event_cmpl_reset_notify {
809 __le16 type;
810 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
811 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
812 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
813 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
814 __le16 event_id;
815 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
816 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
817 __le32 event_data2;
818 u8 opaque_v;
819 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
820 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
821 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
822 u8 timestamp_lo;
823 __le16 timestamp_hi;
824 __le32 event_data1;
825 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
826 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
827 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
828 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
829 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
830 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
831 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
832 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
833 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
834 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
835 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
836 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
837 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
838 };
839
840 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
841 struct hwrm_async_event_cmpl_error_recovery {
842 __le16 type;
843 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
844 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
845 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
846 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
847 __le16 event_id;
848 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
849 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
850 __le32 event_data2;
851 u8 opaque_v;
852 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
853 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
854 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
855 u8 timestamp_lo;
856 __le16 timestamp_hi;
857 __le32 event_data1;
858 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
859 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
860 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
861 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
862 };
863
864 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
865 struct hwrm_async_event_cmpl_ring_monitor_msg {
866 __le16 type;
867 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL
868 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
869 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL
870 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
871 __le16 event_id;
872 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
873 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
874 __le32 event_data2;
875 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
876 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
877 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL
878 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL
879 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL
880 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
881 u8 opaque_v;
882 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL
883 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
884 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
885 u8 timestamp_lo;
886 __le16 timestamp_hi;
887 __le32 event_data1;
888 };
889
890 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
891 struct hwrm_async_event_cmpl_vf_cfg_change {
892 __le16 type;
893 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
894 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
895 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
896 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
897 __le16 event_id;
898 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
899 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
900 __le32 event_data2;
901 u8 opaque_v;
902 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
903 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
904 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
905 u8 timestamp_lo;
906 __le16 timestamp_hi;
907 __le32 event_data1;
908 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
909 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
910 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
911 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
912 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
913 };
914
915 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
916 struct hwrm_async_event_cmpl_default_vnic_change {
917 __le16 type;
918 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
919 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
920 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
921 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
922 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
923 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
924 __le16 event_id;
925 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
926 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
927 __le32 event_data2;
928 u8 opaque_v;
929 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
930 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
931 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
932 u8 timestamp_lo;
933 __le16 timestamp_hi;
934 __le32 event_data1;
935 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
936 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
937 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
938 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
939 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
940 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
941 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
942 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
943 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
944 };
945
946 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
947 struct hwrm_async_event_cmpl_hw_flow_aged {
948 __le16 type;
949 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
950 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
951 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
952 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
953 __le16 event_id;
954 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
955 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
956 __le32 event_data2;
957 u8 opaque_v;
958 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
959 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
960 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
961 u8 timestamp_lo;
962 __le16 timestamp_hi;
963 __le32 event_data1;
964 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
965 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
966 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
967 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
968 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
969 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
970 };
971
972 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
973 struct hwrm_async_event_cmpl_eem_cache_flush_req {
974 __le16 type;
975 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
976 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
977 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
978 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
979 __le16 event_id;
980 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
981 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
982 __le32 event_data2;
983 u8 opaque_v;
984 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
985 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
986 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
987 u8 timestamp_lo;
988 __le16 timestamp_hi;
989 __le32 event_data1;
990 };
991
992 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
993 struct hwrm_async_event_cmpl_eem_cache_flush_done {
994 __le16 type;
995 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
996 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
997 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
998 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
999 __le16 event_id;
1000 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
1001 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
1002 __le32 event_data2;
1003 u8 opaque_v;
1004 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
1005 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
1006 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
1007 u8 timestamp_lo;
1008 __le16 timestamp_hi;
1009 __le32 event_data1;
1010 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
1011 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
1012 };
1013
1014 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
1015 struct hwrm_async_event_cmpl_deferred_response {
1016 __le16 type;
1017 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL
1018 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
1019 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1020 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
1021 __le16 event_id;
1022 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
1023 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
1024 __le32 event_data2;
1025 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
1026 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
1027 u8 opaque_v;
1028 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL
1029 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
1030 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
1031 u8 timestamp_lo;
1032 __le16 timestamp_hi;
1033 __le32 event_data1;
1034 };
1035
1036 /* hwrm_func_reset_input (size:192b/24B) */
1037 struct hwrm_func_reset_input {
1038 __le16 req_type;
1039 __le16 cmpl_ring;
1040 __le16 seq_id;
1041 __le16 target_id;
1042 __le64 resp_addr;
1043 __le32 enables;
1044 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
1045 __le16 vf_id;
1046 u8 func_reset_level;
1047 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
1048 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
1049 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1050 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
1051 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1052 u8 unused_0;
1053 };
1054
1055 /* hwrm_func_reset_output (size:128b/16B) */
1056 struct hwrm_func_reset_output {
1057 __le16 error_code;
1058 __le16 req_type;
1059 __le16 seq_id;
1060 __le16 resp_len;
1061 u8 unused_0[7];
1062 u8 valid;
1063 };
1064
1065 /* hwrm_func_getfid_input (size:192b/24B) */
1066 struct hwrm_func_getfid_input {
1067 __le16 req_type;
1068 __le16 cmpl_ring;
1069 __le16 seq_id;
1070 __le16 target_id;
1071 __le64 resp_addr;
1072 __le32 enables;
1073 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
1074 __le16 pci_id;
1075 u8 unused_0[2];
1076 };
1077
1078 /* hwrm_func_getfid_output (size:128b/16B) */
1079 struct hwrm_func_getfid_output {
1080 __le16 error_code;
1081 __le16 req_type;
1082 __le16 seq_id;
1083 __le16 resp_len;
1084 __le16 fid;
1085 u8 unused_0[5];
1086 u8 valid;
1087 };
1088
1089 /* hwrm_func_vf_alloc_input (size:192b/24B) */
1090 struct hwrm_func_vf_alloc_input {
1091 __le16 req_type;
1092 __le16 cmpl_ring;
1093 __le16 seq_id;
1094 __le16 target_id;
1095 __le64 resp_addr;
1096 __le32 enables;
1097 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
1098 __le16 first_vf_id;
1099 __le16 num_vfs;
1100 };
1101
1102 /* hwrm_func_vf_alloc_output (size:128b/16B) */
1103 struct hwrm_func_vf_alloc_output {
1104 __le16 error_code;
1105 __le16 req_type;
1106 __le16 seq_id;
1107 __le16 resp_len;
1108 __le16 first_vf_id;
1109 u8 unused_0[5];
1110 u8 valid;
1111 };
1112
1113 /* hwrm_func_vf_free_input (size:192b/24B) */
1114 struct hwrm_func_vf_free_input {
1115 __le16 req_type;
1116 __le16 cmpl_ring;
1117 __le16 seq_id;
1118 __le16 target_id;
1119 __le64 resp_addr;
1120 __le32 enables;
1121 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1122 __le16 first_vf_id;
1123 __le16 num_vfs;
1124 };
1125
1126 /* hwrm_func_vf_free_output (size:128b/16B) */
1127 struct hwrm_func_vf_free_output {
1128 __le16 error_code;
1129 __le16 req_type;
1130 __le16 seq_id;
1131 __le16 resp_len;
1132 u8 unused_0[7];
1133 u8 valid;
1134 };
1135
1136 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1137 struct hwrm_func_vf_cfg_input {
1138 __le16 req_type;
1139 __le16 cmpl_ring;
1140 __le16 seq_id;
1141 __le16 target_id;
1142 __le64 resp_addr;
1143 __le32 enables;
1144 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1145 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1146 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1147 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1148 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1149 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1150 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1151 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1152 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1153 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1154 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1155 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1156 __le16 mtu;
1157 __le16 guest_vlan;
1158 __le16 async_event_cr;
1159 u8 dflt_mac_addr[6];
1160 __le32 flags;
1161 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1162 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1163 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1164 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1165 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1166 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1167 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1168 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1169 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL
1170 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL
1171 __le16 num_rsscos_ctxs;
1172 __le16 num_cmpl_rings;
1173 __le16 num_tx_rings;
1174 __le16 num_rx_rings;
1175 __le16 num_l2_ctxs;
1176 __le16 num_vnics;
1177 __le16 num_stat_ctxs;
1178 __le16 num_hw_ring_grps;
1179 u8 unused_0[4];
1180 };
1181
1182 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1183 struct hwrm_func_vf_cfg_output {
1184 __le16 error_code;
1185 __le16 req_type;
1186 __le16 seq_id;
1187 __le16 resp_len;
1188 u8 unused_0[7];
1189 u8 valid;
1190 };
1191
1192 /* hwrm_func_qcaps_input (size:192b/24B) */
1193 struct hwrm_func_qcaps_input {
1194 __le16 req_type;
1195 __le16 cmpl_ring;
1196 __le16 seq_id;
1197 __le16 target_id;
1198 __le64 resp_addr;
1199 __le16 fid;
1200 u8 unused_0[6];
1201 };
1202
1203 /* hwrm_func_qcaps_output (size:704b/88B) */
1204 struct hwrm_func_qcaps_output {
1205 __le16 error_code;
1206 __le16 req_type;
1207 __le16 seq_id;
1208 __le16 resp_len;
1209 __le16 fid;
1210 __le16 port_id;
1211 __le32 flags;
1212 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1213 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1214 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1215 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1216 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1217 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1218 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1219 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1220 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1221 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1222 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1223 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1224 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1225 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1226 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1227 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1228 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1229 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1230 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1231 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1232 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1233 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1234 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1235 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
1236 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
1237 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
1238 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
1239 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL
1240 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL
1241 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL
1242 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL
1243 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL
1244 u8 mac_address[6];
1245 __le16 max_rsscos_ctx;
1246 __le16 max_cmpl_rings;
1247 __le16 max_tx_rings;
1248 __le16 max_rx_rings;
1249 __le16 max_l2_ctxs;
1250 __le16 max_vnics;
1251 __le16 first_vf_id;
1252 __le16 max_vfs;
1253 __le16 max_stat_ctx;
1254 __le32 max_encap_records;
1255 __le32 max_decap_records;
1256 __le32 max_tx_em_flows;
1257 __le32 max_tx_wm_flows;
1258 __le32 max_rx_em_flows;
1259 __le32 max_rx_wm_flows;
1260 __le32 max_mcast_filters;
1261 __le32 max_flow_id;
1262 __le32 max_hw_ring_grps;
1263 __le16 max_sp_tx_rings;
1264 u8 unused_0[2];
1265 __le32 flags_ext;
1266 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL
1267 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL
1268 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL
1269 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL
1270 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL
1271 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL
1272 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL
1273 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL
1274 u8 max_schqs;
1275 u8 mpc_chnls_cap;
1276 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
1277 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL
1278 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL
1279 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL
1280 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL
1281 u8 unused_1;
1282 u8 valid;
1283 };
1284
1285 /* hwrm_func_qcfg_input (size:192b/24B) */
1286 struct hwrm_func_qcfg_input {
1287 __le16 req_type;
1288 __le16 cmpl_ring;
1289 __le16 seq_id;
1290 __le16 target_id;
1291 __le64 resp_addr;
1292 __le16 fid;
1293 u8 unused_0[6];
1294 };
1295
1296 /* hwrm_func_qcfg_output (size:768b/96B) */
1297 struct hwrm_func_qcfg_output {
1298 __le16 error_code;
1299 __le16 req_type;
1300 __le16 seq_id;
1301 __le16 resp_len;
1302 __le16 fid;
1303 __le16 port_id;
1304 __le16 vlan;
1305 __le16 flags;
1306 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1307 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1308 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1309 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1310 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1311 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1312 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1313 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
1314 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL
1315 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL
1316 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL
1317 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL
1318 u8 mac_address[6];
1319 __le16 pci_id;
1320 __le16 alloc_rsscos_ctx;
1321 __le16 alloc_cmpl_rings;
1322 __le16 alloc_tx_rings;
1323 __le16 alloc_rx_rings;
1324 __le16 alloc_l2_ctx;
1325 __le16 alloc_vnics;
1326 __le16 mtu;
1327 __le16 mru;
1328 __le16 stat_ctx_id;
1329 u8 port_partition_type;
1330 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1331 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1332 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1333 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1334 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1335 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1336 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1337 u8 port_pf_cnt;
1338 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1339 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1340 __le16 dflt_vnic_id;
1341 __le16 max_mtu_configured;
1342 __le32 min_bw;
1343 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1344 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1345 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1346 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1347 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1348 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1349 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1350 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1351 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1352 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1353 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1354 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1355 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1356 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1357 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1358 __le32 max_bw;
1359 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1360 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1361 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1362 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1363 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1364 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1365 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1366 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1367 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1368 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1369 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1370 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1371 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1372 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1373 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1374 u8 evb_mode;
1375 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1376 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1377 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1378 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1379 u8 options;
1380 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1381 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1382 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1383 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1384 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1385 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1386 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1387 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1388 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1389 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1390 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1391 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1392 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1393 __le16 alloc_vfs;
1394 __le32 alloc_mcast_filters;
1395 __le32 alloc_hw_ring_grps;
1396 __le16 alloc_sp_tx_rings;
1397 __le16 alloc_stat_ctx;
1398 __le16 alloc_msix;
1399 __le16 registered_vfs;
1400 __le16 l2_doorbell_bar_size_kb;
1401 u8 unused_1;
1402 u8 always_1;
1403 __le32 reset_addr_poll;
1404 __le16 legacy_l2_db_size_kb;
1405 __le16 svif_info;
1406 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL
1407 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0
1408 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL
1409 u8 mpc_chnls;
1410 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL
1411 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL
1412 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL
1413 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL
1414 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL
1415 u8 unused_2[6];
1416 u8 valid;
1417 };
1418
1419 /* hwrm_func_cfg_input (size:768b/96B) */
1420 struct hwrm_func_cfg_input {
1421 __le16 req_type;
1422 __le16 cmpl_ring;
1423 __le16 seq_id;
1424 __le16 target_id;
1425 __le64 resp_addr;
1426 __le16 fid;
1427 __le16 num_msix;
1428 __le32 flags;
1429 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1430 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1431 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1432 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1433 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1434 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1435 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1436 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1437 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1438 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1439 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1440 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1441 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1442 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1443 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1444 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1445 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1446 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1447 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
1448 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
1449 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL
1450 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL
1451 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL
1452 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL
1453 __le32 enables;
1454 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1455 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1456 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1457 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1458 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1459 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1460 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1461 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1462 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1463 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1464 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1465 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1466 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1467 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1468 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1469 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1470 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1471 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1472 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1473 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1474 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1475 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1476 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1477 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL
1478 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL
1479 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL
1480 __le16 mtu;
1481 __le16 mru;
1482 __le16 num_rsscos_ctxs;
1483 __le16 num_cmpl_rings;
1484 __le16 num_tx_rings;
1485 __le16 num_rx_rings;
1486 __le16 num_l2_ctxs;
1487 __le16 num_vnics;
1488 __le16 num_stat_ctxs;
1489 __le16 num_hw_ring_grps;
1490 u8 dflt_mac_addr[6];
1491 __le16 dflt_vlan;
1492 __be32 dflt_ip_addr[4];
1493 __le32 min_bw;
1494 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1495 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1496 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1497 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1498 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1499 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1500 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1501 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1502 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1503 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1504 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1505 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1506 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1507 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1508 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1509 __le32 max_bw;
1510 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1511 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1512 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1513 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1514 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1515 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1516 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1517 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1518 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1519 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1520 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1521 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1522 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1523 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1524 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1525 __le16 async_event_cr;
1526 u8 vlan_antispoof_mode;
1527 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1528 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1529 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1530 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1531 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1532 u8 allowed_vlan_pris;
1533 u8 evb_mode;
1534 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1535 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1536 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1537 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1538 u8 options;
1539 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1540 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1541 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1542 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1543 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1544 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1545 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1546 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1547 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1548 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1549 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1550 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1551 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1552 __le16 num_mcast_filters;
1553 __le16 schq_id;
1554 __le16 mpc_chnls;
1555 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL
1556 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL
1557 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL
1558 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL
1559 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL
1560 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL
1561 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL
1562 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL
1563 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL
1564 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL
1565 u8 unused_0[4];
1566 };
1567
1568 /* hwrm_func_cfg_output (size:128b/16B) */
1569 struct hwrm_func_cfg_output {
1570 __le16 error_code;
1571 __le16 req_type;
1572 __le16 seq_id;
1573 __le16 resp_len;
1574 u8 unused_0[7];
1575 u8 valid;
1576 };
1577
1578 /* hwrm_func_qstats_input (size:192b/24B) */
1579 struct hwrm_func_qstats_input {
1580 __le16 req_type;
1581 __le16 cmpl_ring;
1582 __le16 seq_id;
1583 __le16 target_id;
1584 __le64 resp_addr;
1585 __le16 fid;
1586 u8 flags;
1587 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL
1588 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
1589 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL
1590 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK
1591 u8 unused_0[5];
1592 };
1593
1594 /* hwrm_func_qstats_output (size:1408b/176B) */
1595 struct hwrm_func_qstats_output {
1596 __le16 error_code;
1597 __le16 req_type;
1598 __le16 seq_id;
1599 __le16 resp_len;
1600 __le64 tx_ucast_pkts;
1601 __le64 tx_mcast_pkts;
1602 __le64 tx_bcast_pkts;
1603 __le64 tx_discard_pkts;
1604 __le64 tx_drop_pkts;
1605 __le64 tx_ucast_bytes;
1606 __le64 tx_mcast_bytes;
1607 __le64 tx_bcast_bytes;
1608 __le64 rx_ucast_pkts;
1609 __le64 rx_mcast_pkts;
1610 __le64 rx_bcast_pkts;
1611 __le64 rx_discard_pkts;
1612 __le64 rx_drop_pkts;
1613 __le64 rx_ucast_bytes;
1614 __le64 rx_mcast_bytes;
1615 __le64 rx_bcast_bytes;
1616 __le64 rx_agg_pkts;
1617 __le64 rx_agg_bytes;
1618 __le64 rx_agg_events;
1619 __le64 rx_agg_aborts;
1620 u8 unused_0[7];
1621 u8 valid;
1622 };
1623
1624 /* hwrm_func_qstats_ext_input (size:256b/32B) */
1625 struct hwrm_func_qstats_ext_input {
1626 __le16 req_type;
1627 __le16 cmpl_ring;
1628 __le16 seq_id;
1629 __le16 target_id;
1630 __le64 resp_addr;
1631 __le16 fid;
1632 u8 flags;
1633 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL
1634 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL
1635 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL
1636 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK
1637 u8 unused_0[1];
1638 __le32 enables;
1639 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL
1640 __le16 schq_id;
1641 __le16 traffic_class;
1642 u8 unused_1[4];
1643 };
1644
1645 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
1646 struct hwrm_func_qstats_ext_output {
1647 __le16 error_code;
1648 __le16 req_type;
1649 __le16 seq_id;
1650 __le16 resp_len;
1651 __le64 rx_ucast_pkts;
1652 __le64 rx_mcast_pkts;
1653 __le64 rx_bcast_pkts;
1654 __le64 rx_discard_pkts;
1655 __le64 rx_error_pkts;
1656 __le64 rx_ucast_bytes;
1657 __le64 rx_mcast_bytes;
1658 __le64 rx_bcast_bytes;
1659 __le64 tx_ucast_pkts;
1660 __le64 tx_mcast_pkts;
1661 __le64 tx_bcast_pkts;
1662 __le64 tx_error_pkts;
1663 __le64 tx_discard_pkts;
1664 __le64 tx_ucast_bytes;
1665 __le64 tx_mcast_bytes;
1666 __le64 tx_bcast_bytes;
1667 __le64 rx_tpa_eligible_pkt;
1668 __le64 rx_tpa_eligible_bytes;
1669 __le64 rx_tpa_pkt;
1670 __le64 rx_tpa_bytes;
1671 __le64 rx_tpa_errors;
1672 __le64 rx_tpa_events;
1673 u8 unused_0[7];
1674 u8 valid;
1675 };
1676
1677 /* hwrm_func_clr_stats_input (size:192b/24B) */
1678 struct hwrm_func_clr_stats_input {
1679 __le16 req_type;
1680 __le16 cmpl_ring;
1681 __le16 seq_id;
1682 __le16 target_id;
1683 __le64 resp_addr;
1684 __le16 fid;
1685 u8 unused_0[6];
1686 };
1687
1688 /* hwrm_func_clr_stats_output (size:128b/16B) */
1689 struct hwrm_func_clr_stats_output {
1690 __le16 error_code;
1691 __le16 req_type;
1692 __le16 seq_id;
1693 __le16 resp_len;
1694 u8 unused_0[7];
1695 u8 valid;
1696 };
1697
1698 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1699 struct hwrm_func_vf_resc_free_input {
1700 __le16 req_type;
1701 __le16 cmpl_ring;
1702 __le16 seq_id;
1703 __le16 target_id;
1704 __le64 resp_addr;
1705 __le16 vf_id;
1706 u8 unused_0[6];
1707 };
1708
1709 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1710 struct hwrm_func_vf_resc_free_output {
1711 __le16 error_code;
1712 __le16 req_type;
1713 __le16 seq_id;
1714 __le16 resp_len;
1715 u8 unused_0[7];
1716 u8 valid;
1717 };
1718
1719 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1720 struct hwrm_func_drv_rgtr_input {
1721 __le16 req_type;
1722 __le16 cmpl_ring;
1723 __le16 seq_id;
1724 __le16 target_id;
1725 __le64 resp_addr;
1726 __le32 flags;
1727 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1728 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1729 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1730 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
1731 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1732 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
1733 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
1734 __le32 enables;
1735 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1736 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1737 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1738 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1739 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1740 __le16 os_type;
1741 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1742 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1743 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1744 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1745 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1746 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1747 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1748 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1749 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1750 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1751 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1752 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1753 u8 ver_maj_8b;
1754 u8 ver_min_8b;
1755 u8 ver_upd_8b;
1756 u8 unused_0[3];
1757 __le32 timestamp;
1758 u8 unused_1[4];
1759 __le32 vf_req_fwd[8];
1760 __le32 async_event_fwd[8];
1761 __le16 ver_maj;
1762 __le16 ver_min;
1763 __le16 ver_upd;
1764 __le16 ver_patch;
1765 };
1766
1767 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1768 struct hwrm_func_drv_rgtr_output {
1769 __le16 error_code;
1770 __le16 req_type;
1771 __le16 seq_id;
1772 __le16 resp_len;
1773 __le32 flags;
1774 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1775 u8 unused_0[3];
1776 u8 valid;
1777 };
1778
1779 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1780 struct hwrm_func_drv_unrgtr_input {
1781 __le16 req_type;
1782 __le16 cmpl_ring;
1783 __le16 seq_id;
1784 __le16 target_id;
1785 __le64 resp_addr;
1786 __le32 flags;
1787 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1788 u8 unused_0[4];
1789 };
1790
1791 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1792 struct hwrm_func_drv_unrgtr_output {
1793 __le16 error_code;
1794 __le16 req_type;
1795 __le16 seq_id;
1796 __le16 resp_len;
1797 u8 unused_0[7];
1798 u8 valid;
1799 };
1800
1801 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1802 struct hwrm_func_buf_rgtr_input {
1803 __le16 req_type;
1804 __le16 cmpl_ring;
1805 __le16 seq_id;
1806 __le16 target_id;
1807 __le64 resp_addr;
1808 __le32 enables;
1809 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1810 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1811 __le16 vf_id;
1812 __le16 req_buf_num_pages;
1813 __le16 req_buf_page_size;
1814 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1815 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1816 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1817 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1818 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1819 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1820 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1821 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1822 __le16 req_buf_len;
1823 __le16 resp_buf_len;
1824 u8 unused_0[2];
1825 __le64 req_buf_page_addr0;
1826 __le64 req_buf_page_addr1;
1827 __le64 req_buf_page_addr2;
1828 __le64 req_buf_page_addr3;
1829 __le64 req_buf_page_addr4;
1830 __le64 req_buf_page_addr5;
1831 __le64 req_buf_page_addr6;
1832 __le64 req_buf_page_addr7;
1833 __le64 req_buf_page_addr8;
1834 __le64 req_buf_page_addr9;
1835 __le64 error_buf_addr;
1836 __le64 resp_buf_addr;
1837 };
1838
1839 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1840 struct hwrm_func_buf_rgtr_output {
1841 __le16 error_code;
1842 __le16 req_type;
1843 __le16 seq_id;
1844 __le16 resp_len;
1845 u8 unused_0[7];
1846 u8 valid;
1847 };
1848
1849 /* hwrm_func_drv_qver_input (size:192b/24B) */
1850 struct hwrm_func_drv_qver_input {
1851 __le16 req_type;
1852 __le16 cmpl_ring;
1853 __le16 seq_id;
1854 __le16 target_id;
1855 __le64 resp_addr;
1856 __le32 reserved;
1857 __le16 fid;
1858 u8 unused_0[2];
1859 };
1860
1861 /* hwrm_func_drv_qver_output (size:256b/32B) */
1862 struct hwrm_func_drv_qver_output {
1863 __le16 error_code;
1864 __le16 req_type;
1865 __le16 seq_id;
1866 __le16 resp_len;
1867 __le16 os_type;
1868 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1869 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1870 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1871 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1872 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1873 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1874 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1875 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1876 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1877 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1878 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1879 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1880 u8 ver_maj_8b;
1881 u8 ver_min_8b;
1882 u8 ver_upd_8b;
1883 u8 unused_0[3];
1884 __le16 ver_maj;
1885 __le16 ver_min;
1886 __le16 ver_upd;
1887 __le16 ver_patch;
1888 u8 unused_1[7];
1889 u8 valid;
1890 };
1891
1892 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1893 struct hwrm_func_resource_qcaps_input {
1894 __le16 req_type;
1895 __le16 cmpl_ring;
1896 __le16 seq_id;
1897 __le16 target_id;
1898 __le64 resp_addr;
1899 __le16 fid;
1900 u8 unused_0[6];
1901 };
1902
1903 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1904 struct hwrm_func_resource_qcaps_output {
1905 __le16 error_code;
1906 __le16 req_type;
1907 __le16 seq_id;
1908 __le16 resp_len;
1909 __le16 max_vfs;
1910 __le16 max_msix;
1911 __le16 vf_reservation_strategy;
1912 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1913 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1914 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1915 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1916 __le16 min_rsscos_ctx;
1917 __le16 max_rsscos_ctx;
1918 __le16 min_cmpl_rings;
1919 __le16 max_cmpl_rings;
1920 __le16 min_tx_rings;
1921 __le16 max_tx_rings;
1922 __le16 min_rx_rings;
1923 __le16 max_rx_rings;
1924 __le16 min_l2_ctxs;
1925 __le16 max_l2_ctxs;
1926 __le16 min_vnics;
1927 __le16 max_vnics;
1928 __le16 min_stat_ctx;
1929 __le16 max_stat_ctx;
1930 __le16 min_hw_ring_grps;
1931 __le16 max_hw_ring_grps;
1932 __le16 max_tx_scheduler_inputs;
1933 __le16 flags;
1934 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
1935 u8 unused_0[5];
1936 u8 valid;
1937 };
1938
1939 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1940 struct hwrm_func_vf_resource_cfg_input {
1941 __le16 req_type;
1942 __le16 cmpl_ring;
1943 __le16 seq_id;
1944 __le16 target_id;
1945 __le64 resp_addr;
1946 __le16 vf_id;
1947 __le16 max_msix;
1948 __le16 min_rsscos_ctx;
1949 __le16 max_rsscos_ctx;
1950 __le16 min_cmpl_rings;
1951 __le16 max_cmpl_rings;
1952 __le16 min_tx_rings;
1953 __le16 max_tx_rings;
1954 __le16 min_rx_rings;
1955 __le16 max_rx_rings;
1956 __le16 min_l2_ctxs;
1957 __le16 max_l2_ctxs;
1958 __le16 min_vnics;
1959 __le16 max_vnics;
1960 __le16 min_stat_ctx;
1961 __le16 max_stat_ctx;
1962 __le16 min_hw_ring_grps;
1963 __le16 max_hw_ring_grps;
1964 __le16 flags;
1965 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
1966 u8 unused_0[2];
1967 };
1968
1969 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
1970 struct hwrm_func_vf_resource_cfg_output {
1971 __le16 error_code;
1972 __le16 req_type;
1973 __le16 seq_id;
1974 __le16 resp_len;
1975 __le16 reserved_rsscos_ctx;
1976 __le16 reserved_cmpl_rings;
1977 __le16 reserved_tx_rings;
1978 __le16 reserved_rx_rings;
1979 __le16 reserved_l2_ctxs;
1980 __le16 reserved_vnics;
1981 __le16 reserved_stat_ctx;
1982 __le16 reserved_hw_ring_grps;
1983 u8 unused_0[7];
1984 u8 valid;
1985 };
1986
1987 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
1988 struct hwrm_func_backing_store_qcaps_input {
1989 __le16 req_type;
1990 __le16 cmpl_ring;
1991 __le16 seq_id;
1992 __le16 target_id;
1993 __le64 resp_addr;
1994 };
1995
1996 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
1997 struct hwrm_func_backing_store_qcaps_output {
1998 __le16 error_code;
1999 __le16 req_type;
2000 __le16 seq_id;
2001 __le16 resp_len;
2002 __le32 qp_max_entries;
2003 __le16 qp_min_qp1_entries;
2004 __le16 qp_max_l2_entries;
2005 __le16 qp_entry_size;
2006 __le16 srq_max_l2_entries;
2007 __le32 srq_max_entries;
2008 __le16 srq_entry_size;
2009 __le16 cq_max_l2_entries;
2010 __le32 cq_max_entries;
2011 __le16 cq_entry_size;
2012 __le16 vnic_max_vnic_entries;
2013 __le16 vnic_max_ring_table_entries;
2014 __le16 vnic_entry_size;
2015 __le32 stat_max_entries;
2016 __le16 stat_entry_size;
2017 __le16 tqm_entry_size;
2018 __le32 tqm_min_entries_per_ring;
2019 __le32 tqm_max_entries_per_ring;
2020 __le32 mrav_max_entries;
2021 __le16 mrav_entry_size;
2022 __le16 tim_entry_size;
2023 __le32 tim_max_entries;
2024 __le16 mrav_num_entries_units;
2025 u8 tqm_entries_multiple;
2026 u8 ctx_kind_initializer;
2027 __le32 rsvd;
2028 __le16 rsvd1;
2029 u8 tqm_fp_rings_count;
2030 u8 valid;
2031 };
2032
2033 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
2034 struct hwrm_func_backing_store_cfg_input {
2035 __le16 req_type;
2036 __le16 cmpl_ring;
2037 __le16 seq_id;
2038 __le16 target_id;
2039 __le64 resp_addr;
2040 __le32 flags;
2041 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
2042 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL
2043 __le32 enables;
2044 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
2045 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
2046 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
2047 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
2048 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
2049 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
2050 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
2051 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
2052 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
2053 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
2054 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
2055 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
2056 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
2057 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
2058 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
2059 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
2060 u8 qpc_pg_size_qpc_lvl;
2061 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
2062 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
2063 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
2064 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
2065 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
2066 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2067 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
2068 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
2069 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2070 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2071 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2072 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2073 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2074 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2075 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2076 u8 srq_pg_size_srq_lvl;
2077 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
2078 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
2079 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
2080 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
2081 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
2082 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2083 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
2084 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
2085 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2086 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2087 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2088 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2089 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2090 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2091 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2092 u8 cq_pg_size_cq_lvl;
2093 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
2094 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
2095 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
2096 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
2097 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
2098 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2099 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
2100 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
2101 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2102 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2103 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2104 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2105 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2106 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2107 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2108 u8 vnic_pg_size_vnic_lvl;
2109 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
2110 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
2111 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
2112 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
2113 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
2114 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2115 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
2116 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
2117 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2118 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2119 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2120 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2121 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2122 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2123 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2124 u8 stat_pg_size_stat_lvl;
2125 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
2126 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
2127 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
2128 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
2129 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
2130 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2131 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
2132 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
2133 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2134 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2135 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2136 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2137 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2138 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2139 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2140 u8 tqm_sp_pg_size_tqm_sp_lvl;
2141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
2142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
2143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
2144 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
2145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
2146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
2148 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
2149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2151 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2152 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2155 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2156 u8 tqm_ring0_pg_size_tqm_ring0_lvl;
2157 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
2158 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
2159 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
2160 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
2161 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
2162 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2163 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
2164 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
2165 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2166 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2167 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2168 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2169 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2170 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2171 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2172 u8 tqm_ring1_pg_size_tqm_ring1_lvl;
2173 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
2174 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
2175 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
2176 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
2177 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
2178 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2179 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
2180 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
2181 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2182 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2183 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2184 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2185 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2186 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2187 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2188 u8 tqm_ring2_pg_size_tqm_ring2_lvl;
2189 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
2190 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
2191 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
2192 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
2193 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
2194 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2195 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
2196 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
2197 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2198 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2199 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2200 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2201 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2202 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2203 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2204 u8 tqm_ring3_pg_size_tqm_ring3_lvl;
2205 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
2206 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
2207 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
2208 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
2209 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
2210 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2211 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
2212 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
2213 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2214 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2215 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2216 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2217 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2218 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2219 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2220 u8 tqm_ring4_pg_size_tqm_ring4_lvl;
2221 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
2222 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
2223 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
2224 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
2225 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
2226 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2227 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
2228 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
2229 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2230 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2231 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2232 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2233 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2234 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2235 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2236 u8 tqm_ring5_pg_size_tqm_ring5_lvl;
2237 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
2238 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
2239 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
2240 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
2241 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
2242 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2243 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
2244 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
2245 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2246 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2247 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2248 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2249 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2250 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2251 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2252 u8 tqm_ring6_pg_size_tqm_ring6_lvl;
2253 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
2254 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
2255 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
2256 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
2257 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
2258 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2259 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
2260 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
2261 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2262 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2263 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2264 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2265 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2266 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2267 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2268 u8 tqm_ring7_pg_size_tqm_ring7_lvl;
2269 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
2270 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
2271 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
2272 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
2273 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
2274 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2275 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
2276 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
2277 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2278 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2279 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2280 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2281 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2282 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2283 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2284 u8 mrav_pg_size_mrav_lvl;
2285 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
2286 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
2287 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
2288 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2289 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
2290 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2291 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
2292 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
2293 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2294 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2295 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2296 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2297 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2298 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2299 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2300 u8 tim_pg_size_tim_lvl;
2301 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
2302 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
2303 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
2304 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
2305 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
2306 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2307 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
2308 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
2309 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2310 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2311 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2312 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2313 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2314 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2315 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2316 __le64 qpc_page_dir;
2317 __le64 srq_page_dir;
2318 __le64 cq_page_dir;
2319 __le64 vnic_page_dir;
2320 __le64 stat_page_dir;
2321 __le64 tqm_sp_page_dir;
2322 __le64 tqm_ring0_page_dir;
2323 __le64 tqm_ring1_page_dir;
2324 __le64 tqm_ring2_page_dir;
2325 __le64 tqm_ring3_page_dir;
2326 __le64 tqm_ring4_page_dir;
2327 __le64 tqm_ring5_page_dir;
2328 __le64 tqm_ring6_page_dir;
2329 __le64 tqm_ring7_page_dir;
2330 __le64 mrav_page_dir;
2331 __le64 tim_page_dir;
2332 __le32 qp_num_entries;
2333 __le32 srq_num_entries;
2334 __le32 cq_num_entries;
2335 __le32 stat_num_entries;
2336 __le32 tqm_sp_num_entries;
2337 __le32 tqm_ring0_num_entries;
2338 __le32 tqm_ring1_num_entries;
2339 __le32 tqm_ring2_num_entries;
2340 __le32 tqm_ring3_num_entries;
2341 __le32 tqm_ring4_num_entries;
2342 __le32 tqm_ring5_num_entries;
2343 __le32 tqm_ring6_num_entries;
2344 __le32 tqm_ring7_num_entries;
2345 __le32 mrav_num_entries;
2346 __le32 tim_num_entries;
2347 __le16 qp_num_qp1_entries;
2348 __le16 qp_num_l2_entries;
2349 __le16 qp_entry_size;
2350 __le16 srq_num_l2_entries;
2351 __le16 srq_entry_size;
2352 __le16 cq_num_l2_entries;
2353 __le16 cq_entry_size;
2354 __le16 vnic_num_vnic_entries;
2355 __le16 vnic_num_ring_table_entries;
2356 __le16 vnic_entry_size;
2357 __le16 stat_entry_size;
2358 __le16 tqm_entry_size;
2359 __le16 mrav_entry_size;
2360 __le16 tim_entry_size;
2361 };
2362
2363 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2364 struct hwrm_func_backing_store_cfg_output {
2365 __le16 error_code;
2366 __le16 req_type;
2367 __le16 seq_id;
2368 __le16 resp_len;
2369 u8 unused_0[7];
2370 u8 valid;
2371 };
2372
2373 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
2374 struct hwrm_error_recovery_qcfg_input {
2375 __le16 req_type;
2376 __le16 cmpl_ring;
2377 __le16 seq_id;
2378 __le16 target_id;
2379 __le64 resp_addr;
2380 u8 unused_0[8];
2381 };
2382
2383 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
2384 struct hwrm_error_recovery_qcfg_output {
2385 __le16 error_code;
2386 __le16 req_type;
2387 __le16 seq_id;
2388 __le16 resp_len;
2389 __le32 flags;
2390 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
2391 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
2392 __le32 driver_polling_freq;
2393 __le32 master_func_wait_period;
2394 __le32 normal_func_wait_period;
2395 __le32 master_func_wait_period_after_reset;
2396 __le32 max_bailout_time_after_reset;
2397 __le32 fw_health_status_reg;
2398 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
2399 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
2400 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2401 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
2402 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
2403 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
2404 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
2405 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
2406 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
2407 __le32 fw_heartbeat_reg;
2408 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
2409 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
2410 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2411 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
2412 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
2413 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
2414 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
2415 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
2416 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
2417 __le32 fw_reset_cnt_reg;
2418 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
2419 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
2420 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2421 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
2422 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
2423 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
2424 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
2425 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
2426 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
2427 __le32 reset_inprogress_reg;
2428 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
2429 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
2430 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2431 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
2432 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
2433 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
2434 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
2435 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
2436 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
2437 __le32 reset_inprogress_reg_mask;
2438 u8 unused_0[3];
2439 u8 reg_array_cnt;
2440 __le32 reset_reg[16];
2441 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
2442 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
2443 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2444 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
2445 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
2446 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
2447 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
2448 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
2449 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
2450 __le32 reset_reg_val[16];
2451 u8 delay_after_reset[16];
2452 __le32 err_recovery_cnt_reg;
2453 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL
2454 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0
2455 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2456 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL
2457 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL
2458 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL
2459 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
2460 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL
2461 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2
2462 u8 unused_1[3];
2463 u8 valid;
2464 };
2465
2466 /* hwrm_func_drv_if_change_input (size:192b/24B) */
2467 struct hwrm_func_drv_if_change_input {
2468 __le16 req_type;
2469 __le16 cmpl_ring;
2470 __le16 seq_id;
2471 __le16 target_id;
2472 __le64 resp_addr;
2473 __le32 flags;
2474 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
2475 __le32 unused;
2476 };
2477
2478 /* hwrm_func_drv_if_change_output (size:128b/16B) */
2479 struct hwrm_func_drv_if_change_output {
2480 __le16 error_code;
2481 __le16 req_type;
2482 __le16 seq_id;
2483 __le16 resp_len;
2484 __le32 flags;
2485 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
2486 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
2487 u8 unused_0[3];
2488 u8 valid;
2489 };
2490
2491 /* hwrm_port_phy_cfg_input (size:448b/56B) */
2492 struct hwrm_port_phy_cfg_input {
2493 __le16 req_type;
2494 __le16 cmpl_ring;
2495 __le16 seq_id;
2496 __le16 target_id;
2497 __le64 resp_addr;
2498 __le32 flags;
2499 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
2500 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
2501 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
2502 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
2503 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
2504 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
2505 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
2506 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
2507 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
2508 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
2509 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
2510 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
2511 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
2512 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
2513 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
2514 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
2515 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
2516 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
2517 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
2518 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
2519 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
2520 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
2521 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
2522 __le32 enables;
2523 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
2524 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
2525 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
2526 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
2527 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
2528 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
2529 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
2530 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
2531 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
2532 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
2533 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
2534 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
2535 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
2536 __le16 port_id;
2537 __le16 force_link_speed;
2538 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
2539 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
2540 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
2541 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
2542 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
2543 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
2544 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
2545 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
2546 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
2547 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
2548 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
2549 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
2550 u8 auto_mode;
2551 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
2552 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
2553 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
2554 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
2555 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
2556 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
2557 u8 auto_duplex;
2558 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
2559 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
2560 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
2561 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
2562 u8 auto_pause;
2563 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
2564 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
2565 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2566 u8 unused_0;
2567 __le16 auto_link_speed;
2568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
2569 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
2570 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
2571 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
2572 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
2573 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
2574 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
2575 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
2576 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
2577 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
2578 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
2579 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
2580 __le16 auto_link_speed_mask;
2581 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2582 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2583 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2584 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2585 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2586 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2587 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2588 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2589 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2590 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2591 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2592 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2593 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2594 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2595 u8 wirespeed;
2596 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
2597 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
2598 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
2599 u8 lpbk;
2600 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
2601 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
2602 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
2603 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
2604 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
2605 u8 force_pause;
2606 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
2607 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
2608 u8 unused_1;
2609 __le32 preemphasis;
2610 __le16 eee_link_speed_mask;
2611 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2612 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
2613 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2614 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
2615 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2616 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2617 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
2618 __le16 force_pam4_link_speed;
2619 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
2620 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
2621 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
2622 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
2623 __le32 tx_lpi_timer;
2624 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
2625 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
2626 __le16 auto_link_pam4_speed_mask;
2627 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
2628 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
2629 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
2630 u8 unused_2[2];
2631 };
2632
2633 /* hwrm_port_phy_cfg_output (size:128b/16B) */
2634 struct hwrm_port_phy_cfg_output {
2635 __le16 error_code;
2636 __le16 req_type;
2637 __le16 seq_id;
2638 __le16 resp_len;
2639 u8 unused_0[7];
2640 u8 valid;
2641 };
2642
2643 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
2644 struct hwrm_port_phy_cfg_cmd_err {
2645 u8 code;
2646 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2647 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
2648 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
2649 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
2650 u8 unused_0[7];
2651 };
2652
2653 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
2654 struct hwrm_port_phy_qcfg_input {
2655 __le16 req_type;
2656 __le16 cmpl_ring;
2657 __le16 seq_id;
2658 __le16 target_id;
2659 __le64 resp_addr;
2660 __le16 port_id;
2661 u8 unused_0[6];
2662 };
2663
2664 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
2665 struct hwrm_port_phy_qcfg_output {
2666 __le16 error_code;
2667 __le16 req_type;
2668 __le16 seq_id;
2669 __le16 resp_len;
2670 u8 link;
2671 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
2672 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
2673 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
2674 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
2675 u8 active_fec_signal_mode;
2676 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
2677 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
2678 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
2679 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
2680 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
2681 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
2682 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
2683 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
2684 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
2685 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
2686 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
2687 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
2688 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
2689 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
2690 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
2691 __le16 link_speed;
2692 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
2693 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
2694 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
2695 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
2696 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
2697 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
2698 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
2699 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
2700 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
2701 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
2702 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
2703 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
2704 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
2705 u8 duplex_cfg;
2706 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
2707 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
2708 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
2709 u8 pause;
2710 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
2711 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
2712 __le16 support_speeds;
2713 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
2714 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
2715 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
2716 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
2717 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
2718 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
2719 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
2720 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
2721 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
2722 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
2723 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
2724 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
2725 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
2726 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
2727 __le16 force_link_speed;
2728 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
2729 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
2730 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
2731 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
2732 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
2733 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
2734 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
2735 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
2736 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
2737 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
2738 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
2739 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
2740 u8 auto_mode;
2741 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
2742 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
2743 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
2744 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
2745 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
2746 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
2747 u8 auto_pause;
2748 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
2749 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
2750 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2751 __le16 auto_link_speed;
2752 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
2753 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
2754 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
2755 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
2756 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
2757 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
2758 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
2759 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
2760 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
2761 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
2762 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
2763 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
2764 __le16 auto_link_speed_mask;
2765 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2766 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2767 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2768 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2769 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2770 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2771 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2772 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2773 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2774 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2775 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2776 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2777 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2778 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2779 u8 wirespeed;
2780 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
2781 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
2782 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
2783 u8 lpbk;
2784 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
2785 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
2786 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
2787 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
2788 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
2789 u8 force_pause;
2790 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
2791 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
2792 u8 module_status;
2793 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
2794 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
2795 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
2796 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
2797 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
2798 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL
2799 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
2800 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
2801 __le32 preemphasis;
2802 u8 phy_maj;
2803 u8 phy_min;
2804 u8 phy_bld;
2805 u8 phy_type;
2806 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
2807 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
2808 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
2809 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
2810 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
2811 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
2812 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
2813 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
2814 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
2815 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
2816 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
2817 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
2818 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
2819 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
2820 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
2821 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
2822 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
2823 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
2824 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
2825 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
2826 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
2827 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
2828 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
2829 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
2830 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
2831 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
2832 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
2833 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
2834 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
2835 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
2836 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
2837 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
2838 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
2839 u8 media_type;
2840 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
2841 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
2842 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
2843 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
2844 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
2845 u8 xcvr_pkg_type;
2846 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
2847 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
2848 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
2849 u8 eee_config_phy_addr;
2850 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
2851 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
2852 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
2853 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
2854 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
2855 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
2856 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
2857 u8 parallel_detect;
2858 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
2859 __le16 link_partner_adv_speeds;
2860 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
2861 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
2862 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
2863 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
2864 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
2865 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
2866 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
2867 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
2868 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
2869 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
2870 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
2871 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
2872 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
2873 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
2874 u8 link_partner_adv_auto_mode;
2875 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
2876 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
2877 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
2878 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
2879 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
2880 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
2881 u8 link_partner_adv_pause;
2882 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
2883 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
2884 __le16 adv_eee_link_speed_mask;
2885 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2886 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2887 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2888 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2889 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2890 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2891 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2892 __le16 link_partner_adv_eee_link_speed_mask;
2893 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2894 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2895 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2896 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2897 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2898 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2899 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2900 __le32 xcvr_identifier_type_tx_lpi_timer;
2901 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
2902 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
2903 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
2904 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
2905 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
2906 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
2907 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
2908 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
2909 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
2910 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
2911 __le16 fec_cfg;
2912 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
2913 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
2914 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
2915 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
2916 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
2917 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
2918 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
2919 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
2920 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
2921 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
2922 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
2923 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
2924 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
2925 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
2926 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
2927 u8 duplex_state;
2928 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
2929 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
2930 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
2931 u8 option_flags;
2932 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
2933 char phy_vendor_name[16];
2934 char phy_vendor_partnumber[16];
2935 __le16 support_pam4_speeds;
2936 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
2937 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
2938 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
2939 __le16 force_pam4_link_speed;
2940 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
2941 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
2942 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
2943 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
2944 __le16 auto_pam4_link_speed_mask;
2945 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
2946 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
2947 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
2948 u8 link_partner_pam4_adv_speeds;
2949 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
2950 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
2951 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
2952 u8 valid;
2953 };
2954
2955 /* hwrm_port_mac_cfg_input (size:384b/48B) */
2956 struct hwrm_port_mac_cfg_input {
2957 __le16 req_type;
2958 __le16 cmpl_ring;
2959 __le16 seq_id;
2960 __le16 target_id;
2961 __le64 resp_addr;
2962 __le32 flags;
2963 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
2964 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
2965 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
2966 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
2967 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
2968 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
2969 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
2970 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
2971 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
2972 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
2973 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
2974 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
2975 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
2976 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL
2977 __le32 enables;
2978 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
2979 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
2980 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
2981 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
2982 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
2983 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
2984 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
2985 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
2986 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
2987 __le16 port_id;
2988 u8 ipg;
2989 u8 lpbk;
2990 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
2991 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
2992 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
2993 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
2994 u8 vlan_pri2cos_map_pri;
2995 u8 reserved1;
2996 u8 tunnel_pri2cos_map_pri;
2997 u8 dscp2pri_map_pri;
2998 __le16 rx_ts_capture_ptp_msg_type;
2999 __le16 tx_ts_capture_ptp_msg_type;
3000 u8 cos_field_cfg;
3001 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
3002 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
3003 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
3004 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
3005 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
3006 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
3007 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
3008 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
3009 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
3010 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
3011 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
3012 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
3013 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
3014 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
3015 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
3016 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
3017 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
3018 u8 unused_0[3];
3019 __s32 ptp_freq_adj_ppb;
3020 u8 unused_1[4];
3021 };
3022
3023 /* hwrm_port_mac_cfg_output (size:128b/16B) */
3024 struct hwrm_port_mac_cfg_output {
3025 __le16 error_code;
3026 __le16 req_type;
3027 __le16 seq_id;
3028 __le16 resp_len;
3029 __le16 mru;
3030 __le16 mtu;
3031 u8 ipg;
3032 u8 lpbk;
3033 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
3034 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
3035 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
3036 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
3037 u8 unused_0;
3038 u8 valid;
3039 };
3040
3041 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
3042 struct hwrm_port_mac_ptp_qcfg_input {
3043 __le16 req_type;
3044 __le16 cmpl_ring;
3045 __le16 seq_id;
3046 __le16 target_id;
3047 __le64 resp_addr;
3048 __le16 port_id;
3049 u8 unused_0[6];
3050 };
3051
3052 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
3053 struct hwrm_port_mac_ptp_qcfg_output {
3054 __le16 error_code;
3055 __le16 req_type;
3056 __le16 seq_id;
3057 __le16 resp_len;
3058 u8 flags;
3059 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
3060 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
3061 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
3062 u8 unused_0[3];
3063 __le32 rx_ts_reg_off_lower;
3064 __le32 rx_ts_reg_off_upper;
3065 __le32 rx_ts_reg_off_seq_id;
3066 __le32 rx_ts_reg_off_src_id_0;
3067 __le32 rx_ts_reg_off_src_id_1;
3068 __le32 rx_ts_reg_off_src_id_2;
3069 __le32 rx_ts_reg_off_domain_id;
3070 __le32 rx_ts_reg_off_fifo;
3071 __le32 rx_ts_reg_off_fifo_adv;
3072 __le32 rx_ts_reg_off_granularity;
3073 __le32 tx_ts_reg_off_lower;
3074 __le32 tx_ts_reg_off_upper;
3075 __le32 tx_ts_reg_off_seq_id;
3076 __le32 tx_ts_reg_off_fifo;
3077 __le32 tx_ts_reg_off_granularity;
3078 u8 unused_1[7];
3079 u8 valid;
3080 };
3081
3082 /* tx_port_stats (size:3264b/408B) */
3083 struct tx_port_stats {
3084 __le64 tx_64b_frames;
3085 __le64 tx_65b_127b_frames;
3086 __le64 tx_128b_255b_frames;
3087 __le64 tx_256b_511b_frames;
3088 __le64 tx_512b_1023b_frames;
3089 __le64 tx_1024b_1518b_frames;
3090 __le64 tx_good_vlan_frames;
3091 __le64 tx_1519b_2047b_frames;
3092 __le64 tx_2048b_4095b_frames;
3093 __le64 tx_4096b_9216b_frames;
3094 __le64 tx_9217b_16383b_frames;
3095 __le64 tx_good_frames;
3096 __le64 tx_total_frames;
3097 __le64 tx_ucast_frames;
3098 __le64 tx_mcast_frames;
3099 __le64 tx_bcast_frames;
3100 __le64 tx_pause_frames;
3101 __le64 tx_pfc_frames;
3102 __le64 tx_jabber_frames;
3103 __le64 tx_fcs_err_frames;
3104 __le64 tx_control_frames;
3105 __le64 tx_oversz_frames;
3106 __le64 tx_single_dfrl_frames;
3107 __le64 tx_multi_dfrl_frames;
3108 __le64 tx_single_coll_frames;
3109 __le64 tx_multi_coll_frames;
3110 __le64 tx_late_coll_frames;
3111 __le64 tx_excessive_coll_frames;
3112 __le64 tx_frag_frames;
3113 __le64 tx_err;
3114 __le64 tx_tagged_frames;
3115 __le64 tx_dbl_tagged_frames;
3116 __le64 tx_runt_frames;
3117 __le64 tx_fifo_underruns;
3118 __le64 tx_pfc_ena_frames_pri0;
3119 __le64 tx_pfc_ena_frames_pri1;
3120 __le64 tx_pfc_ena_frames_pri2;
3121 __le64 tx_pfc_ena_frames_pri3;
3122 __le64 tx_pfc_ena_frames_pri4;
3123 __le64 tx_pfc_ena_frames_pri5;
3124 __le64 tx_pfc_ena_frames_pri6;
3125 __le64 tx_pfc_ena_frames_pri7;
3126 __le64 tx_eee_lpi_events;
3127 __le64 tx_eee_lpi_duration;
3128 __le64 tx_llfc_logical_msgs;
3129 __le64 tx_hcfc_msgs;
3130 __le64 tx_total_collisions;
3131 __le64 tx_bytes;
3132 __le64 tx_xthol_frames;
3133 __le64 tx_stat_discard;
3134 __le64 tx_stat_error;
3135 };
3136
3137 /* rx_port_stats (size:4224b/528B) */
3138 struct rx_port_stats {
3139 __le64 rx_64b_frames;
3140 __le64 rx_65b_127b_frames;
3141 __le64 rx_128b_255b_frames;
3142 __le64 rx_256b_511b_frames;
3143 __le64 rx_512b_1023b_frames;
3144 __le64 rx_1024b_1518b_frames;
3145 __le64 rx_good_vlan_frames;
3146 __le64 rx_1519b_2047b_frames;
3147 __le64 rx_2048b_4095b_frames;
3148 __le64 rx_4096b_9216b_frames;
3149 __le64 rx_9217b_16383b_frames;
3150 __le64 rx_total_frames;
3151 __le64 rx_ucast_frames;
3152 __le64 rx_mcast_frames;
3153 __le64 rx_bcast_frames;
3154 __le64 rx_fcs_err_frames;
3155 __le64 rx_ctrl_frames;
3156 __le64 rx_pause_frames;
3157 __le64 rx_pfc_frames;
3158 __le64 rx_unsupported_opcode_frames;
3159 __le64 rx_unsupported_da_pausepfc_frames;
3160 __le64 rx_wrong_sa_frames;
3161 __le64 rx_align_err_frames;
3162 __le64 rx_oor_len_frames;
3163 __le64 rx_code_err_frames;
3164 __le64 rx_false_carrier_frames;
3165 __le64 rx_ovrsz_frames;
3166 __le64 rx_jbr_frames;
3167 __le64 rx_mtu_err_frames;
3168 __le64 rx_match_crc_frames;
3169 __le64 rx_promiscuous_frames;
3170 __le64 rx_tagged_frames;
3171 __le64 rx_double_tagged_frames;
3172 __le64 rx_trunc_frames;
3173 __le64 rx_good_frames;
3174 __le64 rx_pfc_xon2xoff_frames_pri0;
3175 __le64 rx_pfc_xon2xoff_frames_pri1;
3176 __le64 rx_pfc_xon2xoff_frames_pri2;
3177 __le64 rx_pfc_xon2xoff_frames_pri3;
3178 __le64 rx_pfc_xon2xoff_frames_pri4;
3179 __le64 rx_pfc_xon2xoff_frames_pri5;
3180 __le64 rx_pfc_xon2xoff_frames_pri6;
3181 __le64 rx_pfc_xon2xoff_frames_pri7;
3182 __le64 rx_pfc_ena_frames_pri0;
3183 __le64 rx_pfc_ena_frames_pri1;
3184 __le64 rx_pfc_ena_frames_pri2;
3185 __le64 rx_pfc_ena_frames_pri3;
3186 __le64 rx_pfc_ena_frames_pri4;
3187 __le64 rx_pfc_ena_frames_pri5;
3188 __le64 rx_pfc_ena_frames_pri6;
3189 __le64 rx_pfc_ena_frames_pri7;
3190 __le64 rx_sch_crc_err_frames;
3191 __le64 rx_undrsz_frames;
3192 __le64 rx_frag_frames;
3193 __le64 rx_eee_lpi_events;
3194 __le64 rx_eee_lpi_duration;
3195 __le64 rx_llfc_physical_msgs;
3196 __le64 rx_llfc_logical_msgs;
3197 __le64 rx_llfc_msgs_with_crc_err;
3198 __le64 rx_hcfc_msgs;
3199 __le64 rx_hcfc_msgs_with_crc_err;
3200 __le64 rx_bytes;
3201 __le64 rx_runt_bytes;
3202 __le64 rx_runt_frames;
3203 __le64 rx_stat_discard;
3204 __le64 rx_stat_err;
3205 };
3206
3207 /* hwrm_port_qstats_input (size:320b/40B) */
3208 struct hwrm_port_qstats_input {
3209 __le16 req_type;
3210 __le16 cmpl_ring;
3211 __le16 seq_id;
3212 __le16 target_id;
3213 __le64 resp_addr;
3214 __le16 port_id;
3215 u8 flags;
3216 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL
3217 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
3218 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK
3219 u8 unused_0[5];
3220 __le64 tx_stat_host_addr;
3221 __le64 rx_stat_host_addr;
3222 };
3223
3224 /* hwrm_port_qstats_output (size:128b/16B) */
3225 struct hwrm_port_qstats_output {
3226 __le16 error_code;
3227 __le16 req_type;
3228 __le16 seq_id;
3229 __le16 resp_len;
3230 __le16 tx_stat_size;
3231 __le16 rx_stat_size;
3232 u8 unused_0[3];
3233 u8 valid;
3234 };
3235
3236 /* tx_port_stats_ext (size:2048b/256B) */
3237 struct tx_port_stats_ext {
3238 __le64 tx_bytes_cos0;
3239 __le64 tx_bytes_cos1;
3240 __le64 tx_bytes_cos2;
3241 __le64 tx_bytes_cos3;
3242 __le64 tx_bytes_cos4;
3243 __le64 tx_bytes_cos5;
3244 __le64 tx_bytes_cos6;
3245 __le64 tx_bytes_cos7;
3246 __le64 tx_packets_cos0;
3247 __le64 tx_packets_cos1;
3248 __le64 tx_packets_cos2;
3249 __le64 tx_packets_cos3;
3250 __le64 tx_packets_cos4;
3251 __le64 tx_packets_cos5;
3252 __le64 tx_packets_cos6;
3253 __le64 tx_packets_cos7;
3254 __le64 pfc_pri0_tx_duration_us;
3255 __le64 pfc_pri0_tx_transitions;
3256 __le64 pfc_pri1_tx_duration_us;
3257 __le64 pfc_pri1_tx_transitions;
3258 __le64 pfc_pri2_tx_duration_us;
3259 __le64 pfc_pri2_tx_transitions;
3260 __le64 pfc_pri3_tx_duration_us;
3261 __le64 pfc_pri3_tx_transitions;
3262 __le64 pfc_pri4_tx_duration_us;
3263 __le64 pfc_pri4_tx_transitions;
3264 __le64 pfc_pri5_tx_duration_us;
3265 __le64 pfc_pri5_tx_transitions;
3266 __le64 pfc_pri6_tx_duration_us;
3267 __le64 pfc_pri6_tx_transitions;
3268 __le64 pfc_pri7_tx_duration_us;
3269 __le64 pfc_pri7_tx_transitions;
3270 };
3271
3272 /* rx_port_stats_ext (size:3648b/456B) */
3273 struct rx_port_stats_ext {
3274 __le64 link_down_events;
3275 __le64 continuous_pause_events;
3276 __le64 resume_pause_events;
3277 __le64 continuous_roce_pause_events;
3278 __le64 resume_roce_pause_events;
3279 __le64 rx_bytes_cos0;
3280 __le64 rx_bytes_cos1;
3281 __le64 rx_bytes_cos2;
3282 __le64 rx_bytes_cos3;
3283 __le64 rx_bytes_cos4;
3284 __le64 rx_bytes_cos5;
3285 __le64 rx_bytes_cos6;
3286 __le64 rx_bytes_cos7;
3287 __le64 rx_packets_cos0;
3288 __le64 rx_packets_cos1;
3289 __le64 rx_packets_cos2;
3290 __le64 rx_packets_cos3;
3291 __le64 rx_packets_cos4;
3292 __le64 rx_packets_cos5;
3293 __le64 rx_packets_cos6;
3294 __le64 rx_packets_cos7;
3295 __le64 pfc_pri0_rx_duration_us;
3296 __le64 pfc_pri0_rx_transitions;
3297 __le64 pfc_pri1_rx_duration_us;
3298 __le64 pfc_pri1_rx_transitions;
3299 __le64 pfc_pri2_rx_duration_us;
3300 __le64 pfc_pri2_rx_transitions;
3301 __le64 pfc_pri3_rx_duration_us;
3302 __le64 pfc_pri3_rx_transitions;
3303 __le64 pfc_pri4_rx_duration_us;
3304 __le64 pfc_pri4_rx_transitions;
3305 __le64 pfc_pri5_rx_duration_us;
3306 __le64 pfc_pri5_rx_transitions;
3307 __le64 pfc_pri6_rx_duration_us;
3308 __le64 pfc_pri6_rx_transitions;
3309 __le64 pfc_pri7_rx_duration_us;
3310 __le64 pfc_pri7_rx_transitions;
3311 __le64 rx_bits;
3312 __le64 rx_buffer_passed_threshold;
3313 __le64 rx_pcs_symbol_err;
3314 __le64 rx_corrected_bits;
3315 __le64 rx_discard_bytes_cos0;
3316 __le64 rx_discard_bytes_cos1;
3317 __le64 rx_discard_bytes_cos2;
3318 __le64 rx_discard_bytes_cos3;
3319 __le64 rx_discard_bytes_cos4;
3320 __le64 rx_discard_bytes_cos5;
3321 __le64 rx_discard_bytes_cos6;
3322 __le64 rx_discard_bytes_cos7;
3323 __le64 rx_discard_packets_cos0;
3324 __le64 rx_discard_packets_cos1;
3325 __le64 rx_discard_packets_cos2;
3326 __le64 rx_discard_packets_cos3;
3327 __le64 rx_discard_packets_cos4;
3328 __le64 rx_discard_packets_cos5;
3329 __le64 rx_discard_packets_cos6;
3330 __le64 rx_discard_packets_cos7;
3331 };
3332
3333 /* hwrm_port_qstats_ext_input (size:320b/40B) */
3334 struct hwrm_port_qstats_ext_input {
3335 __le16 req_type;
3336 __le16 cmpl_ring;
3337 __le16 seq_id;
3338 __le16 target_id;
3339 __le64 resp_addr;
3340 __le16 port_id;
3341 __le16 tx_stat_size;
3342 __le16 rx_stat_size;
3343 u8 flags;
3344 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL
3345 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL
3346 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK
3347 u8 unused_0;
3348 __le64 tx_stat_host_addr;
3349 __le64 rx_stat_host_addr;
3350 };
3351
3352 /* hwrm_port_qstats_ext_output (size:128b/16B) */
3353 struct hwrm_port_qstats_ext_output {
3354 __le16 error_code;
3355 __le16 req_type;
3356 __le16 seq_id;
3357 __le16 resp_len;
3358 __le16 tx_stat_size;
3359 __le16 rx_stat_size;
3360 __le16 total_active_cos_queues;
3361 u8 flags;
3362 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
3363 u8 valid;
3364 };
3365
3366 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
3367 struct hwrm_port_lpbk_qstats_input {
3368 __le16 req_type;
3369 __le16 cmpl_ring;
3370 __le16 seq_id;
3371 __le16 target_id;
3372 __le64 resp_addr;
3373 };
3374
3375 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
3376 struct hwrm_port_lpbk_qstats_output {
3377 __le16 error_code;
3378 __le16 req_type;
3379 __le16 seq_id;
3380 __le16 resp_len;
3381 __le64 lpbk_ucast_frames;
3382 __le64 lpbk_mcast_frames;
3383 __le64 lpbk_bcast_frames;
3384 __le64 lpbk_ucast_bytes;
3385 __le64 lpbk_mcast_bytes;
3386 __le64 lpbk_bcast_bytes;
3387 __le64 tx_stat_discard;
3388 __le64 tx_stat_error;
3389 __le64 rx_stat_discard;
3390 __le64 rx_stat_error;
3391 u8 unused_0[7];
3392 u8 valid;
3393 };
3394
3395 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
3396 struct hwrm_port_ecn_qstats_input {
3397 __le16 req_type;
3398 __le16 cmpl_ring;
3399 __le16 seq_id;
3400 __le16 target_id;
3401 __le64 resp_addr;
3402 __le16 port_id;
3403 __le16 ecn_stat_buf_size;
3404 u8 flags;
3405 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL
3406 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
3407 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK
3408 u8 unused_0[3];
3409 __le64 ecn_stat_host_addr;
3410 };
3411
3412 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
3413 struct hwrm_port_ecn_qstats_output {
3414 __le16 error_code;
3415 __le16 req_type;
3416 __le16 seq_id;
3417 __le16 resp_len;
3418 __le16 ecn_stat_buf_size;
3419 u8 mark_en;
3420 u8 unused_0[4];
3421 u8 valid;
3422 };
3423
3424 /* port_stats_ecn (size:512b/64B) */
3425 struct port_stats_ecn {
3426 __le64 mark_cnt_cos0;
3427 __le64 mark_cnt_cos1;
3428 __le64 mark_cnt_cos2;
3429 __le64 mark_cnt_cos3;
3430 __le64 mark_cnt_cos4;
3431 __le64 mark_cnt_cos5;
3432 __le64 mark_cnt_cos6;
3433 __le64 mark_cnt_cos7;
3434 };
3435
3436 /* hwrm_port_clr_stats_input (size:192b/24B) */
3437 struct hwrm_port_clr_stats_input {
3438 __le16 req_type;
3439 __le16 cmpl_ring;
3440 __le16 seq_id;
3441 __le16 target_id;
3442 __le64 resp_addr;
3443 __le16 port_id;
3444 u8 flags;
3445 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
3446 u8 unused_0[5];
3447 };
3448
3449 /* hwrm_port_clr_stats_output (size:128b/16B) */
3450 struct hwrm_port_clr_stats_output {
3451 __le16 error_code;
3452 __le16 req_type;
3453 __le16 seq_id;
3454 __le16 resp_len;
3455 u8 unused_0[7];
3456 u8 valid;
3457 };
3458
3459 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
3460 struct hwrm_port_lpbk_clr_stats_input {
3461 __le16 req_type;
3462 __le16 cmpl_ring;
3463 __le16 seq_id;
3464 __le16 target_id;
3465 __le64 resp_addr;
3466 };
3467
3468 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
3469 struct hwrm_port_lpbk_clr_stats_output {
3470 __le16 error_code;
3471 __le16 req_type;
3472 __le16 seq_id;
3473 __le16 resp_len;
3474 u8 unused_0[7];
3475 u8 valid;
3476 };
3477
3478 /* hwrm_port_ts_query_input (size:192b/24B) */
3479 struct hwrm_port_ts_query_input {
3480 __le16 req_type;
3481 __le16 cmpl_ring;
3482 __le16 seq_id;
3483 __le16 target_id;
3484 __le64 resp_addr;
3485 __le32 flags;
3486 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
3487 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
3488 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
3489 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
3490 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
3491 __le16 port_id;
3492 u8 unused_0[2];
3493 };
3494
3495 /* hwrm_port_ts_query_output (size:192b/24B) */
3496 struct hwrm_port_ts_query_output {
3497 __le16 error_code;
3498 __le16 req_type;
3499 __le16 seq_id;
3500 __le16 resp_len;
3501 __le64 ptp_msg_ts;
3502 __le16 ptp_msg_seqid;
3503 u8 unused_0[5];
3504 u8 valid;
3505 };
3506
3507 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
3508 struct hwrm_port_phy_qcaps_input {
3509 __le16 req_type;
3510 __le16 cmpl_ring;
3511 __le16 seq_id;
3512 __le16 target_id;
3513 __le64 resp_addr;
3514 __le16 port_id;
3515 u8 unused_0[6];
3516 };
3517
3518 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
3519 struct hwrm_port_phy_qcaps_output {
3520 __le16 error_code;
3521 __le16 req_type;
3522 __le16 seq_id;
3523 __le16 resp_len;
3524 u8 flags;
3525 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
3526 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
3527 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL
3528 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL
3529 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL
3530 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL
3531 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xc0UL
3532 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 6
3533 u8 port_cnt;
3534 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
3535 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
3536 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
3537 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
3538 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
3539 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
3540 __le16 supported_speeds_force_mode;
3541 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
3542 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
3543 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
3544 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
3545 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
3546 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
3547 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
3548 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
3549 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
3550 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
3551 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
3552 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
3553 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
3554 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
3555 __le16 supported_speeds_auto_mode;
3556 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
3557 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
3558 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
3559 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
3560 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
3561 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
3562 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
3563 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
3564 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
3565 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
3566 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
3567 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
3568 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
3569 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
3570 __le16 supported_speeds_eee_mode;
3571 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
3572 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
3573 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
3574 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
3575 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
3576 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
3577 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
3578 __le32 tx_lpi_timer_low;
3579 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
3580 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
3581 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
3582 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
3583 __le32 valid_tx_lpi_timer_high;
3584 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
3585 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
3586 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL
3587 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24
3588 __le16 supported_pam4_speeds_auto_mode;
3589 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
3590 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
3591 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
3592 __le16 supported_pam4_speeds_force_mode;
3593 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
3594 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
3595 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
3596 u8 unused_0[3];
3597 u8 valid;
3598 };
3599
3600 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
3601 struct hwrm_port_phy_i2c_read_input {
3602 __le16 req_type;
3603 __le16 cmpl_ring;
3604 __le16 seq_id;
3605 __le16 target_id;
3606 __le64 resp_addr;
3607 __le32 flags;
3608 __le32 enables;
3609 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
3610 __le16 port_id;
3611 u8 i2c_slave_addr;
3612 u8 unused_0;
3613 __le16 page_number;
3614 __le16 page_offset;
3615 u8 data_length;
3616 u8 unused_1[7];
3617 };
3618
3619 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
3620 struct hwrm_port_phy_i2c_read_output {
3621 __le16 error_code;
3622 __le16 req_type;
3623 __le16 seq_id;
3624 __le16 resp_len;
3625 __le32 data[16];
3626 u8 unused_0[7];
3627 u8 valid;
3628 };
3629
3630 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
3631 struct hwrm_port_phy_mdio_write_input {
3632 __le16 req_type;
3633 __le16 cmpl_ring;
3634 __le16 seq_id;
3635 __le16 target_id;
3636 __le64 resp_addr;
3637 __le32 unused_0[2];
3638 __le16 port_id;
3639 u8 phy_addr;
3640 u8 dev_addr;
3641 __le16 reg_addr;
3642 __le16 reg_data;
3643 u8 cl45_mdio;
3644 u8 unused_1[7];
3645 };
3646
3647 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
3648 struct hwrm_port_phy_mdio_write_output {
3649 __le16 error_code;
3650 __le16 req_type;
3651 __le16 seq_id;
3652 __le16 resp_len;
3653 u8 unused_0[7];
3654 u8 valid;
3655 };
3656
3657 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
3658 struct hwrm_port_phy_mdio_read_input {
3659 __le16 req_type;
3660 __le16 cmpl_ring;
3661 __le16 seq_id;
3662 __le16 target_id;
3663 __le64 resp_addr;
3664 __le32 unused_0[2];
3665 __le16 port_id;
3666 u8 phy_addr;
3667 u8 dev_addr;
3668 __le16 reg_addr;
3669 u8 cl45_mdio;
3670 u8 unused_1;
3671 };
3672
3673 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
3674 struct hwrm_port_phy_mdio_read_output {
3675 __le16 error_code;
3676 __le16 req_type;
3677 __le16 seq_id;
3678 __le16 resp_len;
3679 __le16 reg_data;
3680 u8 unused_0[5];
3681 u8 valid;
3682 };
3683
3684 /* hwrm_port_led_cfg_input (size:512b/64B) */
3685 struct hwrm_port_led_cfg_input {
3686 __le16 req_type;
3687 __le16 cmpl_ring;
3688 __le16 seq_id;
3689 __le16 target_id;
3690 __le64 resp_addr;
3691 __le32 enables;
3692 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
3693 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
3694 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
3695 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
3696 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
3697 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
3698 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
3699 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
3700 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
3701 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
3702 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
3703 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
3704 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
3705 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
3706 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
3707 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
3708 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
3709 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
3710 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
3711 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
3712 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
3713 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
3714 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
3715 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
3716 __le16 port_id;
3717 u8 num_leds;
3718 u8 rsvd;
3719 u8 led0_id;
3720 u8 led0_state;
3721 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
3722 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
3723 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
3724 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
3725 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
3726 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
3727 u8 led0_color;
3728 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
3729 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
3730 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
3731 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
3732 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
3733 u8 unused_0;
3734 __le16 led0_blink_on;
3735 __le16 led0_blink_off;
3736 u8 led0_group_id;
3737 u8 rsvd0;
3738 u8 led1_id;
3739 u8 led1_state;
3740 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
3741 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
3742 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
3743 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
3744 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
3745 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
3746 u8 led1_color;
3747 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
3748 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
3749 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
3750 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
3751 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
3752 u8 unused_1;
3753 __le16 led1_blink_on;
3754 __le16 led1_blink_off;
3755 u8 led1_group_id;
3756 u8 rsvd1;
3757 u8 led2_id;
3758 u8 led2_state;
3759 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
3760 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
3761 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
3762 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
3763 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
3764 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
3765 u8 led2_color;
3766 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
3767 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
3768 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
3769 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
3770 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
3771 u8 unused_2;
3772 __le16 led2_blink_on;
3773 __le16 led2_blink_off;
3774 u8 led2_group_id;
3775 u8 rsvd2;
3776 u8 led3_id;
3777 u8 led3_state;
3778 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
3779 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
3780 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
3781 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
3782 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
3783 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
3784 u8 led3_color;
3785 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
3786 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
3787 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
3788 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
3789 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
3790 u8 unused_3;
3791 __le16 led3_blink_on;
3792 __le16 led3_blink_off;
3793 u8 led3_group_id;
3794 u8 rsvd3;
3795 };
3796
3797 /* hwrm_port_led_cfg_output (size:128b/16B) */
3798 struct hwrm_port_led_cfg_output {
3799 __le16 error_code;
3800 __le16 req_type;
3801 __le16 seq_id;
3802 __le16 resp_len;
3803 u8 unused_0[7];
3804 u8 valid;
3805 };
3806
3807 /* hwrm_port_led_qcfg_input (size:192b/24B) */
3808 struct hwrm_port_led_qcfg_input {
3809 __le16 req_type;
3810 __le16 cmpl_ring;
3811 __le16 seq_id;
3812 __le16 target_id;
3813 __le64 resp_addr;
3814 __le16 port_id;
3815 u8 unused_0[6];
3816 };
3817
3818 /* hwrm_port_led_qcfg_output (size:448b/56B) */
3819 struct hwrm_port_led_qcfg_output {
3820 __le16 error_code;
3821 __le16 req_type;
3822 __le16 seq_id;
3823 __le16 resp_len;
3824 u8 num_leds;
3825 u8 led0_id;
3826 u8 led0_type;
3827 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
3828 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
3829 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
3830 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
3831 u8 led0_state;
3832 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
3833 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
3834 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
3835 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
3836 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
3837 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
3838 u8 led0_color;
3839 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
3840 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
3841 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
3842 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
3843 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
3844 u8 unused_0;
3845 __le16 led0_blink_on;
3846 __le16 led0_blink_off;
3847 u8 led0_group_id;
3848 u8 led1_id;
3849 u8 led1_type;
3850 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
3851 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
3852 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
3853 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
3854 u8 led1_state;
3855 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
3856 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
3857 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
3858 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
3859 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
3860 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
3861 u8 led1_color;
3862 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
3863 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
3864 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
3865 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
3866 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
3867 u8 unused_1;
3868 __le16 led1_blink_on;
3869 __le16 led1_blink_off;
3870 u8 led1_group_id;
3871 u8 led2_id;
3872 u8 led2_type;
3873 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
3874 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
3875 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
3876 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
3877 u8 led2_state;
3878 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
3879 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
3880 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
3881 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
3882 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
3883 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
3884 u8 led2_color;
3885 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
3886 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
3887 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
3888 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
3889 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
3890 u8 unused_2;
3891 __le16 led2_blink_on;
3892 __le16 led2_blink_off;
3893 u8 led2_group_id;
3894 u8 led3_id;
3895 u8 led3_type;
3896 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
3897 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
3898 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
3899 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
3900 u8 led3_state;
3901 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
3902 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
3903 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
3904 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
3905 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
3906 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
3907 u8 led3_color;
3908 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
3909 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
3910 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
3911 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
3912 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
3913 u8 unused_3;
3914 __le16 led3_blink_on;
3915 __le16 led3_blink_off;
3916 u8 led3_group_id;
3917 u8 unused_4[6];
3918 u8 valid;
3919 };
3920
3921 /* hwrm_port_led_qcaps_input (size:192b/24B) */
3922 struct hwrm_port_led_qcaps_input {
3923 __le16 req_type;
3924 __le16 cmpl_ring;
3925 __le16 seq_id;
3926 __le16 target_id;
3927 __le64 resp_addr;
3928 __le16 port_id;
3929 u8 unused_0[6];
3930 };
3931
3932 /* hwrm_port_led_qcaps_output (size:384b/48B) */
3933 struct hwrm_port_led_qcaps_output {
3934 __le16 error_code;
3935 __le16 req_type;
3936 __le16 seq_id;
3937 __le16 resp_len;
3938 u8 num_leds;
3939 u8 unused[3];
3940 u8 led0_id;
3941 u8 led0_type;
3942 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
3943 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
3944 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
3945 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
3946 u8 led0_group_id;
3947 u8 unused_0;
3948 __le16 led0_state_caps;
3949 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
3950 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
3951 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
3952 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3953 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3954 __le16 led0_color_caps;
3955 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
3956 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3957 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3958 u8 led1_id;
3959 u8 led1_type;
3960 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
3961 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
3962 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
3963 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
3964 u8 led1_group_id;
3965 u8 unused_1;
3966 __le16 led1_state_caps;
3967 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
3968 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
3969 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
3970 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3971 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3972 __le16 led1_color_caps;
3973 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
3974 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3975 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3976 u8 led2_id;
3977 u8 led2_type;
3978 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
3979 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
3980 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
3981 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
3982 u8 led2_group_id;
3983 u8 unused_2;
3984 __le16 led2_state_caps;
3985 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
3986 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
3987 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
3988 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3989 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3990 __le16 led2_color_caps;
3991 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
3992 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3993 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3994 u8 led3_id;
3995 u8 led3_type;
3996 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
3997 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
3998 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
3999 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
4000 u8 led3_group_id;
4001 u8 unused_3;
4002 __le16 led3_state_caps;
4003 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
4004 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
4005 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
4006 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
4007 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
4008 __le16 led3_color_caps;
4009 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
4010 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
4011 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
4012 u8 unused_4[3];
4013 u8 valid;
4014 };
4015
4016 /* hwrm_queue_qportcfg_input (size:192b/24B) */
4017 struct hwrm_queue_qportcfg_input {
4018 __le16 req_type;
4019 __le16 cmpl_ring;
4020 __le16 seq_id;
4021 __le16 target_id;
4022 __le64 resp_addr;
4023 __le32 flags;
4024 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
4025 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
4026 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
4027 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
4028 __le16 port_id;
4029 u8 drv_qmap_cap;
4030 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
4031 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
4032 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
4033 u8 unused_0;
4034 };
4035
4036 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
4037 struct hwrm_queue_qportcfg_output {
4038 __le16 error_code;
4039 __le16 req_type;
4040 __le16 seq_id;
4041 __le16 resp_len;
4042 u8 max_configurable_queues;
4043 u8 max_configurable_lossless_queues;
4044 u8 queue_cfg_allowed;
4045 u8 queue_cfg_info;
4046 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
4047 u8 queue_pfcenable_cfg_allowed;
4048 u8 queue_pri2cos_cfg_allowed;
4049 u8 queue_cos2bw_cfg_allowed;
4050 u8 queue_id0;
4051 u8 queue_id0_service_profile;
4052 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
4053 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
4054 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4055 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4056 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4057 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
4058 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
4059 u8 queue_id1;
4060 u8 queue_id1_service_profile;
4061 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
4062 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
4063 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4064 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4065 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4066 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
4067 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
4068 u8 queue_id2;
4069 u8 queue_id2_service_profile;
4070 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
4071 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
4072 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4073 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4074 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4075 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
4076 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
4077 u8 queue_id3;
4078 u8 queue_id3_service_profile;
4079 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
4080 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
4081 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4082 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4083 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4084 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
4085 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
4086 u8 queue_id4;
4087 u8 queue_id4_service_profile;
4088 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
4089 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
4090 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4091 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4092 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4093 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
4094 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
4095 u8 queue_id5;
4096 u8 queue_id5_service_profile;
4097 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
4098 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
4099 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4100 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4101 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4102 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
4103 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
4104 u8 queue_id6;
4105 u8 queue_id6_service_profile;
4106 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
4107 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
4108 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4109 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4110 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4111 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
4112 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
4113 u8 queue_id7;
4114 u8 queue_id7_service_profile;
4115 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
4116 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
4117 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4118 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4119 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4120 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
4121 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
4122 u8 unused_0;
4123 char qid0_name[16];
4124 char qid1_name[16];
4125 char qid2_name[16];
4126 char qid3_name[16];
4127 char qid4_name[16];
4128 char qid5_name[16];
4129 char qid6_name[16];
4130 char qid7_name[16];
4131 u8 unused_1[7];
4132 u8 valid;
4133 };
4134
4135 /* hwrm_queue_qcfg_input (size:192b/24B) */
4136 struct hwrm_queue_qcfg_input {
4137 __le16 req_type;
4138 __le16 cmpl_ring;
4139 __le16 seq_id;
4140 __le16 target_id;
4141 __le64 resp_addr;
4142 __le32 flags;
4143 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL
4144 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL
4145 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL
4146 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
4147 __le32 queue_id;
4148 };
4149
4150 /* hwrm_queue_qcfg_output (size:128b/16B) */
4151 struct hwrm_queue_qcfg_output {
4152 __le16 error_code;
4153 __le16 req_type;
4154 __le16 seq_id;
4155 __le16 resp_len;
4156 __le32 queue_len;
4157 u8 service_profile;
4158 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL
4159 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
4160 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL
4161 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
4162 u8 queue_cfg_info;
4163 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
4164 u8 unused_0;
4165 u8 valid;
4166 };
4167
4168 /* hwrm_queue_cfg_input (size:320b/40B) */
4169 struct hwrm_queue_cfg_input {
4170 __le16 req_type;
4171 __le16 cmpl_ring;
4172 __le16 seq_id;
4173 __le16 target_id;
4174 __le64 resp_addr;
4175 __le32 flags;
4176 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
4177 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
4178 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
4179 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
4180 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
4181 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
4182 __le32 enables;
4183 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
4184 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
4185 __le32 queue_id;
4186 __le32 dflt_len;
4187 u8 service_profile;
4188 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
4189 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
4190 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
4191 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
4192 u8 unused_0[7];
4193 };
4194
4195 /* hwrm_queue_cfg_output (size:128b/16B) */
4196 struct hwrm_queue_cfg_output {
4197 __le16 error_code;
4198 __le16 req_type;
4199 __le16 seq_id;
4200 __le16 resp_len;
4201 u8 unused_0[7];
4202 u8 valid;
4203 };
4204
4205 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
4206 struct hwrm_queue_pfcenable_qcfg_input {
4207 __le16 req_type;
4208 __le16 cmpl_ring;
4209 __le16 seq_id;
4210 __le16 target_id;
4211 __le64 resp_addr;
4212 __le16 port_id;
4213 u8 unused_0[6];
4214 };
4215
4216 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
4217 struct hwrm_queue_pfcenable_qcfg_output {
4218 __le16 error_code;
4219 __le16 req_type;
4220 __le16 seq_id;
4221 __le16 resp_len;
4222 __le32 flags;
4223 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
4224 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
4225 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
4226 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
4227 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
4228 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
4229 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
4230 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
4231 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
4232 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
4233 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
4234 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
4235 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
4236 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
4237 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
4238 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
4239 u8 unused_0[3];
4240 u8 valid;
4241 };
4242
4243 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
4244 struct hwrm_queue_pfcenable_cfg_input {
4245 __le16 req_type;
4246 __le16 cmpl_ring;
4247 __le16 seq_id;
4248 __le16 target_id;
4249 __le64 resp_addr;
4250 __le32 flags;
4251 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
4252 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
4253 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
4254 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
4255 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
4256 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
4257 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
4258 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
4259 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
4260 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
4261 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
4262 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
4263 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
4264 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
4265 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
4266 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
4267 __le16 port_id;
4268 u8 unused_0[2];
4269 };
4270
4271 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
4272 struct hwrm_queue_pfcenable_cfg_output {
4273 __le16 error_code;
4274 __le16 req_type;
4275 __le16 seq_id;
4276 __le16 resp_len;
4277 u8 unused_0[7];
4278 u8 valid;
4279 };
4280
4281 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
4282 struct hwrm_queue_pri2cos_qcfg_input {
4283 __le16 req_type;
4284 __le16 cmpl_ring;
4285 __le16 seq_id;
4286 __le16 target_id;
4287 __le64 resp_addr;
4288 __le32 flags;
4289 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
4290 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
4291 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
4292 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
4293 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
4294 u8 port_id;
4295 u8 unused_0[3];
4296 };
4297
4298 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
4299 struct hwrm_queue_pri2cos_qcfg_output {
4300 __le16 error_code;
4301 __le16 req_type;
4302 __le16 seq_id;
4303 __le16 resp_len;
4304 u8 pri0_cos_queue_id;
4305 u8 pri1_cos_queue_id;
4306 u8 pri2_cos_queue_id;
4307 u8 pri3_cos_queue_id;
4308 u8 pri4_cos_queue_id;
4309 u8 pri5_cos_queue_id;
4310 u8 pri6_cos_queue_id;
4311 u8 pri7_cos_queue_id;
4312 u8 queue_cfg_info;
4313 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
4314 u8 unused_0[6];
4315 u8 valid;
4316 };
4317
4318 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
4319 struct hwrm_queue_pri2cos_cfg_input {
4320 __le16 req_type;
4321 __le16 cmpl_ring;
4322 __le16 seq_id;
4323 __le16 target_id;
4324 __le64 resp_addr;
4325 __le32 flags;
4326 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
4327 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
4328 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
4329 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
4330 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
4331 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
4332 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
4333 __le32 enables;
4334 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
4335 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
4336 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
4337 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
4338 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
4339 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
4340 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
4341 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
4342 u8 port_id;
4343 u8 pri0_cos_queue_id;
4344 u8 pri1_cos_queue_id;
4345 u8 pri2_cos_queue_id;
4346 u8 pri3_cos_queue_id;
4347 u8 pri4_cos_queue_id;
4348 u8 pri5_cos_queue_id;
4349 u8 pri6_cos_queue_id;
4350 u8 pri7_cos_queue_id;
4351 u8 unused_0[7];
4352 };
4353
4354 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
4355 struct hwrm_queue_pri2cos_cfg_output {
4356 __le16 error_code;
4357 __le16 req_type;
4358 __le16 seq_id;
4359 __le16 resp_len;
4360 u8 unused_0[7];
4361 u8 valid;
4362 };
4363
4364 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
4365 struct hwrm_queue_cos2bw_qcfg_input {
4366 __le16 req_type;
4367 __le16 cmpl_ring;
4368 __le16 seq_id;
4369 __le16 target_id;
4370 __le64 resp_addr;
4371 __le16 port_id;
4372 u8 unused_0[6];
4373 };
4374
4375 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
4376 struct hwrm_queue_cos2bw_qcfg_output {
4377 __le16 error_code;
4378 __le16 req_type;
4379 __le16 seq_id;
4380 __le16 resp_len;
4381 u8 queue_id0;
4382 u8 unused_0;
4383 __le16 unused_1;
4384 __le32 queue_id0_min_bw;
4385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
4387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
4388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
4389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
4390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
4391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
4393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4397 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4399 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4400 __le32 queue_id0_max_bw;
4401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
4403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
4404 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
4405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
4406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
4407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
4409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4410 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4416 u8 queue_id0_tsa_assign;
4417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
4418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
4419 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4420 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
4421 u8 queue_id0_pri_lvl;
4422 u8 queue_id0_bw_weight;
4423 u8 queue_id1;
4424 __le32 queue_id1_min_bw;
4425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
4427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
4428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
4429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
4430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
4431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4432 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
4433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4437 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4438 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4439 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4440 __le32 queue_id1_max_bw;
4441 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4442 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
4443 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
4444 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
4445 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
4446 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
4447 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4448 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
4449 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4450 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4451 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4452 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4453 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4454 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4455 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4456 u8 queue_id1_tsa_assign;
4457 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
4458 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
4459 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4460 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
4461 u8 queue_id1_pri_lvl;
4462 u8 queue_id1_bw_weight;
4463 u8 queue_id2;
4464 __le32 queue_id2_min_bw;
4465 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4466 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
4467 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
4468 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
4469 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
4470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
4471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
4473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4480 __le32 queue_id2_max_bw;
4481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
4483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
4484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
4485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
4486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
4487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
4489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4496 u8 queue_id2_tsa_assign;
4497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
4498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
4499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
4501 u8 queue_id2_pri_lvl;
4502 u8 queue_id2_bw_weight;
4503 u8 queue_id3;
4504 __le32 queue_id3_min_bw;
4505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
4507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
4508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
4509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
4510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
4511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
4513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4520 __le32 queue_id3_max_bw;
4521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
4523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
4524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
4525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
4526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
4527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
4529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4536 u8 queue_id3_tsa_assign;
4537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
4538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
4539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
4541 u8 queue_id3_pri_lvl;
4542 u8 queue_id3_bw_weight;
4543 u8 queue_id4;
4544 __le32 queue_id4_min_bw;
4545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
4547 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
4548 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
4549 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
4550 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
4551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
4553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4560 __le32 queue_id4_max_bw;
4561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
4563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
4564 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
4565 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
4566 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
4567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4568 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
4569 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4576 u8 queue_id4_tsa_assign;
4577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
4578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
4579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
4581 u8 queue_id4_pri_lvl;
4582 u8 queue_id4_bw_weight;
4583 u8 queue_id5;
4584 __le32 queue_id5_min_bw;
4585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
4587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
4588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
4589 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
4590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
4591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
4593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4600 __le32 queue_id5_max_bw;
4601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
4603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
4604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
4605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
4606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
4607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
4609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4616 u8 queue_id5_tsa_assign;
4617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
4618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
4619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
4621 u8 queue_id5_pri_lvl;
4622 u8 queue_id5_bw_weight;
4623 u8 queue_id6;
4624 __le32 queue_id6_min_bw;
4625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
4627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
4628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
4629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
4630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
4631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
4633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4640 __le32 queue_id6_max_bw;
4641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
4643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
4644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
4645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
4646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
4647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
4649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4656 u8 queue_id6_tsa_assign;
4657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
4658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
4659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
4661 u8 queue_id6_pri_lvl;
4662 u8 queue_id6_bw_weight;
4663 u8 queue_id7;
4664 __le32 queue_id7_min_bw;
4665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
4668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
4669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
4670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
4671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
4673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4680 __le32 queue_id7_max_bw;
4681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
4683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
4684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
4685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
4686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
4687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
4689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4696 u8 queue_id7_tsa_assign;
4697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
4698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
4699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
4701 u8 queue_id7_pri_lvl;
4702 u8 queue_id7_bw_weight;
4703 u8 unused_2[4];
4704 u8 valid;
4705 };
4706
4707 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
4708 struct hwrm_queue_cos2bw_cfg_input {
4709 __le16 req_type;
4710 __le16 cmpl_ring;
4711 __le16 seq_id;
4712 __le16 target_id;
4713 __le64 resp_addr;
4714 __le32 flags;
4715 __le32 enables;
4716 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
4717 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
4718 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
4719 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
4720 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
4721 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
4722 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
4723 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
4724 __le16 port_id;
4725 u8 queue_id0;
4726 u8 unused_0;
4727 __le32 queue_id0_min_bw;
4728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
4730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
4731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
4732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
4733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
4734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4735 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
4736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4740 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4742 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4743 __le32 queue_id0_max_bw;
4744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4745 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
4746 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
4747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
4748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
4749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
4750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
4752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4756 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4758 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4759 u8 queue_id0_tsa_assign;
4760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
4761 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
4762 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4763 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
4764 u8 queue_id0_pri_lvl;
4765 u8 queue_id0_bw_weight;
4766 u8 queue_id1;
4767 __le32 queue_id1_min_bw;
4768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4769 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
4770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
4771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
4772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
4773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
4774 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4775 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
4776 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4777 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4778 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4780 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4781 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4782 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4783 __le32 queue_id1_max_bw;
4784 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4785 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
4786 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
4787 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
4788 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
4789 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
4790 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4791 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
4792 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4793 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4794 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4795 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4796 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4797 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4798 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4799 u8 queue_id1_tsa_assign;
4800 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
4801 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
4802 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4803 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
4804 u8 queue_id1_pri_lvl;
4805 u8 queue_id1_bw_weight;
4806 u8 queue_id2;
4807 __le32 queue_id2_min_bw;
4808 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4809 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
4810 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
4811 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
4812 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
4813 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
4814 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4815 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
4816 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4820 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4823 __le32 queue_id2_max_bw;
4824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
4826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
4827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
4828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
4829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
4830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
4832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4836 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4839 u8 queue_id2_tsa_assign;
4840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
4841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
4842 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4843 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
4844 u8 queue_id2_pri_lvl;
4845 u8 queue_id2_bw_weight;
4846 u8 queue_id3;
4847 __le32 queue_id3_min_bw;
4848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
4850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
4851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
4852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
4853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
4854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
4856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4863 __le32 queue_id3_max_bw;
4864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
4866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
4867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
4868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
4869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
4870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
4872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4879 u8 queue_id3_tsa_assign;
4880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
4881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
4882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
4884 u8 queue_id3_pri_lvl;
4885 u8 queue_id3_bw_weight;
4886 u8 queue_id4;
4887 __le32 queue_id4_min_bw;
4888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
4890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
4891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
4892 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
4893 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
4894 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
4896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4903 __le32 queue_id4_max_bw;
4904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
4906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
4907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
4908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
4909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
4910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
4912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4919 u8 queue_id4_tsa_assign;
4920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
4921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
4922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
4924 u8 queue_id4_pri_lvl;
4925 u8 queue_id4_bw_weight;
4926 u8 queue_id5;
4927 __le32 queue_id5_min_bw;
4928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
4930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
4931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
4932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
4933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
4934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
4936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4943 __le32 queue_id5_max_bw;
4944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
4946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
4947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
4948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
4949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
4950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
4952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4959 u8 queue_id5_tsa_assign;
4960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
4961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
4962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
4964 u8 queue_id5_pri_lvl;
4965 u8 queue_id5_bw_weight;
4966 u8 queue_id6;
4967 __le32 queue_id6_min_bw;
4968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
4970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
4971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
4972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
4973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
4974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
4976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4983 __le32 queue_id6_max_bw;
4984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
4986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
4987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
4988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
4989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
4990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
4992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4999 u8 queue_id6_tsa_assign;
5000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
5001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
5002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
5004 u8 queue_id6_pri_lvl;
5005 u8 queue_id6_bw_weight;
5006 u8 queue_id7;
5007 __le32 queue_id7_min_bw;
5008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
5010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
5011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
5012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
5013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
5014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
5016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
5023 __le32 queue_id7_max_bw;
5024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
5026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
5027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
5028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
5029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
5030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
5032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
5039 u8 queue_id7_tsa_assign;
5040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
5041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
5042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
5044 u8 queue_id7_pri_lvl;
5045 u8 queue_id7_bw_weight;
5046 u8 unused_1[5];
5047 };
5048
5049 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
5050 struct hwrm_queue_cos2bw_cfg_output {
5051 __le16 error_code;
5052 __le16 req_type;
5053 __le16 seq_id;
5054 __le16 resp_len;
5055 u8 unused_0[7];
5056 u8 valid;
5057 };
5058
5059 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
5060 struct hwrm_queue_dscp_qcaps_input {
5061 __le16 req_type;
5062 __le16 cmpl_ring;
5063 __le16 seq_id;
5064 __le16 target_id;
5065 __le64 resp_addr;
5066 u8 port_id;
5067 u8 unused_0[7];
5068 };
5069
5070 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
5071 struct hwrm_queue_dscp_qcaps_output {
5072 __le16 error_code;
5073 __le16 req_type;
5074 __le16 seq_id;
5075 __le16 resp_len;
5076 u8 num_dscp_bits;
5077 u8 unused_0;
5078 __le16 max_entries;
5079 u8 unused_1[3];
5080 u8 valid;
5081 };
5082
5083 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
5084 struct hwrm_queue_dscp2pri_qcfg_input {
5085 __le16 req_type;
5086 __le16 cmpl_ring;
5087 __le16 seq_id;
5088 __le16 target_id;
5089 __le64 resp_addr;
5090 __le64 dest_data_addr;
5091 u8 port_id;
5092 u8 unused_0;
5093 __le16 dest_data_buffer_size;
5094 u8 unused_1[4];
5095 };
5096
5097 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
5098 struct hwrm_queue_dscp2pri_qcfg_output {
5099 __le16 error_code;
5100 __le16 req_type;
5101 __le16 seq_id;
5102 __le16 resp_len;
5103 __le16 entry_cnt;
5104 u8 default_pri;
5105 u8 unused_0[4];
5106 u8 valid;
5107 };
5108
5109 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
5110 struct hwrm_queue_dscp2pri_cfg_input {
5111 __le16 req_type;
5112 __le16 cmpl_ring;
5113 __le16 seq_id;
5114 __le16 target_id;
5115 __le64 resp_addr;
5116 __le64 src_data_addr;
5117 __le32 flags;
5118 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
5119 __le32 enables;
5120 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
5121 u8 port_id;
5122 u8 default_pri;
5123 __le16 entry_cnt;
5124 u8 unused_0[4];
5125 };
5126
5127 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
5128 struct hwrm_queue_dscp2pri_cfg_output {
5129 __le16 error_code;
5130 __le16 req_type;
5131 __le16 seq_id;
5132 __le16 resp_len;
5133 u8 unused_0[7];
5134 u8 valid;
5135 };
5136
5137 /* hwrm_vnic_alloc_input (size:192b/24B) */
5138 struct hwrm_vnic_alloc_input {
5139 __le16 req_type;
5140 __le16 cmpl_ring;
5141 __le16 seq_id;
5142 __le16 target_id;
5143 __le64 resp_addr;
5144 __le32 flags;
5145 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
5146 u8 unused_0[4];
5147 };
5148
5149 /* hwrm_vnic_alloc_output (size:128b/16B) */
5150 struct hwrm_vnic_alloc_output {
5151 __le16 error_code;
5152 __le16 req_type;
5153 __le16 seq_id;
5154 __le16 resp_len;
5155 __le32 vnic_id;
5156 u8 unused_0[3];
5157 u8 valid;
5158 };
5159
5160 /* hwrm_vnic_free_input (size:192b/24B) */
5161 struct hwrm_vnic_free_input {
5162 __le16 req_type;
5163 __le16 cmpl_ring;
5164 __le16 seq_id;
5165 __le16 target_id;
5166 __le64 resp_addr;
5167 __le32 vnic_id;
5168 u8 unused_0[4];
5169 };
5170
5171 /* hwrm_vnic_free_output (size:128b/16B) */
5172 struct hwrm_vnic_free_output {
5173 __le16 error_code;
5174 __le16 req_type;
5175 __le16 seq_id;
5176 __le16 resp_len;
5177 u8 unused_0[7];
5178 u8 valid;
5179 };
5180
5181 /* hwrm_vnic_cfg_input (size:384b/48B) */
5182 struct hwrm_vnic_cfg_input {
5183 __le16 req_type;
5184 __le16 cmpl_ring;
5185 __le16 seq_id;
5186 __le16 target_id;
5187 __le64 resp_addr;
5188 __le32 flags;
5189 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
5190 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
5191 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
5192 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
5193 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
5194 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
5195 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
5196 __le32 enables;
5197 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
5198 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
5199 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
5200 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
5201 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
5202 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
5203 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
5204 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
5205 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
5206 __le16 vnic_id;
5207 __le16 dflt_ring_grp;
5208 __le16 rss_rule;
5209 __le16 cos_rule;
5210 __le16 lb_rule;
5211 __le16 mru;
5212 __le16 default_rx_ring_id;
5213 __le16 default_cmpl_ring_id;
5214 __le16 queue_id;
5215 u8 rx_csum_v2_mode;
5216 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL
5217 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL
5218 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL
5219 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX
5220 u8 unused0[5];
5221 };
5222
5223 /* hwrm_vnic_cfg_output (size:128b/16B) */
5224 struct hwrm_vnic_cfg_output {
5225 __le16 error_code;
5226 __le16 req_type;
5227 __le16 seq_id;
5228 __le16 resp_len;
5229 u8 unused_0[7];
5230 u8 valid;
5231 };
5232
5233 /* hwrm_vnic_qcaps_input (size:192b/24B) */
5234 struct hwrm_vnic_qcaps_input {
5235 __le16 req_type;
5236 __le16 cmpl_ring;
5237 __le16 seq_id;
5238 __le16 target_id;
5239 __le64 resp_addr;
5240 __le32 enables;
5241 u8 unused_0[4];
5242 };
5243
5244 /* hwrm_vnic_qcaps_output (size:192b/24B) */
5245 struct hwrm_vnic_qcaps_output {
5246 __le16 error_code;
5247 __le16 req_type;
5248 __le16 seq_id;
5249 __le16 resp_len;
5250 __le16 mru;
5251 u8 unused_0[2];
5252 __le32 flags;
5253 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
5254 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
5255 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
5256 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
5257 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
5258 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
5259 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
5260 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
5261 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
5262 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL
5263 __le16 max_aggs_supported;
5264 u8 unused_1[5];
5265 u8 valid;
5266 };
5267
5268 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
5269 struct hwrm_vnic_tpa_cfg_input {
5270 __le16 req_type;
5271 __le16 cmpl_ring;
5272 __le16 seq_id;
5273 __le16 target_id;
5274 __le64 resp_addr;
5275 __le32 flags;
5276 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
5277 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
5278 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
5279 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
5280 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
5281 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
5282 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
5283 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
5284 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL
5285 __le32 enables;
5286 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
5287 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
5288 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
5289 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
5290 __le16 vnic_id;
5291 __le16 max_agg_segs;
5292 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
5293 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
5294 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
5295 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
5296 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
5297 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
5298 __le16 max_aggs;
5299 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
5300 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
5301 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
5302 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
5303 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
5304 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
5305 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
5306 u8 unused_0[2];
5307 __le32 max_agg_timer;
5308 __le32 min_agg_len;
5309 };
5310
5311 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
5312 struct hwrm_vnic_tpa_cfg_output {
5313 __le16 error_code;
5314 __le16 req_type;
5315 __le16 seq_id;
5316 __le16 resp_len;
5317 u8 unused_0[7];
5318 u8 valid;
5319 };
5320
5321 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
5322 struct hwrm_vnic_tpa_qcfg_input {
5323 __le16 req_type;
5324 __le16 cmpl_ring;
5325 __le16 seq_id;
5326 __le16 target_id;
5327 __le64 resp_addr;
5328 __le16 vnic_id;
5329 u8 unused_0[6];
5330 };
5331
5332 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
5333 struct hwrm_vnic_tpa_qcfg_output {
5334 __le16 error_code;
5335 __le16 req_type;
5336 __le16 seq_id;
5337 __le16 resp_len;
5338 __le32 flags;
5339 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
5340 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
5341 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
5342 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
5343 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
5344 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
5345 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
5346 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
5347 __le16 max_agg_segs;
5348 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
5349 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
5350 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
5351 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
5352 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
5353 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
5354 __le16 max_aggs;
5355 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
5356 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
5357 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
5358 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
5359 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
5360 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
5361 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
5362 __le32 max_agg_timer;
5363 __le32 min_agg_len;
5364 u8 unused_0[7];
5365 u8 valid;
5366 };
5367
5368 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
5369 struct hwrm_vnic_rss_cfg_input {
5370 __le16 req_type;
5371 __le16 cmpl_ring;
5372 __le16 seq_id;
5373 __le16 target_id;
5374 __le64 resp_addr;
5375 __le32 hash_type;
5376 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
5377 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
5378 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
5379 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
5380 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
5381 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
5382 __le16 vnic_id;
5383 u8 ring_table_pair_index;
5384 u8 hash_mode_flags;
5385 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
5386 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
5387 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
5388 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
5389 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
5390 __le64 ring_grp_tbl_addr;
5391 __le64 hash_key_tbl_addr;
5392 __le16 rss_ctx_idx;
5393 u8 unused_1[6];
5394 };
5395
5396 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
5397 struct hwrm_vnic_rss_cfg_output {
5398 __le16 error_code;
5399 __le16 req_type;
5400 __le16 seq_id;
5401 __le16 resp_len;
5402 u8 unused_0[7];
5403 u8 valid;
5404 };
5405
5406 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
5407 struct hwrm_vnic_rss_cfg_cmd_err {
5408 u8 code;
5409 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
5410 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
5411 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
5412 u8 unused_0[7];
5413 };
5414
5415 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
5416 struct hwrm_vnic_plcmodes_cfg_input {
5417 __le16 req_type;
5418 __le16 cmpl_ring;
5419 __le16 seq_id;
5420 __le16 target_id;
5421 __le64 resp_addr;
5422 __le32 flags;
5423 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
5424 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
5425 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
5426 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
5427 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
5428 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
5429 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL
5430 __le32 enables;
5431 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
5432 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
5433 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
5434 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL
5435 __le32 vnic_id;
5436 __le16 jumbo_thresh;
5437 __le16 hds_offset;
5438 __le16 hds_threshold;
5439 __le16 max_bds;
5440 u8 unused_0[4];
5441 };
5442
5443 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
5444 struct hwrm_vnic_plcmodes_cfg_output {
5445 __le16 error_code;
5446 __le16 req_type;
5447 __le16 seq_id;
5448 __le16 resp_len;
5449 u8 unused_0[7];
5450 u8 valid;
5451 };
5452
5453 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
5454 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
5455 __le16 req_type;
5456 __le16 cmpl_ring;
5457 __le16 seq_id;
5458 __le16 target_id;
5459 __le64 resp_addr;
5460 };
5461
5462 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
5463 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
5464 __le16 error_code;
5465 __le16 req_type;
5466 __le16 seq_id;
5467 __le16 resp_len;
5468 __le16 rss_cos_lb_ctx_id;
5469 u8 unused_0[5];
5470 u8 valid;
5471 };
5472
5473 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
5474 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
5475 __le16 req_type;
5476 __le16 cmpl_ring;
5477 __le16 seq_id;
5478 __le16 target_id;
5479 __le64 resp_addr;
5480 __le16 rss_cos_lb_ctx_id;
5481 u8 unused_0[6];
5482 };
5483
5484 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
5485 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
5486 __le16 error_code;
5487 __le16 req_type;
5488 __le16 seq_id;
5489 __le16 resp_len;
5490 u8 unused_0[7];
5491 u8 valid;
5492 };
5493
5494 /* hwrm_ring_alloc_input (size:704b/88B) */
5495 struct hwrm_ring_alloc_input {
5496 __le16 req_type;
5497 __le16 cmpl_ring;
5498 __le16 seq_id;
5499 __le16 target_id;
5500 __le64 resp_addr;
5501 __le32 enables;
5502 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
5503 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
5504 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
5505 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
5506 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
5507 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
5508 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
5509 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
5510 u8 ring_type;
5511 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
5512 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
5513 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
5514 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5515 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
5516 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
5517 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
5518 u8 unused_0;
5519 __le16 flags;
5520 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
5521 __le64 page_tbl_addr;
5522 __le32 fbo;
5523 u8 page_size;
5524 u8 page_tbl_depth;
5525 __le16 schq_id;
5526 __le32 length;
5527 __le16 logical_id;
5528 __le16 cmpl_ring_id;
5529 __le16 queue_id;
5530 __le16 rx_buf_size;
5531 __le16 rx_ring_id;
5532 __le16 nq_ring_id;
5533 __le16 ring_arb_cfg;
5534 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
5535 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
5536 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
5537 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
5538 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
5539 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
5540 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
5541 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
5542 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
5543 __le16 unused_3;
5544 __le32 reserved3;
5545 __le32 stat_ctx_id;
5546 __le32 reserved4;
5547 __le32 max_bw;
5548 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5549 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
5550 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
5551 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
5552 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
5553 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
5554 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5555 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
5556 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5557 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5558 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5559 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5560 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5561 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5562 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
5563 u8 int_mode;
5564 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
5565 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
5566 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
5567 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
5568 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
5569 u8 mpc_chnls_type;
5570 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL
5571 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL
5572 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL
5573 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
5574 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
5575 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
5576 u8 unused_4[2];
5577 __le64 cq_handle;
5578 };
5579
5580 /* hwrm_ring_alloc_output (size:128b/16B) */
5581 struct hwrm_ring_alloc_output {
5582 __le16 error_code;
5583 __le16 req_type;
5584 __le16 seq_id;
5585 __le16 resp_len;
5586 __le16 ring_id;
5587 __le16 logical_ring_id;
5588 u8 unused_0[3];
5589 u8 valid;
5590 };
5591
5592 /* hwrm_ring_free_input (size:192b/24B) */
5593 struct hwrm_ring_free_input {
5594 __le16 req_type;
5595 __le16 cmpl_ring;
5596 __le16 seq_id;
5597 __le16 target_id;
5598 __le64 resp_addr;
5599 u8 ring_type;
5600 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
5601 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
5602 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
5603 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5604 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
5605 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
5606 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
5607 u8 unused_0;
5608 __le16 ring_id;
5609 u8 unused_1[4];
5610 };
5611
5612 /* hwrm_ring_free_output (size:128b/16B) */
5613 struct hwrm_ring_free_output {
5614 __le16 error_code;
5615 __le16 req_type;
5616 __le16 seq_id;
5617 __le16 resp_len;
5618 u8 unused_0[7];
5619 u8 valid;
5620 };
5621
5622 /* hwrm_ring_reset_input (size:192b/24B) */
5623 struct hwrm_ring_reset_input {
5624 __le16 req_type;
5625 __le16 cmpl_ring;
5626 __le16 seq_id;
5627 __le16 target_id;
5628 __le64 resp_addr;
5629 u8 ring_type;
5630 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
5631 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
5632 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
5633 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5634 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL
5635 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP
5636 u8 unused_0;
5637 __le16 ring_id;
5638 u8 unused_1[4];
5639 };
5640
5641 /* hwrm_ring_reset_output (size:128b/16B) */
5642 struct hwrm_ring_reset_output {
5643 __le16 error_code;
5644 __le16 req_type;
5645 __le16 seq_id;
5646 __le16 resp_len;
5647 u8 unused_0[4];
5648 u8 consumer_idx[3];
5649 u8 valid;
5650 };
5651
5652 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
5653 struct hwrm_ring_aggint_qcaps_input {
5654 __le16 req_type;
5655 __le16 cmpl_ring;
5656 __le16 seq_id;
5657 __le16 target_id;
5658 __le64 resp_addr;
5659 };
5660
5661 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
5662 struct hwrm_ring_aggint_qcaps_output {
5663 __le16 error_code;
5664 __le16 req_type;
5665 __le16 seq_id;
5666 __le16 resp_len;
5667 __le32 cmpl_params;
5668 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
5669 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
5670 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
5671 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
5672 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
5673 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
5674 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
5675 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
5676 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
5677 __le32 nq_params;
5678 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
5679 __le16 num_cmpl_dma_aggr_min;
5680 __le16 num_cmpl_dma_aggr_max;
5681 __le16 num_cmpl_dma_aggr_during_int_min;
5682 __le16 num_cmpl_dma_aggr_during_int_max;
5683 __le16 cmpl_aggr_dma_tmr_min;
5684 __le16 cmpl_aggr_dma_tmr_max;
5685 __le16 cmpl_aggr_dma_tmr_during_int_min;
5686 __le16 cmpl_aggr_dma_tmr_during_int_max;
5687 __le16 int_lat_tmr_min_min;
5688 __le16 int_lat_tmr_min_max;
5689 __le16 int_lat_tmr_max_min;
5690 __le16 int_lat_tmr_max_max;
5691 __le16 num_cmpl_aggr_int_min;
5692 __le16 num_cmpl_aggr_int_max;
5693 __le16 timer_units;
5694 u8 unused_0[1];
5695 u8 valid;
5696 };
5697
5698 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
5699 struct hwrm_ring_cmpl_ring_qaggint_params_input {
5700 __le16 req_type;
5701 __le16 cmpl_ring;
5702 __le16 seq_id;
5703 __le16 target_id;
5704 __le64 resp_addr;
5705 __le16 ring_id;
5706 __le16 flags;
5707 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL
5708 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0
5709 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
5710 u8 unused_0[4];
5711 };
5712
5713 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
5714 struct hwrm_ring_cmpl_ring_qaggint_params_output {
5715 __le16 error_code;
5716 __le16 req_type;
5717 __le16 seq_id;
5718 __le16 resp_len;
5719 __le16 flags;
5720 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
5721 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
5722 __le16 num_cmpl_dma_aggr;
5723 __le16 num_cmpl_dma_aggr_during_int;
5724 __le16 cmpl_aggr_dma_tmr;
5725 __le16 cmpl_aggr_dma_tmr_during_int;
5726 __le16 int_lat_tmr_min;
5727 __le16 int_lat_tmr_max;
5728 __le16 num_cmpl_aggr_int;
5729 u8 unused_0[7];
5730 u8 valid;
5731 };
5732
5733 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
5734 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
5735 __le16 req_type;
5736 __le16 cmpl_ring;
5737 __le16 seq_id;
5738 __le16 target_id;
5739 __le64 resp_addr;
5740 __le16 ring_id;
5741 __le16 flags;
5742 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
5743 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
5744 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
5745 __le16 num_cmpl_dma_aggr;
5746 __le16 num_cmpl_dma_aggr_during_int;
5747 __le16 cmpl_aggr_dma_tmr;
5748 __le16 cmpl_aggr_dma_tmr_during_int;
5749 __le16 int_lat_tmr_min;
5750 __le16 int_lat_tmr_max;
5751 __le16 num_cmpl_aggr_int;
5752 __le16 enables;
5753 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
5754 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
5755 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
5756 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
5757 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
5758 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
5759 u8 unused_0[4];
5760 };
5761
5762 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
5763 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
5764 __le16 error_code;
5765 __le16 req_type;
5766 __le16 seq_id;
5767 __le16 resp_len;
5768 u8 unused_0[7];
5769 u8 valid;
5770 };
5771
5772 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
5773 struct hwrm_ring_grp_alloc_input {
5774 __le16 req_type;
5775 __le16 cmpl_ring;
5776 __le16 seq_id;
5777 __le16 target_id;
5778 __le64 resp_addr;
5779 __le16 cr;
5780 __le16 rr;
5781 __le16 ar;
5782 __le16 sc;
5783 };
5784
5785 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
5786 struct hwrm_ring_grp_alloc_output {
5787 __le16 error_code;
5788 __le16 req_type;
5789 __le16 seq_id;
5790 __le16 resp_len;
5791 __le32 ring_group_id;
5792 u8 unused_0[3];
5793 u8 valid;
5794 };
5795
5796 /* hwrm_ring_grp_free_input (size:192b/24B) */
5797 struct hwrm_ring_grp_free_input {
5798 __le16 req_type;
5799 __le16 cmpl_ring;
5800 __le16 seq_id;
5801 __le16 target_id;
5802 __le64 resp_addr;
5803 __le32 ring_group_id;
5804 u8 unused_0[4];
5805 };
5806
5807 /* hwrm_ring_grp_free_output (size:128b/16B) */
5808 struct hwrm_ring_grp_free_output {
5809 __le16 error_code;
5810 __le16 req_type;
5811 __le16 seq_id;
5812 __le16 resp_len;
5813 u8 unused_0[7];
5814 u8 valid;
5815 };
5816
5817 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
5818 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
5819 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
5820 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
5821
5822 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
5823 struct hwrm_cfa_l2_filter_alloc_input {
5824 __le16 req_type;
5825 __le16 cmpl_ring;
5826 __le16 seq_id;
5827 __le16 target_id;
5828 __le64 resp_addr;
5829 __le32 flags;
5830 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
5831 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
5832 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
5833 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
5834 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
5835 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
5836 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
5837 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
5838 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
5839 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
5840 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
5841 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
5842 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
5843 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL
5844 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL
5845 __le32 enables;
5846 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
5847 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
5848 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
5849 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
5850 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
5851 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
5852 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
5853 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
5854 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
5855 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
5856 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
5857 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
5858 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
5859 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
5860 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
5861 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
5862 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5863 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL
5864 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL
5865 u8 l2_addr[6];
5866 u8 num_vlans;
5867 u8 t_num_vlans;
5868 u8 l2_addr_mask[6];
5869 __le16 l2_ovlan;
5870 __le16 l2_ovlan_mask;
5871 __le16 l2_ivlan;
5872 __le16 l2_ivlan_mask;
5873 u8 unused_1[2];
5874 u8 t_l2_addr[6];
5875 u8 unused_2[2];
5876 u8 t_l2_addr_mask[6];
5877 __le16 t_l2_ovlan;
5878 __le16 t_l2_ovlan_mask;
5879 __le16 t_l2_ivlan;
5880 __le16 t_l2_ivlan_mask;
5881 u8 src_type;
5882 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
5883 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
5884 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
5885 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
5886 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
5887 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
5888 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
5889 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
5890 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
5891 u8 unused_3;
5892 __le32 src_id;
5893 u8 tunnel_type;
5894 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5895 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5896 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5897 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5898 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5899 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5900 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5901 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5902 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5903 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5904 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5905 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5906 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5907 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5908 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5909 u8 unused_4;
5910 __le16 dst_id;
5911 __le16 mirror_vnic_id;
5912 u8 pri_hint;
5913 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5914 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
5915 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
5916 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
5917 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
5918 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
5919 u8 unused_5;
5920 __le32 unused_6;
5921 __le64 l2_filter_id_hint;
5922 };
5923
5924 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
5925 struct hwrm_cfa_l2_filter_alloc_output {
5926 __le16 error_code;
5927 __le16 req_type;
5928 __le16 seq_id;
5929 __le16 resp_len;
5930 __le64 l2_filter_id;
5931 __le32 flow_id;
5932 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5933 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5934 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
5935 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
5936 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
5937 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5938 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
5939 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
5940 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
5941 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5942 u8 unused_0[3];
5943 u8 valid;
5944 };
5945
5946 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
5947 struct hwrm_cfa_l2_filter_free_input {
5948 __le16 req_type;
5949 __le16 cmpl_ring;
5950 __le16 seq_id;
5951 __le16 target_id;
5952 __le64 resp_addr;
5953 __le64 l2_filter_id;
5954 };
5955
5956 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
5957 struct hwrm_cfa_l2_filter_free_output {
5958 __le16 error_code;
5959 __le16 req_type;
5960 __le16 seq_id;
5961 __le16 resp_len;
5962 u8 unused_0[7];
5963 u8 valid;
5964 };
5965
5966 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
5967 struct hwrm_cfa_l2_filter_cfg_input {
5968 __le16 req_type;
5969 __le16 cmpl_ring;
5970 __le16 seq_id;
5971 __le16 target_id;
5972 __le64 resp_addr;
5973 __le32 flags;
5974 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
5975 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
5976 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
5977 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
5978 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
5979 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
5980 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
5981 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
5982 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
5983 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
5984 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
5985 __le32 enables;
5986 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
5987 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5988 __le64 l2_filter_id;
5989 __le32 dst_id;
5990 __le32 new_mirror_vnic_id;
5991 };
5992
5993 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
5994 struct hwrm_cfa_l2_filter_cfg_output {
5995 __le16 error_code;
5996 __le16 req_type;
5997 __le16 seq_id;
5998 __le16 resp_len;
5999 u8 unused_0[7];
6000 u8 valid;
6001 };
6002
6003 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
6004 struct hwrm_cfa_l2_set_rx_mask_input {
6005 __le16 req_type;
6006 __le16 cmpl_ring;
6007 __le16 seq_id;
6008 __le16 target_id;
6009 __le64 resp_addr;
6010 __le32 vnic_id;
6011 __le32 mask;
6012 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
6013 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
6014 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
6015 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
6016 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
6017 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
6018 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
6019 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
6020 __le64 mc_tbl_addr;
6021 __le32 num_mc_entries;
6022 u8 unused_0[4];
6023 __le64 vlan_tag_tbl_addr;
6024 __le32 num_vlan_tags;
6025 u8 unused_1[4];
6026 };
6027
6028 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
6029 struct hwrm_cfa_l2_set_rx_mask_output {
6030 __le16 error_code;
6031 __le16 req_type;
6032 __le16 seq_id;
6033 __le16 resp_len;
6034 u8 unused_0[7];
6035 u8 valid;
6036 };
6037
6038 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
6039 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
6040 u8 code;
6041 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
6042 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
6043 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
6044 u8 unused_0[7];
6045 };
6046
6047 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
6048 struct hwrm_cfa_tunnel_filter_alloc_input {
6049 __le16 req_type;
6050 __le16 cmpl_ring;
6051 __le16 seq_id;
6052 __le16 target_id;
6053 __le64 resp_addr;
6054 __le32 flags;
6055 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
6056 __le32 enables;
6057 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
6058 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
6059 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
6060 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
6061 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
6062 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
6063 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
6064 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
6065 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
6066 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
6067 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
6068 __le64 l2_filter_id;
6069 u8 l2_addr[6];
6070 __le16 l2_ivlan;
6071 __le32 l3_addr[4];
6072 __le32 t_l3_addr[4];
6073 u8 l3_addr_type;
6074 u8 t_l3_addr_type;
6075 u8 tunnel_type;
6076 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6077 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6078 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6079 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6080 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6081 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6082 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6083 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6084 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6085 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6086 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6087 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6088 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6089 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6090 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6091 u8 tunnel_flags;
6092 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
6093 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
6094 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
6095 __le32 vni;
6096 __le32 dst_vnic_id;
6097 __le32 mirror_vnic_id;
6098 };
6099
6100 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
6101 struct hwrm_cfa_tunnel_filter_alloc_output {
6102 __le16 error_code;
6103 __le16 req_type;
6104 __le16 seq_id;
6105 __le16 resp_len;
6106 __le64 tunnel_filter_id;
6107 __le32 flow_id;
6108 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6109 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6110 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
6111 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
6112 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
6113 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
6114 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
6115 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
6116 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
6117 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
6118 u8 unused_0[3];
6119 u8 valid;
6120 };
6121
6122 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
6123 struct hwrm_cfa_tunnel_filter_free_input {
6124 __le16 req_type;
6125 __le16 cmpl_ring;
6126 __le16 seq_id;
6127 __le16 target_id;
6128 __le64 resp_addr;
6129 __le64 tunnel_filter_id;
6130 };
6131
6132 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
6133 struct hwrm_cfa_tunnel_filter_free_output {
6134 __le16 error_code;
6135 __le16 req_type;
6136 __le16 seq_id;
6137 __le16 resp_len;
6138 u8 unused_0[7];
6139 u8 valid;
6140 };
6141
6142 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
6143 struct hwrm_vxlan_ipv4_hdr {
6144 u8 ver_hlen;
6145 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
6146 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
6147 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
6148 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
6149 u8 tos;
6150 __be16 ip_id;
6151 __be16 flags_frag_offset;
6152 u8 ttl;
6153 u8 protocol;
6154 __be32 src_ip_addr;
6155 __be32 dest_ip_addr;
6156 };
6157
6158 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
6159 struct hwrm_vxlan_ipv6_hdr {
6160 __be32 ver_tc_flow_label;
6161 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
6162 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
6163 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
6164 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
6165 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
6166 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
6167 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
6168 __be16 payload_len;
6169 u8 next_hdr;
6170 u8 ttl;
6171 __be32 src_ip_addr[4];
6172 __be32 dest_ip_addr[4];
6173 };
6174
6175 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
6176 struct hwrm_cfa_encap_data_vxlan {
6177 u8 src_mac_addr[6];
6178 __le16 unused_0;
6179 u8 dst_mac_addr[6];
6180 u8 num_vlan_tags;
6181 u8 unused_1;
6182 __be16 ovlan_tpid;
6183 __be16 ovlan_tci;
6184 __be16 ivlan_tpid;
6185 __be16 ivlan_tci;
6186 __le32 l3[10];
6187 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
6188 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
6189 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
6190 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
6191 __be16 src_port;
6192 __be16 dst_port;
6193 __be32 vni;
6194 u8 hdr_rsvd0[3];
6195 u8 hdr_rsvd1;
6196 u8 hdr_flags;
6197 u8 unused[3];
6198 };
6199
6200 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
6201 struct hwrm_cfa_encap_record_alloc_input {
6202 __le16 req_type;
6203 __le16 cmpl_ring;
6204 __le16 seq_id;
6205 __le16 target_id;
6206 __le64 resp_addr;
6207 __le32 flags;
6208 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
6209 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL
6210 u8 encap_type;
6211 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
6212 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
6213 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
6214 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
6215 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
6216 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
6217 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
6218 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
6219 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
6220 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
6221 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
6222 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
6223 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
6224 u8 unused_0[3];
6225 __le32 encap_data[20];
6226 };
6227
6228 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
6229 struct hwrm_cfa_encap_record_alloc_output {
6230 __le16 error_code;
6231 __le16 req_type;
6232 __le16 seq_id;
6233 __le16 resp_len;
6234 __le32 encap_record_id;
6235 u8 unused_0[3];
6236 u8 valid;
6237 };
6238
6239 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
6240 struct hwrm_cfa_encap_record_free_input {
6241 __le16 req_type;
6242 __le16 cmpl_ring;
6243 __le16 seq_id;
6244 __le16 target_id;
6245 __le64 resp_addr;
6246 __le32 encap_record_id;
6247 u8 unused_0[4];
6248 };
6249
6250 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
6251 struct hwrm_cfa_encap_record_free_output {
6252 __le16 error_code;
6253 __le16 req_type;
6254 __le16 seq_id;
6255 __le16 resp_len;
6256 u8 unused_0[7];
6257 u8 valid;
6258 };
6259
6260 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
6261 struct hwrm_cfa_ntuple_filter_alloc_input {
6262 __le16 req_type;
6263 __le16 cmpl_ring;
6264 __le16 seq_id;
6265 __le16 target_id;
6266 __le64 resp_addr;
6267 __le32 flags;
6268 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
6269 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
6270 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
6271 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL
6272 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL
6273 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL
6274 __le32 enables;
6275 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
6276 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
6277 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
6278 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
6279 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
6280 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
6281 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
6282 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
6283 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
6284 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
6285 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
6286 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
6287 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
6288 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
6289 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
6290 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
6291 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
6292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
6293 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
6294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL
6295 __le64 l2_filter_id;
6296 u8 src_macaddr[6];
6297 __be16 ethertype;
6298 u8 ip_addr_type;
6299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
6300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
6301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
6302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
6303 u8 ip_protocol;
6304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
6305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
6306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
6307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
6308 __le16 dst_id;
6309 __le16 mirror_vnic_id;
6310 u8 tunnel_type;
6311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6315 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6316 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6317 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6322 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6325 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6326 u8 pri_hint;
6327 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
6328 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
6329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
6330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
6331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
6332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
6333 __be32 src_ipaddr[4];
6334 __be32 src_ipaddr_mask[4];
6335 __be32 dst_ipaddr[4];
6336 __be32 dst_ipaddr_mask[4];
6337 __be16 src_port;
6338 __be16 src_port_mask;
6339 __be16 dst_port;
6340 __be16 dst_port_mask;
6341 __le64 ntuple_filter_id_hint;
6342 };
6343
6344 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
6345 struct hwrm_cfa_ntuple_filter_alloc_output {
6346 __le16 error_code;
6347 __le16 req_type;
6348 __le16 seq_id;
6349 __le16 resp_len;
6350 __le64 ntuple_filter_id;
6351 __le32 flow_id;
6352 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6353 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6354 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
6355 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
6356 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
6357 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
6358 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
6359 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
6360 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
6361 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
6362 u8 unused_0[3];
6363 u8 valid;
6364 };
6365
6366 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
6367 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
6368 u8 code;
6369 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
6370 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
6371 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
6372 u8 unused_0[7];
6373 };
6374
6375 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
6376 struct hwrm_cfa_ntuple_filter_free_input {
6377 __le16 req_type;
6378 __le16 cmpl_ring;
6379 __le16 seq_id;
6380 __le16 target_id;
6381 __le64 resp_addr;
6382 __le64 ntuple_filter_id;
6383 };
6384
6385 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
6386 struct hwrm_cfa_ntuple_filter_free_output {
6387 __le16 error_code;
6388 __le16 req_type;
6389 __le16 seq_id;
6390 __le16 resp_len;
6391 u8 unused_0[7];
6392 u8 valid;
6393 };
6394
6395 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
6396 struct hwrm_cfa_ntuple_filter_cfg_input {
6397 __le16 req_type;
6398 __le16 cmpl_ring;
6399 __le16 seq_id;
6400 __le16 target_id;
6401 __le64 resp_addr;
6402 __le32 enables;
6403 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
6404 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
6405 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
6406 __le32 flags;
6407 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
6408 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL
6409 __le64 ntuple_filter_id;
6410 __le32 new_dst_id;
6411 __le32 new_mirror_vnic_id;
6412 __le16 new_meter_instance_id;
6413 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
6414 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
6415 u8 unused_1[6];
6416 };
6417
6418 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
6419 struct hwrm_cfa_ntuple_filter_cfg_output {
6420 __le16 error_code;
6421 __le16 req_type;
6422 __le16 seq_id;
6423 __le16 resp_len;
6424 u8 unused_0[7];
6425 u8 valid;
6426 };
6427
6428 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
6429 struct hwrm_cfa_decap_filter_alloc_input {
6430 __le16 req_type;
6431 __le16 cmpl_ring;
6432 __le16 seq_id;
6433 __le16 target_id;
6434 __le64 resp_addr;
6435 __le32 flags;
6436 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
6437 __le32 enables;
6438 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
6439 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
6440 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
6441 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
6442 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
6443 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
6444 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
6445 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
6446 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
6447 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
6448 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
6449 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
6450 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
6451 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
6452 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
6453 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
6454 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
6455 __be32 tunnel_id;
6456 u8 tunnel_type;
6457 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6458 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6459 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6460 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6461 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6462 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6463 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6464 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6465 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6466 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6467 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6468 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6469 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6470 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6471 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6472 u8 unused_0;
6473 __le16 unused_1;
6474 u8 src_macaddr[6];
6475 u8 unused_2[2];
6476 u8 dst_macaddr[6];
6477 __be16 ovlan_vid;
6478 __be16 ivlan_vid;
6479 __be16 t_ovlan_vid;
6480 __be16 t_ivlan_vid;
6481 __be16 ethertype;
6482 u8 ip_addr_type;
6483 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
6484 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
6485 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
6486 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
6487 u8 ip_protocol;
6488 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
6489 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
6490 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
6491 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
6492 __le16 unused_3;
6493 __le32 unused_4;
6494 __be32 src_ipaddr[4];
6495 __be32 dst_ipaddr[4];
6496 __be16 src_port;
6497 __be16 dst_port;
6498 __le16 dst_id;
6499 __le16 l2_ctxt_ref_id;
6500 };
6501
6502 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
6503 struct hwrm_cfa_decap_filter_alloc_output {
6504 __le16 error_code;
6505 __le16 req_type;
6506 __le16 seq_id;
6507 __le16 resp_len;
6508 __le32 decap_filter_id;
6509 u8 unused_0[3];
6510 u8 valid;
6511 };
6512
6513 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
6514 struct hwrm_cfa_decap_filter_free_input {
6515 __le16 req_type;
6516 __le16 cmpl_ring;
6517 __le16 seq_id;
6518 __le16 target_id;
6519 __le64 resp_addr;
6520 __le32 decap_filter_id;
6521 u8 unused_0[4];
6522 };
6523
6524 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
6525 struct hwrm_cfa_decap_filter_free_output {
6526 __le16 error_code;
6527 __le16 req_type;
6528 __le16 seq_id;
6529 __le16 resp_len;
6530 u8 unused_0[7];
6531 u8 valid;
6532 };
6533
6534 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
6535 struct hwrm_cfa_flow_alloc_input {
6536 __le16 req_type;
6537 __le16 cmpl_ring;
6538 __le16 seq_id;
6539 __le16 target_id;
6540 __le64 resp_addr;
6541 __le16 flags;
6542 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
6543 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
6544 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
6545 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
6546 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
6547 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
6548 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
6549 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
6550 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
6551 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
6552 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
6553 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
6554 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
6555 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
6556 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
6557 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
6558 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
6559 __le16 src_fid;
6560 __le32 tunnel_handle;
6561 __le16 action_flags;
6562 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
6563 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
6564 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
6565 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
6566 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
6567 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
6568 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
6569 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
6570 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
6571 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
6572 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
6573 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
6574 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
6575 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL
6576 __le16 dst_fid;
6577 __be16 l2_rewrite_vlan_tpid;
6578 __be16 l2_rewrite_vlan_tci;
6579 __le16 act_meter_id;
6580 __le16 ref_flow_handle;
6581 __be16 ethertype;
6582 __be16 outer_vlan_tci;
6583 __be16 dmac[3];
6584 __be16 inner_vlan_tci;
6585 __be16 smac[3];
6586 u8 ip_dst_mask_len;
6587 u8 ip_src_mask_len;
6588 __be32 ip_dst[4];
6589 __be32 ip_src[4];
6590 __be16 l4_src_port;
6591 __be16 l4_src_port_mask;
6592 __be16 l4_dst_port;
6593 __be16 l4_dst_port_mask;
6594 __be32 nat_ip_address[4];
6595 __be16 l2_rewrite_dmac[3];
6596 __be16 nat_port;
6597 __be16 l2_rewrite_smac[3];
6598 u8 ip_proto;
6599 u8 tunnel_type;
6600 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6601 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6602 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6603 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6604 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6605 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6606 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6607 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6608 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6609 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6610 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6611 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6612 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6613 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6614 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6615 };
6616
6617 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
6618 struct hwrm_cfa_flow_alloc_output {
6619 __le16 error_code;
6620 __le16 req_type;
6621 __le16 seq_id;
6622 __le16 resp_len;
6623 __le16 flow_handle;
6624 u8 unused_0[2];
6625 __le32 flow_id;
6626 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6627 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6628 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
6629 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
6630 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
6631 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
6632 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
6633 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
6634 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
6635 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
6636 __le64 ext_flow_handle;
6637 __le32 flow_counter_id;
6638 u8 unused_1[3];
6639 u8 valid;
6640 };
6641
6642 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
6643 struct hwrm_cfa_flow_alloc_cmd_err {
6644 u8 code;
6645 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
6646 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
6647 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL
6648 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL
6649 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL
6650 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL
6651 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL
6652 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL
6653 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
6654 u8 unused_0[7];
6655 };
6656
6657 /* hwrm_cfa_flow_free_input (size:256b/32B) */
6658 struct hwrm_cfa_flow_free_input {
6659 __le16 req_type;
6660 __le16 cmpl_ring;
6661 __le16 seq_id;
6662 __le16 target_id;
6663 __le64 resp_addr;
6664 __le16 flow_handle;
6665 __le16 unused_0;
6666 __le32 flow_counter_id;
6667 __le64 ext_flow_handle;
6668 };
6669
6670 /* hwrm_cfa_flow_free_output (size:256b/32B) */
6671 struct hwrm_cfa_flow_free_output {
6672 __le16 error_code;
6673 __le16 req_type;
6674 __le16 seq_id;
6675 __le16 resp_len;
6676 __le64 packet;
6677 __le64 byte;
6678 u8 unused_0[7];
6679 u8 valid;
6680 };
6681
6682 /* hwrm_cfa_flow_info_input (size:256b/32B) */
6683 struct hwrm_cfa_flow_info_input {
6684 __le16 req_type;
6685 __le16 cmpl_ring;
6686 __le16 seq_id;
6687 __le16 target_id;
6688 __le64 resp_addr;
6689 __le16 flow_handle;
6690 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
6691 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0
6692 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
6693 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
6694 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
6695 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
6696 u8 unused_0[6];
6697 __le64 ext_flow_handle;
6698 };
6699
6700 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
6701 struct hwrm_cfa_flow_info_output {
6702 __le16 error_code;
6703 __le16 req_type;
6704 __le16 seq_id;
6705 __le16 resp_len;
6706 u8 flags;
6707 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL
6708 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL
6709 u8 profile;
6710 __le16 src_fid;
6711 __le16 dst_fid;
6712 __le16 l2_ctxt_id;
6713 __le64 em_info;
6714 __le64 tcam_info;
6715 __le64 vfp_tcam_info;
6716 __le16 ar_id;
6717 __le16 flow_handle;
6718 __le32 tunnel_handle;
6719 __le16 flow_timer;
6720 u8 unused_0[6];
6721 __le32 flow_key_data[130];
6722 __le32 flow_action_info[30];
6723 u8 unused_1[7];
6724 u8 valid;
6725 };
6726
6727 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
6728 struct hwrm_cfa_flow_stats_input {
6729 __le16 req_type;
6730 __le16 cmpl_ring;
6731 __le16 seq_id;
6732 __le16 target_id;
6733 __le64 resp_addr;
6734 __le16 num_flows;
6735 __le16 flow_handle_0;
6736 __le16 flow_handle_1;
6737 __le16 flow_handle_2;
6738 __le16 flow_handle_3;
6739 __le16 flow_handle_4;
6740 __le16 flow_handle_5;
6741 __le16 flow_handle_6;
6742 __le16 flow_handle_7;
6743 __le16 flow_handle_8;
6744 __le16 flow_handle_9;
6745 u8 unused_0[2];
6746 __le32 flow_id_0;
6747 __le32 flow_id_1;
6748 __le32 flow_id_2;
6749 __le32 flow_id_3;
6750 __le32 flow_id_4;
6751 __le32 flow_id_5;
6752 __le32 flow_id_6;
6753 __le32 flow_id_7;
6754 __le32 flow_id_8;
6755 __le32 flow_id_9;
6756 };
6757
6758 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
6759 struct hwrm_cfa_flow_stats_output {
6760 __le16 error_code;
6761 __le16 req_type;
6762 __le16 seq_id;
6763 __le16 resp_len;
6764 __le64 packet_0;
6765 __le64 packet_1;
6766 __le64 packet_2;
6767 __le64 packet_3;
6768 __le64 packet_4;
6769 __le64 packet_5;
6770 __le64 packet_6;
6771 __le64 packet_7;
6772 __le64 packet_8;
6773 __le64 packet_9;
6774 __le64 byte_0;
6775 __le64 byte_1;
6776 __le64 byte_2;
6777 __le64 byte_3;
6778 __le64 byte_4;
6779 __le64 byte_5;
6780 __le64 byte_6;
6781 __le64 byte_7;
6782 __le64 byte_8;
6783 __le64 byte_9;
6784 u8 unused_0[7];
6785 u8 valid;
6786 };
6787
6788 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
6789 struct hwrm_cfa_vfr_alloc_input {
6790 __le16 req_type;
6791 __le16 cmpl_ring;
6792 __le16 seq_id;
6793 __le16 target_id;
6794 __le64 resp_addr;
6795 __le16 vf_id;
6796 __le16 reserved;
6797 u8 unused_0[4];
6798 char vfr_name[32];
6799 };
6800
6801 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
6802 struct hwrm_cfa_vfr_alloc_output {
6803 __le16 error_code;
6804 __le16 req_type;
6805 __le16 seq_id;
6806 __le16 resp_len;
6807 __le16 rx_cfa_code;
6808 __le16 tx_cfa_action;
6809 u8 unused_0[3];
6810 u8 valid;
6811 };
6812
6813 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
6814 struct hwrm_cfa_vfr_free_input {
6815 __le16 req_type;
6816 __le16 cmpl_ring;
6817 __le16 seq_id;
6818 __le16 target_id;
6819 __le64 resp_addr;
6820 char vfr_name[32];
6821 __le16 vf_id;
6822 __le16 reserved;
6823 u8 unused_0[4];
6824 };
6825
6826 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
6827 struct hwrm_cfa_vfr_free_output {
6828 __le16 error_code;
6829 __le16 req_type;
6830 __le16 seq_id;
6831 __le16 resp_len;
6832 u8 unused_0[7];
6833 u8 valid;
6834 };
6835
6836 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
6837 struct hwrm_cfa_eem_qcaps_input {
6838 __le16 req_type;
6839 __le16 cmpl_ring;
6840 __le16 seq_id;
6841 __le16 target_id;
6842 __le64 resp_addr;
6843 __le32 flags;
6844 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
6845 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
6846 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6847 __le32 unused_0;
6848 };
6849
6850 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
6851 struct hwrm_cfa_eem_qcaps_output {
6852 __le16 error_code;
6853 __le16 req_type;
6854 __le16 seq_id;
6855 __le16 resp_len;
6856 __le32 flags;
6857 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
6858 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
6859 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL
6860 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL
6861 __le32 unused_0;
6862 __le32 supported;
6863 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
6864 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
6865 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
6866 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
6867 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL
6868 __le32 max_entries_supported;
6869 __le16 key_entry_size;
6870 __le16 record_entry_size;
6871 __le16 efc_entry_size;
6872 __le16 fid_entry_size;
6873 u8 unused_1[7];
6874 u8 valid;
6875 };
6876
6877 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
6878 struct hwrm_cfa_eem_cfg_input {
6879 __le16 req_type;
6880 __le16 cmpl_ring;
6881 __le16 seq_id;
6882 __le16 target_id;
6883 __le64 resp_addr;
6884 __le32 flags;
6885 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
6886 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
6887 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6888 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL
6889 __le16 group_id;
6890 __le16 unused_0;
6891 __le32 num_entries;
6892 __le32 unused_1;
6893 __le16 key0_ctx_id;
6894 __le16 key1_ctx_id;
6895 __le16 record_ctx_id;
6896 __le16 efc_ctx_id;
6897 __le16 fid_ctx_id;
6898 __le16 unused_2;
6899 __le32 unused_3;
6900 };
6901
6902 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
6903 struct hwrm_cfa_eem_cfg_output {
6904 __le16 error_code;
6905 __le16 req_type;
6906 __le16 seq_id;
6907 __le16 resp_len;
6908 u8 unused_0[7];
6909 u8 valid;
6910 };
6911
6912 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
6913 struct hwrm_cfa_eem_qcfg_input {
6914 __le16 req_type;
6915 __le16 cmpl_ring;
6916 __le16 seq_id;
6917 __le16 target_id;
6918 __le64 resp_addr;
6919 __le32 flags;
6920 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
6921 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
6922 __le32 unused_0;
6923 };
6924
6925 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
6926 struct hwrm_cfa_eem_qcfg_output {
6927 __le16 error_code;
6928 __le16 req_type;
6929 __le16 seq_id;
6930 __le16 resp_len;
6931 __le32 flags;
6932 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
6933 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
6934 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
6935 __le32 num_entries;
6936 __le16 key0_ctx_id;
6937 __le16 key1_ctx_id;
6938 __le16 record_ctx_id;
6939 __le16 efc_ctx_id;
6940 __le16 fid_ctx_id;
6941 u8 unused_2[5];
6942 u8 valid;
6943 };
6944
6945 /* hwrm_cfa_eem_op_input (size:192b/24B) */
6946 struct hwrm_cfa_eem_op_input {
6947 __le16 req_type;
6948 __le16 cmpl_ring;
6949 __le16 seq_id;
6950 __le16 target_id;
6951 __le64 resp_addr;
6952 __le32 flags;
6953 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
6954 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
6955 __le16 unused_0;
6956 __le16 op;
6957 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
6958 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
6959 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
6960 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
6961 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
6962 };
6963
6964 /* hwrm_cfa_eem_op_output (size:128b/16B) */
6965 struct hwrm_cfa_eem_op_output {
6966 __le16 error_code;
6967 __le16 req_type;
6968 __le16 seq_id;
6969 __le16 resp_len;
6970 u8 unused_0[7];
6971 u8 valid;
6972 };
6973
6974 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
6975 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
6976 __le16 req_type;
6977 __le16 cmpl_ring;
6978 __le16 seq_id;
6979 __le16 target_id;
6980 __le64 resp_addr;
6981 __le32 unused_0[4];
6982 };
6983
6984 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
6985 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
6986 __le16 error_code;
6987 __le16 req_type;
6988 __le16 seq_id;
6989 __le16 resp_len;
6990 __le32 flags;
6991 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL
6992 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL
6993 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL
6994 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL
6995 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL
6996 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL
6997 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL
6998 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL
6999 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL
7000 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL
7001 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL
7002 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL
7003 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL
7004 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL
7005 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL
7006 u8 unused_0[3];
7007 u8 valid;
7008 };
7009
7010 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
7011 struct hwrm_tunnel_dst_port_query_input {
7012 __le16 req_type;
7013 __le16 cmpl_ring;
7014 __le16 seq_id;
7015 __le16 target_id;
7016 __le64 resp_addr;
7017 u8 tunnel_type;
7018 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7019 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7020 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7021 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7022 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7023 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7024 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
7025 u8 unused_0[7];
7026 };
7027
7028 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
7029 struct hwrm_tunnel_dst_port_query_output {
7030 __le16 error_code;
7031 __le16 req_type;
7032 __le16 seq_id;
7033 __le16 resp_len;
7034 __le16 tunnel_dst_port_id;
7035 __be16 tunnel_dst_port_val;
7036 u8 unused_0[3];
7037 u8 valid;
7038 };
7039
7040 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
7041 struct hwrm_tunnel_dst_port_alloc_input {
7042 __le16 req_type;
7043 __le16 cmpl_ring;
7044 __le16 seq_id;
7045 __le16 target_id;
7046 __le64 resp_addr;
7047 u8 tunnel_type;
7048 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7049 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7050 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7051 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7052 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7053 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7054 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
7055 u8 unused_0;
7056 __be16 tunnel_dst_port_val;
7057 u8 unused_1[4];
7058 };
7059
7060 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
7061 struct hwrm_tunnel_dst_port_alloc_output {
7062 __le16 error_code;
7063 __le16 req_type;
7064 __le16 seq_id;
7065 __le16 resp_len;
7066 __le16 tunnel_dst_port_id;
7067 u8 unused_0[5];
7068 u8 valid;
7069 };
7070
7071 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
7072 struct hwrm_tunnel_dst_port_free_input {
7073 __le16 req_type;
7074 __le16 cmpl_ring;
7075 __le16 seq_id;
7076 __le16 target_id;
7077 __le64 resp_addr;
7078 u8 tunnel_type;
7079 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7080 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7081 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7082 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7083 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7084 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7085 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
7086 u8 unused_0;
7087 __le16 tunnel_dst_port_id;
7088 u8 unused_1[4];
7089 };
7090
7091 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
7092 struct hwrm_tunnel_dst_port_free_output {
7093 __le16 error_code;
7094 __le16 req_type;
7095 __le16 seq_id;
7096 __le16 resp_len;
7097 u8 unused_1[7];
7098 u8 valid;
7099 };
7100
7101 /* ctx_hw_stats (size:1280b/160B) */
7102 struct ctx_hw_stats {
7103 __le64 rx_ucast_pkts;
7104 __le64 rx_mcast_pkts;
7105 __le64 rx_bcast_pkts;
7106 __le64 rx_discard_pkts;
7107 __le64 rx_error_pkts;
7108 __le64 rx_ucast_bytes;
7109 __le64 rx_mcast_bytes;
7110 __le64 rx_bcast_bytes;
7111 __le64 tx_ucast_pkts;
7112 __le64 tx_mcast_pkts;
7113 __le64 tx_bcast_pkts;
7114 __le64 tx_error_pkts;
7115 __le64 tx_discard_pkts;
7116 __le64 tx_ucast_bytes;
7117 __le64 tx_mcast_bytes;
7118 __le64 tx_bcast_bytes;
7119 __le64 tpa_pkts;
7120 __le64 tpa_bytes;
7121 __le64 tpa_events;
7122 __le64 tpa_aborts;
7123 };
7124
7125 /* ctx_hw_stats_ext (size:1408b/176B) */
7126 struct ctx_hw_stats_ext {
7127 __le64 rx_ucast_pkts;
7128 __le64 rx_mcast_pkts;
7129 __le64 rx_bcast_pkts;
7130 __le64 rx_discard_pkts;
7131 __le64 rx_error_pkts;
7132 __le64 rx_ucast_bytes;
7133 __le64 rx_mcast_bytes;
7134 __le64 rx_bcast_bytes;
7135 __le64 tx_ucast_pkts;
7136 __le64 tx_mcast_pkts;
7137 __le64 tx_bcast_pkts;
7138 __le64 tx_error_pkts;
7139 __le64 tx_discard_pkts;
7140 __le64 tx_ucast_bytes;
7141 __le64 tx_mcast_bytes;
7142 __le64 tx_bcast_bytes;
7143 __le64 rx_tpa_eligible_pkt;
7144 __le64 rx_tpa_eligible_bytes;
7145 __le64 rx_tpa_pkt;
7146 __le64 rx_tpa_bytes;
7147 __le64 rx_tpa_errors;
7148 __le64 rx_tpa_events;
7149 };
7150
7151 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
7152 struct hwrm_stat_ctx_alloc_input {
7153 __le16 req_type;
7154 __le16 cmpl_ring;
7155 __le16 seq_id;
7156 __le16 target_id;
7157 __le64 resp_addr;
7158 __le64 stats_dma_addr;
7159 __le32 update_period_ms;
7160 u8 stat_ctx_flags;
7161 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
7162 u8 unused_0;
7163 __le16 stats_dma_length;
7164 };
7165
7166 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
7167 struct hwrm_stat_ctx_alloc_output {
7168 __le16 error_code;
7169 __le16 req_type;
7170 __le16 seq_id;
7171 __le16 resp_len;
7172 __le32 stat_ctx_id;
7173 u8 unused_0[3];
7174 u8 valid;
7175 };
7176
7177 /* hwrm_stat_ctx_free_input (size:192b/24B) */
7178 struct hwrm_stat_ctx_free_input {
7179 __le16 req_type;
7180 __le16 cmpl_ring;
7181 __le16 seq_id;
7182 __le16 target_id;
7183 __le64 resp_addr;
7184 __le32 stat_ctx_id;
7185 u8 unused_0[4];
7186 };
7187
7188 /* hwrm_stat_ctx_free_output (size:128b/16B) */
7189 struct hwrm_stat_ctx_free_output {
7190 __le16 error_code;
7191 __le16 req_type;
7192 __le16 seq_id;
7193 __le16 resp_len;
7194 __le32 stat_ctx_id;
7195 u8 unused_0[3];
7196 u8 valid;
7197 };
7198
7199 /* hwrm_stat_ctx_query_input (size:192b/24B) */
7200 struct hwrm_stat_ctx_query_input {
7201 __le16 req_type;
7202 __le16 cmpl_ring;
7203 __le16 seq_id;
7204 __le16 target_id;
7205 __le64 resp_addr;
7206 __le32 stat_ctx_id;
7207 u8 flags;
7208 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
7209 u8 unused_0[3];
7210 };
7211
7212 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
7213 struct hwrm_stat_ctx_query_output {
7214 __le16 error_code;
7215 __le16 req_type;
7216 __le16 seq_id;
7217 __le16 resp_len;
7218 __le64 tx_ucast_pkts;
7219 __le64 tx_mcast_pkts;
7220 __le64 tx_bcast_pkts;
7221 __le64 tx_discard_pkts;
7222 __le64 tx_error_pkts;
7223 __le64 tx_ucast_bytes;
7224 __le64 tx_mcast_bytes;
7225 __le64 tx_bcast_bytes;
7226 __le64 rx_ucast_pkts;
7227 __le64 rx_mcast_pkts;
7228 __le64 rx_bcast_pkts;
7229 __le64 rx_discard_pkts;
7230 __le64 rx_error_pkts;
7231 __le64 rx_ucast_bytes;
7232 __le64 rx_mcast_bytes;
7233 __le64 rx_bcast_bytes;
7234 __le64 rx_agg_pkts;
7235 __le64 rx_agg_bytes;
7236 __le64 rx_agg_events;
7237 __le64 rx_agg_aborts;
7238 u8 unused_0[7];
7239 u8 valid;
7240 };
7241
7242 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
7243 struct hwrm_stat_ext_ctx_query_input {
7244 __le16 req_type;
7245 __le16 cmpl_ring;
7246 __le16 seq_id;
7247 __le16 target_id;
7248 __le64 resp_addr;
7249 __le32 stat_ctx_id;
7250 u8 flags;
7251 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
7252 u8 unused_0[3];
7253 };
7254
7255 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
7256 struct hwrm_stat_ext_ctx_query_output {
7257 __le16 error_code;
7258 __le16 req_type;
7259 __le16 seq_id;
7260 __le16 resp_len;
7261 __le64 rx_ucast_pkts;
7262 __le64 rx_mcast_pkts;
7263 __le64 rx_bcast_pkts;
7264 __le64 rx_discard_pkts;
7265 __le64 rx_error_pkts;
7266 __le64 rx_ucast_bytes;
7267 __le64 rx_mcast_bytes;
7268 __le64 rx_bcast_bytes;
7269 __le64 tx_ucast_pkts;
7270 __le64 tx_mcast_pkts;
7271 __le64 tx_bcast_pkts;
7272 __le64 tx_error_pkts;
7273 __le64 tx_discard_pkts;
7274 __le64 tx_ucast_bytes;
7275 __le64 tx_mcast_bytes;
7276 __le64 tx_bcast_bytes;
7277 __le64 rx_tpa_eligible_pkt;
7278 __le64 rx_tpa_eligible_bytes;
7279 __le64 rx_tpa_pkt;
7280 __le64 rx_tpa_bytes;
7281 __le64 rx_tpa_errors;
7282 __le64 rx_tpa_events;
7283 u8 unused_0[7];
7284 u8 valid;
7285 };
7286
7287 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
7288 struct hwrm_stat_ctx_clr_stats_input {
7289 __le16 req_type;
7290 __le16 cmpl_ring;
7291 __le16 seq_id;
7292 __le16 target_id;
7293 __le64 resp_addr;
7294 __le32 stat_ctx_id;
7295 u8 unused_0[4];
7296 };
7297
7298 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
7299 struct hwrm_stat_ctx_clr_stats_output {
7300 __le16 error_code;
7301 __le16 req_type;
7302 __le16 seq_id;
7303 __le16 resp_len;
7304 u8 unused_0[7];
7305 u8 valid;
7306 };
7307
7308 /* hwrm_pcie_qstats_input (size:256b/32B) */
7309 struct hwrm_pcie_qstats_input {
7310 __le16 req_type;
7311 __le16 cmpl_ring;
7312 __le16 seq_id;
7313 __le16 target_id;
7314 __le64 resp_addr;
7315 __le16 pcie_stat_size;
7316 u8 unused_0[6];
7317 __le64 pcie_stat_host_addr;
7318 };
7319
7320 /* hwrm_pcie_qstats_output (size:128b/16B) */
7321 struct hwrm_pcie_qstats_output {
7322 __le16 error_code;
7323 __le16 req_type;
7324 __le16 seq_id;
7325 __le16 resp_len;
7326 __le16 pcie_stat_size;
7327 u8 unused_0[5];
7328 u8 valid;
7329 };
7330
7331 /* pcie_ctx_hw_stats (size:768b/96B) */
7332 struct pcie_ctx_hw_stats {
7333 __le64 pcie_pl_signal_integrity;
7334 __le64 pcie_dl_signal_integrity;
7335 __le64 pcie_tl_signal_integrity;
7336 __le64 pcie_link_integrity;
7337 __le64 pcie_tx_traffic_rate;
7338 __le64 pcie_rx_traffic_rate;
7339 __le64 pcie_tx_dllp_statistics;
7340 __le64 pcie_rx_dllp_statistics;
7341 __le64 pcie_equalization_time;
7342 __le32 pcie_ltssm_histogram[4];
7343 __le64 pcie_recovery_histogram;
7344 };
7345
7346 /* hwrm_fw_reset_input (size:192b/24B) */
7347 struct hwrm_fw_reset_input {
7348 __le16 req_type;
7349 __le16 cmpl_ring;
7350 __le16 seq_id;
7351 __le16 target_id;
7352 __le64 resp_addr;
7353 u8 embedded_proc_type;
7354 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
7355 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
7356 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
7357 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
7358 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
7359 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
7360 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
7361 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
7362 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
7363 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
7364 u8 selfrst_status;
7365 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
7366 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
7367 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
7368 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
7369 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
7370 u8 host_idx;
7371 u8 flags;
7372 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
7373 u8 unused_0[4];
7374 };
7375
7376 /* hwrm_fw_reset_output (size:128b/16B) */
7377 struct hwrm_fw_reset_output {
7378 __le16 error_code;
7379 __le16 req_type;
7380 __le16 seq_id;
7381 __le16 resp_len;
7382 u8 selfrst_status;
7383 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
7384 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
7385 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
7386 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
7387 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
7388 u8 unused_0[6];
7389 u8 valid;
7390 };
7391
7392 /* hwrm_fw_qstatus_input (size:192b/24B) */
7393 struct hwrm_fw_qstatus_input {
7394 __le16 req_type;
7395 __le16 cmpl_ring;
7396 __le16 seq_id;
7397 __le16 target_id;
7398 __le64 resp_addr;
7399 u8 embedded_proc_type;
7400 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
7401 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
7402 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
7403 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
7404 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
7405 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
7406 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
7407 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
7408 u8 unused_0[7];
7409 };
7410
7411 /* hwrm_fw_qstatus_output (size:128b/16B) */
7412 struct hwrm_fw_qstatus_output {
7413 __le16 error_code;
7414 __le16 req_type;
7415 __le16 seq_id;
7416 __le16 resp_len;
7417 u8 selfrst_status;
7418 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
7419 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
7420 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
7421 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL
7422 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
7423 u8 unused_0[6];
7424 u8 valid;
7425 };
7426
7427 /* hwrm_fw_set_time_input (size:256b/32B) */
7428 struct hwrm_fw_set_time_input {
7429 __le16 req_type;
7430 __le16 cmpl_ring;
7431 __le16 seq_id;
7432 __le16 target_id;
7433 __le64 resp_addr;
7434 __le16 year;
7435 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
7436 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
7437 u8 month;
7438 u8 day;
7439 u8 hour;
7440 u8 minute;
7441 u8 second;
7442 u8 unused_0;
7443 __le16 millisecond;
7444 __le16 zone;
7445 #define FW_SET_TIME_REQ_ZONE_UTC 0
7446 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
7447 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
7448 u8 unused_1[4];
7449 };
7450
7451 /* hwrm_fw_set_time_output (size:128b/16B) */
7452 struct hwrm_fw_set_time_output {
7453 __le16 error_code;
7454 __le16 req_type;
7455 __le16 seq_id;
7456 __le16 resp_len;
7457 u8 unused_0[7];
7458 u8 valid;
7459 };
7460
7461 /* hwrm_struct_hdr (size:128b/16B) */
7462 struct hwrm_struct_hdr {
7463 __le16 struct_id;
7464 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
7465 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
7466 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
7467 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
7468 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
7469 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
7470 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
7471 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
7472 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
7473 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
7474 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
7475 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2
7476 __le16 len;
7477 u8 version;
7478 u8 count;
7479 __le16 subtype;
7480 __le16 next_offset;
7481 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
7482 u8 unused_0[6];
7483 };
7484
7485 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
7486 struct hwrm_struct_data_dcbx_app {
7487 __be16 protocol_id;
7488 u8 protocol_selector;
7489 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
7490 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
7491 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
7492 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
7493 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
7494 u8 priority;
7495 u8 valid;
7496 u8 unused_0[3];
7497 };
7498
7499 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
7500 struct hwrm_fw_set_structured_data_input {
7501 __le16 req_type;
7502 __le16 cmpl_ring;
7503 __le16 seq_id;
7504 __le16 target_id;
7505 __le64 resp_addr;
7506 __le64 src_data_addr;
7507 __le16 data_len;
7508 u8 hdr_cnt;
7509 u8 unused_0[5];
7510 };
7511
7512 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
7513 struct hwrm_fw_set_structured_data_output {
7514 __le16 error_code;
7515 __le16 req_type;
7516 __le16 seq_id;
7517 __le16 resp_len;
7518 u8 unused_0[7];
7519 u8 valid;
7520 };
7521
7522 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
7523 struct hwrm_fw_set_structured_data_cmd_err {
7524 u8 code;
7525 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
7526 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
7527 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
7528 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
7529 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
7530 u8 unused_0[7];
7531 };
7532
7533 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
7534 struct hwrm_fw_get_structured_data_input {
7535 __le16 req_type;
7536 __le16 cmpl_ring;
7537 __le16 seq_id;
7538 __le16 target_id;
7539 __le64 resp_addr;
7540 __le64 dest_data_addr;
7541 __le16 data_len;
7542 __le16 structure_id;
7543 __le16 subtype;
7544 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
7545 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
7546 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
7547 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
7548 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
7549 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
7550 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
7551 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
7552 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
7553 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
7554 u8 count;
7555 u8 unused_0;
7556 };
7557
7558 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
7559 struct hwrm_fw_get_structured_data_output {
7560 __le16 error_code;
7561 __le16 req_type;
7562 __le16 seq_id;
7563 __le16 resp_len;
7564 u8 hdr_cnt;
7565 u8 unused_0[6];
7566 u8 valid;
7567 };
7568
7569 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
7570 struct hwrm_fw_get_structured_data_cmd_err {
7571 u8 code;
7572 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
7573 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
7574 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
7575 u8 unused_0[7];
7576 };
7577
7578 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
7579 struct hwrm_exec_fwd_resp_input {
7580 __le16 req_type;
7581 __le16 cmpl_ring;
7582 __le16 seq_id;
7583 __le16 target_id;
7584 __le64 resp_addr;
7585 __le32 encap_request[26];
7586 __le16 encap_resp_target_id;
7587 u8 unused_0[6];
7588 };
7589
7590 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
7591 struct hwrm_exec_fwd_resp_output {
7592 __le16 error_code;
7593 __le16 req_type;
7594 __le16 seq_id;
7595 __le16 resp_len;
7596 u8 unused_0[7];
7597 u8 valid;
7598 };
7599
7600 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
7601 struct hwrm_reject_fwd_resp_input {
7602 __le16 req_type;
7603 __le16 cmpl_ring;
7604 __le16 seq_id;
7605 __le16 target_id;
7606 __le64 resp_addr;
7607 __le32 encap_request[26];
7608 __le16 encap_resp_target_id;
7609 u8 unused_0[6];
7610 };
7611
7612 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
7613 struct hwrm_reject_fwd_resp_output {
7614 __le16 error_code;
7615 __le16 req_type;
7616 __le16 seq_id;
7617 __le16 resp_len;
7618 u8 unused_0[7];
7619 u8 valid;
7620 };
7621
7622 /* hwrm_fwd_resp_input (size:1024b/128B) */
7623 struct hwrm_fwd_resp_input {
7624 __le16 req_type;
7625 __le16 cmpl_ring;
7626 __le16 seq_id;
7627 __le16 target_id;
7628 __le64 resp_addr;
7629 __le16 encap_resp_target_id;
7630 __le16 encap_resp_cmpl_ring;
7631 __le16 encap_resp_len;
7632 u8 unused_0;
7633 u8 unused_1;
7634 __le64 encap_resp_addr;
7635 __le32 encap_resp[24];
7636 };
7637
7638 /* hwrm_fwd_resp_output (size:128b/16B) */
7639 struct hwrm_fwd_resp_output {
7640 __le16 error_code;
7641 __le16 req_type;
7642 __le16 seq_id;
7643 __le16 resp_len;
7644 u8 unused_0[7];
7645 u8 valid;
7646 };
7647
7648 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
7649 struct hwrm_fwd_async_event_cmpl_input {
7650 __le16 req_type;
7651 __le16 cmpl_ring;
7652 __le16 seq_id;
7653 __le16 target_id;
7654 __le64 resp_addr;
7655 __le16 encap_async_event_target_id;
7656 u8 unused_0[6];
7657 __le32 encap_async_event_cmpl[4];
7658 };
7659
7660 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
7661 struct hwrm_fwd_async_event_cmpl_output {
7662 __le16 error_code;
7663 __le16 req_type;
7664 __le16 seq_id;
7665 __le16 resp_len;
7666 u8 unused_0[7];
7667 u8 valid;
7668 };
7669
7670 /* hwrm_temp_monitor_query_input (size:128b/16B) */
7671 struct hwrm_temp_monitor_query_input {
7672 __le16 req_type;
7673 __le16 cmpl_ring;
7674 __le16 seq_id;
7675 __le16 target_id;
7676 __le64 resp_addr;
7677 };
7678
7679 /* hwrm_temp_monitor_query_output (size:128b/16B) */
7680 struct hwrm_temp_monitor_query_output {
7681 __le16 error_code;
7682 __le16 req_type;
7683 __le16 seq_id;
7684 __le16 resp_len;
7685 u8 temp;
7686 u8 phy_temp;
7687 u8 om_temp;
7688 u8 flags;
7689 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
7690 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
7691 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
7692 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
7693 u8 unused_0[3];
7694 u8 valid;
7695 };
7696
7697 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
7698 struct hwrm_wol_filter_alloc_input {
7699 __le16 req_type;
7700 __le16 cmpl_ring;
7701 __le16 seq_id;
7702 __le16 target_id;
7703 __le64 resp_addr;
7704 __le32 flags;
7705 __le32 enables;
7706 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
7707 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
7708 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
7709 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
7710 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
7711 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
7712 __le16 port_id;
7713 u8 wol_type;
7714 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
7715 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
7716 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
7717 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
7718 u8 unused_0[5];
7719 u8 mac_address[6];
7720 __le16 pattern_offset;
7721 __le16 pattern_buf_size;
7722 __le16 pattern_mask_size;
7723 u8 unused_1[4];
7724 __le64 pattern_buf_addr;
7725 __le64 pattern_mask_addr;
7726 };
7727
7728 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
7729 struct hwrm_wol_filter_alloc_output {
7730 __le16 error_code;
7731 __le16 req_type;
7732 __le16 seq_id;
7733 __le16 resp_len;
7734 u8 wol_filter_id;
7735 u8 unused_0[6];
7736 u8 valid;
7737 };
7738
7739 /* hwrm_wol_filter_free_input (size:256b/32B) */
7740 struct hwrm_wol_filter_free_input {
7741 __le16 req_type;
7742 __le16 cmpl_ring;
7743 __le16 seq_id;
7744 __le16 target_id;
7745 __le64 resp_addr;
7746 __le32 flags;
7747 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
7748 __le32 enables;
7749 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
7750 __le16 port_id;
7751 u8 wol_filter_id;
7752 u8 unused_0[5];
7753 };
7754
7755 /* hwrm_wol_filter_free_output (size:128b/16B) */
7756 struct hwrm_wol_filter_free_output {
7757 __le16 error_code;
7758 __le16 req_type;
7759 __le16 seq_id;
7760 __le16 resp_len;
7761 u8 unused_0[7];
7762 u8 valid;
7763 };
7764
7765 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
7766 struct hwrm_wol_filter_qcfg_input {
7767 __le16 req_type;
7768 __le16 cmpl_ring;
7769 __le16 seq_id;
7770 __le16 target_id;
7771 __le64 resp_addr;
7772 __le16 port_id;
7773 __le16 handle;
7774 u8 unused_0[4];
7775 __le64 pattern_buf_addr;
7776 __le16 pattern_buf_size;
7777 u8 unused_1[6];
7778 __le64 pattern_mask_addr;
7779 __le16 pattern_mask_size;
7780 u8 unused_2[6];
7781 };
7782
7783 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
7784 struct hwrm_wol_filter_qcfg_output {
7785 __le16 error_code;
7786 __le16 req_type;
7787 __le16 seq_id;
7788 __le16 resp_len;
7789 __le16 next_handle;
7790 u8 wol_filter_id;
7791 u8 wol_type;
7792 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
7793 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
7794 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
7795 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
7796 __le32 unused_0;
7797 u8 mac_address[6];
7798 __le16 pattern_offset;
7799 __le16 pattern_size;
7800 __le16 pattern_mask_size;
7801 u8 unused_1[3];
7802 u8 valid;
7803 };
7804
7805 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
7806 struct hwrm_wol_reason_qcfg_input {
7807 __le16 req_type;
7808 __le16 cmpl_ring;
7809 __le16 seq_id;
7810 __le16 target_id;
7811 __le64 resp_addr;
7812 __le16 port_id;
7813 u8 unused_0[6];
7814 __le64 wol_pkt_buf_addr;
7815 __le16 wol_pkt_buf_size;
7816 u8 unused_1[6];
7817 };
7818
7819 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
7820 struct hwrm_wol_reason_qcfg_output {
7821 __le16 error_code;
7822 __le16 req_type;
7823 __le16 seq_id;
7824 __le16 resp_len;
7825 u8 wol_filter_id;
7826 u8 wol_reason;
7827 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
7828 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
7829 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
7830 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
7831 u8 wol_pkt_len;
7832 u8 unused_0[4];
7833 u8 valid;
7834 };
7835
7836 /* hwrm_dbg_read_direct_input (size:256b/32B) */
7837 struct hwrm_dbg_read_direct_input {
7838 __le16 req_type;
7839 __le16 cmpl_ring;
7840 __le16 seq_id;
7841 __le16 target_id;
7842 __le64 resp_addr;
7843 __le64 host_dest_addr;
7844 __le32 read_addr;
7845 __le32 read_len32;
7846 };
7847
7848 /* hwrm_dbg_read_direct_output (size:128b/16B) */
7849 struct hwrm_dbg_read_direct_output {
7850 __le16 error_code;
7851 __le16 req_type;
7852 __le16 seq_id;
7853 __le16 resp_len;
7854 __le32 crc32;
7855 u8 unused_0[3];
7856 u8 valid;
7857 };
7858
7859 /* hwrm_dbg_qcaps_input (size:192b/24B) */
7860 struct hwrm_dbg_qcaps_input {
7861 __le16 req_type;
7862 __le16 cmpl_ring;
7863 __le16 seq_id;
7864 __le16 target_id;
7865 __le64 resp_addr;
7866 __le16 fid;
7867 u8 unused_0[6];
7868 };
7869
7870 /* hwrm_dbg_qcaps_output (size:192b/24B) */
7871 struct hwrm_dbg_qcaps_output {
7872 __le16 error_code;
7873 __le16 req_type;
7874 __le16 seq_id;
7875 __le16 resp_len;
7876 __le16 fid;
7877 u8 unused_0[2];
7878 __le32 coredump_component_disable_caps;
7879 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL
7880 __le32 flags;
7881 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL
7882 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL
7883 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL
7884 u8 unused_1[3];
7885 u8 valid;
7886 };
7887
7888 /* hwrm_dbg_qcfg_input (size:192b/24B) */
7889 struct hwrm_dbg_qcfg_input {
7890 __le16 req_type;
7891 __le16 cmpl_ring;
7892 __le16 seq_id;
7893 __le16 target_id;
7894 __le64 resp_addr;
7895 __le16 fid;
7896 __le16 flags;
7897 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL
7898 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0
7899 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL
7900 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL
7901 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL
7902 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR
7903 __le32 coredump_component_disable_flags;
7904 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL
7905 };
7906
7907 /* hwrm_dbg_qcfg_output (size:256b/32B) */
7908 struct hwrm_dbg_qcfg_output {
7909 __le16 error_code;
7910 __le16 req_type;
7911 __le16 seq_id;
7912 __le16 resp_len;
7913 __le16 fid;
7914 u8 unused_0[2];
7915 __le32 coredump_size;
7916 __le32 flags;
7917 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL
7918 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL
7919 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL
7920 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL
7921 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL
7922 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL
7923 __le16 async_cmpl_ring;
7924 u8 unused_2[2];
7925 __le32 crashdump_size;
7926 u8 unused_3[3];
7927 u8 valid;
7928 };
7929
7930 /* coredump_segment_record (size:128b/16B) */
7931 struct coredump_segment_record {
7932 __le16 component_id;
7933 __le16 segment_id;
7934 __le16 max_instances;
7935 u8 version_hi;
7936 u8 version_low;
7937 u8 seg_flags;
7938 u8 compress_flags;
7939 #define SFLAG_COMPRESSED_ZLIB 0x1UL
7940 u8 unused_0[2];
7941 __le32 segment_len;
7942 };
7943
7944 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
7945 struct hwrm_dbg_coredump_list_input {
7946 __le16 req_type;
7947 __le16 cmpl_ring;
7948 __le16 seq_id;
7949 __le16 target_id;
7950 __le64 resp_addr;
7951 __le64 host_dest_addr;
7952 __le32 host_buf_len;
7953 __le16 seq_no;
7954 u8 flags;
7955 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL
7956 u8 unused_0[1];
7957 };
7958
7959 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
7960 struct hwrm_dbg_coredump_list_output {
7961 __le16 error_code;
7962 __le16 req_type;
7963 __le16 seq_id;
7964 __le16 resp_len;
7965 u8 flags;
7966 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
7967 u8 unused_0;
7968 __le16 total_segments;
7969 __le16 data_len;
7970 u8 unused_1;
7971 u8 valid;
7972 };
7973
7974 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
7975 struct hwrm_dbg_coredump_initiate_input {
7976 __le16 req_type;
7977 __le16 cmpl_ring;
7978 __le16 seq_id;
7979 __le16 target_id;
7980 __le64 resp_addr;
7981 __le16 component_id;
7982 __le16 segment_id;
7983 __le16 instance;
7984 __le16 unused_0;
7985 u8 seg_flags;
7986 u8 unused_1[7];
7987 };
7988
7989 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
7990 struct hwrm_dbg_coredump_initiate_output {
7991 __le16 error_code;
7992 __le16 req_type;
7993 __le16 seq_id;
7994 __le16 resp_len;
7995 u8 unused_0[7];
7996 u8 valid;
7997 };
7998
7999 /* coredump_data_hdr (size:128b/16B) */
8000 struct coredump_data_hdr {
8001 __le32 address;
8002 __le32 flags_length;
8003 __le32 instance;
8004 __le32 next_offset;
8005 };
8006
8007 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
8008 struct hwrm_dbg_coredump_retrieve_input {
8009 __le16 req_type;
8010 __le16 cmpl_ring;
8011 __le16 seq_id;
8012 __le16 target_id;
8013 __le64 resp_addr;
8014 __le64 host_dest_addr;
8015 __le32 host_buf_len;
8016 __le32 unused_0;
8017 __le16 component_id;
8018 __le16 segment_id;
8019 __le16 instance;
8020 __le16 unused_1;
8021 u8 seg_flags;
8022 u8 unused_2;
8023 __le16 unused_3;
8024 __le32 unused_4;
8025 __le32 seq_no;
8026 __le32 unused_5;
8027 };
8028
8029 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
8030 struct hwrm_dbg_coredump_retrieve_output {
8031 __le16 error_code;
8032 __le16 req_type;
8033 __le16 seq_id;
8034 __le16 resp_len;
8035 u8 flags;
8036 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
8037 u8 unused_0;
8038 __le16 data_len;
8039 u8 unused_1[3];
8040 u8 valid;
8041 };
8042
8043 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
8044 struct hwrm_dbg_ring_info_get_input {
8045 __le16 req_type;
8046 __le16 cmpl_ring;
8047 __le16 seq_id;
8048 __le16 target_id;
8049 __le64 resp_addr;
8050 u8 ring_type;
8051 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
8052 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
8053 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
8054 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL
8055 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ
8056 u8 unused_0[3];
8057 __le32 fw_ring_id;
8058 };
8059
8060 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
8061 struct hwrm_dbg_ring_info_get_output {
8062 __le16 error_code;
8063 __le16 req_type;
8064 __le16 seq_id;
8065 __le16 resp_len;
8066 __le32 producer_index;
8067 __le32 consumer_index;
8068 __le32 cag_vector_ctrl;
8069 u8 unused_0[3];
8070 u8 valid;
8071 };
8072
8073 /* hwrm_nvm_read_input (size:320b/40B) */
8074 struct hwrm_nvm_read_input {
8075 __le16 req_type;
8076 __le16 cmpl_ring;
8077 __le16 seq_id;
8078 __le16 target_id;
8079 __le64 resp_addr;
8080 __le64 host_dest_addr;
8081 __le16 dir_idx;
8082 u8 unused_0[2];
8083 __le32 offset;
8084 __le32 len;
8085 u8 unused_1[4];
8086 };
8087
8088 /* hwrm_nvm_read_output (size:128b/16B) */
8089 struct hwrm_nvm_read_output {
8090 __le16 error_code;
8091 __le16 req_type;
8092 __le16 seq_id;
8093 __le16 resp_len;
8094 u8 unused_0[7];
8095 u8 valid;
8096 };
8097
8098 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
8099 struct hwrm_nvm_get_dir_entries_input {
8100 __le16 req_type;
8101 __le16 cmpl_ring;
8102 __le16 seq_id;
8103 __le16 target_id;
8104 __le64 resp_addr;
8105 __le64 host_dest_addr;
8106 };
8107
8108 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
8109 struct hwrm_nvm_get_dir_entries_output {
8110 __le16 error_code;
8111 __le16 req_type;
8112 __le16 seq_id;
8113 __le16 resp_len;
8114 u8 unused_0[7];
8115 u8 valid;
8116 };
8117
8118 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
8119 struct hwrm_nvm_get_dir_info_input {
8120 __le16 req_type;
8121 __le16 cmpl_ring;
8122 __le16 seq_id;
8123 __le16 target_id;
8124 __le64 resp_addr;
8125 };
8126
8127 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
8128 struct hwrm_nvm_get_dir_info_output {
8129 __le16 error_code;
8130 __le16 req_type;
8131 __le16 seq_id;
8132 __le16 resp_len;
8133 __le32 entries;
8134 __le32 entry_length;
8135 u8 unused_0[7];
8136 u8 valid;
8137 };
8138
8139 /* hwrm_nvm_write_input (size:384b/48B) */
8140 struct hwrm_nvm_write_input {
8141 __le16 req_type;
8142 __le16 cmpl_ring;
8143 __le16 seq_id;
8144 __le16 target_id;
8145 __le64 resp_addr;
8146 __le64 host_src_addr;
8147 __le16 dir_type;
8148 __le16 dir_ordinal;
8149 __le16 dir_ext;
8150 __le16 dir_attr;
8151 __le32 dir_data_length;
8152 __le16 option;
8153 __le16 flags;
8154 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
8155 __le32 dir_item_length;
8156 __le32 unused_0;
8157 };
8158
8159 /* hwrm_nvm_write_output (size:128b/16B) */
8160 struct hwrm_nvm_write_output {
8161 __le16 error_code;
8162 __le16 req_type;
8163 __le16 seq_id;
8164 __le16 resp_len;
8165 __le32 dir_item_length;
8166 __le16 dir_idx;
8167 u8 unused_0;
8168 u8 valid;
8169 };
8170
8171 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
8172 struct hwrm_nvm_write_cmd_err {
8173 u8 code;
8174 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
8175 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
8176 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
8177 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
8178 u8 unused_0[7];
8179 };
8180
8181 /* hwrm_nvm_modify_input (size:320b/40B) */
8182 struct hwrm_nvm_modify_input {
8183 __le16 req_type;
8184 __le16 cmpl_ring;
8185 __le16 seq_id;
8186 __le16 target_id;
8187 __le64 resp_addr;
8188 __le64 host_src_addr;
8189 __le16 dir_idx;
8190 __le16 flags;
8191 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL
8192 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL
8193 __le32 offset;
8194 __le32 len;
8195 u8 unused_1[4];
8196 };
8197
8198 /* hwrm_nvm_modify_output (size:128b/16B) */
8199 struct hwrm_nvm_modify_output {
8200 __le16 error_code;
8201 __le16 req_type;
8202 __le16 seq_id;
8203 __le16 resp_len;
8204 u8 unused_0[7];
8205 u8 valid;
8206 };
8207
8208 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
8209 struct hwrm_nvm_find_dir_entry_input {
8210 __le16 req_type;
8211 __le16 cmpl_ring;
8212 __le16 seq_id;
8213 __le16 target_id;
8214 __le64 resp_addr;
8215 __le32 enables;
8216 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
8217 __le16 dir_idx;
8218 __le16 dir_type;
8219 __le16 dir_ordinal;
8220 __le16 dir_ext;
8221 u8 opt_ordinal;
8222 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
8223 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
8224 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
8225 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
8226 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
8227 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
8228 u8 unused_0[3];
8229 };
8230
8231 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
8232 struct hwrm_nvm_find_dir_entry_output {
8233 __le16 error_code;
8234 __le16 req_type;
8235 __le16 seq_id;
8236 __le16 resp_len;
8237 __le32 dir_item_length;
8238 __le32 dir_data_length;
8239 __le32 fw_ver;
8240 __le16 dir_ordinal;
8241 __le16 dir_idx;
8242 u8 unused_0[7];
8243 u8 valid;
8244 };
8245
8246 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
8247 struct hwrm_nvm_erase_dir_entry_input {
8248 __le16 req_type;
8249 __le16 cmpl_ring;
8250 __le16 seq_id;
8251 __le16 target_id;
8252 __le64 resp_addr;
8253 __le16 dir_idx;
8254 u8 unused_0[6];
8255 };
8256
8257 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
8258 struct hwrm_nvm_erase_dir_entry_output {
8259 __le16 error_code;
8260 __le16 req_type;
8261 __le16 seq_id;
8262 __le16 resp_len;
8263 u8 unused_0[7];
8264 u8 valid;
8265 };
8266
8267 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
8268 struct hwrm_nvm_get_dev_info_input {
8269 __le16 req_type;
8270 __le16 cmpl_ring;
8271 __le16 seq_id;
8272 __le16 target_id;
8273 __le64 resp_addr;
8274 };
8275
8276 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
8277 struct hwrm_nvm_get_dev_info_output {
8278 __le16 error_code;
8279 __le16 req_type;
8280 __le16 seq_id;
8281 __le16 resp_len;
8282 __le16 manufacturer_id;
8283 __le16 device_id;
8284 __le32 sector_size;
8285 __le32 nvram_size;
8286 __le32 reserved_size;
8287 __le32 available_size;
8288 u8 nvm_cfg_ver_maj;
8289 u8 nvm_cfg_ver_min;
8290 u8 nvm_cfg_ver_upd;
8291 u8 flags;
8292 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL
8293 char pkg_name[16];
8294 __le16 hwrm_fw_major;
8295 __le16 hwrm_fw_minor;
8296 __le16 hwrm_fw_build;
8297 __le16 hwrm_fw_patch;
8298 __le16 mgmt_fw_major;
8299 __le16 mgmt_fw_minor;
8300 __le16 mgmt_fw_build;
8301 __le16 mgmt_fw_patch;
8302 __le16 roce_fw_major;
8303 __le16 roce_fw_minor;
8304 __le16 roce_fw_build;
8305 __le16 roce_fw_patch;
8306 u8 unused_0[7];
8307 u8 valid;
8308 };
8309
8310 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
8311 struct hwrm_nvm_mod_dir_entry_input {
8312 __le16 req_type;
8313 __le16 cmpl_ring;
8314 __le16 seq_id;
8315 __le16 target_id;
8316 __le64 resp_addr;
8317 __le32 enables;
8318 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
8319 __le16 dir_idx;
8320 __le16 dir_ordinal;
8321 __le16 dir_ext;
8322 __le16 dir_attr;
8323 __le32 checksum;
8324 };
8325
8326 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
8327 struct hwrm_nvm_mod_dir_entry_output {
8328 __le16 error_code;
8329 __le16 req_type;
8330 __le16 seq_id;
8331 __le16 resp_len;
8332 u8 unused_0[7];
8333 u8 valid;
8334 };
8335
8336 /* hwrm_nvm_verify_update_input (size:192b/24B) */
8337 struct hwrm_nvm_verify_update_input {
8338 __le16 req_type;
8339 __le16 cmpl_ring;
8340 __le16 seq_id;
8341 __le16 target_id;
8342 __le64 resp_addr;
8343 __le16 dir_type;
8344 __le16 dir_ordinal;
8345 __le16 dir_ext;
8346 u8 unused_0[2];
8347 };
8348
8349 /* hwrm_nvm_verify_update_output (size:128b/16B) */
8350 struct hwrm_nvm_verify_update_output {
8351 __le16 error_code;
8352 __le16 req_type;
8353 __le16 seq_id;
8354 __le16 resp_len;
8355 u8 unused_0[7];
8356 u8 valid;
8357 };
8358
8359 /* hwrm_nvm_install_update_input (size:192b/24B) */
8360 struct hwrm_nvm_install_update_input {
8361 __le16 req_type;
8362 __le16 cmpl_ring;
8363 __le16 seq_id;
8364 __le16 target_id;
8365 __le64 resp_addr;
8366 __le32 install_type;
8367 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
8368 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
8369 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
8370 __le16 flags;
8371 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
8372 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
8373 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
8374 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL
8375 u8 unused_0[2];
8376 };
8377
8378 /* hwrm_nvm_install_update_output (size:192b/24B) */
8379 struct hwrm_nvm_install_update_output {
8380 __le16 error_code;
8381 __le16 req_type;
8382 __le16 seq_id;
8383 __le16 resp_len;
8384 __le64 installed_items;
8385 u8 result;
8386 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
8387 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
8388 u8 problem_item;
8389 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
8390 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
8391 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
8392 u8 reset_required;
8393 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
8394 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
8395 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
8396 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
8397 u8 unused_0[4];
8398 u8 valid;
8399 };
8400
8401 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
8402 struct hwrm_nvm_install_update_cmd_err {
8403 u8 code;
8404 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
8405 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
8406 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
8407 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
8408 u8 unused_0[7];
8409 };
8410
8411 /* hwrm_nvm_get_variable_input (size:320b/40B) */
8412 struct hwrm_nvm_get_variable_input {
8413 __le16 req_type;
8414 __le16 cmpl_ring;
8415 __le16 seq_id;
8416 __le16 target_id;
8417 __le64 resp_addr;
8418 __le64 dest_data_addr;
8419 __le16 data_len;
8420 __le16 option_num;
8421 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
8422 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
8423 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
8424 __le16 dimensions;
8425 __le16 index_0;
8426 __le16 index_1;
8427 __le16 index_2;
8428 __le16 index_3;
8429 u8 flags;
8430 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
8431 u8 unused_0;
8432 };
8433
8434 /* hwrm_nvm_get_variable_output (size:128b/16B) */
8435 struct hwrm_nvm_get_variable_output {
8436 __le16 error_code;
8437 __le16 req_type;
8438 __le16 seq_id;
8439 __le16 resp_len;
8440 __le16 data_len;
8441 __le16 option_num;
8442 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
8443 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
8444 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
8445 u8 unused_0[3];
8446 u8 valid;
8447 };
8448
8449 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
8450 struct hwrm_nvm_get_variable_cmd_err {
8451 u8 code;
8452 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
8453 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
8454 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
8455 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
8456 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
8457 u8 unused_0[7];
8458 };
8459
8460 /* hwrm_nvm_set_variable_input (size:320b/40B) */
8461 struct hwrm_nvm_set_variable_input {
8462 __le16 req_type;
8463 __le16 cmpl_ring;
8464 __le16 seq_id;
8465 __le16 target_id;
8466 __le64 resp_addr;
8467 __le64 src_data_addr;
8468 __le16 data_len;
8469 __le16 option_num;
8470 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
8471 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
8472 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
8473 __le16 dimensions;
8474 __le16 index_0;
8475 __le16 index_1;
8476 __le16 index_2;
8477 __le16 index_3;
8478 u8 flags;
8479 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
8480 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
8481 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
8482 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
8483 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
8484 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
8485 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
8486 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
8487 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL
8488 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4
8489 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
8490 u8 unused_0;
8491 };
8492
8493 /* hwrm_nvm_set_variable_output (size:128b/16B) */
8494 struct hwrm_nvm_set_variable_output {
8495 __le16 error_code;
8496 __le16 req_type;
8497 __le16 seq_id;
8498 __le16 resp_len;
8499 u8 unused_0[7];
8500 u8 valid;
8501 };
8502
8503 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
8504 struct hwrm_nvm_set_variable_cmd_err {
8505 u8 code;
8506 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
8507 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
8508 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
8509 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
8510 u8 unused_0[7];
8511 };
8512
8513 /* hwrm_selftest_qlist_input (size:128b/16B) */
8514 struct hwrm_selftest_qlist_input {
8515 __le16 req_type;
8516 __le16 cmpl_ring;
8517 __le16 seq_id;
8518 __le16 target_id;
8519 __le64 resp_addr;
8520 };
8521
8522 /* hwrm_selftest_qlist_output (size:2240b/280B) */
8523 struct hwrm_selftest_qlist_output {
8524 __le16 error_code;
8525 __le16 req_type;
8526 __le16 seq_id;
8527 __le16 resp_len;
8528 u8 num_tests;
8529 u8 available_tests;
8530 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
8531 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
8532 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
8533 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
8534 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
8535 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
8536 u8 offline_tests;
8537 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
8538 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
8539 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
8540 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
8541 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
8542 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
8543 u8 unused_0;
8544 __le16 test_timeout;
8545 u8 unused_1[2];
8546 char test0_name[32];
8547 char test1_name[32];
8548 char test2_name[32];
8549 char test3_name[32];
8550 char test4_name[32];
8551 char test5_name[32];
8552 char test6_name[32];
8553 char test7_name[32];
8554 u8 eyescope_target_BER_support;
8555 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL
8556 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL
8557 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL
8558 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL
8559 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL
8560 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED
8561 u8 unused_2[6];
8562 u8 valid;
8563 };
8564
8565 /* hwrm_selftest_exec_input (size:192b/24B) */
8566 struct hwrm_selftest_exec_input {
8567 __le16 req_type;
8568 __le16 cmpl_ring;
8569 __le16 seq_id;
8570 __le16 target_id;
8571 __le64 resp_addr;
8572 u8 flags;
8573 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
8574 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
8575 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
8576 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
8577 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
8578 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
8579 u8 unused_0[7];
8580 };
8581
8582 /* hwrm_selftest_exec_output (size:128b/16B) */
8583 struct hwrm_selftest_exec_output {
8584 __le16 error_code;
8585 __le16 req_type;
8586 __le16 seq_id;
8587 __le16 resp_len;
8588 u8 requested_tests;
8589 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
8590 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
8591 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
8592 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
8593 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
8594 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
8595 u8 test_success;
8596 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
8597 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
8598 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
8599 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
8600 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
8601 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
8602 u8 unused_0[5];
8603 u8 valid;
8604 };
8605
8606 /* hwrm_selftest_irq_input (size:128b/16B) */
8607 struct hwrm_selftest_irq_input {
8608 __le16 req_type;
8609 __le16 cmpl_ring;
8610 __le16 seq_id;
8611 __le16 target_id;
8612 __le64 resp_addr;
8613 };
8614
8615 /* hwrm_selftest_irq_output (size:128b/16B) */
8616 struct hwrm_selftest_irq_output {
8617 __le16 error_code;
8618 __le16 req_type;
8619 __le16 seq_id;
8620 __le16 resp_len;
8621 u8 unused_0[7];
8622 u8 valid;
8623 };
8624
8625 /* db_push_info (size:64b/8B) */
8626 struct db_push_info {
8627 u32 push_size_push_index;
8628 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL
8629 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0
8630 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL
8631 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24
8632 u32 reserved32;
8633 };
8634
8635 /* fw_status_reg (size:32b/4B) */
8636 struct fw_status_reg {
8637 u32 fw_status;
8638 #define FW_STATUS_REG_CODE_MASK 0xffffUL
8639 #define FW_STATUS_REG_CODE_SFT 0
8640 #define FW_STATUS_REG_CODE_READY 0x8000UL
8641 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY
8642 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL
8643 #define FW_STATUS_REG_RECOVERABLE 0x20000UL
8644 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL
8645 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL
8646 #define FW_STATUS_REG_SHUTDOWN 0x100000UL
8647 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL
8648 };
8649
8650 /* hcomm_status (size:64b/8B) */
8651 struct hcomm_status {
8652 u32 sig_ver;
8653 #define HCOMM_STATUS_VER_MASK 0xffUL
8654 #define HCOMM_STATUS_VER_SFT 0
8655 #define HCOMM_STATUS_VER_LATEST 0x1UL
8656 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
8657 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL
8658 #define HCOMM_STATUS_SIGNATURE_SFT 8
8659 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8)
8660 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
8661 u32 fw_status_loc;
8662 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL
8663 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
8664 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL
8665 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL
8666 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL
8667 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL
8668 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
8669 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL
8670 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
8671 };
8672
8673 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
8674
8675 #endif /* _BNXT_HSI_H_ */
Linux with added FPC-III support