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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
blob8ff28ed04b7fcd0616760f91d727898d98f01f3e
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Cavium, Inc.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/phy.h>
13 #include <linux/of.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_net.h>
16
17 #include "nic_reg.h"
18 #include "nic.h"
19 #include "thunder_bgx.h"
20
21 #define DRV_NAME "thunder_bgx"
22 #define DRV_VERSION "1.0"
23
24 /* RX_DMAC_CTL configuration */
25 enum MCAST_MODE {
26 MCAST_MODE_REJECT = 0x0,
27 MCAST_MODE_ACCEPT = 0x1,
28 MCAST_MODE_CAM_FILTER = 0x2,
29 RSVD = 0x3
30 };
31
32 #define BCAST_ACCEPT BIT(0)
33 #define CAM_ACCEPT BIT(3)
34 #define MCAST_MODE_MASK 0x3
35 #define BGX_MCAST_MODE(x) (x << 1)
36
37 struct dmac_map {
38 u64 vf_map;
39 u64 dmac;
40 };
41
42 struct lmac {
43 struct bgx *bgx;
44 /* actual number of DMACs configured */
45 u8 dmacs_cfg;
46 /* overal number of possible DMACs could be configured per LMAC */
47 u8 dmacs_count;
48 struct dmac_map *dmacs; /* DMAC:VFs tracking filter array */
49 u8 mac[ETH_ALEN];
50 u8 lmac_type;
51 u8 lane_to_sds;
52 bool use_training;
53 bool autoneg;
54 bool link_up;
55 int lmacid; /* ID within BGX */
56 int lmacid_bd; /* ID on board */
57 struct net_device netdev;
58 struct phy_device *phydev;
59 unsigned int last_duplex;
60 unsigned int last_link;
61 unsigned int last_speed;
62 bool is_sgmii;
63 struct delayed_work dwork;
64 struct workqueue_struct *check_link;
65 };
66
67 struct bgx {
68 u8 bgx_id;
69 struct lmac lmac[MAX_LMAC_PER_BGX];
70 u8 lmac_count;
71 u8 max_lmac;
72 u8 acpi_lmac_idx;
73 void __iomem *reg_base;
74 struct pci_dev *pdev;
75 bool is_dlm;
76 bool is_rgx;
77 };
78
79 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
80 static int lmac_count; /* Total no of LMACs in system */
81
82 static int bgx_xaui_check_link(struct lmac *lmac);
83
84 /* Supported devices */
85 static const struct pci_device_id bgx_id_table[] = {
86 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
87 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
88 { 0, } /* end of table */
89 };
90
91 MODULE_AUTHOR("Cavium Inc");
92 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
93 MODULE_LICENSE("GPL v2");
94 MODULE_VERSION(DRV_VERSION);
95 MODULE_DEVICE_TABLE(pci, bgx_id_table);
96
97 /* The Cavium ThunderX network controller can *only* be found in SoCs
98 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
99 * registers on this platform are implicitly strongly ordered with respect
100 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
101 * with no memory barriers in this driver. The readq()/writeq() functions add
102 * explicit ordering operation which in this case are redundant, and only
103 * add overhead.
104 */
105
106 /* Register read/write APIs */
107 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
108 {
109 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
110
111 return readq_relaxed(addr);
112 }
113
114 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
115 {
116 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
117
118 writeq_relaxed(val, addr);
119 }
120
121 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
122 {
123 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
124
125 writeq_relaxed(val | readq_relaxed(addr), addr);
126 }
127
128 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
129 {
130 int timeout = 100;
131 u64 reg_val;
132
133 while (timeout) {
134 reg_val = bgx_reg_read(bgx, lmac, reg);
135 if (zero && !(reg_val & mask))
136 return 0;
137 if (!zero && (reg_val & mask))
138 return 0;
139 usleep_range(1000, 2000);
140 timeout--;
141 }
142 return 1;
143 }
144
145 static int max_bgx_per_node;
146 static void set_max_bgx_per_node(struct pci_dev *pdev)
147 {
148 u16 sdevid;
149
150 if (max_bgx_per_node)
151 return;
152
153 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
154 switch (sdevid) {
155 case PCI_SUBSYS_DEVID_81XX_BGX:
156 case PCI_SUBSYS_DEVID_81XX_RGX:
157 max_bgx_per_node = MAX_BGX_PER_CN81XX;
158 break;
159 case PCI_SUBSYS_DEVID_83XX_BGX:
160 max_bgx_per_node = MAX_BGX_PER_CN83XX;
161 break;
162 case PCI_SUBSYS_DEVID_88XX_BGX:
163 default:
164 max_bgx_per_node = MAX_BGX_PER_CN88XX;
165 break;
166 }
167 }
168
169 static struct bgx *get_bgx(int node, int bgx_idx)
170 {
171 int idx = (node * max_bgx_per_node) + bgx_idx;
172
173 return bgx_vnic[idx];
174 }
175
176 /* Return number of BGX present in HW */
177 unsigned bgx_get_map(int node)
178 {
179 int i;
180 unsigned map = 0;
181
182 for (i = 0; i < max_bgx_per_node; i++) {
183 if (bgx_vnic[(node * max_bgx_per_node) + i])
184 map |= (1 << i);
185 }
186
187 return map;
188 }
189 EXPORT_SYMBOL(bgx_get_map);
190
191 /* Return number of LMAC configured for this BGX */
192 int bgx_get_lmac_count(int node, int bgx_idx)
193 {
194 struct bgx *bgx;
195
196 bgx = get_bgx(node, bgx_idx);
197 if (bgx)
198 return bgx->lmac_count;
199
200 return 0;
201 }
202 EXPORT_SYMBOL(bgx_get_lmac_count);
203
204 /* Returns the current link status of LMAC */
205 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
206 {
207 struct bgx_link_status *link = (struct bgx_link_status *)status;
208 struct bgx *bgx;
209 struct lmac *lmac;
210
211 bgx = get_bgx(node, bgx_idx);
212 if (!bgx)
213 return;
214
215 lmac = &bgx->lmac[lmacid];
216 link->mac_type = lmac->lmac_type;
217 link->link_up = lmac->link_up;
218 link->duplex = lmac->last_duplex;
219 link->speed = lmac->last_speed;
220 }
221 EXPORT_SYMBOL(bgx_get_lmac_link_state);
222
223 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
224 {
225 struct bgx *bgx = get_bgx(node, bgx_idx);
226
227 if (bgx)
228 return bgx->lmac[lmacid].mac;
229
230 return NULL;
231 }
232 EXPORT_SYMBOL(bgx_get_lmac_mac);
233
234 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
235 {
236 struct bgx *bgx = get_bgx(node, bgx_idx);
237
238 if (!bgx)
239 return;
240
241 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
242 }
243 EXPORT_SYMBOL(bgx_set_lmac_mac);
244
245 static void bgx_flush_dmac_cam_filter(struct bgx *bgx, int lmacid)
246 {
247 struct lmac *lmac = NULL;
248 u8 idx = 0;
249
250 lmac = &bgx->lmac[lmacid];
251 /* reset CAM filters */
252 for (idx = 0; idx < lmac->dmacs_count; idx++)
253 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
254 ((lmacid * lmac->dmacs_count) + idx) *
255 sizeof(u64), 0);
256 }
257
258 static void bgx_lmac_remove_filters(struct lmac *lmac, u8 vf_id)
259 {
260 int i = 0;
261
262 if (!lmac)
263 return;
264
265 /* We've got reset filters request from some of attached VF, while the
266 * others might want to keep their configuration. So in this case lets
267 * iterate over all of configured filters and decrease number of
268 * referencies. if some addresses get zero refs remove them from list
269 */
270 for (i = lmac->dmacs_cfg - 1; i >= 0; i--) {
271 lmac->dmacs[i].vf_map &= ~BIT_ULL(vf_id);
272 if (!lmac->dmacs[i].vf_map) {
273 lmac->dmacs_cfg--;
274 lmac->dmacs[i].dmac = 0;
275 lmac->dmacs[i].vf_map = 0;
276 }
277 }
278 }
279
280 static int bgx_lmac_save_filter(struct lmac *lmac, u64 dmac, u8 vf_id)
281 {
282 u8 i = 0;
283
284 if (!lmac)
285 return -1;
286
287 /* At the same time we could have several VFs 'attached' to some
288 * particular LMAC, and each VF is represented as network interface
289 * for kernel. So from user perspective it should be possible to
290 * manipulate with its' (VF) receive modes. However from PF
291 * driver perspective we need to keep track of filter configurations
292 * for different VFs to prevent filter values dupes
293 */
294 for (i = 0; i < lmac->dmacs_cfg; i++) {
295 if (lmac->dmacs[i].dmac == dmac) {
296 lmac->dmacs[i].vf_map |= BIT_ULL(vf_id);
297 return -1;
298 }
299 }
300
301 if (!(lmac->dmacs_cfg < lmac->dmacs_count))
302 return -1;
303
304 /* keep it for further tracking */
305 lmac->dmacs[lmac->dmacs_cfg].dmac = dmac;
306 lmac->dmacs[lmac->dmacs_cfg].vf_map = BIT_ULL(vf_id);
307 lmac->dmacs_cfg++;
308 return 0;
309 }
310
311 static int bgx_set_dmac_cam_filter_mac(struct bgx *bgx, int lmacid,
312 u64 cam_dmac, u8 idx)
313 {
314 struct lmac *lmac = NULL;
315 u64 cfg = 0;
316
317 /* skip zero addresses as meaningless */
318 if (!cam_dmac || !bgx)
319 return -1;
320
321 lmac = &bgx->lmac[lmacid];
322
323 /* configure DCAM filtering for designated LMAC */
324 cfg = RX_DMACX_CAM_LMACID(lmacid & LMAC_ID_MASK) |
325 RX_DMACX_CAM_EN | cam_dmac;
326 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
327 ((lmacid * lmac->dmacs_count) + idx) * sizeof(u64), cfg);
328 return 0;
329 }
330
331 void bgx_set_dmac_cam_filter(int node, int bgx_idx, int lmacid,
332 u64 cam_dmac, u8 vf_id)
333 {
334 struct bgx *bgx = get_bgx(node, bgx_idx);
335 struct lmac *lmac = NULL;
336
337 if (!bgx)
338 return;
339
340 lmac = &bgx->lmac[lmacid];
341
342 if (!cam_dmac)
343 cam_dmac = ether_addr_to_u64(lmac->mac);
344
345 /* since we might have several VFs attached to particular LMAC
346 * and kernel could call mcast config for each of them with the
347 * same MAC, check if requested MAC is already in filtering list and
348 * updare/prepare list of MACs to be applied later to HW filters
349 */
350 bgx_lmac_save_filter(lmac, cam_dmac, vf_id);
351 }
352 EXPORT_SYMBOL(bgx_set_dmac_cam_filter);
353
354 void bgx_set_xcast_mode(int node, int bgx_idx, int lmacid, u8 mode)
355 {
356 struct bgx *bgx = get_bgx(node, bgx_idx);
357 struct lmac *lmac = NULL;
358 u64 cfg = 0;
359 u8 i = 0;
360
361 if (!bgx)
362 return;
363
364 lmac = &bgx->lmac[lmacid];
365
366 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL);
367 if (mode & BGX_XCAST_BCAST_ACCEPT)
368 cfg |= BCAST_ACCEPT;
369 else
370 cfg &= ~BCAST_ACCEPT;
371
372 /* disable all MCASTs and DMAC filtering */
373 cfg &= ~(CAM_ACCEPT | BGX_MCAST_MODE(MCAST_MODE_MASK));
374
375 /* check requested bits and set filtergin mode appropriately */
376 if (mode & (BGX_XCAST_MCAST_ACCEPT)) {
377 cfg |= (BGX_MCAST_MODE(MCAST_MODE_ACCEPT));
378 } else if (mode & BGX_XCAST_MCAST_FILTER) {
379 cfg |= (BGX_MCAST_MODE(MCAST_MODE_CAM_FILTER) | CAM_ACCEPT);
380 for (i = 0; i < lmac->dmacs_cfg; i++)
381 bgx_set_dmac_cam_filter_mac(bgx, lmacid,
382 lmac->dmacs[i].dmac, i);
383 }
384 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, cfg);
385 }
386 EXPORT_SYMBOL(bgx_set_xcast_mode);
387
388 void bgx_reset_xcast_mode(int node, int bgx_idx, int lmacid, u8 vf_id)
389 {
390 struct bgx *bgx = get_bgx(node, bgx_idx);
391
392 if (!bgx)
393 return;
394
395 bgx_lmac_remove_filters(&bgx->lmac[lmacid], vf_id);
396 bgx_flush_dmac_cam_filter(bgx, lmacid);
397 bgx_set_xcast_mode(node, bgx_idx, lmacid,
398 (BGX_XCAST_BCAST_ACCEPT | BGX_XCAST_MCAST_ACCEPT));
399 }
400 EXPORT_SYMBOL(bgx_reset_xcast_mode);
401
402 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
403 {
404 struct bgx *bgx = get_bgx(node, bgx_idx);
405 struct lmac *lmac;
406 u64 cfg;
407
408 if (!bgx)
409 return;
410 lmac = &bgx->lmac[lmacid];
411
412 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
413 if (enable) {
414 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
415
416 /* enable TX FIFO Underflow interrupt */
417 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1S,
418 GMI_TXX_INT_UNDFLW);
419 } else {
420 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
421
422 /* Disable TX FIFO Underflow interrupt */
423 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1C,
424 GMI_TXX_INT_UNDFLW);
425 }
426 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
427
428 if (bgx->is_rgx)
429 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
430 }
431 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
432
433 /* Enables or disables timestamp insertion by BGX for Rx packets */
434 void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable)
435 {
436 struct bgx *bgx = get_bgx(node, bgx_idx);
437 struct lmac *lmac;
438 u64 csr_offset, cfg;
439
440 if (!bgx)
441 return;
442
443 lmac = &bgx->lmac[lmacid];
444
445 if (lmac->lmac_type == BGX_MODE_SGMII ||
446 lmac->lmac_type == BGX_MODE_QSGMII ||
447 lmac->lmac_type == BGX_MODE_RGMII)
448 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL;
449 else
450 csr_offset = BGX_SMUX_RX_FRM_CTL;
451
452 cfg = bgx_reg_read(bgx, lmacid, csr_offset);
453
454 if (enable)
455 cfg |= BGX_PKT_RX_PTP_EN;
456 else
457 cfg &= ~BGX_PKT_RX_PTP_EN;
458 bgx_reg_write(bgx, lmacid, csr_offset, cfg);
459 }
460 EXPORT_SYMBOL(bgx_config_timestamping);
461
462 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
463 {
464 struct pfc *pfc = (struct pfc *)pause;
465 struct bgx *bgx = get_bgx(node, bgx_idx);
466 struct lmac *lmac;
467 u64 cfg;
468
469 if (!bgx)
470 return;
471 lmac = &bgx->lmac[lmacid];
472 if (lmac->is_sgmii)
473 return;
474
475 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
476 pfc->fc_rx = cfg & RX_EN;
477 pfc->fc_tx = cfg & TX_EN;
478 pfc->autoneg = 0;
479 }
480 EXPORT_SYMBOL(bgx_lmac_get_pfc);
481
482 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
483 {
484 struct pfc *pfc = (struct pfc *)pause;
485 struct bgx *bgx = get_bgx(node, bgx_idx);
486 struct lmac *lmac;
487 u64 cfg;
488
489 if (!bgx)
490 return;
491 lmac = &bgx->lmac[lmacid];
492 if (lmac->is_sgmii)
493 return;
494
495 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
496 cfg &= ~(RX_EN | TX_EN);
497 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
498 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
499 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
500 }
501 EXPORT_SYMBOL(bgx_lmac_set_pfc);
502
503 static void bgx_sgmii_change_link_state(struct lmac *lmac)
504 {
505 struct bgx *bgx = lmac->bgx;
506 u64 cmr_cfg;
507 u64 port_cfg = 0;
508 u64 misc_ctl = 0;
509 bool tx_en, rx_en;
510
511 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
512 tx_en = cmr_cfg & CMR_PKT_TX_EN;
513 rx_en = cmr_cfg & CMR_PKT_RX_EN;
514 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
515 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
516
517 /* Wait for BGX RX to be idle */
518 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
519 GMI_PORT_CFG_RX_IDLE, false)) {
520 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
521 bgx->bgx_id, lmac->lmacid);
522 return;
523 }
524
525 /* Wait for BGX TX to be idle */
526 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
527 GMI_PORT_CFG_TX_IDLE, false)) {
528 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
529 bgx->bgx_id, lmac->lmacid);
530 return;
531 }
532
533 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
534 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
535
536 if (lmac->link_up) {
537 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
538 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
539 port_cfg |= (lmac->last_duplex << 2);
540 } else {
541 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
542 }
543
544 switch (lmac->last_speed) {
545 case 10:
546 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
547 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
548 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
549 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
550 misc_ctl |= 50; /* samp_pt */
551 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
552 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
553 break;
554 case 100:
555 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
556 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
557 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
558 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
559 misc_ctl |= 5; /* samp_pt */
560 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
561 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
562 break;
563 case 1000:
564 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
565 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
566 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
567 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
568 misc_ctl |= 1; /* samp_pt */
569 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
570 if (lmac->last_duplex)
571 bgx_reg_write(bgx, lmac->lmacid,
572 BGX_GMP_GMI_TXX_BURST, 0);
573 else
574 bgx_reg_write(bgx, lmac->lmacid,
575 BGX_GMP_GMI_TXX_BURST, 8192);
576 break;
577 default:
578 break;
579 }
580 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
581 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
582
583 /* Restore CMR config settings */
584 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
585 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
586
587 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
588 xcv_setup_link(lmac->link_up, lmac->last_speed);
589 }
590
591 static void bgx_lmac_handler(struct net_device *netdev)
592 {
593 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
594 struct phy_device *phydev;
595 int link_changed = 0;
596
597 if (!lmac)
598 return;
599
600 phydev = lmac->phydev;
601
602 if (!phydev->link && lmac->last_link)
603 link_changed = -1;
604
605 if (phydev->link &&
606 (lmac->last_duplex != phydev->duplex ||
607 lmac->last_link != phydev->link ||
608 lmac->last_speed != phydev->speed)) {
609 link_changed = 1;
610 }
611
612 lmac->last_link = phydev->link;
613 lmac->last_speed = phydev->speed;
614 lmac->last_duplex = phydev->duplex;
615
616 if (!link_changed)
617 return;
618
619 if (link_changed > 0)
620 lmac->link_up = true;
621 else
622 lmac->link_up = false;
623
624 if (lmac->is_sgmii)
625 bgx_sgmii_change_link_state(lmac);
626 else
627 bgx_xaui_check_link(lmac);
628 }
629
630 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
631 {
632 struct bgx *bgx;
633
634 bgx = get_bgx(node, bgx_idx);
635 if (!bgx)
636 return 0;
637
638 if (idx > 8)
639 lmac = 0;
640 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
641 }
642 EXPORT_SYMBOL(bgx_get_rx_stats);
643
644 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
645 {
646 struct bgx *bgx;
647
648 bgx = get_bgx(node, bgx_idx);
649 if (!bgx)
650 return 0;
651
652 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
653 }
654 EXPORT_SYMBOL(bgx_get_tx_stats);
655
656 /* Configure BGX LMAC in internal loopback mode */
657 void bgx_lmac_internal_loopback(int node, int bgx_idx,
658 int lmac_idx, bool enable)
659 {
660 struct bgx *bgx;
661 struct lmac *lmac;
662 u64 cfg;
663
664 bgx = get_bgx(node, bgx_idx);
665 if (!bgx)
666 return;
667
668 lmac = &bgx->lmac[lmac_idx];
669 if (lmac->is_sgmii) {
670 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
671 if (enable)
672 cfg |= PCS_MRX_CTL_LOOPBACK1;
673 else
674 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
675 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
676 } else {
677 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
678 if (enable)
679 cfg |= SPU_CTL_LOOPBACK;
680 else
681 cfg &= ~SPU_CTL_LOOPBACK;
682 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
683 }
684 }
685 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
686
687 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
688 {
689 int lmacid = lmac->lmacid;
690 u64 cfg;
691
692 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
693 /* max packet size */
694 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
695
696 /* Disable frame alignment if using preamble */
697 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
698 if (cfg & 1)
699 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
700
701 /* Enable lmac */
702 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
703
704 /* PCS reset */
705 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
706 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
707 PCS_MRX_CTL_RESET, true)) {
708 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
709 return -1;
710 }
711
712 /* power down, reset autoneg, autoneg enable */
713 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
714 cfg &= ~PCS_MRX_CTL_PWR_DN;
715 cfg |= PCS_MRX_CTL_RST_AN;
716 if (lmac->phydev) {
717 cfg |= PCS_MRX_CTL_AN_EN;
718 } else {
719 /* In scenarios where PHY driver is not present or it's a
720 * non-standard PHY, FW sets AN_EN to inform Linux driver
721 * to do auto-neg and link polling or not.
722 */
723 if (cfg & PCS_MRX_CTL_AN_EN)
724 lmac->autoneg = true;
725 }
726 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
727
728 if (lmac->lmac_type == BGX_MODE_QSGMII) {
729 /* Disable disparity check for QSGMII */
730 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
731 cfg &= ~PCS_MISC_CTL_DISP_EN;
732 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
733 return 0;
734 }
735
736 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
737 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
738 PCS_MRX_STATUS_AN_CPT, false)) {
739 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
740 return -1;
741 }
742 }
743
744 return 0;
745 }
746
747 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
748 {
749 u64 cfg;
750 int lmacid = lmac->lmacid;
751
752 /* Reset SPU */
753 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
754 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
755 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
756 return -1;
757 }
758
759 /* Disable LMAC */
760 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
761 cfg &= ~CMR_EN;
762 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
763
764 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
765 /* Set interleaved running disparity for RXAUI */
766 if (lmac->lmac_type == BGX_MODE_RXAUI)
767 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
768 SPU_MISC_CTL_INTLV_RDISP);
769
770 /* Clear receive packet disable */
771 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
772 cfg &= ~SPU_MISC_CTL_RX_DIS;
773 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
774
775 /* clear all interrupts */
776 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
777 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
778 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
779 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
780 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
781 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
782
783 if (lmac->use_training) {
784 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
785 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
786 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
787 /* training enable */
788 bgx_reg_modify(bgx, lmacid,
789 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
790 }
791
792 /* Append FCS to each packet */
793 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
794
795 /* Disable forward error correction */
796 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
797 cfg &= ~SPU_FEC_CTL_FEC_EN;
798 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
799
800 /* Disable autoneg */
801 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
802 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
803 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
804
805 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
806 if (lmac->lmac_type == BGX_MODE_10G_KR)
807 cfg |= (1 << 23);
808 else if (lmac->lmac_type == BGX_MODE_40G_KR)
809 cfg |= (1 << 24);
810 else
811 cfg &= ~((1 << 23) | (1 << 24));
812 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
813 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
814
815 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
816 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
817 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
818
819 /* Enable lmac */
820 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
821
822 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
823 cfg &= ~SPU_CTL_LOW_POWER;
824 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
825
826 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
827 cfg &= ~SMU_TX_CTL_UNI_EN;
828 cfg |= SMU_TX_CTL_DIC_EN;
829 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
830
831 /* Enable receive and transmission of pause frames */
832 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
833 BCK_EN | DRP_EN | TX_EN | RX_EN));
834 /* Configure pause time and interval */
835 bgx_reg_write(bgx, lmacid,
836 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
837 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
838 cfg &= ~0xFFFFull;
839 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
840 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
841 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
842
843 /* take lmac_count into account */
844 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
845 /* max packet size */
846 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
847
848 return 0;
849 }
850
851 static int bgx_xaui_check_link(struct lmac *lmac)
852 {
853 struct bgx *bgx = lmac->bgx;
854 int lmacid = lmac->lmacid;
855 int lmac_type = lmac->lmac_type;
856 u64 cfg;
857
858 if (lmac->use_training) {
859 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
860 if (!(cfg & (1ull << 13))) {
861 cfg = (1ull << 13) | (1ull << 14);
862 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
863 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
864 cfg |= (1ull << 0);
865 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
866 return -1;
867 }
868 }
869
870 /* wait for PCS to come out of reset */
871 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
872 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
873 return -1;
874 }
875
876 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
877 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
878 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
879 SPU_BR_STATUS_BLK_LOCK, false)) {
880 dev_err(&bgx->pdev->dev,
881 "SPU_BR_STATUS_BLK_LOCK not completed\n");
882 return -1;
883 }
884 } else {
885 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
886 SPU_BX_STATUS_RX_ALIGN, false)) {
887 dev_err(&bgx->pdev->dev,
888 "SPU_BX_STATUS_RX_ALIGN not completed\n");
889 return -1;
890 }
891 }
892
893 /* Clear rcvflt bit (latching high) and read it back */
894 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
895 bgx_reg_modify(bgx, lmacid,
896 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
897 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
898 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
899 if (lmac->use_training) {
900 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
901 if (!(cfg & (1ull << 13))) {
902 cfg = (1ull << 13) | (1ull << 14);
903 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
904 cfg = bgx_reg_read(bgx, lmacid,
905 BGX_SPUX_BR_PMD_CRTL);
906 cfg |= (1ull << 0);
907 bgx_reg_write(bgx, lmacid,
908 BGX_SPUX_BR_PMD_CRTL, cfg);
909 return -1;
910 }
911 }
912 return -1;
913 }
914
915 /* Wait for BGX RX to be idle */
916 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
917 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
918 return -1;
919 }
920
921 /* Wait for BGX TX to be idle */
922 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
923 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
924 return -1;
925 }
926
927 /* Check for MAC RX faults */
928 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
929 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
930 cfg &= SMU_RX_CTL_STATUS;
931 if (!cfg)
932 return 0;
933
934 /* Rx local/remote fault seen.
935 * Do lmac reinit to see if condition recovers
936 */
937 bgx_lmac_xaui_init(bgx, lmac);
938
939 return -1;
940 }
941
942 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
943 {
944 u64 pcs_link, an_result;
945 u8 speed;
946
947 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
948 BGX_GMP_PCS_MRX_STATUS);
949
950 /*Link state bit is sticky, read it again*/
951 if (!(pcs_link & PCS_MRX_STATUS_LINK))
952 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
953 BGX_GMP_PCS_MRX_STATUS);
954
955 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
956 PCS_MRX_STATUS_AN_CPT, false)) {
957 lmac->link_up = false;
958 lmac->last_speed = SPEED_UNKNOWN;
959 lmac->last_duplex = DUPLEX_UNKNOWN;
960 goto next_poll;
961 }
962
963 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
964 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
965 BGX_GMP_PCS_ANX_AN_RESULTS);
966
967 speed = (an_result >> 3) & 0x3;
968 lmac->last_duplex = (an_result >> 1) & 0x1;
969 switch (speed) {
970 case 0:
971 lmac->last_speed = SPEED_10;
972 break;
973 case 1:
974 lmac->last_speed = SPEED_100;
975 break;
976 case 2:
977 lmac->last_speed = SPEED_1000;
978 break;
979 default:
980 lmac->link_up = false;
981 lmac->last_speed = SPEED_UNKNOWN;
982 lmac->last_duplex = DUPLEX_UNKNOWN;
983 break;
984 }
985
986 next_poll:
987
988 if (lmac->last_link != lmac->link_up) {
989 if (lmac->link_up)
990 bgx_sgmii_change_link_state(lmac);
991 lmac->last_link = lmac->link_up;
992 }
993
994 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
995 }
996
997 static void bgx_poll_for_link(struct work_struct *work)
998 {
999 struct lmac *lmac;
1000 u64 spu_link, smu_link;
1001
1002 lmac = container_of(work, struct lmac, dwork.work);
1003 if (lmac->is_sgmii) {
1004 bgx_poll_for_sgmii_link(lmac);
1005 return;
1006 }
1007
1008 /* Receive link is latching low. Force it high and verify it */
1009 bgx_reg_modify(lmac->bgx, lmac->lmacid,
1010 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
1011 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
1012 SPU_STATUS1_RCV_LNK, false);
1013
1014 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
1015 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
1016
1017 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
1018 !(smu_link & SMU_RX_CTL_STATUS)) {
1019 lmac->link_up = true;
1020 if (lmac->lmac_type == BGX_MODE_XLAUI)
1021 lmac->last_speed = SPEED_40000;
1022 else
1023 lmac->last_speed = SPEED_10000;
1024 lmac->last_duplex = DUPLEX_FULL;
1025 } else {
1026 lmac->link_up = false;
1027 lmac->last_speed = SPEED_UNKNOWN;
1028 lmac->last_duplex = DUPLEX_UNKNOWN;
1029 }
1030
1031 if (lmac->last_link != lmac->link_up) {
1032 if (lmac->link_up) {
1033 if (bgx_xaui_check_link(lmac)) {
1034 /* Errors, clear link_up state */
1035 lmac->link_up = false;
1036 lmac->last_speed = SPEED_UNKNOWN;
1037 lmac->last_duplex = DUPLEX_UNKNOWN;
1038 }
1039 }
1040 lmac->last_link = lmac->link_up;
1041 }
1042
1043 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
1044 }
1045
1046 static int phy_interface_mode(u8 lmac_type)
1047 {
1048 if (lmac_type == BGX_MODE_QSGMII)
1049 return PHY_INTERFACE_MODE_QSGMII;
1050 if (lmac_type == BGX_MODE_RGMII)
1051 return PHY_INTERFACE_MODE_RGMII_RXID;
1052
1053 return PHY_INTERFACE_MODE_SGMII;
1054 }
1055
1056 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
1057 {
1058 struct lmac *lmac;
1059 u64 cfg;
1060
1061 lmac = &bgx->lmac[lmacid];
1062 lmac->bgx = bgx;
1063
1064 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
1065 (lmac->lmac_type == BGX_MODE_QSGMII) ||
1066 (lmac->lmac_type == BGX_MODE_RGMII)) {
1067 lmac->is_sgmii = true;
1068 if (bgx_lmac_sgmii_init(bgx, lmac))
1069 return -1;
1070 } else {
1071 lmac->is_sgmii = false;
1072 if (bgx_lmac_xaui_init(bgx, lmac))
1073 return -1;
1074 }
1075
1076 if (lmac->is_sgmii) {
1077 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
1078 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1079 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
1080 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
1081 } else {
1082 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
1083 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1084 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
1085 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
1086 }
1087
1088 /* actual number of filters available to exact LMAC */
1089 lmac->dmacs_count = (RX_DMAC_COUNT / bgx->lmac_count);
1090 lmac->dmacs = kcalloc(lmac->dmacs_count, sizeof(*lmac->dmacs),
1091 GFP_KERNEL);
1092 if (!lmac->dmacs)
1093 return -ENOMEM;
1094
1095 /* Enable lmac */
1096 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
1097
1098 /* Restore default cfg, incase low level firmware changed it */
1099 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
1100
1101 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1102 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1103 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1104 (lmac->lmac_type != BGX_MODE_10G_KR)) {
1105 if (!lmac->phydev) {
1106 if (lmac->autoneg) {
1107 bgx_reg_write(bgx, lmacid,
1108 BGX_GMP_PCS_LINKX_TIMER,
1109 PCS_LINKX_TIMER_COUNT);
1110 goto poll;
1111 } else {
1112 /* Default to below link speed and duplex */
1113 lmac->link_up = true;
1114 lmac->last_speed = SPEED_1000;
1115 lmac->last_duplex = DUPLEX_FULL;
1116 bgx_sgmii_change_link_state(lmac);
1117 return 0;
1118 }
1119 }
1120 lmac->phydev->dev_flags = 0;
1121
1122 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
1123 bgx_lmac_handler,
1124 phy_interface_mode(lmac->lmac_type)))
1125 return -ENODEV;
1126
1127 phy_start(lmac->phydev);
1128 return 0;
1129 }
1130
1131 poll:
1132 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
1133 WQ_MEM_RECLAIM, 1);
1134 if (!lmac->check_link)
1135 return -ENOMEM;
1136 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
1137 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
1138
1139 return 0;
1140 }
1141
1142 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
1143 {
1144 struct lmac *lmac;
1145 u64 cfg;
1146
1147 lmac = &bgx->lmac[lmacid];
1148 if (lmac->check_link) {
1149 /* Destroy work queue */
1150 cancel_delayed_work_sync(&lmac->dwork);
1151 destroy_workqueue(lmac->check_link);
1152 }
1153
1154 /* Disable packet reception */
1155 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1156 cfg &= ~CMR_PKT_RX_EN;
1157 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1158
1159 /* Give chance for Rx/Tx FIFO to get drained */
1160 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
1161 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
1162
1163 /* Disable packet transmission */
1164 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1165 cfg &= ~CMR_PKT_TX_EN;
1166 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1167
1168 /* Disable serdes lanes */
1169 if (!lmac->is_sgmii)
1170 bgx_reg_modify(bgx, lmacid,
1171 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
1172 else
1173 bgx_reg_modify(bgx, lmacid,
1174 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
1175
1176 /* Disable LMAC */
1177 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1178 cfg &= ~CMR_EN;
1179 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1180
1181 bgx_flush_dmac_cam_filter(bgx, lmacid);
1182 kfree(lmac->dmacs);
1183
1184 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1185 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1186 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1187 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
1188 phy_disconnect(lmac->phydev);
1189
1190 lmac->phydev = NULL;
1191 }
1192
1193 static void bgx_init_hw(struct bgx *bgx)
1194 {
1195 int i;
1196 struct lmac *lmac;
1197
1198 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
1199 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
1200 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
1201
1202 /* Set lmac type and lane2serdes mapping */
1203 for (i = 0; i < bgx->lmac_count; i++) {
1204 lmac = &bgx->lmac[i];
1205 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
1206 (lmac->lmac_type << 8) | lmac->lane_to_sds);
1207 bgx->lmac[i].lmacid_bd = lmac_count;
1208 lmac_count++;
1209 }
1210
1211 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1212 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1213
1214 /* Set the backpressure AND mask */
1215 for (i = 0; i < bgx->lmac_count; i++)
1216 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1217 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1218 (i * MAX_BGX_CHANS_PER_LMAC));
1219
1220 /* Disable all MAC filtering */
1221 for (i = 0; i < RX_DMAC_COUNT; i++)
1222 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1223
1224 /* Disable MAC steering (NCSI traffic) */
1225 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
1226 bgx_reg_write(bgx, 0, BGX_CMR_RX_STEERING + (i * 8), 0x00);
1227 }
1228
1229 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1230 {
1231 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1232 }
1233
1234 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
1235 {
1236 struct device *dev = &bgx->pdev->dev;
1237 struct lmac *lmac;
1238 char str[27];
1239
1240 if (!bgx->is_dlm && lmacid)
1241 return;
1242
1243 lmac = &bgx->lmac[lmacid];
1244 if (!bgx->is_dlm)
1245 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1246 else
1247 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
1248
1249 switch (lmac->lmac_type) {
1250 case BGX_MODE_SGMII:
1251 dev_info(dev, "%s: SGMII\n", (char *)str);
1252 break;
1253 case BGX_MODE_XAUI:
1254 dev_info(dev, "%s: XAUI\n", (char *)str);
1255 break;
1256 case BGX_MODE_RXAUI:
1257 dev_info(dev, "%s: RXAUI\n", (char *)str);
1258 break;
1259 case BGX_MODE_XFI:
1260 if (!lmac->use_training)
1261 dev_info(dev, "%s: XFI\n", (char *)str);
1262 else
1263 dev_info(dev, "%s: 10G_KR\n", (char *)str);
1264 break;
1265 case BGX_MODE_XLAUI:
1266 if (!lmac->use_training)
1267 dev_info(dev, "%s: XLAUI\n", (char *)str);
1268 else
1269 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
1270 break;
1271 case BGX_MODE_QSGMII:
1272 dev_info(dev, "%s: QSGMII\n", (char *)str);
1273 break;
1274 case BGX_MODE_RGMII:
1275 dev_info(dev, "%s: RGMII\n", (char *)str);
1276 break;
1277 case BGX_MODE_INVALID:
1278 /* Nothing to do */
1279 break;
1280 }
1281 }
1282
1283 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
1284 {
1285 switch (lmac->lmac_type) {
1286 case BGX_MODE_SGMII:
1287 case BGX_MODE_XFI:
1288 lmac->lane_to_sds = lmac->lmacid;
1289 break;
1290 case BGX_MODE_XAUI:
1291 case BGX_MODE_XLAUI:
1292 case BGX_MODE_RGMII:
1293 lmac->lane_to_sds = 0xE4;
1294 break;
1295 case BGX_MODE_RXAUI:
1296 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1297 break;
1298 case BGX_MODE_QSGMII:
1299 /* There is no way to determine if DLM0/2 is QSGMII or
1300 * DLM1/3 is configured to QSGMII as bootloader will
1301 * configure all LMACs, so take whatever is configured
1302 * by low level firmware.
1303 */
1304 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1305 break;
1306 default:
1307 lmac->lane_to_sds = 0;
1308 break;
1309 }
1310 }
1311
1312 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1313 {
1314 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1315 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1316 lmac->use_training = false;
1317 return;
1318 }
1319
1320 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1321 SPU_PMD_CRTL_TRAIN_EN;
1322 }
1323
1324 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1325 {
1326 struct lmac *lmac;
1327 u64 cmr_cfg;
1328 u8 lmac_type;
1329 u8 lane_to_sds;
1330
1331 lmac = &bgx->lmac[idx];
1332
1333 if (!bgx->is_dlm || bgx->is_rgx) {
1334 /* Read LMAC0 type to figure out QLM mode
1335 * This is configured by low level firmware
1336 */
1337 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1338 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1339 if (bgx->is_rgx)
1340 lmac->lmac_type = BGX_MODE_RGMII;
1341 lmac_set_training(bgx, lmac, 0);
1342 lmac_set_lane2sds(bgx, lmac);
1343 return;
1344 }
1345
1346 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1347 * are possible and vary across boards. Also Kernel doesn't have
1348 * any way to identify board type/info and since firmware does,
1349 * just take lmac type and serdes lane config as is.
1350 */
1351 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1352 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1353 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1354 /* Check if config is reset value */
1355 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1356 lmac->lmac_type = BGX_MODE_INVALID;
1357 else
1358 lmac->lmac_type = lmac_type;
1359 lmac->lane_to_sds = lane_to_sds;
1360 lmac_set_training(bgx, lmac, lmac->lmacid);
1361 }
1362
1363 static void bgx_get_qlm_mode(struct bgx *bgx)
1364 {
1365 struct lmac *lmac;
1366 u8 idx;
1367
1368 /* Init all LMAC's type to invalid */
1369 for (idx = 0; idx < bgx->max_lmac; idx++) {
1370 lmac = &bgx->lmac[idx];
1371 lmac->lmacid = idx;
1372 lmac->lmac_type = BGX_MODE_INVALID;
1373 lmac->use_training = false;
1374 }
1375
1376 /* It is assumed that low level firmware sets this value */
1377 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1378 if (bgx->lmac_count > bgx->max_lmac)
1379 bgx->lmac_count = bgx->max_lmac;
1380
1381 for (idx = 0; idx < bgx->lmac_count; idx++) {
1382 bgx_set_lmac_config(bgx, idx);
1383 bgx_print_qlm_mode(bgx, idx);
1384 }
1385 }
1386
1387 #ifdef CONFIG_ACPI
1388
1389 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1390 u8 *dst)
1391 {
1392 u8 mac[ETH_ALEN];
1393 u8 *addr;
1394
1395 addr = fwnode_get_mac_address(acpi_fwnode_handle(adev), mac, ETH_ALEN);
1396 if (!addr) {
1397 dev_err(dev, "MAC address invalid: %pM\n", mac);
1398 return -EINVAL;
1399 }
1400
1401 dev_info(dev, "MAC address set to: %pM\n", mac);
1402
1403 ether_addr_copy(dst, mac);
1404 return 0;
1405 }
1406
1407 /* Currently only sets the MAC address. */
1408 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1409 u32 lvl, void *context, void **rv)
1410 {
1411 struct bgx *bgx = context;
1412 struct device *dev = &bgx->pdev->dev;
1413 struct acpi_device *adev;
1414
1415 if (acpi_bus_get_device(handle, &adev))
1416 goto out;
1417
1418 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1419
1420 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1421
1422 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1423 bgx->acpi_lmac_idx++; /* move to next LMAC */
1424 out:
1425 return AE_OK;
1426 }
1427
1428 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1429 void *context, void **ret_val)
1430 {
1431 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1432 struct bgx *bgx = context;
1433 char bgx_sel[5];
1434
1435 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1436 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1437 pr_warn("Invalid link device\n");
1438 return AE_OK;
1439 }
1440
1441 if (strncmp(string.pointer, bgx_sel, 4))
1442 return AE_OK;
1443
1444 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1445 bgx_acpi_register_phy, NULL, bgx, NULL);
1446
1447 kfree(string.pointer);
1448 return AE_CTRL_TERMINATE;
1449 }
1450
1451 static int bgx_init_acpi_phy(struct bgx *bgx)
1452 {
1453 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1454 return 0;
1455 }
1456
1457 #else
1458
1459 static int bgx_init_acpi_phy(struct bgx *bgx)
1460 {
1461 return -ENODEV;
1462 }
1463
1464 #endif /* CONFIG_ACPI */
1465
1466 #if IS_ENABLED(CONFIG_OF_MDIO)
1467
1468 static int bgx_init_of_phy(struct bgx *bgx)
1469 {
1470 struct fwnode_handle *fwn;
1471 struct device_node *node = NULL;
1472 u8 lmac = 0;
1473
1474 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1475 struct phy_device *pd;
1476 struct device_node *phy_np;
1477 const char *mac;
1478
1479 /* Should always be an OF node. But if it is not, we
1480 * cannot handle it, so exit the loop.
1481 */
1482 node = to_of_node(fwn);
1483 if (!node)
1484 break;
1485
1486 mac = of_get_mac_address(node);
1487 if (!IS_ERR(mac))
1488 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1489
1490 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1491 bgx->lmac[lmac].lmacid = lmac;
1492
1493 phy_np = of_parse_phandle(node, "phy-handle", 0);
1494 /* If there is no phy or defective firmware presents
1495 * this cortina phy, for which there is no driver
1496 * support, ignore it.
1497 */
1498 if (phy_np &&
1499 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1500 /* Wait until the phy drivers are available */
1501 pd = of_phy_find_device(phy_np);
1502 if (!pd)
1503 goto defer;
1504 bgx->lmac[lmac].phydev = pd;
1505 }
1506
1507 lmac++;
1508 if (lmac == bgx->max_lmac) {
1509 of_node_put(node);
1510 break;
1511 }
1512 }
1513 return 0;
1514
1515 defer:
1516 /* We are bailing out, try not to leak device reference counts
1517 * for phy devices we may have already found.
1518 */
1519 while (lmac) {
1520 if (bgx->lmac[lmac].phydev) {
1521 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1522 bgx->lmac[lmac].phydev = NULL;
1523 }
1524 lmac--;
1525 }
1526 of_node_put(node);
1527 return -EPROBE_DEFER;
1528 }
1529
1530 #else
1531
1532 static int bgx_init_of_phy(struct bgx *bgx)
1533 {
1534 return -ENODEV;
1535 }
1536
1537 #endif /* CONFIG_OF_MDIO */
1538
1539 static int bgx_init_phy(struct bgx *bgx)
1540 {
1541 if (!acpi_disabled)
1542 return bgx_init_acpi_phy(bgx);
1543
1544 return bgx_init_of_phy(bgx);
1545 }
1546
1547 static irqreturn_t bgx_intr_handler(int irq, void *data)
1548 {
1549 struct bgx *bgx = (struct bgx *)data;
1550 u64 status, val;
1551 int lmac;
1552
1553 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1554 status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
1555 if (status & GMI_TXX_INT_UNDFLW) {
1556 pci_err(bgx->pdev, "BGX%d lmac%d UNDFLW\n",
1557 bgx->bgx_id, lmac);
1558 val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
1559 val &= ~CMR_EN;
1560 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1561 val |= CMR_EN;
1562 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1563 }
1564 /* clear interrupts */
1565 bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
1566 }
1567
1568 return IRQ_HANDLED;
1569 }
1570
1571 static void bgx_register_intr(struct pci_dev *pdev)
1572 {
1573 struct bgx *bgx = pci_get_drvdata(pdev);
1574 int ret;
1575
1576 ret = pci_alloc_irq_vectors(pdev, BGX_LMAC_VEC_OFFSET,
1577 BGX_LMAC_VEC_OFFSET, PCI_IRQ_ALL_TYPES);
1578 if (ret < 0) {
1579 pci_err(pdev, "Req for #%d msix vectors failed\n",
1580 BGX_LMAC_VEC_OFFSET);
1581 return;
1582 }
1583 ret = pci_request_irq(pdev, GMPX_GMI_TX_INT, bgx_intr_handler, NULL,
1584 bgx, "BGX%d", bgx->bgx_id);
1585 if (ret)
1586 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1587 }
1588
1589 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1590 {
1591 int err;
1592 struct device *dev = &pdev->dev;
1593 struct bgx *bgx = NULL;
1594 u8 lmac;
1595 u16 sdevid;
1596
1597 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1598 if (!bgx)
1599 return -ENOMEM;
1600 bgx->pdev = pdev;
1601
1602 pci_set_drvdata(pdev, bgx);
1603
1604 err = pcim_enable_device(pdev);
1605 if (err) {
1606 dev_err(dev, "Failed to enable PCI device\n");
1607 pci_set_drvdata(pdev, NULL);
1608 return err;
1609 }
1610
1611 err = pci_request_regions(pdev, DRV_NAME);
1612 if (err) {
1613 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1614 goto err_disable_device;
1615 }
1616
1617 /* MAP configuration registers */
1618 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1619 if (!bgx->reg_base) {
1620 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1621 err = -ENOMEM;
1622 goto err_release_regions;
1623 }
1624
1625 set_max_bgx_per_node(pdev);
1626
1627 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1628 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1629 bgx->bgx_id = (pci_resource_start(pdev,
1630 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1631 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
1632 bgx->max_lmac = MAX_LMAC_PER_BGX;
1633 bgx_vnic[bgx->bgx_id] = bgx;
1634 } else {
1635 bgx->is_rgx = true;
1636 bgx->max_lmac = 1;
1637 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1638 bgx_vnic[bgx->bgx_id] = bgx;
1639 xcv_init_hw();
1640 }
1641
1642 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1643 * BGX i.e BGX2 can be split across 2 DLMs.
1644 */
1645 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1646 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1647 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1648 bgx->is_dlm = true;
1649
1650 bgx_get_qlm_mode(bgx);
1651
1652 err = bgx_init_phy(bgx);
1653 if (err)
1654 goto err_enable;
1655
1656 bgx_init_hw(bgx);
1657
1658 bgx_register_intr(pdev);
1659
1660 /* Enable all LMACs */
1661 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1662 err = bgx_lmac_enable(bgx, lmac);
1663 if (err) {
1664 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1665 bgx->bgx_id, lmac);
1666 while (lmac)
1667 bgx_lmac_disable(bgx, --lmac);
1668 goto err_enable;
1669 }
1670 }
1671
1672 return 0;
1673
1674 err_enable:
1675 bgx_vnic[bgx->bgx_id] = NULL;
1676 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1677 err_release_regions:
1678 pci_release_regions(pdev);
1679 err_disable_device:
1680 pci_disable_device(pdev);
1681 pci_set_drvdata(pdev, NULL);
1682 return err;
1683 }
1684
1685 static void bgx_remove(struct pci_dev *pdev)
1686 {
1687 struct bgx *bgx = pci_get_drvdata(pdev);
1688 u8 lmac;
1689
1690 /* Disable all LMACs */
1691 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1692 bgx_lmac_disable(bgx, lmac);
1693
1694 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1695
1696 bgx_vnic[bgx->bgx_id] = NULL;
1697 pci_release_regions(pdev);
1698 pci_disable_device(pdev);
1699 pci_set_drvdata(pdev, NULL);
1700 }
1701
1702 static struct pci_driver bgx_driver = {
1703 .name = DRV_NAME,
1704 .id_table = bgx_id_table,
1705 .probe = bgx_probe,
1706 .remove = bgx_remove,
1707 };
1708
1709 static int __init bgx_init_module(void)
1710 {
1711 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1712
1713 return pci_register_driver(&bgx_driver);
1714 }
1715
1716 static void __exit bgx_cleanup_module(void)
1717 {
1718 pci_unregister_driver(&bgx_driver);
1719 }
1720
1721 module_init(bgx_init_module);
1722 module_exit(bgx_cleanup_module);
Linux with added FPC-III support