drivers/net/ethernet/chelsio/cxgb/cphy.h

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: cphy.h                                                              *
   4  * $Revision: 1.7 $                                                          *
   5  * $Date: 2005/06/21 18:29:47 $                                              *
   6  * Description:                                                              *
   7  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   8  *                                                                           *
   9  * This program is free software; you can redistribute it and/or modify      *
  10  * it under the terms of the GNU General Public License, version 2, as       *
  11  * published by the Free Software Foundation.                                *
  12  *                                                                           *
  13  * You should have received a copy of the GNU General Public License along   *
  14  * with this program; if not, see <http://www.gnu.org/licenses/>.            *
  15  *                                                                           *
  16  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  17  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  19  *                                                                           *
  20  * http://www.chelsio.com                                                    *
  21  *                                                                           *
  22  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  23  * All rights reserved.                                                      *
  24  *                                                                           *
  25  * Maintainers: maintainers@chelsio.com                                      *
  26  *                                                                           *
  27  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  28  *          Tina Yang               <tainay@chelsio.com>                     *
  29  *          Felix Marti             <felix@chelsio.com>                      *
  30  *          Scott Bardone           <sbardone@chelsio.com>                   *
  31  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  32  *          Frank DiMambro          <frank@chelsio.com>                      *
  33  *                                                                           *
  34  * History:                                                                  *
  35  *                                                                           *
  36  ****************************************************************************/
  37
  38 #ifndef _CXGB_CPHY_H_
  39 #define _CXGB_CPHY_H_
  40
  41 #include "common.h"
  42
  43 struct mdio_ops {
  44         void (*init)(adapter_t *adapter, const struct board_info *bi);
  45         int  (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
  46                      u16 reg_addr);
  47         int  (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
  48                       u16 reg_addr, u16 val);
  49         unsigned mode_support;
  50 };
  51
  52 /* PHY interrupt types */
  53 enum {
  54         cphy_cause_link_change = 0x1,
  55         cphy_cause_error = 0x2,
  56         cphy_cause_fifo_error = 0x3
  57 };
  58
  59 enum {
  60         PHY_LINK_UP = 0x1,
  61         PHY_AUTONEG_RDY = 0x2,
  62         PHY_AUTONEG_EN = 0x4
  63 };
  64
  65 struct cphy;
  66
  67 /* PHY operations */
  68 struct cphy_ops {
  69         void (*destroy)(struct cphy *);
  70         int (*reset)(struct cphy *, int wait);
  71
  72         int (*interrupt_enable)(struct cphy *);
  73         int (*interrupt_disable)(struct cphy *);
  74         int (*interrupt_clear)(struct cphy *);
  75         int (*interrupt_handler)(struct cphy *);
  76
  77         int (*autoneg_enable)(struct cphy *);
  78         int (*autoneg_disable)(struct cphy *);
  79         int (*autoneg_restart)(struct cphy *);
  80
  81         int (*advertise)(struct cphy *phy, unsigned int advertise_map);
  82         int (*set_loopback)(struct cphy *, int on);
  83         int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
  84         int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
  85                                int *duplex, int *fc);
  86
  87         u32 mmds;
  88 };
  89
  90 /* A PHY instance */
  91 struct cphy {
  92         int state;      /* Link status state machine */
  93         adapter_t *adapter;                  /* associated adapter */
  94
  95         struct delayed_work phy_update;
  96
  97         u16 bmsr;
  98         int count;
  99         int act_count;
 100         int act_on;
 101
 102         u32 elmer_gpo;
 103
 104         const struct cphy_ops *ops;            /* PHY operations */
 105         struct mdio_if_info mdio;
 106         struct cphy_instance *instance;
 107 };
 108
 109 /* Convenience MDIO read/write wrappers */
 110 static inline int cphy_mdio_read(struct cphy *cphy, int mmd, int reg,
 111                                  unsigned int *valp)
 112 {
 113         int rc = cphy->mdio.mdio_read(cphy->mdio.dev, cphy->mdio.prtad, mmd,
 114                                       reg);
 115         *valp = (rc >= 0) ? rc : -1;
 116         return (rc >= 0) ? 0 : rc;
 117 }
 118
 119 static inline int cphy_mdio_write(struct cphy *cphy, int mmd, int reg,
 120                                   unsigned int val)
 121 {
 122         return cphy->mdio.mdio_write(cphy->mdio.dev, cphy->mdio.prtad, mmd,
 123                                      reg, val);
 124 }
 125
 126 static inline int simple_mdio_read(struct cphy *cphy, int reg,
 127                                    unsigned int *valp)
 128 {
 129         return cphy_mdio_read(cphy, MDIO_DEVAD_NONE, reg, valp);
 130 }
 131
 132 static inline int simple_mdio_write(struct cphy *cphy, int reg,
 133                                     unsigned int val)
 134 {
 135         return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val);
 136 }
 137
 138 /* Convenience initializer */
 139 static inline void cphy_init(struct cphy *phy, struct net_device *dev,
 140                              int phy_addr, const struct cphy_ops *phy_ops,
 141                              const struct mdio_ops *mdio_ops)
 142 {
 143         struct adapter *adapter = netdev_priv(dev);
 144         phy->adapter = adapter;
 145         phy->ops     = phy_ops;
 146         if (mdio_ops) {
 147                 phy->mdio.prtad = phy_addr;
 148                 phy->mdio.mmds = phy_ops->mmds;
 149                 phy->mdio.mode_support = mdio_ops->mode_support;
 150                 phy->mdio.mdio_read = mdio_ops->read;
 151                 phy->mdio.mdio_write = mdio_ops->write;
 152         }
 153         phy->mdio.dev = dev;
 154 }
 155
 156 /* Operations of the PHY-instance factory */
 157 struct gphy {
 158         /* Construct a PHY instance with the given PHY address */
 159         struct cphy *(*create)(struct net_device *dev, int phy_addr,
 160                                const struct mdio_ops *mdio_ops);
 161
 162         /*
 163          * Reset the PHY chip.  This resets the whole PHY chip, not individual
 164          * ports.
 165          */
 166         int (*reset)(adapter_t *adapter);
 167 };
 168
 169 extern const struct gphy t1_my3126_ops;
 170 extern const struct gphy t1_mv88e1xxx_ops;
 171 extern const struct gphy t1_vsc8244_ops;
 172 extern const struct gphy t1_mv88x201x_ops;
 173
 174 #endif /* _CXGB_CPHY_H_ */