2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter
*adapter
, int reg
, u32 mask
,
58 int polarity
, int attempts
, int delay
, u32
*valp
)
61 u32 val
= t4_read_reg(adapter
, reg
);
63 if (!!(val
& mask
) == polarity
) {
75 static inline int t4_wait_op_done(struct adapter
*adapter
, int reg
, u32 mask
,
76 int polarity
, int attempts
, int delay
)
78 return t4_wait_op_done_val(adapter
, reg
, mask
, polarity
, attempts
,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter
*adapter
, unsigned int addr
, u32 mask
,
95 u32 v
= t4_read_reg(adapter
, addr
) & ~mask
;
97 t4_write_reg(adapter
, addr
, v
| val
);
98 (void) t4_read_reg(adapter
, addr
); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
114 unsigned int data_reg
, u32
*vals
,
115 unsigned int nregs
, unsigned int start_idx
)
118 t4_write_reg(adap
, addr_reg
, start_idx
);
119 *vals
++ = t4_read_reg(adap
, data_reg
);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
137 unsigned int data_reg
, const u32
*vals
,
138 unsigned int nregs
, unsigned int start_idx
)
141 t4_write_reg(adap
, addr_reg
, start_idx
++);
142 t4_write_reg(adap
, data_reg
, *vals
++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter
*adap
, int reg
, u32
*val
)
154 u32 req
= FUNCTION_V(adap
->pf
) | REGISTER_V(reg
);
156 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
161 if (is_t4(adap
->params
.chip
))
164 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, req
);
165 *val
= t4_read_reg(adap
, PCIE_CFG_SPACE_DATA_A
);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter
*adap
)
185 static const char *const reason
[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
198 if (pcie_fw
& PCIE_FW_ERR_F
) {
199 dev_err(adap
->pdev_dev
, "Firmware reports adapter error: %s\n",
200 reason
[PCIE_FW_EVAL_G(pcie_fw
)]);
201 adap
->flags
&= ~CXGB4_FW_OK
;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter
*adap
, __be64
*rpl
, int nflit
,
211 for ( ; nflit
; nflit
--, mbox_addr
+= 8)
212 *rpl
++ = cpu_to_be64(t4_read_reg64(adap
, mbox_addr
));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter
*adap
, u32 mbox_addr
)
220 struct fw_debug_cmd asrt
;
222 get_mbox_rpl(adap
, (__be64
*)&asrt
, sizeof(asrt
) / 8, mbox_addr
);
223 dev_alert(adap
->pdev_dev
,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt
.u
.assert.filename_0_7
, be32_to_cpu(asrt
.u
.assert.line
),
226 be32_to_cpu(asrt
.u
.assert.x
), be32_to_cpu(asrt
.u
.assert.y
));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter
*adapter
,
238 const __be64
*cmd
, unsigned int size
,
239 int access
, int execute
)
241 struct mbox_cmd_log
*log
= adapter
->mbox_log
;
242 struct mbox_cmd
*entry
;
245 entry
= mbox_cmd_log_entry(log
, log
->cursor
++);
246 if (log
->cursor
== log
->size
)
249 for (i
= 0; i
< size
/ 8; i
++)
250 entry
->cmd
[i
] = be64_to_cpu(cmd
[i
]);
251 while (i
< MBOX_LEN
/ 8)
253 entry
->timestamp
= jiffies
;
254 entry
->seqno
= log
->seqno
++;
255 entry
->access
= access
;
256 entry
->execute
= execute
;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter
*adap
, int mbox
, const void *cmd
,
283 int size
, void *rpl
, bool sleep_ok
, int timeout
)
285 static const int delay
[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry
;
294 int i
, ms
, delay_idx
, ret
;
295 const __be64
*p
= cmd
;
296 u32 data_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
297 u32 ctl_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_CTRL_A
);
298 __be64 cmd_rpl
[MBOX_LEN
/ 8];
301 if ((size
& 15) || size
> MBOX_LEN
)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap
->pdev
->error_state
!= pci_channel_io_normal
)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap
->mbox_lock
);
323 list_add_tail(&entry
.list
, &adap
->mlist
.list
);
324 spin_unlock_bh(&adap
->mbox_lock
);
329 for (i
= 0; ; i
+= ms
) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
335 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
336 if (i
> FW_CMD_MAX_TIMEOUT
|| (pcie_fw
& PCIE_FW_ERR_F
)) {
337 spin_lock_bh(&adap
->mbox_lock
);
338 list_del(&entry
.list
);
339 spin_unlock_bh(&adap
->mbox_lock
);
340 ret
= (pcie_fw
& PCIE_FW_ERR_F
) ? -ENXIO
: -EBUSY
;
341 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap
->mlist
.list
, struct mbox_list
,
352 /* Delay for a bit before checking again ... */
354 ms
= delay
[delay_idx
]; /* last element may repeat */
355 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
367 for (i
= 0; v
== MBOX_OWNER_NONE
&& i
< 3; i
++)
368 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
369 if (v
!= MBOX_OWNER_DRV
) {
370 spin_lock_bh(&adap
->mbox_lock
);
371 list_del(&entry
.list
);
372 spin_unlock_bh(&adap
->mbox_lock
);
373 ret
= (v
== MBOX_OWNER_FW
) ? -EBUSY
: -ETIMEDOUT
;
374 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap
, cmd
, size
, access
, 0);
380 for (i
= 0; i
< size
; i
+= 8)
381 t4_write_reg64(adap
, data_reg
+ i
, be64_to_cpu(*p
++));
383 t4_write_reg(adap
, ctl_reg
, MBMSGVALID_F
| MBOWNER_V(MBOX_OWNER_FW
));
384 t4_read_reg(adap
, ctl_reg
); /* flush write */
390 !((pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
)) & PCIE_FW_ERR_F
) &&
394 ms
= delay
[delay_idx
]; /* last element may repeat */
395 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
401 v
= t4_read_reg(adap
, ctl_reg
);
402 if (MBOWNER_G(v
) == MBOX_OWNER_DRV
) {
403 if (!(v
& MBMSGVALID_F
)) {
404 t4_write_reg(adap
, ctl_reg
, 0);
408 get_mbox_rpl(adap
, cmd_rpl
, MBOX_LEN
/ 8, data_reg
);
409 res
= be64_to_cpu(cmd_rpl
[0]);
411 if (FW_CMD_OP_G(res
>> 32) == FW_DEBUG_CMD
) {
412 fw_asrt(adap
, data_reg
);
413 res
= FW_CMD_RETVAL_V(EIO
);
415 memcpy(rpl
, cmd_rpl
, size
);
418 t4_write_reg(adap
, ctl_reg
, 0);
421 t4_record_mbox(adap
, cmd_rpl
,
422 MBOX_LEN
, access
, execute
);
423 spin_lock_bh(&adap
->mbox_lock
);
424 list_del(&entry
.list
);
425 spin_unlock_bh(&adap
->mbox_lock
);
426 return -FW_CMD_RETVAL_G((int)res
);
430 ret
= (pcie_fw
& PCIE_FW_ERR_F
) ? -ENXIO
: -ETIMEDOUT
;
431 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
432 dev_err(adap
->pdev_dev
, "command %#x in mailbox %d timed out\n",
433 *(const u8
*)cmd
, mbox
);
434 t4_report_fw_error(adap
);
435 spin_lock_bh(&adap
->mbox_lock
);
436 list_del(&entry
.list
);
437 spin_unlock_bh(&adap
->mbox_lock
);
442 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
443 void *rpl
, bool sleep_ok
)
445 return t4_wr_mbox_meat_timeout(adap
, mbox
, cmd
, size
, rpl
, sleep_ok
,
449 static int t4_edc_err_read(struct adapter
*adap
, int idx
)
451 u32 edc_ecc_err_addr_reg
;
454 if (is_t4(adap
->params
.chip
)) {
455 CH_WARN(adap
, "%s: T4 NOT supported.\n", __func__
);
458 if (idx
!= 0 && idx
!= 1) {
459 CH_WARN(adap
, "%s: idx %d NOT supported.\n", __func__
, idx
);
463 edc_ecc_err_addr_reg
= EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A
, idx
);
464 rdata_reg
= EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A
, idx
);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx
, edc_ecc_err_addr_reg
,
469 t4_read_reg(adap
, edc_ecc_err_addr_reg
));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap
, rdata_reg
),
474 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 8),
475 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 16),
476 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 24),
477 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 32),
478 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 40),
479 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 48),
480 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 56),
481 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter
*adap
, int win
, int mtype
, u32
*mem_off
,
498 u32
*mem_base
, u32
*mem_aperture
)
500 u32 edc_size
, mc_size
, mem_reg
;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size
= EDRAM0_SIZE_G(t4_read_reg(adap
, MA_EDRAM0_BAR_A
));
510 if (mtype
== MEM_HMA
) {
511 *mem_off
= 2 * (edc_size
* 1024 * 1024);
512 } else if (mtype
!= MEM_MC1
) {
513 *mem_off
= (mtype
* (edc_size
* 1024 * 1024));
515 mc_size
= EXT_MEM0_SIZE_G(t4_read_reg(adap
,
516 MA_EXT_MEMORY0_BAR_A
));
517 *mem_off
= (MEM_MC0
* edc_size
+ mc_size
) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg
= t4_read_reg(adap
,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg
== 0xffffffff)
535 *mem_aperture
= 1 << (WINDOW_G(mem_reg
) + WINDOW_SHIFT_X
);
536 *mem_base
= PCIEOFST_G(mem_reg
) << PCIEOFST_SHIFT_X
;
537 if (is_t4(adap
->params
.chip
))
538 *mem_base
-= adap
->t4_bar0
;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter
*adap
, int win
, u32 addr
)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter
*adap
, u32 off
, u32 addr
, u8
*buf
,
583 if (dir
== T4_MEMORY_READ
) {
584 last
.word
= le32_to_cpu((__force __le32
)
585 t4_read_reg(adap
, addr
));
586 for (bp
= (unsigned char *)buf
, i
= off
; i
< 4; i
++)
587 bp
[i
] = last
.byte
[i
];
590 for (i
= off
; i
< 4; i
++)
592 t4_write_reg(adap
, addr
,
593 (__force u32
)cpu_to_le32(last
.word
));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
,
615 u32 len
, void *hbuf
, int dir
)
617 u32 pos
, offset
, resid
, memoffset
;
618 u32 win_pf
, mem_aperture
, mem_base
;
622 /* Argument sanity checks ...
624 if (addr
& 0x3 || (uintptr_t)hbuf
& 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret
= t4_memory_rw_init(adap
, win
, mtype
, &memoffset
, &mem_base
,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr
= addr
+ memoffset
;
644 win_pf
= is_t4(adap
->params
.chip
) ? 0 : PFNUM_V(adap
->pf
);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos
= addr
& ~(mem_aperture
- 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap
, win
, pos
| win_pf
);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir
== T4_MEMORY_READ
)
693 *buf
++ = le32_to_cpu((__force __le32
)t4_read_reg(adap
,
696 t4_write_reg(adap
, mem_base
+ offset
,
697 (__force u32
)cpu_to_le32(*buf
++));
698 offset
+= sizeof(__be32
);
699 len
-= sizeof(__be32
);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset
== mem_aperture
) {
710 t4_memory_update_win(adap
, win
, pos
| win_pf
);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap
, resid
, mem_base
+ offset
,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
)
733 u32 val
, ldst_addrspace
;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd
;
741 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
742 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE
);
743 ldst_cmd
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
747 ldst_cmd
.cycles_to_len16
= cpu_to_be32(FW_LEN16(ldst_cmd
));
748 ldst_cmd
.u
.pcie
.select_naccess
= FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd
.u
.pcie
.ctrl_to_fn
=
750 (FW_LDST_CMD_LC_F
| FW_LDST_CMD_FN_V(adap
->pf
));
751 ldst_cmd
.u
.pcie
.r
= reg
;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret
= t4_wr_mbox(adap
, adap
->mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
759 val
= be32_to_cpu(ldst_cmd
.u
.pcie
.data
[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap
, reg
, &val
);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32
t4_get_window(struct adapter
*adap
, u32 pci_base
, u64 pci_mask
,
777 if (is_t4(adap
->params
.chip
)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0
= t4_read_pcie_cfg4(adap
, pci_base
);
791 adap
->t4_bar0
= bar0
;
793 ret
= bar0
+ memwin_base
;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32
t4_get_util_window(struct adapter
*adap
)
804 return t4_get_window(adap
, PCI_BASE_ADDRESS_0
,
805 PCI_BASE_ADDRESS_MEM_MASK
, MEMWIN0_BASE
);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter
*adap
, u32 memwin_base
, u32 window
)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
, window
),
816 memwin_base
| BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE
) - WINDOW_SHIFT_X
));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
, window
));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter
*adapter
)
830 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
832 switch (chip_version
) {
834 return T4_REGMAP_SIZE
;
838 return T5_REGMAP_SIZE
;
841 dev_err(adapter
->pdev_dev
,
842 "Unsupported chip version %d\n", chip_version
);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
)
858 static const unsigned int t4_reg_ranges
[] = {
1317 static const unsigned int t5_reg_ranges
[] = {
2081 static const unsigned int t6_reg_ranges
[] = {
2639 u32
*buf_end
= (u32
*)((char *)buf
+ buf_size
);
2640 const unsigned int *reg_ranges
;
2641 int reg_ranges_size
, range
;
2642 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
2644 /* Select the right set of register ranges to dump depending on the
2645 * adapter chip type.
2647 switch (chip_version
) {
2649 reg_ranges
= t4_reg_ranges
;
2650 reg_ranges_size
= ARRAY_SIZE(t4_reg_ranges
);
2654 reg_ranges
= t5_reg_ranges
;
2655 reg_ranges_size
= ARRAY_SIZE(t5_reg_ranges
);
2659 reg_ranges
= t6_reg_ranges
;
2660 reg_ranges_size
= ARRAY_SIZE(t6_reg_ranges
);
2664 dev_err(adap
->pdev_dev
,
2665 "Unsupported chip version %d\n", chip_version
);
2669 /* Clear the register buffer and insert the appropriate register
2670 * values selected by the above register ranges.
2672 memset(buf
, 0, buf_size
);
2673 for (range
= 0; range
< reg_ranges_size
; range
+= 2) {
2674 unsigned int reg
= reg_ranges
[range
];
2675 unsigned int last_reg
= reg_ranges
[range
+ 1];
2676 u32
*bufp
= (u32
*)((char *)buf
+ reg
);
2678 /* Iterate across the register range filling in the register
2679 * buffer but don't write past the end of the register buffer.
2681 while (reg
<= last_reg
&& bufp
< buf_end
) {
2682 *bufp
++ = t4_read_reg(adap
, reg
);
2688 #define EEPROM_STAT_ADDR 0x7bfc
2689 #define VPD_BASE 0x400
2690 #define VPD_BASE_OLD 0
2691 #define VPD_LEN 1024
2692 #define CHELSIO_VPD_UNIQUE_ID 0x82
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696 * @phys_addr: the physical EEPROM address
2697 * @fn: the PCI function number
2698 * @sz: size of function-specific area
2700 * Translate a physical EEPROM address to virtual. The first 1K is
2701 * accessed through virtual addresses starting at 31K, the rest is
2702 * accessed through virtual addresses starting at 0.
2704 * The mapping is as follows:
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2709 * where A = @fn * @sz, and ES = EEPROM size.
2711 int t4_eeprom_ptov(unsigned int phys_addr
, unsigned int fn
, unsigned int sz
)
2714 if (phys_addr
< 1024)
2715 return phys_addr
+ (31 << 10);
2716 if (phys_addr
< 1024 + fn
)
2717 return 31744 - fn
+ phys_addr
- 1024;
2718 if (phys_addr
< EEPROMSIZE
)
2719 return phys_addr
- 1024 - fn
;
2724 * t4_seeprom_wp - enable/disable EEPROM write protection
2725 * @adapter: the adapter
2726 * @enable: whether to enable or disable write protection
2728 * Enables or disables write protection on the serial EEPROM.
2730 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
)
2732 unsigned int v
= enable
? 0xc : 0;
2733 int ret
= pci_write_vpd(adapter
->pdev
, EEPROM_STAT_ADDR
, 4, &v
);
2734 return ret
< 0 ? ret
: 0;
2738 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739 * @adapter: adapter to read
2740 * @p: where to store the parameters
2742 * Reads card parameters stored in VPD EEPROM.
2744 int t4_get_raw_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
2746 int i
, ret
= 0, addr
;
2749 unsigned int vpdr_len
, kw_offset
, id_len
;
2751 vpd
= vmalloc(VPD_LEN
);
2755 /* Card information normally starts at VPD_BASE but early cards had
2758 ret
= pci_read_vpd(adapter
->pdev
, VPD_BASE
, sizeof(u32
), vpd
);
2762 /* The VPD shall have a unique identifier specified by the PCI SIG.
2763 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2764 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2765 * is expected to automatically put this entry at the
2766 * beginning of the VPD.
2768 addr
= *vpd
== CHELSIO_VPD_UNIQUE_ID
? VPD_BASE
: VPD_BASE_OLD
;
2770 ret
= pci_read_vpd(adapter
->pdev
, addr
, VPD_LEN
, vpd
);
2774 if (vpd
[0] != PCI_VPD_LRDT_ID_STRING
) {
2775 dev_err(adapter
->pdev_dev
, "missing VPD ID string\n");
2780 id_len
= pci_vpd_lrdt_size(vpd
);
2781 if (id_len
> ID_LEN
)
2784 i
= pci_vpd_find_tag(vpd
, 0, VPD_LEN
, PCI_VPD_LRDT_RO_DATA
);
2786 dev_err(adapter
->pdev_dev
, "missing VPD-R section\n");
2791 vpdr_len
= pci_vpd_lrdt_size(&vpd
[i
]);
2792 kw_offset
= i
+ PCI_VPD_LRDT_TAG_SIZE
;
2793 if (vpdr_len
+ kw_offset
> VPD_LEN
) {
2794 dev_err(adapter
->pdev_dev
, "bad VPD-R length %u\n", vpdr_len
);
2799 #define FIND_VPD_KW(var, name) do { \
2800 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2802 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2806 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2809 FIND_VPD_KW(i
, "RV");
2810 for (csum
= 0; i
>= 0; i
--)
2814 dev_err(adapter
->pdev_dev
,
2815 "corrupted VPD EEPROM, actual csum %u\n", csum
);
2820 FIND_VPD_KW(ec
, "EC");
2821 FIND_VPD_KW(sn
, "SN");
2822 FIND_VPD_KW(pn
, "PN");
2823 FIND_VPD_KW(na
, "NA");
2826 memcpy(p
->id
, vpd
+ PCI_VPD_LRDT_TAG_SIZE
, id_len
);
2828 memcpy(p
->ec
, vpd
+ ec
, EC_LEN
);
2830 i
= pci_vpd_info_field_size(vpd
+ sn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
2831 memcpy(p
->sn
, vpd
+ sn
, min(i
, SERNUM_LEN
));
2833 i
= pci_vpd_info_field_size(vpd
+ pn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
2834 memcpy(p
->pn
, vpd
+ pn
, min(i
, PN_LEN
));
2836 memcpy(p
->na
, vpd
+ na
, min(i
, MACADDR_LEN
));
2837 strim((char *)p
->na
);
2841 return ret
< 0 ? ret
: 0;
2845 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2846 * @adapter: adapter to read
2847 * @p: where to store the parameters
2849 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2850 * Clock. This can only be called after a connection to the firmware
2853 int t4_get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
2855 u32 cclk_param
, cclk_val
;
2858 /* Grab the raw VPD parameters.
2860 ret
= t4_get_raw_vpd_params(adapter
, p
);
2864 /* Ask firmware for the Core Clock since it knows how to translate the
2865 * Reference Clock ('V2') VPD field into a Core Clock value ...
2867 cclk_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
2868 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK
));
2869 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
2870 1, &cclk_param
, &cclk_val
);
2880 * t4_get_pfres - retrieve VF resource limits
2881 * @adapter: the adapter
2883 * Retrieves configured resource limits and capabilities for a physical
2884 * function. The results are stored in @adapter->pfres.
2886 int t4_get_pfres(struct adapter
*adapter
)
2888 struct pf_resources
*pfres
= &adapter
->params
.pfres
;
2889 struct fw_pfvf_cmd cmd
, rpl
;
2893 /* Execute PFVF Read command to get VF resource limits; bail out early
2894 * with error on command failure.
2896 memset(&cmd
, 0, sizeof(cmd
));
2897 cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD
) |
2900 FW_PFVF_CMD_PFN_V(adapter
->pf
) |
2901 FW_PFVF_CMD_VFN_V(0));
2902 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
2903 v
= t4_wr_mbox(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
), &rpl
);
2904 if (v
!= FW_SUCCESS
)
2907 /* Extract PF resource limits and return success.
2909 word
= be32_to_cpu(rpl
.niqflint_niq
);
2910 pfres
->niqflint
= FW_PFVF_CMD_NIQFLINT_G(word
);
2911 pfres
->niq
= FW_PFVF_CMD_NIQ_G(word
);
2913 word
= be32_to_cpu(rpl
.type_to_neq
);
2914 pfres
->neq
= FW_PFVF_CMD_NEQ_G(word
);
2915 pfres
->pmask
= FW_PFVF_CMD_PMASK_G(word
);
2917 word
= be32_to_cpu(rpl
.tc_to_nexactf
);
2918 pfres
->tc
= FW_PFVF_CMD_TC_G(word
);
2919 pfres
->nvi
= FW_PFVF_CMD_NVI_G(word
);
2920 pfres
->nexactf
= FW_PFVF_CMD_NEXACTF_G(word
);
2922 word
= be32_to_cpu(rpl
.r_caps_to_nethctrl
);
2923 pfres
->r_caps
= FW_PFVF_CMD_R_CAPS_G(word
);
2924 pfres
->wx_caps
= FW_PFVF_CMD_WX_CAPS_G(word
);
2925 pfres
->nethctrl
= FW_PFVF_CMD_NETHCTRL_G(word
);
2930 /* serial flash and firmware constants */
2932 SF_ATTEMPTS
= 10, /* max retries for SF operations */
2934 /* flash command opcodes */
2935 SF_PROG_PAGE
= 2, /* program page */
2936 SF_WR_DISABLE
= 4, /* disable writes */
2937 SF_RD_STATUS
= 5, /* read status register */
2938 SF_WR_ENABLE
= 6, /* enable writes */
2939 SF_RD_DATA_FAST
= 0xb, /* read flash */
2940 SF_RD_ID
= 0x9f, /* read ID */
2941 SF_ERASE_SECTOR
= 0xd8, /* erase sector */
2945 * sf1_read - read data from the serial flash
2946 * @adapter: the adapter
2947 * @byte_cnt: number of bytes to read
2948 * @cont: whether another operation will be chained
2949 * @lock: whether to lock SF for PL access only
2950 * @valp: where to store the read data
2952 * Reads up to 4 bytes of data from the serial flash. The location of
2953 * the read needs to be specified prior to calling this by issuing the
2954 * appropriate commands to the serial flash.
2956 static int sf1_read(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
2957 int lock
, u32
*valp
)
2961 if (!byte_cnt
|| byte_cnt
> 4)
2963 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
2965 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
2966 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1));
2967 ret
= t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
2969 *valp
= t4_read_reg(adapter
, SF_DATA_A
);
2974 * sf1_write - write data to the serial flash
2975 * @adapter: the adapter
2976 * @byte_cnt: number of bytes to write
2977 * @cont: whether another operation will be chained
2978 * @lock: whether to lock SF for PL access only
2979 * @val: value to write
2981 * Writes up to 4 bytes of data to the serial flash. The location of
2982 * the write needs to be specified prior to calling this by issuing the
2983 * appropriate commands to the serial flash.
2985 static int sf1_write(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
2988 if (!byte_cnt
|| byte_cnt
> 4)
2990 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
2992 t4_write_reg(adapter
, SF_DATA_A
, val
);
2993 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
2994 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1) | OP_V(1));
2995 return t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
2999 * flash_wait_op - wait for a flash operation to complete
3000 * @adapter: the adapter
3001 * @attempts: max number of polls of the status register
3002 * @delay: delay between polls in ms
3004 * Wait for a flash operation to complete by polling the status register.
3006 static int flash_wait_op(struct adapter
*adapter
, int attempts
, int delay
)
3012 if ((ret
= sf1_write(adapter
, 1, 1, 1, SF_RD_STATUS
)) != 0 ||
3013 (ret
= sf1_read(adapter
, 1, 0, 1, &status
)) != 0)
3017 if (--attempts
== 0)
3025 * t4_read_flash - read words from serial flash
3026 * @adapter: the adapter
3027 * @addr: the start address for the read
3028 * @nwords: how many 32-bit words to read
3029 * @data: where to store the read data
3030 * @byte_oriented: whether to store data as bytes or as words
3032 * Read the specified number of 32-bit words from the serial flash.
3033 * If @byte_oriented is set the read data is stored as a byte array
3034 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3035 * natural endianness.
3037 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
3038 unsigned int nwords
, u32
*data
, int byte_oriented
)
3042 if (addr
+ nwords
* sizeof(u32
) > adapter
->params
.sf_size
|| (addr
& 3))
3045 addr
= swab32(addr
) | SF_RD_DATA_FAST
;
3047 if ((ret
= sf1_write(adapter
, 4, 1, 0, addr
)) != 0 ||
3048 (ret
= sf1_read(adapter
, 1, 1, 0, data
)) != 0)
3051 for ( ; nwords
; nwords
--, data
++) {
3052 ret
= sf1_read(adapter
, 4, nwords
> 1, nwords
== 1, data
);
3054 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3058 *data
= (__force __u32
)(cpu_to_be32(*data
));
3064 * t4_write_flash - write up to a page of data to the serial flash
3065 * @adapter: the adapter
3066 * @addr: the start address to write
3067 * @n: length of data to write in bytes
3068 * @data: the data to write
3070 * Writes up to a page of data (256 bytes) to the serial flash starting
3071 * at the given address. All the data must be written to the same page.
3073 static int t4_write_flash(struct adapter
*adapter
, unsigned int addr
,
3074 unsigned int n
, const u8
*data
)
3078 unsigned int i
, c
, left
, val
, offset
= addr
& 0xff;
3080 if (addr
>= adapter
->params
.sf_size
|| offset
+ n
> SF_PAGE_SIZE
)
3083 val
= swab32(addr
) | SF_PROG_PAGE
;
3085 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
3086 (ret
= sf1_write(adapter
, 4, 1, 1, val
)) != 0)
3089 for (left
= n
; left
; left
-= c
) {
3091 for (val
= 0, i
= 0; i
< c
; ++i
)
3092 val
= (val
<< 8) + *data
++;
3094 ret
= sf1_write(adapter
, c
, c
!= left
, 1, val
);
3098 ret
= flash_wait_op(adapter
, 8, 1);
3102 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3104 /* Read the page to verify the write succeeded */
3105 ret
= t4_read_flash(adapter
, addr
& ~0xff, ARRAY_SIZE(buf
), buf
, 1);
3109 if (memcmp(data
- n
, (u8
*)buf
+ offset
, n
)) {
3110 dev_err(adapter
->pdev_dev
,
3111 "failed to correctly write the flash page at %#x\n",
3118 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3123 * t4_get_fw_version - read the firmware version
3124 * @adapter: the adapter
3125 * @vers: where to place the version
3127 * Reads the FW version from flash.
3129 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
)
3131 return t4_read_flash(adapter
, FLASH_FW_START
+
3132 offsetof(struct fw_hdr
, fw_ver
), 1,
3137 * t4_get_bs_version - read the firmware bootstrap version
3138 * @adapter: the adapter
3139 * @vers: where to place the version
3141 * Reads the FW Bootstrap version from flash.
3143 int t4_get_bs_version(struct adapter
*adapter
, u32
*vers
)
3145 return t4_read_flash(adapter
, FLASH_FWBOOTSTRAP_START
+
3146 offsetof(struct fw_hdr
, fw_ver
), 1,
3151 * t4_get_tp_version - read the TP microcode version
3152 * @adapter: the adapter
3153 * @vers: where to place the version
3155 * Reads the TP microcode version from flash.
3157 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
)
3159 return t4_read_flash(adapter
, FLASH_FW_START
+
3160 offsetof(struct fw_hdr
, tp_microcode_ver
),
3165 * t4_get_exprom_version - return the Expansion ROM version (if any)
3166 * @adap: the adapter
3167 * @vers: where to place the version
3169 * Reads the Expansion ROM header from FLASH and returns the version
3170 * number (if present) through the @vers return value pointer. We return
3171 * this in the Firmware Version Format since it's convenient. Return
3172 * 0 on success, -ENOENT if no Expansion ROM is present.
3174 int t4_get_exprom_version(struct adapter
*adap
, u32
*vers
)
3176 struct exprom_header
{
3177 unsigned char hdr_arr
[16]; /* must start with 0x55aa */
3178 unsigned char hdr_ver
[4]; /* Expansion ROM version */
3180 u32 exprom_header_buf
[DIV_ROUND_UP(sizeof(struct exprom_header
),
3184 ret
= t4_read_flash(adap
, FLASH_EXP_ROM_START
,
3185 ARRAY_SIZE(exprom_header_buf
), exprom_header_buf
,
3190 hdr
= (struct exprom_header
*)exprom_header_buf
;
3191 if (hdr
->hdr_arr
[0] != 0x55 || hdr
->hdr_arr
[1] != 0xaa)
3194 *vers
= (FW_HDR_FW_VER_MAJOR_V(hdr
->hdr_ver
[0]) |
3195 FW_HDR_FW_VER_MINOR_V(hdr
->hdr_ver
[1]) |
3196 FW_HDR_FW_VER_MICRO_V(hdr
->hdr_ver
[2]) |
3197 FW_HDR_FW_VER_BUILD_V(hdr
->hdr_ver
[3]));
3202 * t4_get_vpd_version - return the VPD version
3203 * @adapter: the adapter
3204 * @vers: where to place the version
3206 * Reads the VPD via the Firmware interface (thus this can only be called
3207 * once we're ready to issue Firmware commands). The format of the
3208 * VPD version is adapter specific. Returns 0 on success, an error on
3211 * Note that early versions of the Firmware didn't include the ability
3212 * to retrieve the VPD version, so we zero-out the return-value parameter
3213 * in that case to avoid leaving it with garbage in it.
3215 * Also note that the Firmware will return its cached copy of the VPD
3216 * Revision ID, not the actual Revision ID as written in the Serial
3217 * EEPROM. This is only an issue if a new VPD has been written and the
3218 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3219 * to defer calling this routine till after a FW_RESET_CMD has been issued
3220 * if the Host Driver will be performing a full adapter initialization.
3222 int t4_get_vpd_version(struct adapter
*adapter
, u32
*vers
)
3227 vpdrev_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3228 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV
));
3229 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
3230 1, &vpdrev_param
, vers
);
3237 * t4_get_scfg_version - return the Serial Configuration version
3238 * @adapter: the adapter
3239 * @vers: where to place the version
3241 * Reads the Serial Configuration Version via the Firmware interface
3242 * (thus this can only be called once we're ready to issue Firmware
3243 * commands). The format of the Serial Configuration version is
3244 * adapter specific. Returns 0 on success, an error on failure.
3246 * Note that early versions of the Firmware didn't include the ability
3247 * to retrieve the Serial Configuration version, so we zero-out the
3248 * return-value parameter in that case to avoid leaving it with
3251 * Also note that the Firmware will return its cached copy of the Serial
3252 * Initialization Revision ID, not the actual Revision ID as written in
3253 * the Serial EEPROM. This is only an issue if a new VPD has been written
3254 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3255 * it's best to defer calling this routine till after a FW_RESET_CMD has
3256 * been issued if the Host Driver will be performing a full adapter
3259 int t4_get_scfg_version(struct adapter
*adapter
, u32
*vers
)
3264 scfgrev_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3265 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV
));
3266 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
3267 1, &scfgrev_param
, vers
);
3274 * t4_get_version_info - extract various chip/firmware version information
3275 * @adapter: the adapter
3277 * Reads various chip/firmware version numbers and stores them into the
3278 * adapter Adapter Parameters structure. If any of the efforts fails
3279 * the first failure will be returned, but all of the version numbers
3282 int t4_get_version_info(struct adapter
*adapter
)
3286 #define FIRST_RET(__getvinfo) \
3288 int __ret = __getvinfo; \
3289 if (__ret && !ret) \
3293 FIRST_RET(t4_get_fw_version(adapter
, &adapter
->params
.fw_vers
));
3294 FIRST_RET(t4_get_bs_version(adapter
, &adapter
->params
.bs_vers
));
3295 FIRST_RET(t4_get_tp_version(adapter
, &adapter
->params
.tp_vers
));
3296 FIRST_RET(t4_get_exprom_version(adapter
, &adapter
->params
.er_vers
));
3297 FIRST_RET(t4_get_scfg_version(adapter
, &adapter
->params
.scfg_vers
));
3298 FIRST_RET(t4_get_vpd_version(adapter
, &adapter
->params
.vpd_vers
));
3305 * t4_dump_version_info - dump all of the adapter configuration IDs
3306 * @adapter: the adapter
3308 * Dumps all of the various bits of adapter configuration version/revision
3309 * IDs information. This is typically called at some point after
3310 * t4_get_version_info() has been called.
3312 void t4_dump_version_info(struct adapter
*adapter
)
3314 /* Device information */
3315 dev_info(adapter
->pdev_dev
, "Chelsio %s rev %d\n",
3316 adapter
->params
.vpd
.id
,
3317 CHELSIO_CHIP_RELEASE(adapter
->params
.chip
));
3318 dev_info(adapter
->pdev_dev
, "S/N: %s, P/N: %s\n",
3319 adapter
->params
.vpd
.sn
, adapter
->params
.vpd
.pn
);
3321 /* Firmware Version */
3322 if (!adapter
->params
.fw_vers
)
3323 dev_warn(adapter
->pdev_dev
, "No firmware loaded\n");
3325 dev_info(adapter
->pdev_dev
, "Firmware version: %u.%u.%u.%u\n",
3326 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.fw_vers
),
3327 FW_HDR_FW_VER_MINOR_G(adapter
->params
.fw_vers
),
3328 FW_HDR_FW_VER_MICRO_G(adapter
->params
.fw_vers
),
3329 FW_HDR_FW_VER_BUILD_G(adapter
->params
.fw_vers
));
3331 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3332 * Firmware, so dev_info() is more appropriate here.)
3334 if (!adapter
->params
.bs_vers
)
3335 dev_info(adapter
->pdev_dev
, "No bootstrap loaded\n");
3337 dev_info(adapter
->pdev_dev
, "Bootstrap version: %u.%u.%u.%u\n",
3338 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.bs_vers
),
3339 FW_HDR_FW_VER_MINOR_G(adapter
->params
.bs_vers
),
3340 FW_HDR_FW_VER_MICRO_G(adapter
->params
.bs_vers
),
3341 FW_HDR_FW_VER_BUILD_G(adapter
->params
.bs_vers
));
3343 /* TP Microcode Version */
3344 if (!adapter
->params
.tp_vers
)
3345 dev_warn(adapter
->pdev_dev
, "No TP Microcode loaded\n");
3347 dev_info(adapter
->pdev_dev
,
3348 "TP Microcode version: %u.%u.%u.%u\n",
3349 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.tp_vers
),
3350 FW_HDR_FW_VER_MINOR_G(adapter
->params
.tp_vers
),
3351 FW_HDR_FW_VER_MICRO_G(adapter
->params
.tp_vers
),
3352 FW_HDR_FW_VER_BUILD_G(adapter
->params
.tp_vers
));
3354 /* Expansion ROM version */
3355 if (!adapter
->params
.er_vers
)
3356 dev_info(adapter
->pdev_dev
, "No Expansion ROM loaded\n");
3358 dev_info(adapter
->pdev_dev
,
3359 "Expansion ROM version: %u.%u.%u.%u\n",
3360 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.er_vers
),
3361 FW_HDR_FW_VER_MINOR_G(adapter
->params
.er_vers
),
3362 FW_HDR_FW_VER_MICRO_G(adapter
->params
.er_vers
),
3363 FW_HDR_FW_VER_BUILD_G(adapter
->params
.er_vers
));
3365 /* Serial Configuration version */
3366 dev_info(adapter
->pdev_dev
, "Serial Configuration version: %#x\n",
3367 adapter
->params
.scfg_vers
);
3370 dev_info(adapter
->pdev_dev
, "VPD version: %#x\n",
3371 adapter
->params
.vpd_vers
);
3375 * t4_check_fw_version - check if the FW is supported with this driver
3376 * @adap: the adapter
3378 * Checks if an adapter's FW is compatible with the driver. Returns 0
3379 * if there's exact match, a negative error if the version could not be
3380 * read or there's a major version mismatch
3382 int t4_check_fw_version(struct adapter
*adap
)
3384 int i
, ret
, major
, minor
, micro
;
3385 int exp_major
, exp_minor
, exp_micro
;
3386 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
3388 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3389 /* Try multiple times before returning error */
3390 for (i
= 0; (ret
== -EBUSY
|| ret
== -EAGAIN
) && i
< 3; i
++)
3391 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3396 major
= FW_HDR_FW_VER_MAJOR_G(adap
->params
.fw_vers
);
3397 minor
= FW_HDR_FW_VER_MINOR_G(adap
->params
.fw_vers
);
3398 micro
= FW_HDR_FW_VER_MICRO_G(adap
->params
.fw_vers
);
3400 switch (chip_version
) {
3402 exp_major
= T4FW_MIN_VERSION_MAJOR
;
3403 exp_minor
= T4FW_MIN_VERSION_MINOR
;
3404 exp_micro
= T4FW_MIN_VERSION_MICRO
;
3407 exp_major
= T5FW_MIN_VERSION_MAJOR
;
3408 exp_minor
= T5FW_MIN_VERSION_MINOR
;
3409 exp_micro
= T5FW_MIN_VERSION_MICRO
;
3412 exp_major
= T6FW_MIN_VERSION_MAJOR
;
3413 exp_minor
= T6FW_MIN_VERSION_MINOR
;
3414 exp_micro
= T6FW_MIN_VERSION_MICRO
;
3417 dev_err(adap
->pdev_dev
, "Unsupported chip type, %x\n",
3422 if (major
< exp_major
|| (major
== exp_major
&& minor
< exp_minor
) ||
3423 (major
== exp_major
&& minor
== exp_minor
&& micro
< exp_micro
)) {
3424 dev_err(adap
->pdev_dev
,
3425 "Card has firmware version %u.%u.%u, minimum "
3426 "supported firmware is %u.%u.%u.\n", major
, minor
,
3427 micro
, exp_major
, exp_minor
, exp_micro
);
3433 /* Is the given firmware API compatible with the one the driver was compiled
3436 static int fw_compatible(const struct fw_hdr
*hdr1
, const struct fw_hdr
*hdr2
)
3439 /* short circuit if it's the exact same firmware version */
3440 if (hdr1
->chip
== hdr2
->chip
&& hdr1
->fw_ver
== hdr2
->fw_ver
)
3443 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3444 if (hdr1
->chip
== hdr2
->chip
&& SAME_INTF(nic
) && SAME_INTF(vnic
) &&
3445 SAME_INTF(ri
) && SAME_INTF(iscsi
) && SAME_INTF(fcoe
))
3452 /* The firmware in the filesystem is usable, but should it be installed?
3453 * This routine explains itself in detail if it indicates the filesystem
3454 * firmware should be installed.
3456 static int should_install_fs_fw(struct adapter
*adap
, int card_fw_usable
,
3461 if (!card_fw_usable
) {
3462 reason
= "incompatible or unusable";
3467 reason
= "older than the version supported with this driver";
3474 dev_err(adap
->pdev_dev
, "firmware on card (%u.%u.%u.%u) is %s, "
3475 "installing firmware %u.%u.%u.%u on card.\n",
3476 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
3477 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
), reason
,
3478 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
3479 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
3484 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
3485 const u8
*fw_data
, unsigned int fw_size
,
3486 struct fw_hdr
*card_fw
, enum dev_state state
,
3489 int ret
, card_fw_usable
, fs_fw_usable
;
3490 const struct fw_hdr
*fs_fw
;
3491 const struct fw_hdr
*drv_fw
;
3493 drv_fw
= &fw_info
->fw_hdr
;
3495 /* Read the header of the firmware on the card */
3496 ret
= t4_read_flash(adap
, FLASH_FW_START
,
3497 sizeof(*card_fw
) / sizeof(uint32_t),
3498 (uint32_t *)card_fw
, 1);
3500 card_fw_usable
= fw_compatible(drv_fw
, (const void *)card_fw
);
3502 dev_err(adap
->pdev_dev
,
3503 "Unable to read card's firmware header: %d\n", ret
);
3507 if (fw_data
!= NULL
) {
3508 fs_fw
= (const void *)fw_data
;
3509 fs_fw_usable
= fw_compatible(drv_fw
, fs_fw
);
3515 if (card_fw_usable
&& card_fw
->fw_ver
== drv_fw
->fw_ver
&&
3516 (!fs_fw_usable
|| fs_fw
->fw_ver
== drv_fw
->fw_ver
)) {
3517 /* Common case: the firmware on the card is an exact match and
3518 * the filesystem one is an exact match too, or the filesystem
3519 * one is absent/incompatible.
3521 } else if (fs_fw_usable
&& state
== DEV_STATE_UNINIT
&&
3522 should_install_fs_fw(adap
, card_fw_usable
,
3523 be32_to_cpu(fs_fw
->fw_ver
),
3524 be32_to_cpu(card_fw
->fw_ver
))) {
3525 ret
= t4_fw_upgrade(adap
, adap
->mbox
, fw_data
,
3528 dev_err(adap
->pdev_dev
,
3529 "failed to install firmware: %d\n", ret
);
3533 /* Installed successfully, update the cached header too. */
3536 *reset
= 0; /* already reset as part of load_fw */
3539 if (!card_fw_usable
) {
3542 d
= be32_to_cpu(drv_fw
->fw_ver
);
3543 c
= be32_to_cpu(card_fw
->fw_ver
);
3544 k
= fs_fw
? be32_to_cpu(fs_fw
->fw_ver
) : 0;
3546 dev_err(adap
->pdev_dev
, "Cannot find a usable firmware: "
3548 "driver compiled with %d.%d.%d.%d, "
3549 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3551 FW_HDR_FW_VER_MAJOR_G(d
), FW_HDR_FW_VER_MINOR_G(d
),
3552 FW_HDR_FW_VER_MICRO_G(d
), FW_HDR_FW_VER_BUILD_G(d
),
3553 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
3554 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
),
3555 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
3556 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
3561 /* We're using whatever's on the card and it's known to be good. */
3562 adap
->params
.fw_vers
= be32_to_cpu(card_fw
->fw_ver
);
3563 adap
->params
.tp_vers
= be32_to_cpu(card_fw
->tp_microcode_ver
);
3570 * t4_flash_erase_sectors - erase a range of flash sectors
3571 * @adapter: the adapter
3572 * @start: the first sector to erase
3573 * @end: the last sector to erase
3575 * Erases the sectors in the given inclusive range.
3577 static int t4_flash_erase_sectors(struct adapter
*adapter
, int start
, int end
)
3581 if (end
>= adapter
->params
.sf_nsec
)
3584 while (start
<= end
) {
3585 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
3586 (ret
= sf1_write(adapter
, 4, 0, 1,
3587 SF_ERASE_SECTOR
| (start
<< 8))) != 0 ||
3588 (ret
= flash_wait_op(adapter
, 14, 500)) != 0) {
3589 dev_err(adapter
->pdev_dev
,
3590 "erase of flash sector %d failed, error %d\n",
3596 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3601 * t4_flash_cfg_addr - return the address of the flash configuration file
3602 * @adapter: the adapter
3604 * Return the address within the flash where the Firmware Configuration
3607 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
)
3609 if (adapter
->params
.sf_size
== 0x100000)
3610 return FLASH_FPGA_CFG_START
;
3612 return FLASH_CFG_START
;
3615 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3616 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3617 * and emit an error message for mismatched firmware to save our caller the
3620 static bool t4_fw_matches_chip(const struct adapter
*adap
,
3621 const struct fw_hdr
*hdr
)
3623 /* The expression below will return FALSE for any unsupported adapter
3624 * which will keep us "honest" in the future ...
3626 if ((is_t4(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T4
) ||
3627 (is_t5(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T5
) ||
3628 (is_t6(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T6
))
3631 dev_err(adap
->pdev_dev
,
3632 "FW image (%d) is not suitable for this adapter (%d)\n",
3633 hdr
->chip
, CHELSIO_CHIP_VERSION(adap
->params
.chip
));
3638 * t4_load_fw - download firmware
3639 * @adap: the adapter
3640 * @fw_data: the firmware image to write
3643 * Write the supplied firmware image to the card's serial flash.
3645 int t4_load_fw(struct adapter
*adap
, const u8
*fw_data
, unsigned int size
)
3650 u8 first_page
[SF_PAGE_SIZE
];
3651 const __be32
*p
= (const __be32
*)fw_data
;
3652 const struct fw_hdr
*hdr
= (const struct fw_hdr
*)fw_data
;
3653 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
3654 unsigned int fw_start_sec
= FLASH_FW_START_SEC
;
3655 unsigned int fw_size
= FLASH_FW_MAX_SIZE
;
3656 unsigned int fw_start
= FLASH_FW_START
;
3659 dev_err(adap
->pdev_dev
, "FW image has no data\n");
3663 dev_err(adap
->pdev_dev
,
3664 "FW image size not multiple of 512 bytes\n");
3667 if ((unsigned int)be16_to_cpu(hdr
->len512
) * 512 != size
) {
3668 dev_err(adap
->pdev_dev
,
3669 "FW image size differs from size in FW header\n");
3672 if (size
> fw_size
) {
3673 dev_err(adap
->pdev_dev
, "FW image too large, max is %u bytes\n",
3677 if (!t4_fw_matches_chip(adap
, hdr
))
3680 for (csum
= 0, i
= 0; i
< size
/ sizeof(csum
); i
++)
3681 csum
+= be32_to_cpu(p
[i
]);
3683 if (csum
!= 0xffffffff) {
3684 dev_err(adap
->pdev_dev
,
3685 "corrupted firmware image, checksum %#x\n", csum
);
3689 i
= DIV_ROUND_UP(size
, sf_sec_size
); /* # of sectors spanned */
3690 ret
= t4_flash_erase_sectors(adap
, fw_start_sec
, fw_start_sec
+ i
- 1);
3695 * We write the correct version at the end so the driver can see a bad
3696 * version if the FW write fails. Start by writing a copy of the
3697 * first page with a bad version.
3699 memcpy(first_page
, fw_data
, SF_PAGE_SIZE
);
3700 ((struct fw_hdr
*)first_page
)->fw_ver
= cpu_to_be32(0xffffffff);
3701 ret
= t4_write_flash(adap
, fw_start
, SF_PAGE_SIZE
, first_page
);
3706 for (size
-= SF_PAGE_SIZE
; size
; size
-= SF_PAGE_SIZE
) {
3707 addr
+= SF_PAGE_SIZE
;
3708 fw_data
+= SF_PAGE_SIZE
;
3709 ret
= t4_write_flash(adap
, addr
, SF_PAGE_SIZE
, fw_data
);
3714 ret
= t4_write_flash(adap
,
3715 fw_start
+ offsetof(struct fw_hdr
, fw_ver
),
3716 sizeof(hdr
->fw_ver
), (const u8
*)&hdr
->fw_ver
);
3719 dev_err(adap
->pdev_dev
, "firmware download failed, error %d\n",
3722 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3727 * t4_phy_fw_ver - return current PHY firmware version
3728 * @adap: the adapter
3729 * @phy_fw_ver: return value buffer for PHY firmware version
3731 * Returns the current version of external PHY firmware on the
3734 int t4_phy_fw_ver(struct adapter
*adap
, int *phy_fw_ver
)
3739 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3740 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3741 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3742 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION
));
3743 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3752 * t4_load_phy_fw - download port PHY firmware
3753 * @adap: the adapter
3754 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3755 * @phy_fw_version: function to check PHY firmware versions
3756 * @phy_fw_data: the PHY firmware image to write
3757 * @phy_fw_size: image size
3759 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3760 * @phy_fw_version is supplied, then it will be used to determine if
3761 * it's necessary to perform the transfer by comparing the version
3762 * of any existing adapter PHY firmware with that of the passed in
3763 * PHY firmware image.
3765 * A negative error number will be returned if an error occurs. If
3766 * version number support is available and there's no need to upgrade
3767 * the firmware, 0 will be returned. If firmware is successfully
3768 * transferred to the adapter, 1 will be returned.
3770 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3771 * a result, a RESET of the adapter would cause that RAM to lose its
3772 * contents. Thus, loading PHY firmware on such adapters must happen
3773 * after any FW_RESET_CMDs ...
3775 int t4_load_phy_fw(struct adapter
*adap
, int win
,
3776 int (*phy_fw_version
)(const u8
*, size_t),
3777 const u8
*phy_fw_data
, size_t phy_fw_size
)
3779 int cur_phy_fw_ver
= 0, new_phy_fw_vers
= 0;
3780 unsigned long mtype
= 0, maddr
= 0;
3784 /* If we have version number support, then check to see if the adapter
3785 * already has up-to-date PHY firmware loaded.
3787 if (phy_fw_version
) {
3788 new_phy_fw_vers
= phy_fw_version(phy_fw_data
, phy_fw_size
);
3789 ret
= t4_phy_fw_ver(adap
, &cur_phy_fw_ver
);
3793 if (cur_phy_fw_ver
>= new_phy_fw_vers
) {
3794 CH_WARN(adap
, "PHY Firmware already up-to-date, "
3795 "version %#x\n", cur_phy_fw_ver
);
3800 /* Ask the firmware where it wants us to copy the PHY firmware image.
3801 * The size of the file requires a special version of the READ command
3802 * which will pass the file size via the values field in PARAMS_CMD and
3803 * retrieve the return value from firmware and place it in the same
3806 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3807 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3808 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3809 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
));
3811 ret
= t4_query_params_rw(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3812 ¶m
, &val
, 1, true);
3816 maddr
= (val
& 0xff) << 16;
3818 /* Copy the supplied PHY Firmware image to the adapter memory location
3819 * allocated by the adapter firmware.
3821 ret
= t4_memory_rw(adap
, win
, mtype
, maddr
,
3822 phy_fw_size
, (__be32
*)phy_fw_data
,
3827 /* Tell the firmware that the PHY firmware image has been written to
3828 * RAM and it can now start copying it over to the PHYs. The chip
3829 * firmware will RESET the affected PHYs as part of this operation
3830 * leaving them running the new PHY firmware image.
3832 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3833 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3834 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3835 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
));
3836 ret
= t4_set_params_timeout(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3837 ¶m
, &val
, 30000);
3839 /* If we have version number support, then check to see that the new
3840 * firmware got loaded properly.
3842 if (phy_fw_version
) {
3843 ret
= t4_phy_fw_ver(adap
, &cur_phy_fw_ver
);
3847 if (cur_phy_fw_ver
!= new_phy_fw_vers
) {
3848 CH_WARN(adap
, "PHY Firmware did not update: "
3849 "version on adapter %#x, "
3850 "version flashed %#x\n",
3851 cur_phy_fw_ver
, new_phy_fw_vers
);
3860 * t4_fwcache - firmware cache operation
3861 * @adap: the adapter
3862 * @op : the operation (flush or flush and invalidate)
3864 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
)
3866 struct fw_params_cmd c
;
3868 memset(&c
, 0, sizeof(c
));
3870 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
3871 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
3872 FW_PARAMS_CMD_PFN_V(adap
->pf
) |
3873 FW_PARAMS_CMD_VFN_V(0));
3874 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
3876 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3877 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE
));
3878 c
.param
[0].val
= cpu_to_be32(op
);
3880 return t4_wr_mbox(adap
, adap
->mbox
, &c
, sizeof(c
), NULL
);
3883 void t4_cim_read_pif_la(struct adapter
*adap
, u32
*pif_req
, u32
*pif_rsp
,
3884 unsigned int *pif_req_wrptr
,
3885 unsigned int *pif_rsp_wrptr
)
3888 u32 cfg
, val
, req
, rsp
;
3890 cfg
= t4_read_reg(adap
, CIM_DEBUGCFG_A
);
3891 if (cfg
& LADBGEN_F
)
3892 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
^ LADBGEN_F
);
3894 val
= t4_read_reg(adap
, CIM_DEBUGSTS_A
);
3895 req
= POLADBGWRPTR_G(val
);
3896 rsp
= PILADBGWRPTR_G(val
);
3898 *pif_req_wrptr
= req
;
3900 *pif_rsp_wrptr
= rsp
;
3902 for (i
= 0; i
< CIM_PIFLA_SIZE
; i
++) {
3903 for (j
= 0; j
< 6; j
++) {
3904 t4_write_reg(adap
, CIM_DEBUGCFG_A
, POLADBGRDPTR_V(req
) |
3905 PILADBGRDPTR_V(rsp
));
3906 *pif_req
++ = t4_read_reg(adap
, CIM_PO_LA_DEBUGDATA_A
);
3907 *pif_rsp
++ = t4_read_reg(adap
, CIM_PI_LA_DEBUGDATA_A
);
3911 req
= (req
+ 2) & POLADBGRDPTR_M
;
3912 rsp
= (rsp
+ 2) & PILADBGRDPTR_M
;
3914 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
);
3917 void t4_cim_read_ma_la(struct adapter
*adap
, u32
*ma_req
, u32
*ma_rsp
)
3922 cfg
= t4_read_reg(adap
, CIM_DEBUGCFG_A
);
3923 if (cfg
& LADBGEN_F
)
3924 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
^ LADBGEN_F
);
3926 for (i
= 0; i
< CIM_MALA_SIZE
; i
++) {
3927 for (j
= 0; j
< 5; j
++) {
3929 t4_write_reg(adap
, CIM_DEBUGCFG_A
, POLADBGRDPTR_V(idx
) |
3930 PILADBGRDPTR_V(idx
));
3931 *ma_req
++ = t4_read_reg(adap
, CIM_PO_LA_MADEBUGDATA_A
);
3932 *ma_rsp
++ = t4_read_reg(adap
, CIM_PI_LA_MADEBUGDATA_A
);
3935 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
);
3938 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
)
3942 for (i
= 0; i
< 8; i
++) {
3943 u32
*p
= la_buf
+ i
;
3945 t4_write_reg(adap
, ULP_RX_LA_CTL_A
, i
);
3946 j
= t4_read_reg(adap
, ULP_RX_LA_WRPTR_A
);
3947 t4_write_reg(adap
, ULP_RX_LA_RDPTR_A
, j
);
3948 for (j
= 0; j
< ULPRX_LA_SIZE
; j
++, p
+= 8)
3949 *p
= t4_read_reg(adap
, ULP_RX_LA_RDDATA_A
);
3953 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3954 * Capabilities which we control with separate controls -- see, for instance,
3955 * Pause Frames and Forward Error Correction. In order to determine what the
3956 * full set of Advertised Port Capabilities are, the base Advertised Port
3957 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3958 * Port Capabilities associated with those other controls. See
3959 * t4_link_acaps() for how this is done.
3961 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3965 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3966 * @caps16: a 16-bit Port Capabilities value
3968 * Returns the equivalent 32-bit Port Capabilities value.
3970 static fw_port_cap32_t
fwcaps16_to_caps32(fw_port_cap16_t caps16
)
3972 fw_port_cap32_t caps32
= 0;
3974 #define CAP16_TO_CAP32(__cap) \
3976 if (caps16 & FW_PORT_CAP_##__cap) \
3977 caps32 |= FW_PORT_CAP32_##__cap; \
3980 CAP16_TO_CAP32(SPEED_100M
);
3981 CAP16_TO_CAP32(SPEED_1G
);
3982 CAP16_TO_CAP32(SPEED_25G
);
3983 CAP16_TO_CAP32(SPEED_10G
);
3984 CAP16_TO_CAP32(SPEED_40G
);
3985 CAP16_TO_CAP32(SPEED_100G
);
3986 CAP16_TO_CAP32(FC_RX
);
3987 CAP16_TO_CAP32(FC_TX
);
3988 CAP16_TO_CAP32(ANEG
);
3989 CAP16_TO_CAP32(FORCE_PAUSE
);
3990 CAP16_TO_CAP32(MDIAUTO
);
3991 CAP16_TO_CAP32(MDISTRAIGHT
);
3992 CAP16_TO_CAP32(FEC_RS
);
3993 CAP16_TO_CAP32(FEC_BASER_RS
);
3994 CAP16_TO_CAP32(802_3_PAUSE
);
3995 CAP16_TO_CAP32(802_3_ASM_DIR
);
3997 #undef CAP16_TO_CAP32
4003 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4004 * @caps32: a 32-bit Port Capabilities value
4006 * Returns the equivalent 16-bit Port Capabilities value. Note that
4007 * not all 32-bit Port Capabilities can be represented in the 16-bit
4008 * Port Capabilities and some fields/values may not make it.
4010 static fw_port_cap16_t
fwcaps32_to_caps16(fw_port_cap32_t caps32
)
4012 fw_port_cap16_t caps16
= 0;
4014 #define CAP32_TO_CAP16(__cap) \
4016 if (caps32 & FW_PORT_CAP32_##__cap) \
4017 caps16 |= FW_PORT_CAP_##__cap; \
4020 CAP32_TO_CAP16(SPEED_100M
);
4021 CAP32_TO_CAP16(SPEED_1G
);
4022 CAP32_TO_CAP16(SPEED_10G
);
4023 CAP32_TO_CAP16(SPEED_25G
);
4024 CAP32_TO_CAP16(SPEED_40G
);
4025 CAP32_TO_CAP16(SPEED_100G
);
4026 CAP32_TO_CAP16(FC_RX
);
4027 CAP32_TO_CAP16(FC_TX
);
4028 CAP32_TO_CAP16(802_3_PAUSE
);
4029 CAP32_TO_CAP16(802_3_ASM_DIR
);
4030 CAP32_TO_CAP16(ANEG
);
4031 CAP32_TO_CAP16(FORCE_PAUSE
);
4032 CAP32_TO_CAP16(MDIAUTO
);
4033 CAP32_TO_CAP16(MDISTRAIGHT
);
4034 CAP32_TO_CAP16(FEC_RS
);
4035 CAP32_TO_CAP16(FEC_BASER_RS
);
4037 #undef CAP32_TO_CAP16
4042 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4043 static inline enum cc_pause
fwcap_to_cc_pause(fw_port_cap32_t fw_pause
)
4045 enum cc_pause cc_pause
= 0;
4047 if (fw_pause
& FW_PORT_CAP32_FC_RX
)
4048 cc_pause
|= PAUSE_RX
;
4049 if (fw_pause
& FW_PORT_CAP32_FC_TX
)
4050 cc_pause
|= PAUSE_TX
;
4055 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4056 static inline fw_port_cap32_t
cc_to_fwcap_pause(enum cc_pause cc_pause
)
4058 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4061 fw_port_cap32_t fw_pause
= 0;
4063 if (cc_pause
& PAUSE_RX
)
4064 fw_pause
|= FW_PORT_CAP32_FC_RX
;
4065 if (cc_pause
& PAUSE_TX
)
4066 fw_pause
|= FW_PORT_CAP32_FC_TX
;
4067 if (!(cc_pause
& PAUSE_AUTONEG
))
4068 fw_pause
|= FW_PORT_CAP32_FORCE_PAUSE
;
4070 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4071 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4072 * Note that these bits are ignored in L1 Configure commands.
4074 if (cc_pause
& PAUSE_RX
) {
4075 if (cc_pause
& PAUSE_TX
)
4076 fw_pause
|= FW_PORT_CAP32_802_3_PAUSE
;
4078 fw_pause
|= FW_PORT_CAP32_802_3_ASM_DIR
|
4079 FW_PORT_CAP32_802_3_PAUSE
;
4080 } else if (cc_pause
& PAUSE_TX
) {
4081 fw_pause
|= FW_PORT_CAP32_802_3_ASM_DIR
;
4087 /* Translate Firmware Forward Error Correction specification to Common Code */
4088 static inline enum cc_fec
fwcap_to_cc_fec(fw_port_cap32_t fw_fec
)
4090 enum cc_fec cc_fec
= 0;
4092 if (fw_fec
& FW_PORT_CAP32_FEC_RS
)
4094 if (fw_fec
& FW_PORT_CAP32_FEC_BASER_RS
)
4095 cc_fec
|= FEC_BASER_RS
;
4100 /* Translate Common Code Forward Error Correction specification to Firmware */
4101 static inline fw_port_cap32_t
cc_to_fwcap_fec(enum cc_fec cc_fec
)
4103 fw_port_cap32_t fw_fec
= 0;
4105 if (cc_fec
& FEC_RS
)
4106 fw_fec
|= FW_PORT_CAP32_FEC_RS
;
4107 if (cc_fec
& FEC_BASER_RS
)
4108 fw_fec
|= FW_PORT_CAP32_FEC_BASER_RS
;
4114 * t4_link_acaps - compute Link Advertised Port Capabilities
4115 * @adapter: the adapter
4116 * @port: the Port ID
4117 * @lc: the Port's Link Configuration
4119 * Synthesize the Advertised Port Capabilities we'll be using based on
4120 * the base Advertised Port Capabilities (which have been filtered by
4121 * ADVERT_MASK) plus the individual controls for things like Pause
4122 * Frames, Forward Error Correction, MDI, etc.
4124 fw_port_cap32_t
t4_link_acaps(struct adapter
*adapter
, unsigned int port
,
4125 struct link_config
*lc
)
4127 fw_port_cap32_t fw_fc
, fw_fec
, acaps
;
4128 unsigned int fw_mdi
;
4131 fw_mdi
= (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO
) & lc
->pcaps
);
4133 /* Convert driver coding of Pause Frame Flow Control settings into the
4136 fw_fc
= cc_to_fwcap_pause(lc
->requested_fc
);
4138 /* Convert Common Code Forward Error Control settings into the
4139 * Firmware's API. If the current Requested FEC has "Automatic"
4140 * (IEEE 802.3) specified, then we use whatever the Firmware
4141 * sent us as part of its IEEE 802.3-based interpretation of
4142 * the Transceiver Module EPROM FEC parameters. Otherwise we
4143 * use whatever is in the current Requested FEC settings.
4145 if (lc
->requested_fec
& FEC_AUTO
)
4146 cc_fec
= fwcap_to_cc_fec(lc
->def_acaps
);
4148 cc_fec
= lc
->requested_fec
;
4149 fw_fec
= cc_to_fwcap_fec(cc_fec
);
4151 /* Figure out what our Requested Port Capabilities are going to be.
4152 * Note parallel structure in t4_handle_get_port_info() and
4153 * init_link_config().
4155 if (!(lc
->pcaps
& FW_PORT_CAP32_ANEG
)) {
4156 acaps
= lc
->acaps
| fw_fc
| fw_fec
;
4157 lc
->fc
= lc
->requested_fc
& ~PAUSE_AUTONEG
;
4159 } else if (lc
->autoneg
== AUTONEG_DISABLE
) {
4160 acaps
= lc
->speed_caps
| fw_fc
| fw_fec
| fw_mdi
;
4161 lc
->fc
= lc
->requested_fc
& ~PAUSE_AUTONEG
;
4164 acaps
= lc
->acaps
| fw_fc
| fw_fec
| fw_mdi
;
4167 /* Some Requested Port Capabilities are trivially wrong if they exceed
4168 * the Physical Port Capabilities. We can check that here and provide
4169 * moderately useful feedback in the system log.
4171 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4172 * we need to exclude this from this check in order to maintain
4175 if ((acaps
& ~lc
->pcaps
) & ~FW_PORT_CAP32_FORCE_PAUSE
) {
4176 dev_err(adapter
->pdev_dev
, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4185 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4186 * @adapter: the adapter
4187 * @mbox: the Firmware Mailbox to use
4188 * @port: the Port ID
4189 * @lc: the Port's Link Configuration
4190 * @sleep_ok: if true we may sleep while awaiting command completion
4191 * @timeout: time to wait for command to finish before timing out
4192 * (negative implies @sleep_ok=false)
4194 * Set up a port's MAC and PHY according to a desired link configuration.
4195 * - If the PHY can auto-negotiate first decide what to advertise, then
4196 * enable/disable auto-negotiation as desired, and reset.
4197 * - If the PHY does not auto-negotiate just reset it.
4198 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4199 * otherwise do it later based on the outcome of auto-negotiation.
4201 int t4_link_l1cfg_core(struct adapter
*adapter
, unsigned int mbox
,
4202 unsigned int port
, struct link_config
*lc
,
4203 u8 sleep_ok
, int timeout
)
4205 unsigned int fw_caps
= adapter
->params
.fw_caps_support
;
4206 struct fw_port_cmd cmd
;
4207 fw_port_cap32_t rcap
;
4210 if (!(lc
->pcaps
& FW_PORT_CAP32_ANEG
) &&
4211 lc
->autoneg
== AUTONEG_ENABLE
) {
4215 /* Compute our Requested Port Capabilities and send that on to the
4218 rcap
= t4_link_acaps(adapter
, port
, lc
);
4219 memset(&cmd
, 0, sizeof(cmd
));
4220 cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
4221 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
4222 FW_PORT_CMD_PORTID_V(port
));
4223 cmd
.action_to_len16
=
4224 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
4225 ? FW_PORT_ACTION_L1_CFG
4226 : FW_PORT_ACTION_L1_CFG32
) |
4228 if (fw_caps
== FW_CAPS16
)
4229 cmd
.u
.l1cfg
.rcap
= cpu_to_be32(fwcaps32_to_caps16(rcap
));
4231 cmd
.u
.l1cfg32
.rcap32
= cpu_to_be32(rcap
);
4233 ret
= t4_wr_mbox_meat_timeout(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
,
4236 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4237 * the Physical Port Capabilities, some combinations of features may
4238 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4239 * Error Correction. So if the Firmware rejects the L1 Configure
4240 * request, flag that here.
4243 dev_err(adapter
->pdev_dev
,
4244 "Requested Port Capabilities %#x rejected, error %d\n",
4252 * t4_restart_aneg - restart autonegotiation
4253 * @adap: the adapter
4254 * @mbox: mbox to use for the FW command
4255 * @port: the port id
4257 * Restarts autonegotiation for the selected port.
4259 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
)
4261 unsigned int fw_caps
= adap
->params
.fw_caps_support
;
4262 struct fw_port_cmd c
;
4264 memset(&c
, 0, sizeof(c
));
4265 c
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
4266 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
4267 FW_PORT_CMD_PORTID_V(port
));
4269 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
4270 ? FW_PORT_ACTION_L1_CFG
4271 : FW_PORT_ACTION_L1_CFG32
) |
4273 if (fw_caps
== FW_CAPS16
)
4274 c
.u
.l1cfg
.rcap
= cpu_to_be32(FW_PORT_CAP_ANEG
);
4276 c
.u
.l1cfg32
.rcap32
= cpu_to_be32(FW_PORT_CAP32_ANEG
);
4277 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4280 typedef void (*int_handler_t
)(struct adapter
*adap
);
4283 unsigned int mask
; /* bits to check in interrupt status */
4284 const char *msg
; /* message to print or NULL */
4285 short stat_idx
; /* stat counter to increment or -1 */
4286 unsigned short fatal
; /* whether the condition reported is fatal */
4287 int_handler_t int_handler
; /* platform-specific int handler */
4291 * t4_handle_intr_status - table driven interrupt handler
4292 * @adapter: the adapter that generated the interrupt
4293 * @reg: the interrupt status register to process
4294 * @acts: table of interrupt actions
4296 * A table driven interrupt handler that applies a set of masks to an
4297 * interrupt status word and performs the corresponding actions if the
4298 * interrupts described by the mask have occurred. The actions include
4299 * optionally emitting a warning or alert message. The table is terminated
4300 * by an entry specifying mask 0. Returns the number of fatal interrupt
4303 static int t4_handle_intr_status(struct adapter
*adapter
, unsigned int reg
,
4304 const struct intr_info
*acts
)
4307 unsigned int mask
= 0;
4308 unsigned int status
= t4_read_reg(adapter
, reg
);
4310 for ( ; acts
->mask
; ++acts
) {
4311 if (!(status
& acts
->mask
))
4315 dev_alert(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
4316 status
& acts
->mask
);
4317 } else if (acts
->msg
&& printk_ratelimit())
4318 dev_warn(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
4319 status
& acts
->mask
);
4320 if (acts
->int_handler
)
4321 acts
->int_handler(adapter
);
4325 if (status
) /* clear processed interrupts */
4326 t4_write_reg(adapter
, reg
, status
);
4331 * Interrupt handler for the PCIE module.
4333 static void pcie_intr_handler(struct adapter
*adapter
)
4335 static const struct intr_info sysbus_intr_info
[] = {
4336 { RNPP_F
, "RXNP array parity error", -1, 1 },
4337 { RPCP_F
, "RXPC array parity error", -1, 1 },
4338 { RCIP_F
, "RXCIF array parity error", -1, 1 },
4339 { RCCP_F
, "Rx completions control array parity error", -1, 1 },
4340 { RFTP_F
, "RXFT array parity error", -1, 1 },
4343 static const struct intr_info pcie_port_intr_info
[] = {
4344 { TPCP_F
, "TXPC array parity error", -1, 1 },
4345 { TNPP_F
, "TXNP array parity error", -1, 1 },
4346 { TFTP_F
, "TXFT array parity error", -1, 1 },
4347 { TCAP_F
, "TXCA array parity error", -1, 1 },
4348 { TCIP_F
, "TXCIF array parity error", -1, 1 },
4349 { RCAP_F
, "RXCA array parity error", -1, 1 },
4350 { OTDD_F
, "outbound request TLP discarded", -1, 1 },
4351 { RDPE_F
, "Rx data parity error", -1, 1 },
4352 { TDUE_F
, "Tx uncorrectable data error", -1, 1 },
4355 static const struct intr_info pcie_intr_info
[] = {
4356 { MSIADDRLPERR_F
, "MSI AddrL parity error", -1, 1 },
4357 { MSIADDRHPERR_F
, "MSI AddrH parity error", -1, 1 },
4358 { MSIDATAPERR_F
, "MSI data parity error", -1, 1 },
4359 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
4360 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
4361 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
4362 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
4363 { PIOCPLPERR_F
, "PCI PIO completion FIFO parity error", -1, 1 },
4364 { PIOREQPERR_F
, "PCI PIO request FIFO parity error", -1, 1 },
4365 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
4366 { CCNTPERR_F
, "PCI CMD channel count parity error", -1, 1 },
4367 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
4368 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
4369 { DCNTPERR_F
, "PCI DMA channel count parity error", -1, 1 },
4370 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
4371 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
4372 { HCNTPERR_F
, "PCI HMA channel count parity error", -1, 1 },
4373 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
4374 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
4375 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
4376 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
4377 { INTXCLRPERR_F
, "PCI INTx clear parity error", -1, 1 },
4378 { MATAGPERR_F
, "PCI MA tag parity error", -1, 1 },
4379 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
4380 { RXCPLPERR_F
, "PCI Rx completion parity error", -1, 1 },
4381 { RXWRPERR_F
, "PCI Rx write parity error", -1, 1 },
4382 { RPLPERR_F
, "PCI replay buffer parity error", -1, 1 },
4383 { PCIESINT_F
, "PCI core secondary fault", -1, 1 },
4384 { PCIEPINT_F
, "PCI core primary fault", -1, 1 },
4385 { UNXSPLCPLERR_F
, "PCI unexpected split completion error",
4390 static struct intr_info t5_pcie_intr_info
[] = {
4391 { MSTGRPPERR_F
, "Master Response Read Queue parity error",
4393 { MSTTIMEOUTPERR_F
, "Master Timeout FIFO parity error", -1, 1 },
4394 { MSIXSTIPERR_F
, "MSI-X STI SRAM parity error", -1, 1 },
4395 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
4396 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
4397 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
4398 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
4399 { PIOCPLGRPPERR_F
, "PCI PIO completion Group FIFO parity error",
4401 { PIOREQGRPPERR_F
, "PCI PIO request Group FIFO parity error",
4403 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
4404 { MSTTAGQPERR_F
, "PCI master tag queue parity error", -1, 1 },
4405 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
4406 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
4407 { DREQWRPERR_F
, "PCI DMA channel write request parity error",
4409 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
4410 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
4411 { HREQWRPERR_F
, "PCI HMA channel count parity error", -1, 1 },
4412 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
4413 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
4414 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
4415 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
4416 { VFIDPERR_F
, "PCI INTx clear parity error", -1, 1 },
4417 { MAGRPPERR_F
, "PCI MA group FIFO parity error", -1, 1 },
4418 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
4419 { IPRXHDRGRPPERR_F
, "PCI IP Rx header group parity error",
4421 { IPRXDATAGRPPERR_F
, "PCI IP Rx data group parity error",
4423 { RPLPERR_F
, "PCI IP replay buffer parity error", -1, 1 },
4424 { IPSOTPERR_F
, "PCI IP SOT buffer parity error", -1, 1 },
4425 { TRGT1GRPPERR_F
, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4426 { READRSPERR_F
, "Outbound read error", -1, 0 },
4432 if (is_t4(adapter
->params
.chip
))
4433 fat
= t4_handle_intr_status(adapter
,
4434 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A
,
4436 t4_handle_intr_status(adapter
,
4437 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A
,
4438 pcie_port_intr_info
) +
4439 t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
4442 fat
= t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
4446 t4_fatal_err(adapter
);
4450 * TP interrupt handler.
4452 static void tp_intr_handler(struct adapter
*adapter
)
4454 static const struct intr_info tp_intr_info
[] = {
4455 { 0x3fffffff, "TP parity error", -1, 1 },
4456 { FLMTXFLSTEMPTY_F
, "TP out of Tx pages", -1, 1 },
4460 if (t4_handle_intr_status(adapter
, TP_INT_CAUSE_A
, tp_intr_info
))
4461 t4_fatal_err(adapter
);
4465 * SGE interrupt handler.
4467 static void sge_intr_handler(struct adapter
*adapter
)
4472 static const struct intr_info sge_intr_info
[] = {
4473 { ERR_CPL_EXCEED_IQE_SIZE_F
,
4474 "SGE received CPL exceeding IQE size", -1, 1 },
4475 { ERR_INVALID_CIDX_INC_F
,
4476 "SGE GTS CIDX increment too large", -1, 0 },
4477 { ERR_CPL_OPCODE_0_F
, "SGE received 0-length CPL", -1, 0 },
4478 { DBFIFO_LP_INT_F
, NULL
, -1, 0, t4_db_full
},
4479 { ERR_DATA_CPL_ON_HIGH_QID1_F
| ERR_DATA_CPL_ON_HIGH_QID0_F
,
4480 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4481 { ERR_BAD_DB_PIDX3_F
, "SGE DBP 3 pidx increment too large", -1,
4483 { ERR_BAD_DB_PIDX2_F
, "SGE DBP 2 pidx increment too large", -1,
4485 { ERR_BAD_DB_PIDX1_F
, "SGE DBP 1 pidx increment too large", -1,
4487 { ERR_BAD_DB_PIDX0_F
, "SGE DBP 0 pidx increment too large", -1,
4489 { ERR_ING_CTXT_PRIO_F
,
4490 "SGE too many priority ingress contexts", -1, 0 },
4491 { INGRESS_SIZE_ERR_F
, "SGE illegal ingress QID", -1, 0 },
4492 { EGRESS_SIZE_ERR_F
, "SGE illegal egress QID", -1, 0 },
4496 static struct intr_info t4t5_sge_intr_info
[] = {
4497 { ERR_DROPPED_DB_F
, NULL
, -1, 0, t4_db_dropped
},
4498 { DBFIFO_HP_INT_F
, NULL
, -1, 0, t4_db_full
},
4499 { ERR_EGR_CTXT_PRIO_F
,
4500 "SGE too many priority egress contexts", -1, 0 },
4504 perr
= t4_read_reg(adapter
, SGE_INT_CAUSE1_A
);
4507 dev_alert(adapter
->pdev_dev
, "SGE Cause1 Parity Error %#x\n",
4511 perr
= t4_read_reg(adapter
, SGE_INT_CAUSE2_A
);
4514 dev_alert(adapter
->pdev_dev
, "SGE Cause2 Parity Error %#x\n",
4518 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) >= CHELSIO_T5
) {
4519 perr
= t4_read_reg(adapter
, SGE_INT_CAUSE5_A
);
4520 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4521 perr
&= ~ERR_T_RXCRC_F
;
4524 dev_alert(adapter
->pdev_dev
,
4525 "SGE Cause5 Parity Error %#x\n", perr
);
4529 v
|= t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
, sge_intr_info
);
4530 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
4531 v
|= t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
,
4532 t4t5_sge_intr_info
);
4534 err
= t4_read_reg(adapter
, SGE_ERROR_STATS_A
);
4535 if (err
& ERROR_QID_VALID_F
) {
4536 dev_err(adapter
->pdev_dev
, "SGE error for queue %u\n",
4538 if (err
& UNCAPTURED_ERROR_F
)
4539 dev_err(adapter
->pdev_dev
,
4540 "SGE UNCAPTURED_ERROR set (clearing)\n");
4541 t4_write_reg(adapter
, SGE_ERROR_STATS_A
, ERROR_QID_VALID_F
|
4542 UNCAPTURED_ERROR_F
);
4546 t4_fatal_err(adapter
);
4549 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4550 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4551 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4552 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4555 * CIM interrupt handler.
4557 static void cim_intr_handler(struct adapter
*adapter
)
4559 static const struct intr_info cim_intr_info
[] = {
4560 { PREFDROPINT_F
, "CIM control register prefetch drop", -1, 1 },
4561 { CIM_OBQ_INTR
, "CIM OBQ parity error", -1, 1 },
4562 { CIM_IBQ_INTR
, "CIM IBQ parity error", -1, 1 },
4563 { MBUPPARERR_F
, "CIM mailbox uP parity error", -1, 1 },
4564 { MBHOSTPARERR_F
, "CIM mailbox host parity error", -1, 1 },
4565 { TIEQINPARERRINT_F
, "CIM TIEQ outgoing parity error", -1, 1 },
4566 { TIEQOUTPARERRINT_F
, "CIM TIEQ incoming parity error", -1, 1 },
4567 { TIMER0INT_F
, "CIM TIMER0 interrupt", -1, 1 },
4570 static const struct intr_info cim_upintr_info
[] = {
4571 { RSVDSPACEINT_F
, "CIM reserved space access", -1, 1 },
4572 { ILLTRANSINT_F
, "CIM illegal transaction", -1, 1 },
4573 { ILLWRINT_F
, "CIM illegal write", -1, 1 },
4574 { ILLRDINT_F
, "CIM illegal read", -1, 1 },
4575 { ILLRDBEINT_F
, "CIM illegal read BE", -1, 1 },
4576 { ILLWRBEINT_F
, "CIM illegal write BE", -1, 1 },
4577 { SGLRDBOOTINT_F
, "CIM single read from boot space", -1, 1 },
4578 { SGLWRBOOTINT_F
, "CIM single write to boot space", -1, 1 },
4579 { BLKWRBOOTINT_F
, "CIM block write to boot space", -1, 1 },
4580 { SGLRDFLASHINT_F
, "CIM single read from flash space", -1, 1 },
4581 { SGLWRFLASHINT_F
, "CIM single write to flash space", -1, 1 },
4582 { BLKWRFLASHINT_F
, "CIM block write to flash space", -1, 1 },
4583 { SGLRDEEPROMINT_F
, "CIM single EEPROM read", -1, 1 },
4584 { SGLWREEPROMINT_F
, "CIM single EEPROM write", -1, 1 },
4585 { BLKRDEEPROMINT_F
, "CIM block EEPROM read", -1, 1 },
4586 { BLKWREEPROMINT_F
, "CIM block EEPROM write", -1, 1 },
4587 { SGLRDCTLINT_F
, "CIM single read from CTL space", -1, 1 },
4588 { SGLWRCTLINT_F
, "CIM single write to CTL space", -1, 1 },
4589 { BLKRDCTLINT_F
, "CIM block read from CTL space", -1, 1 },
4590 { BLKWRCTLINT_F
, "CIM block write to CTL space", -1, 1 },
4591 { SGLRDPLINT_F
, "CIM single read from PL space", -1, 1 },
4592 { SGLWRPLINT_F
, "CIM single write to PL space", -1, 1 },
4593 { BLKRDPLINT_F
, "CIM block read from PL space", -1, 1 },
4594 { BLKWRPLINT_F
, "CIM block write to PL space", -1, 1 },
4595 { REQOVRLOOKUPINT_F
, "CIM request FIFO overwrite", -1, 1 },
4596 { RSPOVRLOOKUPINT_F
, "CIM response FIFO overwrite", -1, 1 },
4597 { TIMEOUTINT_F
, "CIM PIF timeout", -1, 1 },
4598 { TIMEOUTMAINT_F
, "CIM PIF MA timeout", -1, 1 },
4605 fw_err
= t4_read_reg(adapter
, PCIE_FW_A
);
4606 if (fw_err
& PCIE_FW_ERR_F
)
4607 t4_report_fw_error(adapter
);
4609 /* When the Firmware detects an internal error which normally
4610 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4611 * in order to make sure the Host sees the Firmware Crash. So
4612 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4613 * ignore the Timer0 interrupt.
4616 val
= t4_read_reg(adapter
, CIM_HOST_INT_CAUSE_A
);
4617 if (val
& TIMER0INT_F
)
4618 if (!(fw_err
& PCIE_FW_ERR_F
) ||
4619 (PCIE_FW_EVAL_G(fw_err
) != PCIE_FW_EVAL_CRASH
))
4620 t4_write_reg(adapter
, CIM_HOST_INT_CAUSE_A
,
4623 fat
= t4_handle_intr_status(adapter
, CIM_HOST_INT_CAUSE_A
,
4625 t4_handle_intr_status(adapter
, CIM_HOST_UPACC_INT_CAUSE_A
,
4628 t4_fatal_err(adapter
);
4632 * ULP RX interrupt handler.
4634 static void ulprx_intr_handler(struct adapter
*adapter
)
4636 static const struct intr_info ulprx_intr_info
[] = {
4637 { 0x1800000, "ULPRX context error", -1, 1 },
4638 { 0x7fffff, "ULPRX parity error", -1, 1 },
4642 if (t4_handle_intr_status(adapter
, ULP_RX_INT_CAUSE_A
, ulprx_intr_info
))
4643 t4_fatal_err(adapter
);
4647 * ULP TX interrupt handler.
4649 static void ulptx_intr_handler(struct adapter
*adapter
)
4651 static const struct intr_info ulptx_intr_info
[] = {
4652 { PBL_BOUND_ERR_CH3_F
, "ULPTX channel 3 PBL out of bounds", -1,
4654 { PBL_BOUND_ERR_CH2_F
, "ULPTX channel 2 PBL out of bounds", -1,
4656 { PBL_BOUND_ERR_CH1_F
, "ULPTX channel 1 PBL out of bounds", -1,
4658 { PBL_BOUND_ERR_CH0_F
, "ULPTX channel 0 PBL out of bounds", -1,
4660 { 0xfffffff, "ULPTX parity error", -1, 1 },
4664 if (t4_handle_intr_status(adapter
, ULP_TX_INT_CAUSE_A
, ulptx_intr_info
))
4665 t4_fatal_err(adapter
);
4669 * PM TX interrupt handler.
4671 static void pmtx_intr_handler(struct adapter
*adapter
)
4673 static const struct intr_info pmtx_intr_info
[] = {
4674 { PCMD_LEN_OVFL0_F
, "PMTX channel 0 pcmd too large", -1, 1 },
4675 { PCMD_LEN_OVFL1_F
, "PMTX channel 1 pcmd too large", -1, 1 },
4676 { PCMD_LEN_OVFL2_F
, "PMTX channel 2 pcmd too large", -1, 1 },
4677 { ZERO_C_CMD_ERROR_F
, "PMTX 0-length pcmd", -1, 1 },
4678 { PMTX_FRAMING_ERROR_F
, "PMTX framing error", -1, 1 },
4679 { OESPI_PAR_ERROR_F
, "PMTX oespi parity error", -1, 1 },
4680 { DB_OPTIONS_PAR_ERROR_F
, "PMTX db_options parity error",
4682 { ICSPI_PAR_ERROR_F
, "PMTX icspi parity error", -1, 1 },
4683 { PMTX_C_PCMD_PAR_ERROR_F
, "PMTX c_pcmd parity error", -1, 1},
4687 if (t4_handle_intr_status(adapter
, PM_TX_INT_CAUSE_A
, pmtx_intr_info
))
4688 t4_fatal_err(adapter
);
4692 * PM RX interrupt handler.
4694 static void pmrx_intr_handler(struct adapter
*adapter
)
4696 static const struct intr_info pmrx_intr_info
[] = {
4697 { ZERO_E_CMD_ERROR_F
, "PMRX 0-length pcmd", -1, 1 },
4698 { PMRX_FRAMING_ERROR_F
, "PMRX framing error", -1, 1 },
4699 { OCSPI_PAR_ERROR_F
, "PMRX ocspi parity error", -1, 1 },
4700 { DB_OPTIONS_PAR_ERROR_F
, "PMRX db_options parity error",
4702 { IESPI_PAR_ERROR_F
, "PMRX iespi parity error", -1, 1 },
4703 { PMRX_E_PCMD_PAR_ERROR_F
, "PMRX e_pcmd parity error", -1, 1},
4707 if (t4_handle_intr_status(adapter
, PM_RX_INT_CAUSE_A
, pmrx_intr_info
))
4708 t4_fatal_err(adapter
);
4712 * CPL switch interrupt handler.
4714 static void cplsw_intr_handler(struct adapter
*adapter
)
4716 static const struct intr_info cplsw_intr_info
[] = {
4717 { CIM_OP_MAP_PERR_F
, "CPLSW CIM op_map parity error", -1, 1 },
4718 { CIM_OVFL_ERROR_F
, "CPLSW CIM overflow", -1, 1 },
4719 { TP_FRAMING_ERROR_F
, "CPLSW TP framing error", -1, 1 },
4720 { SGE_FRAMING_ERROR_F
, "CPLSW SGE framing error", -1, 1 },
4721 { CIM_FRAMING_ERROR_F
, "CPLSW CIM framing error", -1, 1 },
4722 { ZERO_SWITCH_ERROR_F
, "CPLSW no-switch error", -1, 1 },
4726 if (t4_handle_intr_status(adapter
, CPL_INTR_CAUSE_A
, cplsw_intr_info
))
4727 t4_fatal_err(adapter
);
4731 * LE interrupt handler.
4733 static void le_intr_handler(struct adapter
*adap
)
4735 enum chip_type chip
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
4736 static const struct intr_info le_intr_info
[] = {
4737 { LIPMISS_F
, "LE LIP miss", -1, 0 },
4738 { LIP0_F
, "LE 0 LIP error", -1, 0 },
4739 { PARITYERR_F
, "LE parity error", -1, 1 },
4740 { UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
4741 { REQQPARERR_F
, "LE request queue parity error", -1, 1 },
4745 static struct intr_info t6_le_intr_info
[] = {
4746 { T6_LIPMISS_F
, "LE LIP miss", -1, 0 },
4747 { T6_LIP0_F
, "LE 0 LIP error", -1, 0 },
4748 { CMDTIDERR_F
, "LE cmd tid error", -1, 1 },
4749 { TCAMINTPERR_F
, "LE parity error", -1, 1 },
4750 { T6_UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
4751 { SSRAMINTPERR_F
, "LE request queue parity error", -1, 1 },
4752 { HASHTBLMEMCRCERR_F
, "LE hash table mem crc error", -1, 0 },
4756 if (t4_handle_intr_status(adap
, LE_DB_INT_CAUSE_A
,
4757 (chip
<= CHELSIO_T5
) ?
4758 le_intr_info
: t6_le_intr_info
))
4763 * MPS interrupt handler.
4765 static void mps_intr_handler(struct adapter
*adapter
)
4767 static const struct intr_info mps_rx_intr_info
[] = {
4768 { 0xffffff, "MPS Rx parity error", -1, 1 },
4771 static const struct intr_info mps_tx_intr_info
[] = {
4772 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
4773 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4774 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
4776 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
4778 { BUBBLE_F
, "MPS Tx underflow", -1, 1 },
4779 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
4780 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
4783 static const struct intr_info t6_mps_tx_intr_info
[] = {
4784 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
4785 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4786 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
4788 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
4790 /* MPS Tx Bubble is normal for T6 */
4791 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
4792 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
4795 static const struct intr_info mps_trc_intr_info
[] = {
4796 { FILTMEM_V(FILTMEM_M
), "MPS TRC filter parity error", -1, 1 },
4797 { PKTFIFO_V(PKTFIFO_M
), "MPS TRC packet FIFO parity error",
4799 { MISCPERR_F
, "MPS TRC misc parity error", -1, 1 },
4802 static const struct intr_info mps_stat_sram_intr_info
[] = {
4803 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4806 static const struct intr_info mps_stat_tx_intr_info
[] = {
4807 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4810 static const struct intr_info mps_stat_rx_intr_info
[] = {
4811 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4814 static const struct intr_info mps_cls_intr_info
[] = {
4815 { MATCHSRAM_F
, "MPS match SRAM parity error", -1, 1 },
4816 { MATCHTCAM_F
, "MPS match TCAM parity error", -1, 1 },
4817 { HASHSRAM_F
, "MPS hash SRAM parity error", -1, 1 },
4823 fat
= t4_handle_intr_status(adapter
, MPS_RX_PERR_INT_CAUSE_A
,
4825 t4_handle_intr_status(adapter
, MPS_TX_INT_CAUSE_A
,
4826 is_t6(adapter
->params
.chip
)
4827 ? t6_mps_tx_intr_info
4828 : mps_tx_intr_info
) +
4829 t4_handle_intr_status(adapter
, MPS_TRC_INT_CAUSE_A
,
4830 mps_trc_intr_info
) +
4831 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_SRAM_A
,
4832 mps_stat_sram_intr_info
) +
4833 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A
,
4834 mps_stat_tx_intr_info
) +
4835 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A
,
4836 mps_stat_rx_intr_info
) +
4837 t4_handle_intr_status(adapter
, MPS_CLS_INT_CAUSE_A
,
4840 t4_write_reg(adapter
, MPS_INT_CAUSE_A
, 0);
4841 t4_read_reg(adapter
, MPS_INT_CAUSE_A
); /* flush */
4843 t4_fatal_err(adapter
);
4846 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4850 * EDC/MC interrupt handler.
4852 static void mem_intr_handler(struct adapter
*adapter
, int idx
)
4854 static const char name
[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4856 unsigned int addr
, cnt_addr
, v
;
4858 if (idx
<= MEM_EDC1
) {
4859 addr
= EDC_REG(EDC_INT_CAUSE_A
, idx
);
4860 cnt_addr
= EDC_REG(EDC_ECC_STATUS_A
, idx
);
4861 } else if (idx
== MEM_MC
) {
4862 if (is_t4(adapter
->params
.chip
)) {
4863 addr
= MC_INT_CAUSE_A
;
4864 cnt_addr
= MC_ECC_STATUS_A
;
4866 addr
= MC_P_INT_CAUSE_A
;
4867 cnt_addr
= MC_P_ECC_STATUS_A
;
4870 addr
= MC_REG(MC_P_INT_CAUSE_A
, 1);
4871 cnt_addr
= MC_REG(MC_P_ECC_STATUS_A
, 1);
4874 v
= t4_read_reg(adapter
, addr
) & MEM_INT_MASK
;
4875 if (v
& PERR_INT_CAUSE_F
)
4876 dev_alert(adapter
->pdev_dev
, "%s FIFO parity error\n",
4878 if (v
& ECC_CE_INT_CAUSE_F
) {
4879 u32 cnt
= ECC_CECNT_G(t4_read_reg(adapter
, cnt_addr
));
4881 t4_edc_err_read(adapter
, idx
);
4883 t4_write_reg(adapter
, cnt_addr
, ECC_CECNT_V(ECC_CECNT_M
));
4884 if (printk_ratelimit())
4885 dev_warn(adapter
->pdev_dev
,
4886 "%u %s correctable ECC data error%s\n",
4887 cnt
, name
[idx
], cnt
> 1 ? "s" : "");
4889 if (v
& ECC_UE_INT_CAUSE_F
)
4890 dev_alert(adapter
->pdev_dev
,
4891 "%s uncorrectable ECC data error\n", name
[idx
]);
4893 t4_write_reg(adapter
, addr
, v
);
4894 if (v
& (PERR_INT_CAUSE_F
| ECC_UE_INT_CAUSE_F
))
4895 t4_fatal_err(adapter
);
4899 * MA interrupt handler.
4901 static void ma_intr_handler(struct adapter
*adap
)
4903 u32 v
, status
= t4_read_reg(adap
, MA_INT_CAUSE_A
);
4905 if (status
& MEM_PERR_INT_CAUSE_F
) {
4906 dev_alert(adap
->pdev_dev
,
4907 "MA parity error, parity status %#x\n",
4908 t4_read_reg(adap
, MA_PARITY_ERROR_STATUS1_A
));
4909 if (is_t5(adap
->params
.chip
))
4910 dev_alert(adap
->pdev_dev
,
4911 "MA parity error, parity status %#x\n",
4913 MA_PARITY_ERROR_STATUS2_A
));
4915 if (status
& MEM_WRAP_INT_CAUSE_F
) {
4916 v
= t4_read_reg(adap
, MA_INT_WRAP_STATUS_A
);
4917 dev_alert(adap
->pdev_dev
, "MA address wrap-around error by "
4918 "client %u to address %#x\n",
4919 MEM_WRAP_CLIENT_NUM_G(v
),
4920 MEM_WRAP_ADDRESS_G(v
) << 4);
4922 t4_write_reg(adap
, MA_INT_CAUSE_A
, status
);
4927 * SMB interrupt handler.
4929 static void smb_intr_handler(struct adapter
*adap
)
4931 static const struct intr_info smb_intr_info
[] = {
4932 { MSTTXFIFOPARINT_F
, "SMB master Tx FIFO parity error", -1, 1 },
4933 { MSTRXFIFOPARINT_F
, "SMB master Rx FIFO parity error", -1, 1 },
4934 { SLVFIFOPARINT_F
, "SMB slave FIFO parity error", -1, 1 },
4938 if (t4_handle_intr_status(adap
, SMB_INT_CAUSE_A
, smb_intr_info
))
4943 * NC-SI interrupt handler.
4945 static void ncsi_intr_handler(struct adapter
*adap
)
4947 static const struct intr_info ncsi_intr_info
[] = {
4948 { CIM_DM_PRTY_ERR_F
, "NC-SI CIM parity error", -1, 1 },
4949 { MPS_DM_PRTY_ERR_F
, "NC-SI MPS parity error", -1, 1 },
4950 { TXFIFO_PRTY_ERR_F
, "NC-SI Tx FIFO parity error", -1, 1 },
4951 { RXFIFO_PRTY_ERR_F
, "NC-SI Rx FIFO parity error", -1, 1 },
4955 if (t4_handle_intr_status(adap
, NCSI_INT_CAUSE_A
, ncsi_intr_info
))
4960 * XGMAC interrupt handler.
4962 static void xgmac_intr_handler(struct adapter
*adap
, int port
)
4964 u32 v
, int_cause_reg
;
4966 if (is_t4(adap
->params
.chip
))
4967 int_cause_reg
= PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
);
4969 int_cause_reg
= T5_PORT_REG(port
, MAC_PORT_INT_CAUSE_A
);
4971 v
= t4_read_reg(adap
, int_cause_reg
);
4973 v
&= TXFIFO_PRTY_ERR_F
| RXFIFO_PRTY_ERR_F
;
4977 if (v
& TXFIFO_PRTY_ERR_F
)
4978 dev_alert(adap
->pdev_dev
, "XGMAC %d Tx FIFO parity error\n",
4980 if (v
& RXFIFO_PRTY_ERR_F
)
4981 dev_alert(adap
->pdev_dev
, "XGMAC %d Rx FIFO parity error\n",
4983 t4_write_reg(adap
, PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
), v
);
4988 * PL interrupt handler.
4990 static void pl_intr_handler(struct adapter
*adap
)
4992 static const struct intr_info pl_intr_info
[] = {
4993 { FATALPERR_F
, "T4 fatal parity error", -1, 1 },
4994 { PERRVFID_F
, "PL VFID_MAP parity error", -1, 1 },
4998 if (t4_handle_intr_status(adap
, PL_PL_INT_CAUSE_A
, pl_intr_info
))
5002 #define PF_INTR_MASK (PFSW_F)
5003 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5004 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5005 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5008 * t4_slow_intr_handler - control path interrupt handler
5009 * @adapter: the adapter
5011 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5012 * The designation 'slow' is because it involves register reads, while
5013 * data interrupts typically don't involve any MMIOs.
5015 int t4_slow_intr_handler(struct adapter
*adapter
)
5017 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5018 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5019 * easiest just to mask that case here.
5021 u32 raw_cause
= t4_read_reg(adapter
, PL_INT_CAUSE_A
);
5022 u32 enable
= t4_read_reg(adapter
, PL_INT_ENABLE_A
);
5023 u32 cause
= raw_cause
& enable
;
5025 if (!(cause
& GLBL_INTR_MASK
))
5028 cim_intr_handler(adapter
);
5030 mps_intr_handler(adapter
);
5032 ncsi_intr_handler(adapter
);
5034 pl_intr_handler(adapter
);
5036 smb_intr_handler(adapter
);
5037 if (cause
& XGMAC0_F
)
5038 xgmac_intr_handler(adapter
, 0);
5039 if (cause
& XGMAC1_F
)
5040 xgmac_intr_handler(adapter
, 1);
5041 if (cause
& XGMAC_KR0_F
)
5042 xgmac_intr_handler(adapter
, 2);
5043 if (cause
& XGMAC_KR1_F
)
5044 xgmac_intr_handler(adapter
, 3);
5046 pcie_intr_handler(adapter
);
5048 mem_intr_handler(adapter
, MEM_MC
);
5049 if (is_t5(adapter
->params
.chip
) && (cause
& MC1_F
))
5050 mem_intr_handler(adapter
, MEM_MC1
);
5052 mem_intr_handler(adapter
, MEM_EDC0
);
5054 mem_intr_handler(adapter
, MEM_EDC1
);
5056 le_intr_handler(adapter
);
5058 tp_intr_handler(adapter
);
5060 ma_intr_handler(adapter
);
5061 if (cause
& PM_TX_F
)
5062 pmtx_intr_handler(adapter
);
5063 if (cause
& PM_RX_F
)
5064 pmrx_intr_handler(adapter
);
5065 if (cause
& ULP_RX_F
)
5066 ulprx_intr_handler(adapter
);
5067 if (cause
& CPL_SWITCH_F
)
5068 cplsw_intr_handler(adapter
);
5070 sge_intr_handler(adapter
);
5071 if (cause
& ULP_TX_F
)
5072 ulptx_intr_handler(adapter
);
5074 /* Clear the interrupts just processed for which we are the master. */
5075 t4_write_reg(adapter
, PL_INT_CAUSE_A
, raw_cause
& GLBL_INTR_MASK
);
5076 (void)t4_read_reg(adapter
, PL_INT_CAUSE_A
); /* flush */
5081 * t4_intr_enable - enable interrupts
5082 * @adapter: the adapter whose interrupts should be enabled
5084 * Enable PF-specific interrupts for the calling function and the top-level
5085 * interrupt concentrator for global interrupts. Interrupts are already
5086 * enabled at each module, here we just enable the roots of the interrupt
5089 * Note: this function should be called only when the driver manages
5090 * non PF-specific interrupts from the various HW modules. Only one PCI
5091 * function at a time should be doing this.
5093 void t4_intr_enable(struct adapter
*adapter
)
5096 u32 whoami
= t4_read_reg(adapter
, PL_WHOAMI_A
);
5097 u32 pf
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
?
5098 SOURCEPF_G(whoami
) : T6_SOURCEPF_G(whoami
);
5100 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
5101 val
= ERR_DROPPED_DB_F
| ERR_EGR_CTXT_PRIO_F
| DBFIFO_HP_INT_F
;
5102 t4_write_reg(adapter
, SGE_INT_ENABLE3_A
, ERR_CPL_EXCEED_IQE_SIZE_F
|
5103 ERR_INVALID_CIDX_INC_F
| ERR_CPL_OPCODE_0_F
|
5104 ERR_DATA_CPL_ON_HIGH_QID1_F
| INGRESS_SIZE_ERR_F
|
5105 ERR_DATA_CPL_ON_HIGH_QID0_F
| ERR_BAD_DB_PIDX3_F
|
5106 ERR_BAD_DB_PIDX2_F
| ERR_BAD_DB_PIDX1_F
|
5107 ERR_BAD_DB_PIDX0_F
| ERR_ING_CTXT_PRIO_F
|
5108 DBFIFO_LP_INT_F
| EGRESS_SIZE_ERR_F
| val
);
5109 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), PF_INTR_MASK
);
5110 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 0, 1 << pf
);
5114 * t4_intr_disable - disable interrupts
5115 * @adapter: the adapter whose interrupts should be disabled
5117 * Disable interrupts. We only disable the top-level interrupt
5118 * concentrators. The caller must be a PCI function managing global
5121 void t4_intr_disable(struct adapter
*adapter
)
5125 if (pci_channel_offline(adapter
->pdev
))
5128 whoami
= t4_read_reg(adapter
, PL_WHOAMI_A
);
5129 pf
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
?
5130 SOURCEPF_G(whoami
) : T6_SOURCEPF_G(whoami
);
5132 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), 0);
5133 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 1 << pf
, 0);
5136 unsigned int t4_chip_rss_size(struct adapter
*adap
)
5138 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
5139 return RSS_NENTRIES
;
5141 return T6_RSS_NENTRIES
;
5145 * t4_config_rss_range - configure a portion of the RSS mapping table
5146 * @adapter: the adapter
5147 * @mbox: mbox to use for the FW command
5148 * @viid: virtual interface whose RSS subtable is to be written
5149 * @start: start entry in the table to write
5150 * @n: how many table entries to write
5151 * @rspq: values for the response queue lookup table
5152 * @nrspq: number of values in @rspq
5154 * Programs the selected part of the VI's RSS mapping table with the
5155 * provided values. If @nrspq < @n the supplied values are used repeatedly
5156 * until the full table range is populated.
5158 * The caller must ensure the values in @rspq are in the range allowed for
5161 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
5162 int start
, int n
, const u16
*rspq
, unsigned int nrspq
)
5165 const u16
*rsp
= rspq
;
5166 const u16
*rsp_end
= rspq
+ nrspq
;
5167 struct fw_rss_ind_tbl_cmd cmd
;
5169 memset(&cmd
, 0, sizeof(cmd
));
5170 cmd
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD
) |
5171 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
5172 FW_RSS_IND_TBL_CMD_VIID_V(viid
));
5173 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
5175 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5177 int nq
= min(n
, 32);
5178 __be32
*qp
= &cmd
.iq0_to_iq2
;
5180 cmd
.niqid
= cpu_to_be16(nq
);
5181 cmd
.startidx
= cpu_to_be16(start
);
5189 v
= FW_RSS_IND_TBL_CMD_IQ0_V(*rsp
);
5190 if (++rsp
>= rsp_end
)
5192 v
|= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp
);
5193 if (++rsp
>= rsp_end
)
5195 v
|= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp
);
5196 if (++rsp
>= rsp_end
)
5199 *qp
++ = cpu_to_be32(v
);
5203 ret
= t4_wr_mbox(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
);
5211 * t4_config_glbl_rss - configure the global RSS mode
5212 * @adapter: the adapter
5213 * @mbox: mbox to use for the FW command
5214 * @mode: global RSS mode
5215 * @flags: mode-specific flags
5217 * Sets the global RSS mode.
5219 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
5222 struct fw_rss_glb_config_cmd c
;
5224 memset(&c
, 0, sizeof(c
));
5225 c
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD
) |
5226 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
5227 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
5228 if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
) {
5229 c
.u
.manual
.mode_pkd
=
5230 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
5231 } else if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
) {
5232 c
.u
.basicvirtual
.mode_pkd
=
5233 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
5234 c
.u
.basicvirtual
.synmapen_to_hashtoeplitz
= cpu_to_be32(flags
);
5237 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
5241 * t4_config_vi_rss - configure per VI RSS settings
5242 * @adapter: the adapter
5243 * @mbox: mbox to use for the FW command
5246 * @defq: id of the default RSS queue for the VI.
5248 * Configures VI-specific RSS properties.
5250 int t4_config_vi_rss(struct adapter
*adapter
, int mbox
, unsigned int viid
,
5251 unsigned int flags
, unsigned int defq
)
5253 struct fw_rss_vi_config_cmd c
;
5255 memset(&c
, 0, sizeof(c
));
5256 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
5257 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
5258 FW_RSS_VI_CONFIG_CMD_VIID_V(viid
));
5259 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
5260 c
.u
.basicvirtual
.defaultq_to_udpen
= cpu_to_be32(flags
|
5261 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq
));
5262 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
5265 /* Read an RSS table row */
5266 static int rd_rss_row(struct adapter
*adap
, int row
, u32
*val
)
5268 t4_write_reg(adap
, TP_RSS_LKP_TABLE_A
, 0xfff00000 | row
);
5269 return t4_wait_op_done_val(adap
, TP_RSS_LKP_TABLE_A
, LKPTBLROWVLD_F
, 1,
5274 * t4_read_rss - read the contents of the RSS mapping table
5275 * @adapter: the adapter
5276 * @map: holds the contents of the RSS mapping table
5278 * Reads the contents of the RSS hash->queue mapping table.
5280 int t4_read_rss(struct adapter
*adapter
, u16
*map
)
5282 int i
, ret
, nentries
;
5285 nentries
= t4_chip_rss_size(adapter
);
5286 for (i
= 0; i
< nentries
/ 2; ++i
) {
5287 ret
= rd_rss_row(adapter
, i
, &val
);
5290 *map
++ = LKPTBLQUEUE0_G(val
);
5291 *map
++ = LKPTBLQUEUE1_G(val
);
5296 static unsigned int t4_use_ldst(struct adapter
*adap
)
5298 return (adap
->flags
& CXGB4_FW_OK
) && !adap
->use_bd
;
5302 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5303 * @adap: the adapter
5304 * @cmd: TP fw ldst address space type
5305 * @vals: where the indirect register values are stored/written
5306 * @nregs: how many indirect registers to read/write
5307 * @start_index: index of first indirect register to read/write
5308 * @rw: Read (1) or Write (0)
5309 * @sleep_ok: if true we may sleep while awaiting command completion
5311 * Access TP indirect registers through LDST
5313 static int t4_tp_fw_ldst_rw(struct adapter
*adap
, int cmd
, u32
*vals
,
5314 unsigned int nregs
, unsigned int start_index
,
5315 unsigned int rw
, bool sleep_ok
)
5319 struct fw_ldst_cmd c
;
5321 for (i
= 0; i
< nregs
; i
++) {
5322 memset(&c
, 0, sizeof(c
));
5323 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
5325 (rw
? FW_CMD_READ_F
:
5327 FW_LDST_CMD_ADDRSPACE_V(cmd
));
5328 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
5330 c
.u
.addrval
.addr
= cpu_to_be32(start_index
+ i
);
5331 c
.u
.addrval
.val
= rw
? 0 : cpu_to_be32(vals
[i
]);
5332 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
,
5338 vals
[i
] = be32_to_cpu(c
.u
.addrval
.val
);
5344 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5345 * @adap: the adapter
5346 * @reg_addr: Address Register
5347 * @reg_data: Data register
5348 * @buff: where the indirect register values are stored/written
5349 * @nregs: how many indirect registers to read/write
5350 * @start_index: index of first indirect register to read/write
5351 * @rw: READ(1) or WRITE(0)
5352 * @sleep_ok: if true we may sleep while awaiting command completion
5354 * Read/Write TP indirect registers through LDST if possible.
5355 * Else, use backdoor access
5357 static void t4_tp_indirect_rw(struct adapter
*adap
, u32 reg_addr
, u32 reg_data
,
5358 u32
*buff
, u32 nregs
, u32 start_index
, int rw
,
5366 cmd
= FW_LDST_ADDRSPC_TP_PIO
;
5368 case TP_TM_PIO_ADDR_A
:
5369 cmd
= FW_LDST_ADDRSPC_TP_TM_PIO
;
5371 case TP_MIB_INDEX_A
:
5372 cmd
= FW_LDST_ADDRSPC_TP_MIB
;
5375 goto indirect_access
;
5378 if (t4_use_ldst(adap
))
5379 rc
= t4_tp_fw_ldst_rw(adap
, cmd
, buff
, nregs
, start_index
, rw
,
5386 t4_read_indirect(adap
, reg_addr
, reg_data
, buff
, nregs
,
5389 t4_write_indirect(adap
, reg_addr
, reg_data
, buff
, nregs
,
5395 * t4_tp_pio_read - Read TP PIO registers
5396 * @adap: the adapter
5397 * @buff: where the indirect register values are written
5398 * @nregs: how many indirect registers to read
5399 * @start_index: index of first indirect register to read
5400 * @sleep_ok: if true we may sleep while awaiting command completion
5402 * Read TP PIO Registers
5404 void t4_tp_pio_read(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5405 u32 start_index
, bool sleep_ok
)
5407 t4_tp_indirect_rw(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, buff
, nregs
,
5408 start_index
, 1, sleep_ok
);
5412 * t4_tp_pio_write - Write TP PIO registers
5413 * @adap: the adapter
5414 * @buff: where the indirect register values are stored
5415 * @nregs: how many indirect registers to write
5416 * @start_index: index of first indirect register to write
5417 * @sleep_ok: if true we may sleep while awaiting command completion
5419 * Write TP PIO Registers
5421 static void t4_tp_pio_write(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5422 u32 start_index
, bool sleep_ok
)
5424 t4_tp_indirect_rw(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, buff
, nregs
,
5425 start_index
, 0, sleep_ok
);
5429 * t4_tp_tm_pio_read - Read TP TM PIO registers
5430 * @adap: the adapter
5431 * @buff: where the indirect register values are written
5432 * @nregs: how many indirect registers to read
5433 * @start_index: index of first indirect register to read
5434 * @sleep_ok: if true we may sleep while awaiting command completion
5436 * Read TP TM PIO Registers
5438 void t4_tp_tm_pio_read(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5439 u32 start_index
, bool sleep_ok
)
5441 t4_tp_indirect_rw(adap
, TP_TM_PIO_ADDR_A
, TP_TM_PIO_DATA_A
, buff
,
5442 nregs
, start_index
, 1, sleep_ok
);
5446 * t4_tp_mib_read - Read TP MIB registers
5447 * @adap: the adapter
5448 * @buff: where the indirect register values are written
5449 * @nregs: how many indirect registers to read
5450 * @start_index: index of first indirect register to read
5451 * @sleep_ok: if true we may sleep while awaiting command completion
5453 * Read TP MIB Registers
5455 void t4_tp_mib_read(struct adapter
*adap
, u32
*buff
, u32 nregs
, u32 start_index
,
5458 t4_tp_indirect_rw(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, buff
, nregs
,
5459 start_index
, 1, sleep_ok
);
5463 * t4_read_rss_key - read the global RSS key
5464 * @adap: the adapter
5465 * @key: 10-entry array holding the 320-bit RSS key
5466 * @sleep_ok: if true we may sleep while awaiting command completion
5468 * Reads the global 320-bit RSS key.
5470 void t4_read_rss_key(struct adapter
*adap
, u32
*key
, bool sleep_ok
)
5472 t4_tp_pio_read(adap
, key
, 10, TP_RSS_SECRET_KEY0_A
, sleep_ok
);
5476 * t4_write_rss_key - program one of the RSS keys
5477 * @adap: the adapter
5478 * @key: 10-entry array holding the 320-bit RSS key
5479 * @idx: which RSS key to write
5480 * @sleep_ok: if true we may sleep while awaiting command completion
5482 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5483 * 0..15 the corresponding entry in the RSS key table is written,
5484 * otherwise the global RSS key is written.
5486 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
,
5489 u8 rss_key_addr_cnt
= 16;
5490 u32 vrt
= t4_read_reg(adap
, TP_RSS_CONFIG_VRT_A
);
5492 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5493 * allows access to key addresses 16-63 by using KeyWrAddrX
5494 * as index[5:4](upper 2) into key table
5496 if ((CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) &&
5497 (vrt
& KEYEXTEND_F
) && (KEYMODE_G(vrt
) == 3))
5498 rss_key_addr_cnt
= 32;
5500 t4_tp_pio_write(adap
, (void *)key
, 10, TP_RSS_SECRET_KEY0_A
, sleep_ok
);
5502 if (idx
>= 0 && idx
< rss_key_addr_cnt
) {
5503 if (rss_key_addr_cnt
> 16)
5504 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
5505 KEYWRADDRX_V(idx
>> 4) |
5506 T6_VFWRADDR_V(idx
) | KEYWREN_F
);
5508 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
5509 KEYWRADDR_V(idx
) | KEYWREN_F
);
5514 * t4_read_rss_pf_config - read PF RSS Configuration Table
5515 * @adapter: the adapter
5516 * @index: the entry in the PF RSS table to read
5517 * @valp: where to store the returned value
5518 * @sleep_ok: if true we may sleep while awaiting command completion
5520 * Reads the PF RSS Configuration Table at the specified index and returns
5521 * the value found there.
5523 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
5524 u32
*valp
, bool sleep_ok
)
5526 t4_tp_pio_read(adapter
, valp
, 1, TP_RSS_PF0_CONFIG_A
+ index
, sleep_ok
);
5530 * t4_read_rss_vf_config - read VF RSS Configuration Table
5531 * @adapter: the adapter
5532 * @index: the entry in the VF RSS table to read
5533 * @vfl: where to store the returned VFL
5534 * @vfh: where to store the returned VFH
5535 * @sleep_ok: if true we may sleep while awaiting command completion
5537 * Reads the VF RSS Configuration Table at the specified index and returns
5538 * the (VFL, VFH) values found there.
5540 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
5541 u32
*vfl
, u32
*vfh
, bool sleep_ok
)
5543 u32 vrt
, mask
, data
;
5545 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
) {
5546 mask
= VFWRADDR_V(VFWRADDR_M
);
5547 data
= VFWRADDR_V(index
);
5549 mask
= T6_VFWRADDR_V(T6_VFWRADDR_M
);
5550 data
= T6_VFWRADDR_V(index
);
5553 /* Request that the index'th VF Table values be read into VFL/VFH.
5555 vrt
= t4_read_reg(adapter
, TP_RSS_CONFIG_VRT_A
);
5556 vrt
&= ~(VFRDRG_F
| VFWREN_F
| KEYWREN_F
| mask
);
5557 vrt
|= data
| VFRDEN_F
;
5558 t4_write_reg(adapter
, TP_RSS_CONFIG_VRT_A
, vrt
);
5560 /* Grab the VFL/VFH values ...
5562 t4_tp_pio_read(adapter
, vfl
, 1, TP_RSS_VFL_CONFIG_A
, sleep_ok
);
5563 t4_tp_pio_read(adapter
, vfh
, 1, TP_RSS_VFH_CONFIG_A
, sleep_ok
);
5567 * t4_read_rss_pf_map - read PF RSS Map
5568 * @adapter: the adapter
5569 * @sleep_ok: if true we may sleep while awaiting command completion
5571 * Reads the PF RSS Map register and returns its value.
5573 u32
t4_read_rss_pf_map(struct adapter
*adapter
, bool sleep_ok
)
5577 t4_tp_pio_read(adapter
, &pfmap
, 1, TP_RSS_PF_MAP_A
, sleep_ok
);
5582 * t4_read_rss_pf_mask - read PF RSS Mask
5583 * @adapter: the adapter
5584 * @sleep_ok: if true we may sleep while awaiting command completion
5586 * Reads the PF RSS Mask register and returns its value.
5588 u32
t4_read_rss_pf_mask(struct adapter
*adapter
, bool sleep_ok
)
5592 t4_tp_pio_read(adapter
, &pfmask
, 1, TP_RSS_PF_MSK_A
, sleep_ok
);
5597 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5598 * @adap: the adapter
5599 * @v4: holds the TCP/IP counter values
5600 * @v6: holds the TCP/IPv6 counter values
5601 * @sleep_ok: if true we may sleep while awaiting command completion
5603 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5604 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5606 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
5607 struct tp_tcp_stats
*v6
, bool sleep_ok
)
5609 u32 val
[TP_MIB_TCP_RXT_SEG_LO_A
- TP_MIB_TCP_OUT_RST_A
+ 1];
5611 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5612 #define STAT(x) val[STAT_IDX(x)]
5613 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5616 t4_tp_mib_read(adap
, val
, ARRAY_SIZE(val
),
5617 TP_MIB_TCP_OUT_RST_A
, sleep_ok
);
5618 v4
->tcp_out_rsts
= STAT(OUT_RST
);
5619 v4
->tcp_in_segs
= STAT64(IN_SEG
);
5620 v4
->tcp_out_segs
= STAT64(OUT_SEG
);
5621 v4
->tcp_retrans_segs
= STAT64(RXT_SEG
);
5624 t4_tp_mib_read(adap
, val
, ARRAY_SIZE(val
),
5625 TP_MIB_TCP_V6OUT_RST_A
, sleep_ok
);
5626 v6
->tcp_out_rsts
= STAT(OUT_RST
);
5627 v6
->tcp_in_segs
= STAT64(IN_SEG
);
5628 v6
->tcp_out_segs
= STAT64(OUT_SEG
);
5629 v6
->tcp_retrans_segs
= STAT64(RXT_SEG
);
5637 * t4_tp_get_err_stats - read TP's error MIB counters
5638 * @adap: the adapter
5639 * @st: holds the counter values
5640 * @sleep_ok: if true we may sleep while awaiting command completion
5642 * Returns the values of TP's error counters.
5644 void t4_tp_get_err_stats(struct adapter
*adap
, struct tp_err_stats
*st
,
5647 int nchan
= adap
->params
.arch
.nchan
;
5649 t4_tp_mib_read(adap
, st
->mac_in_errs
, nchan
, TP_MIB_MAC_IN_ERR_0_A
,
5651 t4_tp_mib_read(adap
, st
->hdr_in_errs
, nchan
, TP_MIB_HDR_IN_ERR_0_A
,
5653 t4_tp_mib_read(adap
, st
->tcp_in_errs
, nchan
, TP_MIB_TCP_IN_ERR_0_A
,
5655 t4_tp_mib_read(adap
, st
->tnl_cong_drops
, nchan
,
5656 TP_MIB_TNL_CNG_DROP_0_A
, sleep_ok
);
5657 t4_tp_mib_read(adap
, st
->ofld_chan_drops
, nchan
,
5658 TP_MIB_OFD_CHN_DROP_0_A
, sleep_ok
);
5659 t4_tp_mib_read(adap
, st
->tnl_tx_drops
, nchan
, TP_MIB_TNL_DROP_0_A
,
5661 t4_tp_mib_read(adap
, st
->ofld_vlan_drops
, nchan
,
5662 TP_MIB_OFD_VLN_DROP_0_A
, sleep_ok
);
5663 t4_tp_mib_read(adap
, st
->tcp6_in_errs
, nchan
,
5664 TP_MIB_TCP_V6IN_ERR_0_A
, sleep_ok
);
5665 t4_tp_mib_read(adap
, &st
->ofld_no_neigh
, 2, TP_MIB_OFD_ARP_DROP_A
,
5670 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5671 * @adap: the adapter
5672 * @st: holds the counter values
5673 * @sleep_ok: if true we may sleep while awaiting command completion
5675 * Returns the values of TP's CPL counters.
5677 void t4_tp_get_cpl_stats(struct adapter
*adap
, struct tp_cpl_stats
*st
,
5680 int nchan
= adap
->params
.arch
.nchan
;
5682 t4_tp_mib_read(adap
, st
->req
, nchan
, TP_MIB_CPL_IN_REQ_0_A
, sleep_ok
);
5684 t4_tp_mib_read(adap
, st
->rsp
, nchan
, TP_MIB_CPL_OUT_RSP_0_A
, sleep_ok
);
5688 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5689 * @adap: the adapter
5690 * @st: holds the counter values
5691 * @sleep_ok: if true we may sleep while awaiting command completion
5693 * Returns the values of TP's RDMA counters.
5695 void t4_tp_get_rdma_stats(struct adapter
*adap
, struct tp_rdma_stats
*st
,
5698 t4_tp_mib_read(adap
, &st
->rqe_dfr_pkt
, 2, TP_MIB_RQE_DFR_PKT_A
,
5703 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5704 * @adap: the adapter
5705 * @idx: the port index
5706 * @st: holds the counter values
5707 * @sleep_ok: if true we may sleep while awaiting command completion
5709 * Returns the values of TP's FCoE counters for the selected port.
5711 void t4_get_fcoe_stats(struct adapter
*adap
, unsigned int idx
,
5712 struct tp_fcoe_stats
*st
, bool sleep_ok
)
5716 t4_tp_mib_read(adap
, &st
->frames_ddp
, 1, TP_MIB_FCOE_DDP_0_A
+ idx
,
5719 t4_tp_mib_read(adap
, &st
->frames_drop
, 1,
5720 TP_MIB_FCOE_DROP_0_A
+ idx
, sleep_ok
);
5722 t4_tp_mib_read(adap
, val
, 2, TP_MIB_FCOE_BYTE_0_HI_A
+ 2 * idx
,
5725 st
->octets_ddp
= ((u64
)val
[0] << 32) | val
[1];
5729 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5730 * @adap: the adapter
5731 * @st: holds the counter values
5732 * @sleep_ok: if true we may sleep while awaiting command completion
5734 * Returns the values of TP's counters for non-TCP directly-placed packets.
5736 void t4_get_usm_stats(struct adapter
*adap
, struct tp_usm_stats
*st
,
5741 t4_tp_mib_read(adap
, val
, 4, TP_MIB_USM_PKTS_A
, sleep_ok
);
5742 st
->frames
= val
[0];
5744 st
->octets
= ((u64
)val
[2] << 32) | val
[3];
5748 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5749 * @adap: the adapter
5750 * @mtus: where to store the MTU values
5751 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5753 * Reads the HW path MTU table.
5755 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
)
5760 for (i
= 0; i
< NMTUS
; ++i
) {
5761 t4_write_reg(adap
, TP_MTU_TABLE_A
,
5762 MTUINDEX_V(0xff) | MTUVALUE_V(i
));
5763 v
= t4_read_reg(adap
, TP_MTU_TABLE_A
);
5764 mtus
[i
] = MTUVALUE_G(v
);
5766 mtu_log
[i
] = MTUWIDTH_G(v
);
5771 * t4_read_cong_tbl - reads the congestion control table
5772 * @adap: the adapter
5773 * @incr: where to store the alpha values
5775 * Reads the additive increments programmed into the HW congestion
5778 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
])
5780 unsigned int mtu
, w
;
5782 for (mtu
= 0; mtu
< NMTUS
; ++mtu
)
5783 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
5784 t4_write_reg(adap
, TP_CCTRL_TABLE_A
,
5785 ROWINDEX_V(0xffff) | (mtu
<< 5) | w
);
5786 incr
[mtu
][w
] = (u16
)t4_read_reg(adap
,
5787 TP_CCTRL_TABLE_A
) & 0x1fff;
5792 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5793 * @adap: the adapter
5794 * @addr: the indirect TP register address
5795 * @mask: specifies the field within the register to modify
5796 * @val: new value for the field
5798 * Sets a field of an indirect TP register to the given value.
5800 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
5801 unsigned int mask
, unsigned int val
)
5803 t4_write_reg(adap
, TP_PIO_ADDR_A
, addr
);
5804 val
|= t4_read_reg(adap
, TP_PIO_DATA_A
) & ~mask
;
5805 t4_write_reg(adap
, TP_PIO_DATA_A
, val
);
5809 * init_cong_ctrl - initialize congestion control parameters
5810 * @a: the alpha values for congestion control
5811 * @b: the beta values for congestion control
5813 * Initialize the congestion control parameters.
5815 static void init_cong_ctrl(unsigned short *a
, unsigned short *b
)
5817 a
[0] = a
[1] = a
[2] = a
[3] = a
[4] = a
[5] = a
[6] = a
[7] = a
[8] = 1;
5842 b
[0] = b
[1] = b
[2] = b
[3] = b
[4] = b
[5] = b
[6] = b
[7] = b
[8] = 0;
5845 b
[13] = b
[14] = b
[15] = b
[16] = 3;
5846 b
[17] = b
[18] = b
[19] = b
[20] = b
[21] = 4;
5847 b
[22] = b
[23] = b
[24] = b
[25] = b
[26] = b
[27] = 5;
5852 /* The minimum additive increment value for the congestion control table */
5853 #define CC_MIN_INCR 2U
5856 * t4_load_mtus - write the MTU and congestion control HW tables
5857 * @adap: the adapter
5858 * @mtus: the values for the MTU table
5859 * @alpha: the values for the congestion control alpha parameter
5860 * @beta: the values for the congestion control beta parameter
5862 * Write the HW MTU table with the supplied MTUs and the high-speed
5863 * congestion control table with the supplied alpha, beta, and MTUs.
5864 * We write the two tables together because the additive increments
5865 * depend on the MTUs.
5867 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
5868 const unsigned short *alpha
, const unsigned short *beta
)
5870 static const unsigned int avg_pkts
[NCCTRL_WIN
] = {
5871 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5872 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5873 28672, 40960, 57344, 81920, 114688, 163840, 229376
5878 for (i
= 0; i
< NMTUS
; ++i
) {
5879 unsigned int mtu
= mtus
[i
];
5880 unsigned int log2
= fls(mtu
);
5882 if (!(mtu
& ((1 << log2
) >> 2))) /* round */
5884 t4_write_reg(adap
, TP_MTU_TABLE_A
, MTUINDEX_V(i
) |
5885 MTUWIDTH_V(log2
) | MTUVALUE_V(mtu
));
5887 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
5890 inc
= max(((mtu
- 40) * alpha
[w
]) / avg_pkts
[w
],
5893 t4_write_reg(adap
, TP_CCTRL_TABLE_A
, (i
<< 21) |
5894 (w
<< 16) | (beta
[w
] << 13) | inc
);
5899 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5900 * clocks. The formula is
5902 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5904 * which is equivalent to
5906 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5908 static u64
chan_rate(struct adapter
*adap
, unsigned int bytes256
)
5910 u64 v
= bytes256
* adap
->params
.vpd
.cclk
;
5912 return v
* 62 + v
/ 2;
5916 * t4_get_chan_txrate - get the current per channel Tx rates
5917 * @adap: the adapter
5918 * @nic_rate: rates for NIC traffic
5919 * @ofld_rate: rates for offloaded traffic
5921 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5924 void t4_get_chan_txrate(struct adapter
*adap
, u64
*nic_rate
, u64
*ofld_rate
)
5928 v
= t4_read_reg(adap
, TP_TX_TRATE_A
);
5929 nic_rate
[0] = chan_rate(adap
, TNLRATE0_G(v
));
5930 nic_rate
[1] = chan_rate(adap
, TNLRATE1_G(v
));
5931 if (adap
->params
.arch
.nchan
== NCHAN
) {
5932 nic_rate
[2] = chan_rate(adap
, TNLRATE2_G(v
));
5933 nic_rate
[3] = chan_rate(adap
, TNLRATE3_G(v
));
5936 v
= t4_read_reg(adap
, TP_TX_ORATE_A
);
5937 ofld_rate
[0] = chan_rate(adap
, OFDRATE0_G(v
));
5938 ofld_rate
[1] = chan_rate(adap
, OFDRATE1_G(v
));
5939 if (adap
->params
.arch
.nchan
== NCHAN
) {
5940 ofld_rate
[2] = chan_rate(adap
, OFDRATE2_G(v
));
5941 ofld_rate
[3] = chan_rate(adap
, OFDRATE3_G(v
));
5946 * t4_set_trace_filter - configure one of the tracing filters
5947 * @adap: the adapter
5948 * @tp: the desired trace filter parameters
5949 * @idx: which filter to configure
5950 * @enable: whether to enable or disable the filter
5952 * Configures one of the tracing filters available in HW. If @enable is
5953 * %0 @tp is not examined and may be %NULL. The user is responsible to
5954 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5956 int t4_set_trace_filter(struct adapter
*adap
, const struct trace_params
*tp
,
5957 int idx
, int enable
)
5959 int i
, ofst
= idx
* 4;
5960 u32 data_reg
, mask_reg
, cfg
;
5963 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
, 0);
5967 cfg
= t4_read_reg(adap
, MPS_TRC_CFG_A
);
5968 if (cfg
& TRCMULTIFILTER_F
) {
5969 /* If multiple tracers are enabled, then maximum
5970 * capture size is 2.5KB (FIFO size of a single channel)
5971 * minus 2 flits for CPL_TRACE_PKT header.
5973 if (tp
->snap_len
> ((10 * 1024 / 4) - (2 * 8)))
5976 /* If multiple tracers are disabled, to avoid deadlocks
5977 * maximum packet capture size of 9600 bytes is recommended.
5978 * Also in this mode, only trace0 can be enabled and running.
5980 if (tp
->snap_len
> 9600 || idx
)
5984 if (tp
->port
> (is_t4(adap
->params
.chip
) ? 11 : 19) || tp
->invert
> 1 ||
5985 tp
->skip_len
> TFLENGTH_M
|| tp
->skip_ofst
> TFOFFSET_M
||
5986 tp
->min_len
> TFMINPKTSIZE_M
)
5989 /* stop the tracer we'll be changing */
5990 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
, 0);
5992 idx
*= (MPS_TRC_FILTER1_MATCH_A
- MPS_TRC_FILTER0_MATCH_A
);
5993 data_reg
= MPS_TRC_FILTER0_MATCH_A
+ idx
;
5994 mask_reg
= MPS_TRC_FILTER0_DONT_CARE_A
+ idx
;
5996 for (i
= 0; i
< TRACE_LEN
/ 4; i
++, data_reg
+= 4, mask_reg
+= 4) {
5997 t4_write_reg(adap
, data_reg
, tp
->data
[i
]);
5998 t4_write_reg(adap
, mask_reg
, ~tp
->mask
[i
]);
6000 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_B_A
+ ofst
,
6001 TFCAPTUREMAX_V(tp
->snap_len
) |
6002 TFMINPKTSIZE_V(tp
->min_len
));
6003 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
,
6004 TFOFFSET_V(tp
->skip_ofst
) | TFLENGTH_V(tp
->skip_len
) |
6005 (is_t4(adap
->params
.chip
) ?
6006 TFPORT_V(tp
->port
) | TFEN_F
| TFINVERTMATCH_V(tp
->invert
) :
6007 T5_TFPORT_V(tp
->port
) | T5_TFEN_F
|
6008 T5_TFINVERTMATCH_V(tp
->invert
)));
6014 * t4_get_trace_filter - query one of the tracing filters
6015 * @adap: the adapter
6016 * @tp: the current trace filter parameters
6017 * @idx: which trace filter to query
6018 * @enabled: non-zero if the filter is enabled
6020 * Returns the current settings of one of the HW tracing filters.
6022 void t4_get_trace_filter(struct adapter
*adap
, struct trace_params
*tp
, int idx
,
6026 int i
, ofst
= idx
* 4;
6027 u32 data_reg
, mask_reg
;
6029 ctla
= t4_read_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
);
6030 ctlb
= t4_read_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_B_A
+ ofst
);
6032 if (is_t4(adap
->params
.chip
)) {
6033 *enabled
= !!(ctla
& TFEN_F
);
6034 tp
->port
= TFPORT_G(ctla
);
6035 tp
->invert
= !!(ctla
& TFINVERTMATCH_F
);
6037 *enabled
= !!(ctla
& T5_TFEN_F
);
6038 tp
->port
= T5_TFPORT_G(ctla
);
6039 tp
->invert
= !!(ctla
& T5_TFINVERTMATCH_F
);
6041 tp
->snap_len
= TFCAPTUREMAX_G(ctlb
);
6042 tp
->min_len
= TFMINPKTSIZE_G(ctlb
);
6043 tp
->skip_ofst
= TFOFFSET_G(ctla
);
6044 tp
->skip_len
= TFLENGTH_G(ctla
);
6046 ofst
= (MPS_TRC_FILTER1_MATCH_A
- MPS_TRC_FILTER0_MATCH_A
) * idx
;
6047 data_reg
= MPS_TRC_FILTER0_MATCH_A
+ ofst
;
6048 mask_reg
= MPS_TRC_FILTER0_DONT_CARE_A
+ ofst
;
6050 for (i
= 0; i
< TRACE_LEN
/ 4; i
++, data_reg
+= 4, mask_reg
+= 4) {
6051 tp
->mask
[i
] = ~t4_read_reg(adap
, mask_reg
);
6052 tp
->data
[i
] = t4_read_reg(adap
, data_reg
) & tp
->mask
[i
];
6057 * t4_pmtx_get_stats - returns the HW stats from PMTX
6058 * @adap: the adapter
6059 * @cnt: where to store the count statistics
6060 * @cycles: where to store the cycle statistics
6062 * Returns performance statistics from PMTX.
6064 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
6069 for (i
= 0; i
< adap
->params
.arch
.pm_stats_cnt
; i
++) {
6070 t4_write_reg(adap
, PM_TX_STAT_CONFIG_A
, i
+ 1);
6071 cnt
[i
] = t4_read_reg(adap
, PM_TX_STAT_COUNT_A
);
6072 if (is_t4(adap
->params
.chip
)) {
6073 cycles
[i
] = t4_read_reg64(adap
, PM_TX_STAT_LSB_A
);
6075 t4_read_indirect(adap
, PM_TX_DBG_CTRL_A
,
6076 PM_TX_DBG_DATA_A
, data
, 2,
6077 PM_TX_DBG_STAT_MSB_A
);
6078 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
6084 * t4_pmrx_get_stats - returns the HW stats from PMRX
6085 * @adap: the adapter
6086 * @cnt: where to store the count statistics
6087 * @cycles: where to store the cycle statistics
6089 * Returns performance statistics from PMRX.
6091 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
6096 for (i
= 0; i
< adap
->params
.arch
.pm_stats_cnt
; i
++) {
6097 t4_write_reg(adap
, PM_RX_STAT_CONFIG_A
, i
+ 1);
6098 cnt
[i
] = t4_read_reg(adap
, PM_RX_STAT_COUNT_A
);
6099 if (is_t4(adap
->params
.chip
)) {
6100 cycles
[i
] = t4_read_reg64(adap
, PM_RX_STAT_LSB_A
);
6102 t4_read_indirect(adap
, PM_RX_DBG_CTRL_A
,
6103 PM_RX_DBG_DATA_A
, data
, 2,
6104 PM_RX_DBG_STAT_MSB_A
);
6105 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
6111 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6112 * @adapter: the adapter
6113 * @pidx: the port index
6115 * Computes and returns a bitmap indicating which MPS buffer groups are
6116 * associated with the given Port. Bit i is set if buffer group i is
6119 static inline unsigned int compute_mps_bg_map(struct adapter
*adapter
,
6122 unsigned int chip_version
, nports
;
6124 chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
6125 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6127 switch (chip_version
) {
6132 case 2: return 3 << (2 * pidx
);
6133 case 4: return 1 << pidx
;
6139 case 2: return 1 << (2 * pidx
);
6144 dev_err(adapter
->pdev_dev
, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6145 chip_version
, nports
);
6151 * t4_get_mps_bg_map - return the buffer groups associated with a port
6152 * @adapter: the adapter
6153 * @pidx: the port index
6155 * Returns a bitmap indicating which MPS buffer groups are associated
6156 * with the given Port. Bit i is set if buffer group i is used by the
6159 unsigned int t4_get_mps_bg_map(struct adapter
*adapter
, int pidx
)
6162 unsigned int nports
;
6164 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6165 if (pidx
>= nports
) {
6166 CH_WARN(adapter
, "MPS Port Index %d >= Nports %d\n",
6171 /* If we've already retrieved/computed this, just return the result.
6173 mps_bg_map
= adapter
->params
.mps_bg_map
;
6174 if (mps_bg_map
[pidx
])
6175 return mps_bg_map
[pidx
];
6177 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6178 * If we're talking to such Firmware, let it tell us. If the new
6179 * API isn't supported, revert back to old hardcoded way. The value
6180 * obtained from Firmware is encoded in below format:
6182 * val = (( MPSBGMAP[Port 3] << 24 ) |
6183 * ( MPSBGMAP[Port 2] << 16 ) |
6184 * ( MPSBGMAP[Port 1] << 8 ) |
6185 * ( MPSBGMAP[Port 0] << 0 ))
6187 if (adapter
->flags
& CXGB4_FW_OK
) {
6191 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6192 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP
));
6193 ret
= t4_query_params_ns(adapter
, adapter
->mbox
, adapter
->pf
,
6194 0, 1, ¶m
, &val
);
6198 /* Store the BG Map for all of the Ports in order to
6199 * avoid more calls to the Firmware in the future.
6201 for (p
= 0; p
< MAX_NPORTS
; p
++, val
>>= 8)
6202 mps_bg_map
[p
] = val
& 0xff;
6204 return mps_bg_map
[pidx
];
6208 /* Either we're not talking to the Firmware or we're dealing with
6209 * older Firmware which doesn't support the new API to get the MPS
6210 * Buffer Group Map. Fall back to computing it ourselves.
6212 mps_bg_map
[pidx
] = compute_mps_bg_map(adapter
, pidx
);
6213 return mps_bg_map
[pidx
];
6217 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6218 * @adapter: the adapter
6219 * @pidx: the port index
6221 static unsigned int t4_get_tp_e2c_map(struct adapter
*adapter
, int pidx
)
6223 unsigned int nports
;
6227 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6228 if (pidx
>= nports
) {
6229 CH_WARN(adapter
, "TP E2C Channel Port Index %d >= Nports %d\n",
6234 /* FW version >= 1.16.44.0 can determine E2C channel map using
6235 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6237 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6238 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP
));
6239 ret
= t4_query_params_ns(adapter
, adapter
->mbox
, adapter
->pf
,
6240 0, 1, ¶m
, &val
);
6242 return (val
>> (8 * pidx
)) & 0xff;
6248 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6249 * @adap: the adapter
6250 * @pidx: the port index
6252 * Returns a bitmap indicating which TP Ingress Channels are associated
6253 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6256 unsigned int t4_get_tp_ch_map(struct adapter
*adap
, int pidx
)
6258 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
6259 unsigned int nports
= 1 << NUMPORTS_G(t4_read_reg(adap
, MPS_CMN_CTL_A
));
6261 if (pidx
>= nports
) {
6262 dev_warn(adap
->pdev_dev
, "TP Port Index %d >= Nports %d\n",
6267 switch (chip_version
) {
6270 /* Note that this happens to be the same values as the MPS
6271 * Buffer Group Map for these Chips. But we replicate the code
6272 * here because they're really separate concepts.
6276 case 2: return 3 << (2 * pidx
);
6277 case 4: return 1 << pidx
;
6284 case 2: return 1 << pidx
;
6289 dev_err(adap
->pdev_dev
, "Need TP Channel Map for Chip %0x, Nports %d\n",
6290 chip_version
, nports
);
6295 * t4_get_port_type_description - return Port Type string description
6296 * @port_type: firmware Port Type enumeration
6298 const char *t4_get_port_type_description(enum fw_port_type port_type
)
6300 static const char *const port_type_description
[] = {
6326 if (port_type
< ARRAY_SIZE(port_type_description
))
6327 return port_type_description
[port_type
];
6332 * t4_get_port_stats_offset - collect port stats relative to a previous
6334 * @adap: The adapter
6336 * @stats: Current stats to fill
6337 * @offset: Previous stats snapshot
6339 void t4_get_port_stats_offset(struct adapter
*adap
, int idx
,
6340 struct port_stats
*stats
,
6341 struct port_stats
*offset
)
6346 t4_get_port_stats(adap
, idx
, stats
);
6347 for (i
= 0, s
= (u64
*)stats
, o
= (u64
*)offset
;
6348 i
< (sizeof(struct port_stats
) / sizeof(u64
));
6354 * t4_get_port_stats - collect port statistics
6355 * @adap: the adapter
6356 * @idx: the port index
6357 * @p: the stats structure to fill
6359 * Collect statistics related to the given port from HW.
6361 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
)
6363 u32 bgmap
= t4_get_mps_bg_map(adap
, idx
);
6364 u32 stat_ctl
= t4_read_reg(adap
, MPS_STAT_CTL_A
);
6366 #define GET_STAT(name) \
6367 t4_read_reg64(adap, \
6368 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6369 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6370 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6372 p
->tx_octets
= GET_STAT(TX_PORT_BYTES
);
6373 p
->tx_frames
= GET_STAT(TX_PORT_FRAMES
);
6374 p
->tx_bcast_frames
= GET_STAT(TX_PORT_BCAST
);
6375 p
->tx_mcast_frames
= GET_STAT(TX_PORT_MCAST
);
6376 p
->tx_ucast_frames
= GET_STAT(TX_PORT_UCAST
);
6377 p
->tx_error_frames
= GET_STAT(TX_PORT_ERROR
);
6378 p
->tx_frames_64
= GET_STAT(TX_PORT_64B
);
6379 p
->tx_frames_65_127
= GET_STAT(TX_PORT_65B_127B
);
6380 p
->tx_frames_128_255
= GET_STAT(TX_PORT_128B_255B
);
6381 p
->tx_frames_256_511
= GET_STAT(TX_PORT_256B_511B
);
6382 p
->tx_frames_512_1023
= GET_STAT(TX_PORT_512B_1023B
);
6383 p
->tx_frames_1024_1518
= GET_STAT(TX_PORT_1024B_1518B
);
6384 p
->tx_frames_1519_max
= GET_STAT(TX_PORT_1519B_MAX
);
6385 p
->tx_drop
= GET_STAT(TX_PORT_DROP
);
6386 p
->tx_pause
= GET_STAT(TX_PORT_PAUSE
);
6387 p
->tx_ppp0
= GET_STAT(TX_PORT_PPP0
);
6388 p
->tx_ppp1
= GET_STAT(TX_PORT_PPP1
);
6389 p
->tx_ppp2
= GET_STAT(TX_PORT_PPP2
);
6390 p
->tx_ppp3
= GET_STAT(TX_PORT_PPP3
);
6391 p
->tx_ppp4
= GET_STAT(TX_PORT_PPP4
);
6392 p
->tx_ppp5
= GET_STAT(TX_PORT_PPP5
);
6393 p
->tx_ppp6
= GET_STAT(TX_PORT_PPP6
);
6394 p
->tx_ppp7
= GET_STAT(TX_PORT_PPP7
);
6396 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) >= CHELSIO_T5
) {
6397 if (stat_ctl
& COUNTPAUSESTATTX_F
)
6398 p
->tx_frames_64
-= p
->tx_pause
;
6399 if (stat_ctl
& COUNTPAUSEMCTX_F
)
6400 p
->tx_mcast_frames
-= p
->tx_pause
;
6402 p
->rx_octets
= GET_STAT(RX_PORT_BYTES
);
6403 p
->rx_frames
= GET_STAT(RX_PORT_FRAMES
);
6404 p
->rx_bcast_frames
= GET_STAT(RX_PORT_BCAST
);
6405 p
->rx_mcast_frames
= GET_STAT(RX_PORT_MCAST
);
6406 p
->rx_ucast_frames
= GET_STAT(RX_PORT_UCAST
);
6407 p
->rx_too_long
= GET_STAT(RX_PORT_MTU_ERROR
);
6408 p
->rx_jabber
= GET_STAT(RX_PORT_MTU_CRC_ERROR
);
6409 p
->rx_fcs_err
= GET_STAT(RX_PORT_CRC_ERROR
);
6410 p
->rx_len_err
= GET_STAT(RX_PORT_LEN_ERROR
);
6411 p
->rx_symbol_err
= GET_STAT(RX_PORT_SYM_ERROR
);
6412 p
->rx_runt
= GET_STAT(RX_PORT_LESS_64B
);
6413 p
->rx_frames_64
= GET_STAT(RX_PORT_64B
);
6414 p
->rx_frames_65_127
= GET_STAT(RX_PORT_65B_127B
);
6415 p
->rx_frames_128_255
= GET_STAT(RX_PORT_128B_255B
);
6416 p
->rx_frames_256_511
= GET_STAT(RX_PORT_256B_511B
);
6417 p
->rx_frames_512_1023
= GET_STAT(RX_PORT_512B_1023B
);
6418 p
->rx_frames_1024_1518
= GET_STAT(RX_PORT_1024B_1518B
);
6419 p
->rx_frames_1519_max
= GET_STAT(RX_PORT_1519B_MAX
);
6420 p
->rx_pause
= GET_STAT(RX_PORT_PAUSE
);
6421 p
->rx_ppp0
= GET_STAT(RX_PORT_PPP0
);
6422 p
->rx_ppp1
= GET_STAT(RX_PORT_PPP1
);
6423 p
->rx_ppp2
= GET_STAT(RX_PORT_PPP2
);
6424 p
->rx_ppp3
= GET_STAT(RX_PORT_PPP3
);
6425 p
->rx_ppp4
= GET_STAT(RX_PORT_PPP4
);
6426 p
->rx_ppp5
= GET_STAT(RX_PORT_PPP5
);
6427 p
->rx_ppp6
= GET_STAT(RX_PORT_PPP6
);
6428 p
->rx_ppp7
= GET_STAT(RX_PORT_PPP7
);
6430 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) >= CHELSIO_T5
) {
6431 if (stat_ctl
& COUNTPAUSESTATRX_F
)
6432 p
->rx_frames_64
-= p
->rx_pause
;
6433 if (stat_ctl
& COUNTPAUSEMCRX_F
)
6434 p
->rx_mcast_frames
-= p
->rx_pause
;
6437 p
->rx_ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME
) : 0;
6438 p
->rx_ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME
) : 0;
6439 p
->rx_ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME
) : 0;
6440 p
->rx_ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME
) : 0;
6441 p
->rx_trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME
) : 0;
6442 p
->rx_trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME
) : 0;
6443 p
->rx_trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME
) : 0;
6444 p
->rx_trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME
) : 0;
6451 * t4_get_lb_stats - collect loopback port statistics
6452 * @adap: the adapter
6453 * @idx: the loopback port index
6454 * @p: the stats structure to fill
6456 * Return HW statistics for the given loopback port.
6458 void t4_get_lb_stats(struct adapter
*adap
, int idx
, struct lb_port_stats
*p
)
6460 u32 bgmap
= t4_get_mps_bg_map(adap
, idx
);
6462 #define GET_STAT(name) \
6463 t4_read_reg64(adap, \
6464 (is_t4(adap->params.chip) ? \
6465 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6466 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6467 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6469 p
->octets
= GET_STAT(BYTES
);
6470 p
->frames
= GET_STAT(FRAMES
);
6471 p
->bcast_frames
= GET_STAT(BCAST
);
6472 p
->mcast_frames
= GET_STAT(MCAST
);
6473 p
->ucast_frames
= GET_STAT(UCAST
);
6474 p
->error_frames
= GET_STAT(ERROR
);
6476 p
->frames_64
= GET_STAT(64B
);
6477 p
->frames_65_127
= GET_STAT(65B_127B
);
6478 p
->frames_128_255
= GET_STAT(128B_255B
);
6479 p
->frames_256_511
= GET_STAT(256B_511B
);
6480 p
->frames_512_1023
= GET_STAT(512B_1023B
);
6481 p
->frames_1024_1518
= GET_STAT(1024B_1518B
);
6482 p
->frames_1519_max
= GET_STAT(1519B_MAX
);
6483 p
->drop
= GET_STAT(DROP_FRAMES
);
6485 p
->ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME
) : 0;
6486 p
->ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME
) : 0;
6487 p
->ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME
) : 0;
6488 p
->ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME
) : 0;
6489 p
->trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME
) : 0;
6490 p
->trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME
) : 0;
6491 p
->trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME
) : 0;
6492 p
->trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME
) : 0;
6498 /* t4_mk_filtdelwr - create a delete filter WR
6499 * @ftid: the filter ID
6500 * @wr: the filter work request to populate
6501 * @qid: ingress queue to receive the delete notification
6503 * Creates a filter work request to delete the supplied filter. If @qid is
6504 * negative the delete notification is suppressed.
6506 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
)
6508 memset(wr
, 0, sizeof(*wr
));
6509 wr
->op_pkd
= cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR
));
6510 wr
->len16_pkd
= cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr
) / 16));
6511 wr
->tid_to_iq
= cpu_to_be32(FW_FILTER_WR_TID_V(ftid
) |
6512 FW_FILTER_WR_NOREPLY_V(qid
< 0));
6513 wr
->del_filter_to_l2tix
= cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F
);
6515 wr
->rx_chan_rx_rpl_iq
=
6516 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid
));
6519 #define INIT_CMD(var, cmd, rd_wr) do { \
6520 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6521 FW_CMD_REQUEST_F | \
6522 FW_CMD_##rd_wr##_F); \
6523 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6526 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
6530 struct fw_ldst_cmd c
;
6532 memset(&c
, 0, sizeof(c
));
6533 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE
);
6534 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6538 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6539 c
.u
.addrval
.addr
= cpu_to_be32(addr
);
6540 c
.u
.addrval
.val
= cpu_to_be32(val
);
6542 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6546 * t4_mdio_rd - read a PHY register through MDIO
6547 * @adap: the adapter
6548 * @mbox: mailbox to use for the FW command
6549 * @phy_addr: the PHY address
6550 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6551 * @reg: the register to read
6552 * @valp: where to store the value
6554 * Issues a FW command through the given mailbox to read a PHY register.
6556 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
6557 unsigned int mmd
, unsigned int reg
, u16
*valp
)
6561 struct fw_ldst_cmd c
;
6563 memset(&c
, 0, sizeof(c
));
6564 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
);
6565 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6566 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
6568 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6569 c
.u
.mdio
.paddr_mmd
= cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr
) |
6570 FW_LDST_CMD_MMD_V(mmd
));
6571 c
.u
.mdio
.raddr
= cpu_to_be16(reg
);
6573 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6575 *valp
= be16_to_cpu(c
.u
.mdio
.rval
);
6580 * t4_mdio_wr - write a PHY register through MDIO
6581 * @adap: the adapter
6582 * @mbox: mailbox to use for the FW command
6583 * @phy_addr: the PHY address
6584 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6585 * @reg: the register to write
6586 * @val: value to write
6588 * Issues a FW command through the given mailbox to write a PHY register.
6590 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
6591 unsigned int mmd
, unsigned int reg
, u16 val
)
6594 struct fw_ldst_cmd c
;
6596 memset(&c
, 0, sizeof(c
));
6597 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
);
6598 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6599 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
6601 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6602 c
.u
.mdio
.paddr_mmd
= cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr
) |
6603 FW_LDST_CMD_MMD_V(mmd
));
6604 c
.u
.mdio
.raddr
= cpu_to_be16(reg
);
6605 c
.u
.mdio
.rval
= cpu_to_be16(val
);
6607 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6611 * t4_sge_decode_idma_state - decode the idma state
6612 * @adapter: the adapter
6613 * @state: the state idma is stuck in
6615 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
)
6617 static const char * const t4_decode
[] = {
6619 "IDMA_PUSH_MORE_CPL_FIFO",
6620 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6622 "IDMA_PHYSADDR_SEND_PCIEHDR",
6623 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6624 "IDMA_PHYSADDR_SEND_PAYLOAD",
6625 "IDMA_SEND_FIFO_TO_IMSG",
6626 "IDMA_FL_REQ_DATA_FL_PREP",
6627 "IDMA_FL_REQ_DATA_FL",
6629 "IDMA_FL_H_REQ_HEADER_FL",
6630 "IDMA_FL_H_SEND_PCIEHDR",
6631 "IDMA_FL_H_PUSH_CPL_FIFO",
6632 "IDMA_FL_H_SEND_CPL",
6633 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6634 "IDMA_FL_H_SEND_IP_HDR",
6635 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6636 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6637 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6638 "IDMA_FL_D_SEND_PCIEHDR",
6639 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6640 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6641 "IDMA_FL_SEND_PCIEHDR",
6642 "IDMA_FL_PUSH_CPL_FIFO",
6644 "IDMA_FL_SEND_PAYLOAD_FIRST",
6645 "IDMA_FL_SEND_PAYLOAD",
6646 "IDMA_FL_REQ_NEXT_DATA_FL",
6647 "IDMA_FL_SEND_NEXT_PCIEHDR",
6648 "IDMA_FL_SEND_PADDING",
6649 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6650 "IDMA_FL_SEND_FIFO_TO_IMSG",
6651 "IDMA_FL_REQ_DATAFL_DONE",
6652 "IDMA_FL_REQ_HEADERFL_DONE",
6654 static const char * const t5_decode
[] = {
6657 "IDMA_PUSH_MORE_CPL_FIFO",
6658 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6659 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6660 "IDMA_PHYSADDR_SEND_PCIEHDR",
6661 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6662 "IDMA_PHYSADDR_SEND_PAYLOAD",
6663 "IDMA_SEND_FIFO_TO_IMSG",
6664 "IDMA_FL_REQ_DATA_FL",
6666 "IDMA_FL_DROP_SEND_INC",
6667 "IDMA_FL_H_REQ_HEADER_FL",
6668 "IDMA_FL_H_SEND_PCIEHDR",
6669 "IDMA_FL_H_PUSH_CPL_FIFO",
6670 "IDMA_FL_H_SEND_CPL",
6671 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6672 "IDMA_FL_H_SEND_IP_HDR",
6673 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6674 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6675 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6676 "IDMA_FL_D_SEND_PCIEHDR",
6677 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6678 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6679 "IDMA_FL_SEND_PCIEHDR",
6680 "IDMA_FL_PUSH_CPL_FIFO",
6682 "IDMA_FL_SEND_PAYLOAD_FIRST",
6683 "IDMA_FL_SEND_PAYLOAD",
6684 "IDMA_FL_REQ_NEXT_DATA_FL",
6685 "IDMA_FL_SEND_NEXT_PCIEHDR",
6686 "IDMA_FL_SEND_PADDING",
6687 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6689 static const char * const t6_decode
[] = {
6691 "IDMA_PUSH_MORE_CPL_FIFO",
6692 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6693 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6694 "IDMA_PHYSADDR_SEND_PCIEHDR",
6695 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6696 "IDMA_PHYSADDR_SEND_PAYLOAD",
6697 "IDMA_FL_REQ_DATA_FL",
6699 "IDMA_FL_DROP_SEND_INC",
6700 "IDMA_FL_H_REQ_HEADER_FL",
6701 "IDMA_FL_H_SEND_PCIEHDR",
6702 "IDMA_FL_H_PUSH_CPL_FIFO",
6703 "IDMA_FL_H_SEND_CPL",
6704 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6705 "IDMA_FL_H_SEND_IP_HDR",
6706 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6707 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6708 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6709 "IDMA_FL_D_SEND_PCIEHDR",
6710 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6711 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6712 "IDMA_FL_SEND_PCIEHDR",
6713 "IDMA_FL_PUSH_CPL_FIFO",
6715 "IDMA_FL_SEND_PAYLOAD_FIRST",
6716 "IDMA_FL_SEND_PAYLOAD",
6717 "IDMA_FL_REQ_NEXT_DATA_FL",
6718 "IDMA_FL_SEND_NEXT_PCIEHDR",
6719 "IDMA_FL_SEND_PADDING",
6720 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6722 static const u32 sge_regs
[] = {
6723 SGE_DEBUG_DATA_LOW_INDEX_2_A
,
6724 SGE_DEBUG_DATA_LOW_INDEX_3_A
,
6725 SGE_DEBUG_DATA_HIGH_INDEX_10_A
,
6727 const char **sge_idma_decode
;
6728 int sge_idma_decode_nstates
;
6730 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
6732 /* Select the right set of decode strings to dump depending on the
6733 * adapter chip type.
6735 switch (chip_version
) {
6737 sge_idma_decode
= (const char **)t4_decode
;
6738 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
6742 sge_idma_decode
= (const char **)t5_decode
;
6743 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
6747 sge_idma_decode
= (const char **)t6_decode
;
6748 sge_idma_decode_nstates
= ARRAY_SIZE(t6_decode
);
6752 dev_err(adapter
->pdev_dev
,
6753 "Unsupported chip version %d\n", chip_version
);
6757 if (is_t4(adapter
->params
.chip
)) {
6758 sge_idma_decode
= (const char **)t4_decode
;
6759 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
6761 sge_idma_decode
= (const char **)t5_decode
;
6762 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
6765 if (state
< sge_idma_decode_nstates
)
6766 CH_WARN(adapter
, "idma state %s\n", sge_idma_decode
[state
]);
6768 CH_WARN(adapter
, "idma state %d unknown\n", state
);
6770 for (i
= 0; i
< ARRAY_SIZE(sge_regs
); i
++)
6771 CH_WARN(adapter
, "SGE register %#x value %#x\n",
6772 sge_regs
[i
], t4_read_reg(adapter
, sge_regs
[i
]));
6776 * t4_sge_ctxt_flush - flush the SGE context cache
6777 * @adap: the adapter
6778 * @mbox: mailbox to use for the FW command
6779 * @ctxt_type: Egress or Ingress
6781 * Issues a FW command through the given mailbox to flush the
6782 * SGE context cache.
6784 int t4_sge_ctxt_flush(struct adapter
*adap
, unsigned int mbox
, int ctxt_type
)
6788 struct fw_ldst_cmd c
;
6790 memset(&c
, 0, sizeof(c
));
6791 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(ctxt_type
== CTXT_EGRESS
?
6792 FW_LDST_ADDRSPC_SGE_EGRC
:
6793 FW_LDST_ADDRSPC_SGE_INGC
);
6794 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6795 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
6797 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6798 c
.u
.idctxt
.msg_ctxtflush
= cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F
);
6800 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6805 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6806 * @adap: the adapter
6807 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6808 * @dbqtimers: SGE Doorbell Queue Timer table
6810 * Reads the SGE Doorbell Queue Timer values into the provided table.
6811 * Returns 0 on success (Firmware and Hardware support this feature),
6812 * an error on failure.
6814 int t4_read_sge_dbqtimers(struct adapter
*adap
, unsigned int ndbqtimers
,
6817 int ret
, dbqtimerix
;
6821 while (dbqtimerix
< ndbqtimers
) {
6823 u32 params
[7], vals
[7];
6825 nparams
= ndbqtimers
- dbqtimerix
;
6826 if (nparams
> ARRAY_SIZE(params
))
6827 nparams
= ARRAY_SIZE(params
);
6829 for (param
= 0; param
< nparams
; param
++)
6831 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6832 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER
) |
6833 FW_PARAMS_PARAM_Y_V(dbqtimerix
+ param
));
6834 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0,
6835 nparams
, params
, vals
);
6839 for (param
= 0; param
< nparams
; param
++)
6840 dbqtimers
[dbqtimerix
++] = vals
[param
];
6846 * t4_fw_hello - establish communication with FW
6847 * @adap: the adapter
6848 * @mbox: mailbox to use for the FW command
6849 * @evt_mbox: mailbox to receive async FW events
6850 * @master: specifies the caller's willingness to be the device master
6851 * @state: returns the current device state (if non-NULL)
6853 * Issues a command to establish communication with FW. Returns either
6854 * an error (negative integer) or the mailbox of the Master PF.
6856 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
6857 enum dev_master master
, enum dev_state
*state
)
6860 struct fw_hello_cmd c
;
6862 unsigned int master_mbox
;
6863 int retries
= FW_CMD_HELLO_RETRIES
;
6866 memset(&c
, 0, sizeof(c
));
6867 INIT_CMD(c
, HELLO
, WRITE
);
6868 c
.err_to_clearinit
= cpu_to_be32(
6869 FW_HELLO_CMD_MASTERDIS_V(master
== MASTER_CANT
) |
6870 FW_HELLO_CMD_MASTERFORCE_V(master
== MASTER_MUST
) |
6871 FW_HELLO_CMD_MBMASTER_V(master
== MASTER_MUST
?
6872 mbox
: FW_HELLO_CMD_MBMASTER_M
) |
6873 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox
) |
6874 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os
) |
6875 FW_HELLO_CMD_CLEARINIT_F
);
6878 * Issue the HELLO command to the firmware. If it's not successful
6879 * but indicates that we got a "busy" or "timeout" condition, retry
6880 * the HELLO until we exhaust our retry limit. If we do exceed our
6881 * retry limit, check to see if the firmware left us any error
6882 * information and report that if so.
6884 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6886 if ((ret
== -EBUSY
|| ret
== -ETIMEDOUT
) && retries
-- > 0)
6888 if (t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
6889 t4_report_fw_error(adap
);
6893 v
= be32_to_cpu(c
.err_to_clearinit
);
6894 master_mbox
= FW_HELLO_CMD_MBMASTER_G(v
);
6896 if (v
& FW_HELLO_CMD_ERR_F
)
6897 *state
= DEV_STATE_ERR
;
6898 else if (v
& FW_HELLO_CMD_INIT_F
)
6899 *state
= DEV_STATE_INIT
;
6901 *state
= DEV_STATE_UNINIT
;
6905 * If we're not the Master PF then we need to wait around for the
6906 * Master PF Driver to finish setting up the adapter.
6908 * Note that we also do this wait if we're a non-Master-capable PF and
6909 * there is no current Master PF; a Master PF may show up momentarily
6910 * and we wouldn't want to fail pointlessly. (This can happen when an
6911 * OS loads lots of different drivers rapidly at the same time). In
6912 * this case, the Master PF returned by the firmware will be
6913 * PCIE_FW_MASTER_M so the test below will work ...
6915 if ((v
& (FW_HELLO_CMD_ERR_F
|FW_HELLO_CMD_INIT_F
)) == 0 &&
6916 master_mbox
!= mbox
) {
6917 int waiting
= FW_CMD_HELLO_TIMEOUT
;
6920 * Wait for the firmware to either indicate an error or
6921 * initialized state. If we see either of these we bail out
6922 * and report the issue to the caller. If we exhaust the
6923 * "hello timeout" and we haven't exhausted our retries, try
6924 * again. Otherwise bail with a timeout error.
6933 * If neither Error nor Initialized are indicated
6934 * by the firmware keep waiting till we exhaust our
6935 * timeout ... and then retry if we haven't exhausted
6938 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
6939 if (!(pcie_fw
& (PCIE_FW_ERR_F
|PCIE_FW_INIT_F
))) {
6950 * We either have an Error or Initialized condition
6951 * report errors preferentially.
6954 if (pcie_fw
& PCIE_FW_ERR_F
)
6955 *state
= DEV_STATE_ERR
;
6956 else if (pcie_fw
& PCIE_FW_INIT_F
)
6957 *state
= DEV_STATE_INIT
;
6961 * If we arrived before a Master PF was selected and
6962 * there's not a valid Master PF, grab its identity
6965 if (master_mbox
== PCIE_FW_MASTER_M
&&
6966 (pcie_fw
& PCIE_FW_MASTER_VLD_F
))
6967 master_mbox
= PCIE_FW_MASTER_G(pcie_fw
);
6976 * t4_fw_bye - end communication with FW
6977 * @adap: the adapter
6978 * @mbox: mailbox to use for the FW command
6980 * Issues a command to terminate communication with FW.
6982 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
)
6984 struct fw_bye_cmd c
;
6986 memset(&c
, 0, sizeof(c
));
6987 INIT_CMD(c
, BYE
, WRITE
);
6988 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6992 * t4_init_cmd - ask FW to initialize the device
6993 * @adap: the adapter
6994 * @mbox: mailbox to use for the FW command
6996 * Issues a command to FW to partially initialize the device. This
6997 * performs initialization that generally doesn't depend on user input.
6999 int t4_early_init(struct adapter
*adap
, unsigned int mbox
)
7001 struct fw_initialize_cmd c
;
7003 memset(&c
, 0, sizeof(c
));
7004 INIT_CMD(c
, INITIALIZE
, WRITE
);
7005 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7009 * t4_fw_reset - issue a reset to FW
7010 * @adap: the adapter
7011 * @mbox: mailbox to use for the FW command
7012 * @reset: specifies the type of reset to perform
7014 * Issues a reset command of the specified type to FW.
7016 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
)
7018 struct fw_reset_cmd c
;
7020 memset(&c
, 0, sizeof(c
));
7021 INIT_CMD(c
, RESET
, WRITE
);
7022 c
.val
= cpu_to_be32(reset
);
7023 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7027 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7028 * @adap: the adapter
7029 * @mbox: mailbox to use for the FW RESET command (if desired)
7030 * @force: force uP into RESET even if FW RESET command fails
7032 * Issues a RESET command to firmware (if desired) with a HALT indication
7033 * and then puts the microprocessor into RESET state. The RESET command
7034 * will only be issued if a legitimate mailbox is provided (mbox <=
7035 * PCIE_FW_MASTER_M).
7037 * This is generally used in order for the host to safely manipulate the
7038 * adapter without fear of conflicting with whatever the firmware might
7039 * be doing. The only way out of this state is to RESTART the firmware
7042 static int t4_fw_halt(struct adapter
*adap
, unsigned int mbox
, int force
)
7047 * If a legitimate mailbox is provided, issue a RESET command
7048 * with a HALT indication.
7050 if (mbox
<= PCIE_FW_MASTER_M
) {
7051 struct fw_reset_cmd c
;
7053 memset(&c
, 0, sizeof(c
));
7054 INIT_CMD(c
, RESET
, WRITE
);
7055 c
.val
= cpu_to_be32(PIORST_F
| PIORSTMODE_F
);
7056 c
.halt_pkd
= cpu_to_be32(FW_RESET_CMD_HALT_F
);
7057 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7061 * Normally we won't complete the operation if the firmware RESET
7062 * command fails but if our caller insists we'll go ahead and put the
7063 * uP into RESET. This can be useful if the firmware is hung or even
7064 * missing ... We'll have to take the risk of putting the uP into
7065 * RESET without the cooperation of firmware in that case.
7067 * We also force the firmware's HALT flag to be on in case we bypassed
7068 * the firmware RESET command above or we're dealing with old firmware
7069 * which doesn't have the HALT capability. This will serve as a flag
7070 * for the incoming firmware to know that it's coming out of a HALT
7071 * rather than a RESET ... if it's new enough to understand that ...
7073 if (ret
== 0 || force
) {
7074 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, UPCRST_F
);
7075 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
,
7080 * And we always return the result of the firmware RESET command
7081 * even when we force the uP into RESET ...
7087 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7088 * @adap: the adapter
7089 * @mbox: mailbox to use for the FW command
7090 * @reset: if we want to do a RESET to restart things
7092 * Restart firmware previously halted by t4_fw_halt(). On successful
7093 * return the previous PF Master remains as the new PF Master and there
7094 * is no need to issue a new HELLO command, etc.
7096 * We do this in two ways:
7098 * 1. If we're dealing with newer firmware we'll simply want to take
7099 * the chip's microprocessor out of RESET. This will cause the
7100 * firmware to start up from its start vector. And then we'll loop
7101 * until the firmware indicates it's started again (PCIE_FW.HALT
7102 * reset to 0) or we timeout.
7104 * 2. If we're dealing with older firmware then we'll need to RESET
7105 * the chip since older firmware won't recognize the PCIE_FW.HALT
7106 * flag and automatically RESET itself on startup.
7108 static int t4_fw_restart(struct adapter
*adap
, unsigned int mbox
, int reset
)
7112 * Since we're directing the RESET instead of the firmware
7113 * doing it automatically, we need to clear the PCIE_FW.HALT
7116 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
, 0);
7119 * If we've been given a valid mailbox, first try to get the
7120 * firmware to do the RESET. If that works, great and we can
7121 * return success. Otherwise, if we haven't been given a
7122 * valid mailbox or the RESET command failed, fall back to
7123 * hitting the chip with a hammer.
7125 if (mbox
<= PCIE_FW_MASTER_M
) {
7126 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
7128 if (t4_fw_reset(adap
, mbox
,
7129 PIORST_F
| PIORSTMODE_F
) == 0)
7133 t4_write_reg(adap
, PL_RST_A
, PIORST_F
| PIORSTMODE_F
);
7138 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
7139 for (ms
= 0; ms
< FW_CMD_MAX_TIMEOUT
; ) {
7140 if (!(t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_HALT_F
))
7151 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7152 * @adap: the adapter
7153 * @mbox: mailbox to use for the FW RESET command (if desired)
7154 * @fw_data: the firmware image to write
7156 * @force: force upgrade even if firmware doesn't cooperate
7158 * Perform all of the steps necessary for upgrading an adapter's
7159 * firmware image. Normally this requires the cooperation of the
7160 * existing firmware in order to halt all existing activities
7161 * but if an invalid mailbox token is passed in we skip that step
7162 * (though we'll still put the adapter microprocessor into RESET in
7165 * On successful return the new firmware will have been loaded and
7166 * the adapter will have been fully RESET losing all previous setup
7167 * state. On unsuccessful return the adapter may be completely hosed ...
7168 * positive errno indicates that the adapter is ~probably~ intact, a
7169 * negative errno indicates that things are looking bad ...
7171 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
7172 const u8
*fw_data
, unsigned int size
, int force
)
7174 const struct fw_hdr
*fw_hdr
= (const struct fw_hdr
*)fw_data
;
7177 if (!t4_fw_matches_chip(adap
, fw_hdr
))
7180 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7181 * set wont be sent when we are flashing FW.
7183 adap
->flags
&= ~CXGB4_FW_OK
;
7185 ret
= t4_fw_halt(adap
, mbox
, force
);
7186 if (ret
< 0 && !force
)
7189 ret
= t4_load_fw(adap
, fw_data
, size
);
7194 * If there was a Firmware Configuration File stored in FLASH,
7195 * there's a good chance that it won't be compatible with the new
7196 * Firmware. In order to prevent difficult to diagnose adapter
7197 * initialization issues, we clear out the Firmware Configuration File
7198 * portion of the FLASH . The user will need to re-FLASH a new
7199 * Firmware Configuration File which is compatible with the new
7200 * Firmware if that's desired.
7202 (void)t4_load_cfg(adap
, NULL
, 0);
7205 * Older versions of the firmware don't understand the new
7206 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7207 * restart. So for newly loaded older firmware we'll have to do the
7208 * RESET for it so it starts up on a clean slate. We can tell if
7209 * the newly loaded firmware will handle this right by checking
7210 * its header flags to see if it advertises the capability.
7212 reset
= ((be32_to_cpu(fw_hdr
->flags
) & FW_HDR_FLAGS_RESET_HALT
) == 0);
7213 ret
= t4_fw_restart(adap
, mbox
, reset
);
7215 /* Grab potentially new Firmware Device Log parameters so we can see
7216 * how healthy the new Firmware is. It's okay to contact the new
7217 * Firmware for these parameters even though, as far as it's
7218 * concerned, we've never said "HELLO" to it ...
7220 (void)t4_init_devlog_params(adap
);
7222 adap
->flags
|= CXGB4_FW_OK
;
7227 * t4_fl_pkt_align - return the fl packet alignment
7228 * @adap: the adapter
7230 * T4 has a single field to specify the packing and padding boundary.
7231 * T5 onwards has separate fields for this and hence the alignment for
7232 * next packet offset is maximum of these two.
7235 int t4_fl_pkt_align(struct adapter
*adap
)
7237 u32 sge_control
, sge_control2
;
7238 unsigned int ingpadboundary
, ingpackboundary
, fl_align
, ingpad_shift
;
7240 sge_control
= t4_read_reg(adap
, SGE_CONTROL_A
);
7242 /* T4 uses a single control field to specify both the PCIe Padding and
7243 * Packing Boundary. T5 introduced the ability to specify these
7244 * separately. The actual Ingress Packet Data alignment boundary
7245 * within Packed Buffer Mode is the maximum of these two
7246 * specifications. (Note that it makes no real practical sense to
7247 * have the Padding Boundary be larger than the Packing Boundary but you
7248 * could set the chip up that way and, in fact, legacy T4 code would
7249 * end doing this because it would initialize the Padding Boundary and
7250 * leave the Packing Boundary initialized to 0 (16 bytes).)
7251 * Padding Boundary values in T6 starts from 8B,
7252 * where as it is 32B for T4 and T5.
7254 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
7255 ingpad_shift
= INGPADBOUNDARY_SHIFT_X
;
7257 ingpad_shift
= T6_INGPADBOUNDARY_SHIFT_X
;
7259 ingpadboundary
= 1 << (INGPADBOUNDARY_G(sge_control
) + ingpad_shift
);
7261 fl_align
= ingpadboundary
;
7262 if (!is_t4(adap
->params
.chip
)) {
7263 /* T5 has a weird interpretation of one of the PCIe Packing
7264 * Boundary values. No idea why ...
7266 sge_control2
= t4_read_reg(adap
, SGE_CONTROL2_A
);
7267 ingpackboundary
= INGPACKBOUNDARY_G(sge_control2
);
7268 if (ingpackboundary
== INGPACKBOUNDARY_16B_X
)
7269 ingpackboundary
= 16;
7271 ingpackboundary
= 1 << (ingpackboundary
+
7272 INGPACKBOUNDARY_SHIFT_X
);
7274 fl_align
= max(ingpadboundary
, ingpackboundary
);
7280 * t4_fixup_host_params - fix up host-dependent parameters
7281 * @adap: the adapter
7282 * @page_size: the host's Base Page Size
7283 * @cache_line_size: the host's Cache Line Size
7285 * Various registers in T4 contain values which are dependent on the
7286 * host's Base Page and Cache Line Sizes. This function will fix all of
7287 * those registers with the appropriate values as passed in ...
7289 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
7290 unsigned int cache_line_size
)
7292 unsigned int page_shift
= fls(page_size
) - 1;
7293 unsigned int sge_hps
= page_shift
- 10;
7294 unsigned int stat_len
= cache_line_size
> 64 ? 128 : 64;
7295 unsigned int fl_align
= cache_line_size
< 32 ? 32 : cache_line_size
;
7296 unsigned int fl_align_log
= fls(fl_align
) - 1;
7298 t4_write_reg(adap
, SGE_HOST_PAGE_SIZE_A
,
7299 HOSTPAGESIZEPF0_V(sge_hps
) |
7300 HOSTPAGESIZEPF1_V(sge_hps
) |
7301 HOSTPAGESIZEPF2_V(sge_hps
) |
7302 HOSTPAGESIZEPF3_V(sge_hps
) |
7303 HOSTPAGESIZEPF4_V(sge_hps
) |
7304 HOSTPAGESIZEPF5_V(sge_hps
) |
7305 HOSTPAGESIZEPF6_V(sge_hps
) |
7306 HOSTPAGESIZEPF7_V(sge_hps
));
7308 if (is_t4(adap
->params
.chip
)) {
7309 t4_set_reg_field(adap
, SGE_CONTROL_A
,
7310 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
7311 EGRSTATUSPAGESIZE_F
,
7312 INGPADBOUNDARY_V(fl_align_log
-
7313 INGPADBOUNDARY_SHIFT_X
) |
7314 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
7316 unsigned int pack_align
;
7317 unsigned int ingpad
, ingpack
;
7319 /* T5 introduced the separation of the Free List Padding and
7320 * Packing Boundaries. Thus, we can select a smaller Padding
7321 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7322 * Bandwidth, and use a Packing Boundary which is large enough
7323 * to avoid false sharing between CPUs, etc.
7325 * For the PCI Link, the smaller the Padding Boundary the
7326 * better. For the Memory Controller, a smaller Padding
7327 * Boundary is better until we cross under the Memory Line
7328 * Size (the minimum unit of transfer to/from Memory). If we
7329 * have a Padding Boundary which is smaller than the Memory
7330 * Line Size, that'll involve a Read-Modify-Write cycle on the
7331 * Memory Controller which is never good.
7334 /* We want the Packing Boundary to be based on the Cache Line
7335 * Size in order to help avoid False Sharing performance
7336 * issues between CPUs, etc. We also want the Packing
7337 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7338 * get best performance when the Packing Boundary is a
7339 * multiple of the Maximum Payload Size.
7341 pack_align
= fl_align
;
7342 if (pci_is_pcie(adap
->pdev
)) {
7343 unsigned int mps
, mps_log
;
7346 /* The PCIe Device Control Maximum Payload Size field
7347 * [bits 7:5] encodes sizes as powers of 2 starting at
7350 pcie_capability_read_word(adap
->pdev
, PCI_EXP_DEVCTL
,
7352 mps_log
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5) + 7;
7354 if (mps
> pack_align
)
7358 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7359 * value for the Packing Boundary. This corresponds to 16
7360 * bytes instead of the expected 32 bytes. So if we want 32
7361 * bytes, the best we can really do is 64 bytes ...
7363 if (pack_align
<= 16) {
7364 ingpack
= INGPACKBOUNDARY_16B_X
;
7366 } else if (pack_align
== 32) {
7367 ingpack
= INGPACKBOUNDARY_64B_X
;
7370 unsigned int pack_align_log
= fls(pack_align
) - 1;
7372 ingpack
= pack_align_log
- INGPACKBOUNDARY_SHIFT_X
;
7373 fl_align
= pack_align
;
7376 /* Use the smallest Ingress Padding which isn't smaller than
7377 * the Memory Controller Read/Write Size. We'll take that as
7378 * being 8 bytes since we don't know of any system with a
7379 * wider Memory Controller Bus Width.
7381 if (is_t5(adap
->params
.chip
))
7382 ingpad
= INGPADBOUNDARY_32B_X
;
7384 ingpad
= T6_INGPADBOUNDARY_8B_X
;
7386 t4_set_reg_field(adap
, SGE_CONTROL_A
,
7387 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
7388 EGRSTATUSPAGESIZE_F
,
7389 INGPADBOUNDARY_V(ingpad
) |
7390 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
7391 t4_set_reg_field(adap
, SGE_CONTROL2_A
,
7392 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M
),
7393 INGPACKBOUNDARY_V(ingpack
));
7396 * Adjust various SGE Free List Host Buffer Sizes.
7398 * This is something of a crock since we're using fixed indices into
7399 * the array which are also known by the sge.c code and the T4
7400 * Firmware Configuration File. We need to come up with a much better
7401 * approach to managing this array. For now, the first four entries
7406 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7407 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7409 * For the single-MTU buffers in unpacked mode we need to include
7410 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7411 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7412 * Padding boundary. All of these are accommodated in the Factory
7413 * Default Firmware Configuration File but we need to adjust it for
7414 * this host's cache line size.
7416 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE0_A
, page_size
);
7417 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE2_A
,
7418 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE2_A
) + fl_align
-1)
7420 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE3_A
,
7421 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE3_A
) + fl_align
-1)
7424 t4_write_reg(adap
, ULP_RX_TDDP_PSZ_A
, HPZ0_V(page_shift
- 12));
7430 * t4_fw_initialize - ask FW to initialize the device
7431 * @adap: the adapter
7432 * @mbox: mailbox to use for the FW command
7434 * Issues a command to FW to partially initialize the device. This
7435 * performs initialization that generally doesn't depend on user input.
7437 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
)
7439 struct fw_initialize_cmd c
;
7441 memset(&c
, 0, sizeof(c
));
7442 INIT_CMD(c
, INITIALIZE
, WRITE
);
7443 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7447 * t4_query_params_rw - query FW or device parameters
7448 * @adap: the adapter
7449 * @mbox: mailbox to use for the FW command
7452 * @nparams: the number of parameters
7453 * @params: the parameter names
7454 * @val: the parameter values
7455 * @rw: Write and read flag
7456 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7458 * Reads the value of FW or device parameters. Up to 7 parameters can be
7461 int t4_query_params_rw(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7462 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7463 u32
*val
, int rw
, bool sleep_ok
)
7466 struct fw_params_cmd c
;
7467 __be32
*p
= &c
.param
[0].mnem
;
7472 memset(&c
, 0, sizeof(c
));
7473 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
7474 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
7475 FW_PARAMS_CMD_PFN_V(pf
) |
7476 FW_PARAMS_CMD_VFN_V(vf
));
7477 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7479 for (i
= 0; i
< nparams
; i
++) {
7480 *p
++ = cpu_to_be32(*params
++);
7482 *p
= cpu_to_be32(*(val
+ i
));
7486 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7488 for (i
= 0, p
= &c
.param
[0].val
; i
< nparams
; i
++, p
+= 2)
7489 *val
++ = be32_to_cpu(*p
);
7493 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7494 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7497 return t4_query_params_rw(adap
, mbox
, pf
, vf
, nparams
, params
, val
, 0,
7501 int t4_query_params_ns(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7502 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7505 return t4_query_params_rw(adap
, mbox
, pf
, vf
, nparams
, params
, val
, 0,
7510 * t4_set_params_timeout - sets FW or device parameters
7511 * @adap: the adapter
7512 * @mbox: mailbox to use for the FW command
7515 * @nparams: the number of parameters
7516 * @params: the parameter names
7517 * @val: the parameter values
7518 * @timeout: the timeout time
7520 * Sets the value of FW or device parameters. Up to 7 parameters can be
7521 * specified at once.
7523 int t4_set_params_timeout(struct adapter
*adap
, unsigned int mbox
,
7524 unsigned int pf
, unsigned int vf
,
7525 unsigned int nparams
, const u32
*params
,
7526 const u32
*val
, int timeout
)
7528 struct fw_params_cmd c
;
7529 __be32
*p
= &c
.param
[0].mnem
;
7534 memset(&c
, 0, sizeof(c
));
7535 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
7536 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7537 FW_PARAMS_CMD_PFN_V(pf
) |
7538 FW_PARAMS_CMD_VFN_V(vf
));
7539 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7542 *p
++ = cpu_to_be32(*params
++);
7543 *p
++ = cpu_to_be32(*val
++);
7546 return t4_wr_mbox_timeout(adap
, mbox
, &c
, sizeof(c
), NULL
, timeout
);
7550 * t4_set_params - sets FW or device parameters
7551 * @adap: the adapter
7552 * @mbox: mailbox to use for the FW command
7555 * @nparams: the number of parameters
7556 * @params: the parameter names
7557 * @val: the parameter values
7559 * Sets the value of FW or device parameters. Up to 7 parameters can be
7560 * specified at once.
7562 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7563 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7566 return t4_set_params_timeout(adap
, mbox
, pf
, vf
, nparams
, params
, val
,
7567 FW_CMD_MAX_TIMEOUT
);
7571 * t4_cfg_pfvf - configure PF/VF resource limits
7572 * @adap: the adapter
7573 * @mbox: mailbox to use for the FW command
7574 * @pf: the PF being configured
7575 * @vf: the VF being configured
7576 * @txq: the max number of egress queues
7577 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7578 * @rxqi: the max number of interrupt-capable ingress queues
7579 * @rxq: the max number of interruptless ingress queues
7580 * @tc: the PCI traffic class
7581 * @vi: the max number of virtual interfaces
7582 * @cmask: the channel access rights mask for the PF/VF
7583 * @pmask: the port access rights mask for the PF/VF
7584 * @nexact: the maximum number of exact MPS filters
7585 * @rcaps: read capabilities
7586 * @wxcaps: write/execute capabilities
7588 * Configures resource limits and capabilities for a physical or virtual
7591 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7592 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
7593 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
7594 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
7595 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
)
7597 struct fw_pfvf_cmd c
;
7599 memset(&c
, 0, sizeof(c
));
7600 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD
) | FW_CMD_REQUEST_F
|
7601 FW_CMD_WRITE_F
| FW_PFVF_CMD_PFN_V(pf
) |
7602 FW_PFVF_CMD_VFN_V(vf
));
7603 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7604 c
.niqflint_niq
= cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi
) |
7605 FW_PFVF_CMD_NIQ_V(rxq
));
7606 c
.type_to_neq
= cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask
) |
7607 FW_PFVF_CMD_PMASK_V(pmask
) |
7608 FW_PFVF_CMD_NEQ_V(txq
));
7609 c
.tc_to_nexactf
= cpu_to_be32(FW_PFVF_CMD_TC_V(tc
) |
7610 FW_PFVF_CMD_NVI_V(vi
) |
7611 FW_PFVF_CMD_NEXACTF_V(nexact
));
7612 c
.r_caps_to_nethctrl
= cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps
) |
7613 FW_PFVF_CMD_WX_CAPS_V(wxcaps
) |
7614 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl
));
7615 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7619 * t4_alloc_vi - allocate a virtual interface
7620 * @adap: the adapter
7621 * @mbox: mailbox to use for the FW command
7622 * @port: physical port associated with the VI
7623 * @pf: the PF owning the VI
7624 * @vf: the VF owning the VI
7625 * @nmac: number of MAC addresses needed (1 to 5)
7626 * @mac: the MAC addresses of the VI
7627 * @rss_size: size of RSS table slice associated with this VI
7628 * @vivld: the destination to store the VI Valid value.
7629 * @vin: the destination to store the VIN value.
7631 * Allocates a virtual interface for the given physical port. If @mac is
7632 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7633 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7634 * stored consecutively so the space needed is @nmac * 6 bytes.
7635 * Returns a negative error number or the non-negative VI id.
7637 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
7638 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
7639 unsigned int *rss_size
, u8
*vivld
, u8
*vin
)
7644 memset(&c
, 0, sizeof(c
));
7645 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD
) | FW_CMD_REQUEST_F
|
7646 FW_CMD_WRITE_F
| FW_CMD_EXEC_F
|
7647 FW_VI_CMD_PFN_V(pf
) | FW_VI_CMD_VFN_V(vf
));
7648 c
.alloc_to_len16
= cpu_to_be32(FW_VI_CMD_ALLOC_F
| FW_LEN16(c
));
7649 c
.portid_pkd
= FW_VI_CMD_PORTID_V(port
);
7652 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
7657 memcpy(mac
, c
.mac
, sizeof(c
.mac
));
7660 memcpy(mac
+ 24, c
.nmac3
, sizeof(c
.nmac3
));
7663 memcpy(mac
+ 18, c
.nmac2
, sizeof(c
.nmac2
));
7666 memcpy(mac
+ 12, c
.nmac1
, sizeof(c
.nmac1
));
7669 memcpy(mac
+ 6, c
.nmac0
, sizeof(c
.nmac0
));
7673 *rss_size
= FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c
.rsssize_pkd
));
7676 *vivld
= FW_VI_CMD_VFVLD_G(be32_to_cpu(c
.alloc_to_len16
));
7679 *vin
= FW_VI_CMD_VIN_G(be32_to_cpu(c
.alloc_to_len16
));
7681 return FW_VI_CMD_VIID_G(be16_to_cpu(c
.type_viid
));
7685 * t4_free_vi - free a virtual interface
7686 * @adap: the adapter
7687 * @mbox: mailbox to use for the FW command
7688 * @pf: the PF owning the VI
7689 * @vf: the VF owning the VI
7690 * @viid: virtual interface identifiler
7692 * Free a previously allocated virtual interface.
7694 int t4_free_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7695 unsigned int vf
, unsigned int viid
)
7699 memset(&c
, 0, sizeof(c
));
7700 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD
) |
7703 FW_VI_CMD_PFN_V(pf
) |
7704 FW_VI_CMD_VFN_V(vf
));
7705 c
.alloc_to_len16
= cpu_to_be32(FW_VI_CMD_FREE_F
| FW_LEN16(c
));
7706 c
.type_viid
= cpu_to_be16(FW_VI_CMD_VIID_V(viid
));
7708 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
7712 * t4_set_rxmode - set Rx properties of a virtual interface
7713 * @adap: the adapter
7714 * @mbox: mailbox to use for the FW command
7716 * @viid_mirror: the mirror VI id
7717 * @mtu: the new MTU or -1
7718 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7719 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7720 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7721 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7722 * @sleep_ok: if true we may sleep while awaiting command completion
7724 * Sets Rx properties of a virtual interface.
7726 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
7727 unsigned int viid_mirror
, int mtu
, int promisc
, int all_multi
,
7728 int bcast
, int vlanex
, bool sleep_ok
)
7730 struct fw_vi_rxmode_cmd c
, c_mirror
;
7733 /* convert to FW values */
7735 mtu
= FW_RXMODE_MTU_NO_CHG
;
7737 promisc
= FW_VI_RXMODE_CMD_PROMISCEN_M
;
7739 all_multi
= FW_VI_RXMODE_CMD_ALLMULTIEN_M
;
7741 bcast
= FW_VI_RXMODE_CMD_BROADCASTEN_M
;
7743 vlanex
= FW_VI_RXMODE_CMD_VLANEXEN_M
;
7745 memset(&c
, 0, sizeof(c
));
7746 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD
) |
7747 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7748 FW_VI_RXMODE_CMD_VIID_V(viid
));
7749 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7751 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu
) |
7752 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc
) |
7753 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi
) |
7754 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast
) |
7755 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex
));
7758 memcpy(&c_mirror
, &c
, sizeof(c_mirror
));
7759 c_mirror
.op_to_viid
=
7760 cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD
) |
7761 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7762 FW_VI_RXMODE_CMD_VIID_V(viid_mirror
));
7765 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
7770 ret
= t4_wr_mbox_meat(adap
, mbox
, &c_mirror
, sizeof(c_mirror
),
7777 * t4_free_encap_mac_filt - frees MPS entry at given index
7778 * @adap: the adapter
7780 * @idx: index of MPS entry to be freed
7781 * @sleep_ok: call is allowed to sleep
7783 * Frees the MPS entry at supplied index
7785 * Returns a negative error number or zero on success
7787 int t4_free_encap_mac_filt(struct adapter
*adap
, unsigned int viid
,
7788 int idx
, bool sleep_ok
)
7790 struct fw_vi_mac_exact
*p
;
7791 u8 addr
[] = {0, 0, 0, 0, 0, 0};
7792 struct fw_vi_mac_cmd c
;
7796 memset(&c
, 0, sizeof(c
));
7797 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7798 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7800 FW_VI_MAC_CMD_VIID_V(viid
));
7801 exact
= FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC
);
7802 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7806 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7807 FW_VI_MAC_CMD_IDX_V(idx
));
7808 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7809 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7814 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7815 * @adap: the adapter
7817 * @addr: the MAC address
7819 * @idx: index of the entry in mps tcam
7820 * @lookup_type: MAC address for inner (1) or outer (0) header
7821 * @port_id: the port index
7822 * @sleep_ok: call is allowed to sleep
7824 * Removes the mac entry at the specified index using raw mac interface.
7826 * Returns a negative error number on failure.
7828 int t4_free_raw_mac_filt(struct adapter
*adap
, unsigned int viid
,
7829 const u8
*addr
, const u8
*mask
, unsigned int idx
,
7830 u8 lookup_type
, u8 port_id
, bool sleep_ok
)
7832 struct fw_vi_mac_cmd c
;
7833 struct fw_vi_mac_raw
*p
= &c
.u
.raw
;
7836 memset(&c
, 0, sizeof(c
));
7837 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7838 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7840 FW_VI_MAC_CMD_VIID_V(viid
));
7841 val
= FW_CMD_LEN16_V(1) |
7842 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW
);
7843 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7844 FW_CMD_LEN16_V(val
));
7846 p
->raw_idx_pkd
= cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx
) |
7847 FW_VI_MAC_ID_BASED_FREE
);
7849 /* Lookup Type. Outer header: 0, Inner header: 1 */
7850 p
->data0_pkd
= cpu_to_be32(DATALKPTYPE_V(lookup_type
) |
7851 DATAPORTNUM_V(port_id
));
7852 /* Lookup mask and port mask */
7853 p
->data0m_pkd
= cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M
) |
7854 DATAPORTNUM_V(DATAPORTNUM_M
));
7856 /* Copy the address and the mask */
7857 memcpy((u8
*)&p
->data1
[0] + 2, addr
, ETH_ALEN
);
7858 memcpy((u8
*)&p
->data1m
[0] + 2, mask
, ETH_ALEN
);
7860 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7864 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7865 * @adap: the adapter
7867 * @addr: the MAC address
7869 * @vni: the VNI id for the tunnel protocol
7870 * @vni_mask: mask for the VNI id
7871 * @dip_hit: to enable DIP match for the MPS entry
7872 * @lookup_type: MAC address for inner (1) or outer (0) header
7873 * @sleep_ok: call is allowed to sleep
7875 * Allocates an MPS entry with specified MAC address and VNI value.
7877 * Returns a negative error number or the allocated index for this mac.
7879 int t4_alloc_encap_mac_filt(struct adapter
*adap
, unsigned int viid
,
7880 const u8
*addr
, const u8
*mask
, unsigned int vni
,
7881 unsigned int vni_mask
, u8 dip_hit
, u8 lookup_type
,
7884 struct fw_vi_mac_cmd c
;
7885 struct fw_vi_mac_vni
*p
= c
.u
.exact_vni
;
7889 memset(&c
, 0, sizeof(c
));
7890 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7891 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7892 FW_VI_MAC_CMD_VIID_V(viid
));
7893 val
= FW_CMD_LEN16_V(1) |
7894 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI
);
7895 c
.freemacs_to_len16
= cpu_to_be32(val
);
7896 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7897 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC
));
7898 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7899 memcpy(p
->macaddr_mask
, mask
, sizeof(p
->macaddr_mask
));
7901 p
->lookup_type_to_vni
=
7902 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni
) |
7903 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit
) |
7904 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type
));
7905 p
->vni_mask_pkd
= cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask
));
7906 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7908 ret
= FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p
->valid_to_idx
));
7913 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7914 * @adap: the adapter
7916 * @addr: the MAC address
7918 * @idx: index at which to add this entry
7919 * @lookup_type: MAC address for inner (1) or outer (0) header
7920 * @port_id: the port index
7921 * @sleep_ok: call is allowed to sleep
7923 * Adds the mac entry at the specified index using raw mac interface.
7925 * Returns a negative error number or the allocated index for this mac.
7927 int t4_alloc_raw_mac_filt(struct adapter
*adap
, unsigned int viid
,
7928 const u8
*addr
, const u8
*mask
, unsigned int idx
,
7929 u8 lookup_type
, u8 port_id
, bool sleep_ok
)
7932 struct fw_vi_mac_cmd c
;
7933 struct fw_vi_mac_raw
*p
= &c
.u
.raw
;
7936 memset(&c
, 0, sizeof(c
));
7937 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7938 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7939 FW_VI_MAC_CMD_VIID_V(viid
));
7940 val
= FW_CMD_LEN16_V(1) |
7941 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW
);
7942 c
.freemacs_to_len16
= cpu_to_be32(val
);
7944 /* Specify that this is an inner mac address */
7945 p
->raw_idx_pkd
= cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx
));
7947 /* Lookup Type. Outer header: 0, Inner header: 1 */
7948 p
->data0_pkd
= cpu_to_be32(DATALKPTYPE_V(lookup_type
) |
7949 DATAPORTNUM_V(port_id
));
7950 /* Lookup mask and port mask */
7951 p
->data0m_pkd
= cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M
) |
7952 DATAPORTNUM_V(DATAPORTNUM_M
));
7954 /* Copy the address and the mask */
7955 memcpy((u8
*)&p
->data1
[0] + 2, addr
, ETH_ALEN
);
7956 memcpy((u8
*)&p
->data1m
[0] + 2, mask
, ETH_ALEN
);
7958 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7960 ret
= FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p
->raw_idx_pkd
));
7969 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7970 * @adap: the adapter
7971 * @mbox: mailbox to use for the FW command
7973 * @free: if true any existing filters for this VI id are first removed
7974 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7975 * @addr: the MAC address(es)
7976 * @idx: where to store the index of each allocated filter
7977 * @hash: pointer to hash address filter bitmap
7978 * @sleep_ok: call is allowed to sleep
7980 * Allocates an exact-match filter for each of the supplied addresses and
7981 * sets it to the corresponding address. If @idx is not %NULL it should
7982 * have at least @naddr entries, each of which will be set to the index of
7983 * the filter allocated for the corresponding MAC address. If a filter
7984 * could not be allocated for an address its index is set to 0xffff.
7985 * If @hash is not %NULL addresses that fail to allocate an exact filter
7986 * are hashed and update the hash filter bitmap pointed at by @hash.
7988 * Returns a negative error number or the number of filters allocated.
7990 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
7991 unsigned int viid
, bool free
, unsigned int naddr
,
7992 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
)
7994 int offset
, ret
= 0;
7995 struct fw_vi_mac_cmd c
;
7996 unsigned int nfilters
= 0;
7997 unsigned int max_naddr
= adap
->params
.arch
.mps_tcam_size
;
7998 unsigned int rem
= naddr
;
8000 if (naddr
> max_naddr
)
8003 for (offset
= 0; offset
< naddr
; /**/) {
8004 unsigned int fw_naddr
= (rem
< ARRAY_SIZE(c
.u
.exact
) ?
8005 rem
: ARRAY_SIZE(c
.u
.exact
));
8006 size_t len16
= DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd
,
8007 u
.exact
[fw_naddr
]), 16);
8008 struct fw_vi_mac_exact
*p
;
8011 memset(&c
, 0, sizeof(c
));
8012 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8015 FW_CMD_EXEC_V(free
) |
8016 FW_VI_MAC_CMD_VIID_V(viid
));
8017 c
.freemacs_to_len16
=
8018 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free
) |
8019 FW_CMD_LEN16_V(len16
));
8021 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
8023 cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
8024 FW_VI_MAC_CMD_IDX_V(
8025 FW_VI_MAC_ADD_MAC
));
8026 memcpy(p
->macaddr
, addr
[offset
+ i
],
8027 sizeof(p
->macaddr
));
8030 /* It's okay if we run out of space in our MAC address arena.
8031 * Some of the addresses we submit may get stored so we need
8032 * to run through the reply to see what the results were ...
8034 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
8035 if (ret
&& ret
!= -FW_ENOMEM
)
8038 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
8039 u16 index
= FW_VI_MAC_CMD_IDX_G(
8040 be16_to_cpu(p
->valid_to_idx
));
8043 idx
[offset
+ i
] = (index
>= max_naddr
?
8045 if (index
< max_naddr
)
8049 hash_mac_addr(addr
[offset
+ i
]));
8057 if (ret
== 0 || ret
== -FW_ENOMEM
)
8063 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8064 * @adap: the adapter
8065 * @mbox: mailbox to use for the FW command
8067 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8068 * @addr: the MAC address(es)
8069 * @sleep_ok: call is allowed to sleep
8071 * Frees the exact-match filter for each of the supplied addresses
8073 * Returns a negative error number or the number of filters freed.
8075 int t4_free_mac_filt(struct adapter
*adap
, unsigned int mbox
,
8076 unsigned int viid
, unsigned int naddr
,
8077 const u8
**addr
, bool sleep_ok
)
8079 int offset
, ret
= 0;
8080 struct fw_vi_mac_cmd c
;
8081 unsigned int nfilters
= 0;
8082 unsigned int max_naddr
= is_t4(adap
->params
.chip
) ?
8083 NUM_MPS_CLS_SRAM_L_INSTANCES
:
8084 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
8085 unsigned int rem
= naddr
;
8087 if (naddr
> max_naddr
)
8090 for (offset
= 0; offset
< (int)naddr
; /**/) {
8091 unsigned int fw_naddr
= (rem
< ARRAY_SIZE(c
.u
.exact
)
8093 : ARRAY_SIZE(c
.u
.exact
));
8094 size_t len16
= DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd
,
8095 u
.exact
[fw_naddr
]), 16);
8096 struct fw_vi_mac_exact
*p
;
8099 memset(&c
, 0, sizeof(c
));
8100 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8104 FW_VI_MAC_CMD_VIID_V(viid
));
8105 c
.freemacs_to_len16
=
8106 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8107 FW_CMD_LEN16_V(len16
));
8109 for (i
= 0, p
= c
.u
.exact
; i
< (int)fw_naddr
; i
++, p
++) {
8110 p
->valid_to_idx
= cpu_to_be16(
8111 FW_VI_MAC_CMD_VALID_F
|
8112 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE
));
8113 memcpy(p
->macaddr
, addr
[offset
+i
], sizeof(p
->macaddr
));
8116 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
8120 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
8121 u16 index
= FW_VI_MAC_CMD_IDX_G(
8122 be16_to_cpu(p
->valid_to_idx
));
8124 if (index
< max_naddr
)
8138 * t4_change_mac - modifies the exact-match filter for a MAC address
8139 * @adap: the adapter
8140 * @mbox: mailbox to use for the FW command
8142 * @idx: index of existing filter for old value of MAC address, or -1
8143 * @addr: the new MAC address value
8144 * @persist: whether a new MAC allocation should be persistent
8145 * @smt_idx: the destination to store the new SMT index.
8147 * Modifies an exact-match filter and sets it to the new MAC address.
8148 * Note that in general it is not possible to modify the value of a given
8149 * filter so the generic way to modify an address filter is to free the one
8150 * being used by the old address value and allocate a new filter for the
8151 * new address value. @idx can be -1 if the address is a new addition.
8153 * Returns a negative error number or the index of the filter with the new
8156 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8157 int idx
, const u8
*addr
, bool persist
, u8
*smt_idx
)
8160 struct fw_vi_mac_cmd c
;
8161 struct fw_vi_mac_exact
*p
= c
.u
.exact
;
8162 unsigned int max_mac_addr
= adap
->params
.arch
.mps_tcam_size
;
8164 if (idx
< 0) /* new allocation */
8165 idx
= persist
? FW_VI_MAC_ADD_PERSIST_MAC
: FW_VI_MAC_ADD_MAC
;
8166 mode
= smt_idx
? FW_VI_MAC_SMT_AND_MPSTCAM
: FW_VI_MAC_MPS_TCAM_ENTRY
;
8168 memset(&c
, 0, sizeof(c
));
8169 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8170 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
8171 FW_VI_MAC_CMD_VIID_V(viid
));
8172 c
.freemacs_to_len16
= cpu_to_be32(FW_CMD_LEN16_V(1));
8173 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
8174 FW_VI_MAC_CMD_SMAC_RESULT_V(mode
) |
8175 FW_VI_MAC_CMD_IDX_V(idx
));
8176 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
8178 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
8180 ret
= FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p
->valid_to_idx
));
8181 if (ret
>= max_mac_addr
)
8184 if (adap
->params
.viid_smt_extn_support
) {
8185 *smt_idx
= FW_VI_MAC_CMD_SMTID_G
8186 (be32_to_cpu(c
.op_to_viid
));
8188 /* In T4/T5, SMT contains 256 SMAC entries
8189 * organized in 128 rows of 2 entries each.
8190 * In T6, SMT contains 256 SMAC entries in
8193 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <=
8195 *smt_idx
= (viid
& FW_VIID_VIN_M
) << 1;
8197 *smt_idx
= (viid
& FW_VIID_VIN_M
);
8205 * t4_set_addr_hash - program the MAC inexact-match hash filter
8206 * @adap: the adapter
8207 * @mbox: mailbox to use for the FW command
8209 * @ucast: whether the hash filter should also match unicast addresses
8210 * @vec: the value to be written to the hash filter
8211 * @sleep_ok: call is allowed to sleep
8213 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8215 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8216 bool ucast
, u64 vec
, bool sleep_ok
)
8218 struct fw_vi_mac_cmd c
;
8220 memset(&c
, 0, sizeof(c
));
8221 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8222 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
8223 FW_VI_ENABLE_CMD_VIID_V(viid
));
8224 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F
|
8225 FW_VI_MAC_CMD_HASHUNIEN_V(ucast
) |
8227 c
.u
.hash
.hashvec
= cpu_to_be64(vec
);
8228 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
8232 * t4_enable_vi_params - enable/disable a virtual interface
8233 * @adap: the adapter
8234 * @mbox: mailbox to use for the FW command
8236 * @rx_en: 1=enable Rx, 0=disable Rx
8237 * @tx_en: 1=enable Tx, 0=disable Tx
8238 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8240 * Enables/disables a virtual interface. Note that setting DCB Enable
8241 * only makes sense when enabling a Virtual Interface ...
8243 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
8244 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
)
8246 struct fw_vi_enable_cmd c
;
8248 memset(&c
, 0, sizeof(c
));
8249 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) |
8250 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8251 FW_VI_ENABLE_CMD_VIID_V(viid
));
8252 c
.ien_to_len16
= cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en
) |
8253 FW_VI_ENABLE_CMD_EEN_V(tx_en
) |
8254 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en
) |
8256 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
8260 * t4_enable_vi - enable/disable a virtual interface
8261 * @adap: the adapter
8262 * @mbox: mailbox to use for the FW command
8264 * @rx_en: 1=enable Rx, 0=disable Rx
8265 * @tx_en: 1=enable Tx, 0=disable Tx
8267 * Enables/disables a virtual interface.
8269 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8270 bool rx_en
, bool tx_en
)
8272 return t4_enable_vi_params(adap
, mbox
, viid
, rx_en
, tx_en
, 0);
8276 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8277 * @adap: the adapter
8278 * @mbox: mailbox to use for the FW command
8279 * @pi: the Port Information structure
8280 * @rx_en: 1=enable Rx, 0=disable Rx
8281 * @tx_en: 1=enable Tx, 0=disable Tx
8282 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8284 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8285 * Enable only makes sense when enabling a Virtual Interface ...
8286 * If the Virtual Interface enable/disable operation is successful,
8287 * we notify the OS-specific code of a potential Link Status change
8288 * via the OS Contract API t4_os_link_changed().
8290 int t4_enable_pi_params(struct adapter
*adap
, unsigned int mbox
,
8291 struct port_info
*pi
,
8292 bool rx_en
, bool tx_en
, bool dcb_en
)
8294 int ret
= t4_enable_vi_params(adap
, mbox
, pi
->viid
,
8295 rx_en
, tx_en
, dcb_en
);
8298 t4_os_link_changed(adap
, pi
->port_id
,
8299 rx_en
&& tx_en
&& pi
->link_cfg
.link_ok
);
8304 * t4_identify_port - identify a VI's port by blinking its LED
8305 * @adap: the adapter
8306 * @mbox: mailbox to use for the FW command
8308 * @nblinks: how many times to blink LED at 2.5 Hz
8310 * Identifies a VI's port by blinking its LED.
8312 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8313 unsigned int nblinks
)
8315 struct fw_vi_enable_cmd c
;
8317 memset(&c
, 0, sizeof(c
));
8318 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) |
8319 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8320 FW_VI_ENABLE_CMD_VIID_V(viid
));
8321 c
.ien_to_len16
= cpu_to_be32(FW_VI_ENABLE_CMD_LED_F
| FW_LEN16(c
));
8322 c
.blinkdur
= cpu_to_be16(nblinks
);
8323 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8327 * t4_iq_stop - stop an ingress queue and its FLs
8328 * @adap: the adapter
8329 * @mbox: mailbox to use for the FW command
8330 * @pf: the PF owning the queues
8331 * @vf: the VF owning the queues
8332 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8333 * @iqid: ingress queue id
8334 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8335 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8337 * Stops an ingress queue and its associated FLs, if any. This causes
8338 * any current or future data/messages destined for these queues to be
8341 int t4_iq_stop(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8342 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
8343 unsigned int fl0id
, unsigned int fl1id
)
8347 memset(&c
, 0, sizeof(c
));
8348 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
8349 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
8350 FW_IQ_CMD_VFN_V(vf
));
8351 c
.alloc_to_len16
= cpu_to_be32(FW_IQ_CMD_IQSTOP_F
| FW_LEN16(c
));
8352 c
.type_to_iqandstindex
= cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype
));
8353 c
.iqid
= cpu_to_be16(iqid
);
8354 c
.fl0id
= cpu_to_be16(fl0id
);
8355 c
.fl1id
= cpu_to_be16(fl1id
);
8356 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8360 * t4_iq_free - free an ingress queue and its FLs
8361 * @adap: the adapter
8362 * @mbox: mailbox to use for the FW command
8363 * @pf: the PF owning the queues
8364 * @vf: the VF owning the queues
8365 * @iqtype: the ingress queue type
8366 * @iqid: ingress queue id
8367 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8368 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8370 * Frees an ingress queue and its associated FLs, if any.
8372 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8373 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
8374 unsigned int fl0id
, unsigned int fl1id
)
8378 memset(&c
, 0, sizeof(c
));
8379 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
8380 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
8381 FW_IQ_CMD_VFN_V(vf
));
8382 c
.alloc_to_len16
= cpu_to_be32(FW_IQ_CMD_FREE_F
| FW_LEN16(c
));
8383 c
.type_to_iqandstindex
= cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype
));
8384 c
.iqid
= cpu_to_be16(iqid
);
8385 c
.fl0id
= cpu_to_be16(fl0id
);
8386 c
.fl1id
= cpu_to_be16(fl1id
);
8387 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8391 * t4_eth_eq_free - free an Ethernet egress queue
8392 * @adap: the adapter
8393 * @mbox: mailbox to use for the FW command
8394 * @pf: the PF owning the queue
8395 * @vf: the VF owning the queue
8396 * @eqid: egress queue id
8398 * Frees an Ethernet egress queue.
8400 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8401 unsigned int vf
, unsigned int eqid
)
8403 struct fw_eq_eth_cmd c
;
8405 memset(&c
, 0, sizeof(c
));
8406 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD
) |
8407 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8408 FW_EQ_ETH_CMD_PFN_V(pf
) |
8409 FW_EQ_ETH_CMD_VFN_V(vf
));
8410 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_ETH_CMD_FREE_F
| FW_LEN16(c
));
8411 c
.eqid_pkd
= cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid
));
8412 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8416 * t4_ctrl_eq_free - free a control egress queue
8417 * @adap: the adapter
8418 * @mbox: mailbox to use for the FW command
8419 * @pf: the PF owning the queue
8420 * @vf: the VF owning the queue
8421 * @eqid: egress queue id
8423 * Frees a control egress queue.
8425 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8426 unsigned int vf
, unsigned int eqid
)
8428 struct fw_eq_ctrl_cmd c
;
8430 memset(&c
, 0, sizeof(c
));
8431 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD
) |
8432 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8433 FW_EQ_CTRL_CMD_PFN_V(pf
) |
8434 FW_EQ_CTRL_CMD_VFN_V(vf
));
8435 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F
| FW_LEN16(c
));
8436 c
.cmpliqid_eqid
= cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid
));
8437 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8441 * t4_ofld_eq_free - free an offload egress queue
8442 * @adap: the adapter
8443 * @mbox: mailbox to use for the FW command
8444 * @pf: the PF owning the queue
8445 * @vf: the VF owning the queue
8446 * @eqid: egress queue id
8448 * Frees a control egress queue.
8450 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8451 unsigned int vf
, unsigned int eqid
)
8453 struct fw_eq_ofld_cmd c
;
8455 memset(&c
, 0, sizeof(c
));
8456 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) |
8457 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8458 FW_EQ_OFLD_CMD_PFN_V(pf
) |
8459 FW_EQ_OFLD_CMD_VFN_V(vf
));
8460 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F
| FW_LEN16(c
));
8461 c
.eqid_pkd
= cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid
));
8462 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8466 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8467 * @link_down_rc: Link Down Reason Code
8469 * Returns a string representation of the Link Down Reason Code.
8471 static const char *t4_link_down_rc_str(unsigned char link_down_rc
)
8473 static const char * const reason
[] = {
8476 "Auto-negotiation Failure",
8478 "Insufficient Airflow",
8479 "Unable To Determine Reason",
8480 "No RX Signal Detected",
8484 if (link_down_rc
>= ARRAY_SIZE(reason
))
8485 return "Bad Reason Code";
8487 return reason
[link_down_rc
];
8490 /* Return the highest speed set in the port capabilities, in Mb/s. */
8491 static unsigned int fwcap_to_speed(fw_port_cap32_t caps
)
8493 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8495 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8499 TEST_SPEED_RETURN(400G
, 400000);
8500 TEST_SPEED_RETURN(200G
, 200000);
8501 TEST_SPEED_RETURN(100G
, 100000);
8502 TEST_SPEED_RETURN(50G
, 50000);
8503 TEST_SPEED_RETURN(40G
, 40000);
8504 TEST_SPEED_RETURN(25G
, 25000);
8505 TEST_SPEED_RETURN(10G
, 10000);
8506 TEST_SPEED_RETURN(1G
, 1000);
8507 TEST_SPEED_RETURN(100M
, 100);
8509 #undef TEST_SPEED_RETURN
8515 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8516 * @acaps: advertised Port Capabilities
8518 * Get the highest speed for the port from the advertised Port
8519 * Capabilities. It will be either the highest speed from the list of
8520 * speeds or whatever user has set using ethtool.
8522 static fw_port_cap32_t
fwcap_to_fwspeed(fw_port_cap32_t acaps
)
8524 #define TEST_SPEED_RETURN(__caps_speed) \
8526 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8527 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8530 TEST_SPEED_RETURN(400G
);
8531 TEST_SPEED_RETURN(200G
);
8532 TEST_SPEED_RETURN(100G
);
8533 TEST_SPEED_RETURN(50G
);
8534 TEST_SPEED_RETURN(40G
);
8535 TEST_SPEED_RETURN(25G
);
8536 TEST_SPEED_RETURN(10G
);
8537 TEST_SPEED_RETURN(1G
);
8538 TEST_SPEED_RETURN(100M
);
8540 #undef TEST_SPEED_RETURN
8546 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8547 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8549 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8550 * 32-bit Port Capabilities value.
8552 static fw_port_cap32_t
lstatus_to_fwcap(u32 lstatus
)
8554 fw_port_cap32_t linkattr
= 0;
8556 /* Unfortunately the format of the Link Status in the old
8557 * 16-bit Port Information message isn't the same as the
8558 * 16-bit Port Capabilities bitfield used everywhere else ...
8560 if (lstatus
& FW_PORT_CMD_RXPAUSE_F
)
8561 linkattr
|= FW_PORT_CAP32_FC_RX
;
8562 if (lstatus
& FW_PORT_CMD_TXPAUSE_F
)
8563 linkattr
|= FW_PORT_CAP32_FC_TX
;
8564 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M
))
8565 linkattr
|= FW_PORT_CAP32_SPEED_100M
;
8566 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G
))
8567 linkattr
|= FW_PORT_CAP32_SPEED_1G
;
8568 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G
))
8569 linkattr
|= FW_PORT_CAP32_SPEED_10G
;
8570 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G
))
8571 linkattr
|= FW_PORT_CAP32_SPEED_25G
;
8572 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G
))
8573 linkattr
|= FW_PORT_CAP32_SPEED_40G
;
8574 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G
))
8575 linkattr
|= FW_PORT_CAP32_SPEED_100G
;
8581 * t4_handle_get_port_info - process a FW reply message
8582 * @pi: the port info
8583 * @rpl: start of the FW message
8585 * Processes a GET_PORT_INFO FW reply message.
8587 void t4_handle_get_port_info(struct port_info
*pi
, const __be64
*rpl
)
8589 const struct fw_port_cmd
*cmd
= (const void *)rpl
;
8590 fw_port_cap32_t pcaps
, acaps
, lpacaps
, linkattr
;
8591 struct link_config
*lc
= &pi
->link_cfg
;
8592 struct adapter
*adapter
= pi
->adapter
;
8593 unsigned int speed
, fc
, fec
, adv_fc
;
8594 enum fw_port_module_type mod_type
;
8595 int action
, link_ok
, linkdnrc
;
8596 enum fw_port_type port_type
;
8598 /* Extract the various fields from the Port Information message.
8600 action
= FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd
->action_to_len16
));
8602 case FW_PORT_ACTION_GET_PORT_INFO
: {
8603 u32 lstatus
= be32_to_cpu(cmd
->u
.info
.lstatus_to_modtype
);
8605 link_ok
= (lstatus
& FW_PORT_CMD_LSTATUS_F
) != 0;
8606 linkdnrc
= FW_PORT_CMD_LINKDNRC_G(lstatus
);
8607 port_type
= FW_PORT_CMD_PTYPE_G(lstatus
);
8608 mod_type
= FW_PORT_CMD_MODTYPE_G(lstatus
);
8609 pcaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.pcap
));
8610 acaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.acap
));
8611 lpacaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.lpacap
));
8612 linkattr
= lstatus_to_fwcap(lstatus
);
8616 case FW_PORT_ACTION_GET_PORT_INFO32
: {
8619 lstatus32
= be32_to_cpu(cmd
->u
.info32
.lstatus32_to_cbllen32
);
8620 link_ok
= (lstatus32
& FW_PORT_CMD_LSTATUS32_F
) != 0;
8621 linkdnrc
= FW_PORT_CMD_LINKDNRC32_G(lstatus32
);
8622 port_type
= FW_PORT_CMD_PORTTYPE32_G(lstatus32
);
8623 mod_type
= FW_PORT_CMD_MODTYPE32_G(lstatus32
);
8624 pcaps
= be32_to_cpu(cmd
->u
.info32
.pcaps32
);
8625 acaps
= be32_to_cpu(cmd
->u
.info32
.acaps32
);
8626 lpacaps
= be32_to_cpu(cmd
->u
.info32
.lpacaps32
);
8627 linkattr
= be32_to_cpu(cmd
->u
.info32
.linkattr32
);
8632 dev_err(adapter
->pdev_dev
, "Handle Port Information: Bad Command/Action %#x\n",
8633 be32_to_cpu(cmd
->action_to_len16
));
8637 fec
= fwcap_to_cc_fec(acaps
);
8638 adv_fc
= fwcap_to_cc_pause(acaps
);
8639 fc
= fwcap_to_cc_pause(linkattr
);
8640 speed
= fwcap_to_speed(linkattr
);
8642 /* Reset state for communicating new Transceiver Module status and
8643 * whether the OS-dependent layer wants us to redo the current
8644 * "sticky" L1 Configure Link Parameters.
8646 lc
->new_module
= false;
8647 lc
->redo_l1cfg
= false;
8649 if (mod_type
!= pi
->mod_type
) {
8650 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8651 * various fundamental Port Capabilities which used to be
8652 * immutable can now change radically. We can now have
8653 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8654 * all change based on what Transceiver Module is inserted.
8655 * So we need to record the Physical "Port" Capabilities on
8656 * every Transceiver Module change.
8660 /* When a new Transceiver Module is inserted, the Firmware
8661 * will examine its i2c EPROM to determine its type and
8662 * general operating parameters including things like Forward
8663 * Error Control, etc. Various IEEE 802.3 standards dictate
8664 * how to interpret these i2c values to determine default
8665 * "sutomatic" settings. We record these for future use when
8666 * the user explicitly requests these standards-based values.
8668 lc
->def_acaps
= acaps
;
8670 /* Some versions of the early T6 Firmware "cheated" when
8671 * handling different Transceiver Modules by changing the
8672 * underlaying Port Type reported to the Host Drivers. As
8673 * such we need to capture whatever Port Type the Firmware
8674 * sends us and record it in case it's different from what we
8675 * were told earlier. Unfortunately, since Firmware is
8676 * forever, we'll need to keep this code here forever, but in
8677 * later T6 Firmware it should just be an assignment of the
8678 * same value already recorded.
8680 pi
->port_type
= port_type
;
8682 /* Record new Module Type information.
8684 pi
->mod_type
= mod_type
;
8686 /* Let the OS-dependent layer know if we have a new
8687 * Transceiver Module inserted.
8689 lc
->new_module
= t4_is_inserted_mod_type(mod_type
);
8691 t4_os_portmod_changed(adapter
, pi
->port_id
);
8694 if (link_ok
!= lc
->link_ok
|| speed
!= lc
->speed
||
8695 fc
!= lc
->fc
|| adv_fc
!= lc
->advertised_fc
||
8697 /* something changed */
8698 if (!link_ok
&& lc
->link_ok
) {
8699 lc
->link_down_rc
= linkdnrc
;
8700 dev_warn_ratelimited(adapter
->pdev_dev
,
8701 "Port %d link down, reason: %s\n",
8703 t4_link_down_rc_str(linkdnrc
));
8705 lc
->link_ok
= link_ok
;
8707 lc
->advertised_fc
= adv_fc
;
8711 lc
->lpacaps
= lpacaps
;
8712 lc
->acaps
= acaps
& ADVERT_MASK
;
8714 /* If we're not physically capable of Auto-Negotiation, note
8715 * this as Auto-Negotiation disabled. Otherwise, we track
8716 * what Auto-Negotiation settings we have. Note parallel
8717 * structure in t4_link_l1cfg_core() and init_link_config().
8719 if (!(lc
->acaps
& FW_PORT_CAP32_ANEG
)) {
8720 lc
->autoneg
= AUTONEG_DISABLE
;
8721 } else if (lc
->acaps
& FW_PORT_CAP32_ANEG
) {
8722 lc
->autoneg
= AUTONEG_ENABLE
;
8724 /* When Autoneg is disabled, user needs to set
8726 * Similar to cxgb4_ethtool.c: set_link_ksettings
8729 lc
->speed_caps
= fwcap_to_fwspeed(acaps
);
8730 lc
->autoneg
= AUTONEG_DISABLE
;
8733 t4_os_link_changed(adapter
, pi
->port_id
, link_ok
);
8736 /* If we have a new Transceiver Module and the OS-dependent code has
8737 * told us that it wants us to redo whatever "sticky" L1 Configuration
8738 * Link Parameters are set, do that now.
8740 if (lc
->new_module
&& lc
->redo_l1cfg
) {
8741 struct link_config old_lc
;
8744 /* Save the current L1 Configuration and restore it if an
8745 * error occurs. We probably should fix the l1_cfg*()
8746 * routines not to change the link_config when an error
8750 ret
= t4_link_l1cfg_ns(adapter
, adapter
->mbox
, pi
->lport
, lc
);
8753 dev_warn(adapter
->pdev_dev
,
8754 "Attempt to update new Transceiver Module settings failed\n");
8757 lc
->new_module
= false;
8758 lc
->redo_l1cfg
= false;
8762 * t4_update_port_info - retrieve and update port information if changed
8763 * @pi: the port_info
8765 * We issue a Get Port Information Command to the Firmware and, if
8766 * successful, we check to see if anything is different from what we
8767 * last recorded and update things accordingly.
8769 int t4_update_port_info(struct port_info
*pi
)
8771 unsigned int fw_caps
= pi
->adapter
->params
.fw_caps_support
;
8772 struct fw_port_cmd port_cmd
;
8775 memset(&port_cmd
, 0, sizeof(port_cmd
));
8776 port_cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
8777 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
8778 FW_PORT_CMD_PORTID_V(pi
->tx_chan
));
8779 port_cmd
.action_to_len16
= cpu_to_be32(
8780 FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
8781 ? FW_PORT_ACTION_GET_PORT_INFO
8782 : FW_PORT_ACTION_GET_PORT_INFO32
) |
8783 FW_LEN16(port_cmd
));
8784 ret
= t4_wr_mbox(pi
->adapter
, pi
->adapter
->mbox
,
8785 &port_cmd
, sizeof(port_cmd
), &port_cmd
);
8789 t4_handle_get_port_info(pi
, (__be64
*)&port_cmd
);
8794 * t4_get_link_params - retrieve basic link parameters for given port
8796 * @link_okp: value return pointer for link up/down
8797 * @speedp: value return pointer for speed (Mb/s)
8798 * @mtup: value return pointer for mtu
8800 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8801 * and MTU for a specified port. A negative error is returned on
8802 * failure; 0 on success.
8804 int t4_get_link_params(struct port_info
*pi
, unsigned int *link_okp
,
8805 unsigned int *speedp
, unsigned int *mtup
)
8807 unsigned int fw_caps
= pi
->adapter
->params
.fw_caps_support
;
8808 unsigned int action
, link_ok
, mtu
;
8809 struct fw_port_cmd port_cmd
;
8810 fw_port_cap32_t linkattr
;
8813 memset(&port_cmd
, 0, sizeof(port_cmd
));
8814 port_cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
8815 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
8816 FW_PORT_CMD_PORTID_V(pi
->tx_chan
));
8817 action
= (fw_caps
== FW_CAPS16
8818 ? FW_PORT_ACTION_GET_PORT_INFO
8819 : FW_PORT_ACTION_GET_PORT_INFO32
);
8820 port_cmd
.action_to_len16
= cpu_to_be32(
8821 FW_PORT_CMD_ACTION_V(action
) |
8822 FW_LEN16(port_cmd
));
8823 ret
= t4_wr_mbox(pi
->adapter
, pi
->adapter
->mbox
,
8824 &port_cmd
, sizeof(port_cmd
), &port_cmd
);
8828 if (action
== FW_PORT_ACTION_GET_PORT_INFO
) {
8829 u32 lstatus
= be32_to_cpu(port_cmd
.u
.info
.lstatus_to_modtype
);
8831 link_ok
= !!(lstatus
& FW_PORT_CMD_LSTATUS_F
);
8832 linkattr
= lstatus_to_fwcap(lstatus
);
8833 mtu
= be16_to_cpu(port_cmd
.u
.info
.mtu
);
8836 be32_to_cpu(port_cmd
.u
.info32
.lstatus32_to_cbllen32
);
8838 link_ok
= !!(lstatus32
& FW_PORT_CMD_LSTATUS32_F
);
8839 linkattr
= be32_to_cpu(port_cmd
.u
.info32
.linkattr32
);
8840 mtu
= FW_PORT_CMD_MTU32_G(
8841 be32_to_cpu(port_cmd
.u
.info32
.auxlinfo32_mtu32
));
8845 *link_okp
= link_ok
;
8847 *speedp
= fwcap_to_speed(linkattr
);
8855 * t4_handle_fw_rpl - process a FW reply message
8856 * @adap: the adapter
8857 * @rpl: start of the FW message
8859 * Processes a FW message, such as link state change messages.
8861 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
)
8863 u8 opcode
= *(const u8
*)rpl
;
8865 /* This might be a port command ... this simplifies the following
8866 * conditionals ... We can get away with pre-dereferencing
8867 * action_to_len16 because it's in the first 16 bytes and all messages
8868 * will be at least that long.
8870 const struct fw_port_cmd
*p
= (const void *)rpl
;
8871 unsigned int action
=
8872 FW_PORT_CMD_ACTION_G(be32_to_cpu(p
->action_to_len16
));
8874 if (opcode
== FW_PORT_CMD
&&
8875 (action
== FW_PORT_ACTION_GET_PORT_INFO
||
8876 action
== FW_PORT_ACTION_GET_PORT_INFO32
)) {
8878 int chan
= FW_PORT_CMD_PORTID_G(be32_to_cpu(p
->op_to_portid
));
8879 struct port_info
*pi
= NULL
;
8881 for_each_port(adap
, i
) {
8882 pi
= adap2pinfo(adap
, i
);
8883 if (pi
->tx_chan
== chan
)
8887 t4_handle_get_port_info(pi
, rpl
);
8889 dev_warn(adap
->pdev_dev
, "Unknown firmware reply %d\n",
8896 static void get_pci_mode(struct adapter
*adapter
, struct pci_params
*p
)
8900 if (pci_is_pcie(adapter
->pdev
)) {
8901 pcie_capability_read_word(adapter
->pdev
, PCI_EXP_LNKSTA
, &val
);
8902 p
->speed
= val
& PCI_EXP_LNKSTA_CLS
;
8903 p
->width
= (val
& PCI_EXP_LNKSTA_NLW
) >> 4;
8908 * init_link_config - initialize a link's SW state
8909 * @lc: pointer to structure holding the link state
8910 * @pcaps: link Port Capabilities
8911 * @acaps: link current Advertised Port Capabilities
8913 * Initializes the SW state maintained for each link, including the link's
8914 * capabilities and default speed/flow-control/autonegotiation settings.
8916 static void init_link_config(struct link_config
*lc
, fw_port_cap32_t pcaps
,
8917 fw_port_cap32_t acaps
)
8920 lc
->def_acaps
= acaps
;
8924 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
8926 /* For Forward Error Control, we default to whatever the Firmware
8927 * tells us the Link is currently advertising.
8929 lc
->requested_fec
= FEC_AUTO
;
8930 lc
->fec
= fwcap_to_cc_fec(lc
->def_acaps
);
8932 /* If the Port is capable of Auto-Negtotiation, initialize it as
8933 * "enabled" and copy over all of the Physical Port Capabilities
8934 * to the Advertised Port Capabilities. Otherwise mark it as
8935 * Auto-Negotiate disabled and select the highest supported speed
8936 * for the link. Note parallel structure in t4_link_l1cfg_core()
8937 * and t4_handle_get_port_info().
8939 if (lc
->pcaps
& FW_PORT_CAP32_ANEG
) {
8940 lc
->acaps
= lc
->pcaps
& ADVERT_MASK
;
8941 lc
->autoneg
= AUTONEG_ENABLE
;
8942 lc
->requested_fc
|= PAUSE_AUTONEG
;
8945 lc
->autoneg
= AUTONEG_DISABLE
;
8946 lc
->speed_caps
= fwcap_to_fwspeed(acaps
);
8950 #define CIM_PF_NOACCESS 0xeeeeeeee
8952 int t4_wait_dev_ready(void __iomem
*regs
)
8956 whoami
= readl(regs
+ PL_WHOAMI_A
);
8957 if (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
)
8961 whoami
= readl(regs
+ PL_WHOAMI_A
);
8962 return (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
? 0 : -EIO
);
8966 u32 vendor_and_model_id
;
8970 static int t4_get_flash_params(struct adapter
*adap
)
8972 /* Table for non-Numonix supported flash parts. Numonix parts are left
8973 * to the preexisting code. All flash parts have 64KB sectors.
8975 static struct flash_desc supported_flash
[] = {
8976 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8979 unsigned int part
, manufacturer
;
8980 unsigned int density
, size
= 0;
8984 /* Issue a Read ID Command to the Flash part. We decode supported
8985 * Flash parts and their sizes from this. There's a newer Query
8986 * Command which can retrieve detailed geometry information but many
8987 * Flash parts don't support it.
8990 ret
= sf1_write(adap
, 1, 1, 0, SF_RD_ID
);
8992 ret
= sf1_read(adap
, 3, 0, 1, &flashid
);
8993 t4_write_reg(adap
, SF_OP_A
, 0); /* unlock SF */
8997 /* Check to see if it's one of our non-standard supported Flash parts.
8999 for (part
= 0; part
< ARRAY_SIZE(supported_flash
); part
++)
9000 if (supported_flash
[part
].vendor_and_model_id
== flashid
) {
9001 adap
->params
.sf_size
= supported_flash
[part
].size_mb
;
9002 adap
->params
.sf_nsec
=
9003 adap
->params
.sf_size
/ SF_SEC_SIZE
;
9007 /* Decode Flash part size. The code below looks repetitive with
9008 * common encodings, but that's not guaranteed in the JEDEC
9009 * specification for the Read JEDEC ID command. The only thing that
9010 * we're guaranteed by the JEDEC specification is where the
9011 * Manufacturer ID is in the returned result. After that each
9012 * Manufacturer ~could~ encode things completely differently.
9013 * Note, all Flash parts must have 64KB sectors.
9015 manufacturer
= flashid
& 0xff;
9016 switch (manufacturer
) {
9017 case 0x20: { /* Micron/Numonix */
9018 /* This Density -> Size decoding table is taken from Micron
9021 density
= (flashid
>> 16) & 0xff;
9023 case 0x14: /* 1MB */
9026 case 0x15: /* 2MB */
9029 case 0x16: /* 4MB */
9032 case 0x17: /* 8MB */
9035 case 0x18: /* 16MB */
9038 case 0x19: /* 32MB */
9041 case 0x20: /* 64MB */
9044 case 0x21: /* 128MB */
9047 case 0x22: /* 256MB */
9053 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9054 /* This Density -> Size decoding table is taken from ISSI
9057 density
= (flashid
>> 16) & 0xff;
9059 case 0x16: /* 32 MB */
9062 case 0x17: /* 64MB */
9068 case 0xc2: { /* Macronix */
9069 /* This Density -> Size decoding table is taken from Macronix
9072 density
= (flashid
>> 16) & 0xff;
9074 case 0x17: /* 8MB */
9077 case 0x18: /* 16MB */
9083 case 0xef: { /* Winbond */
9084 /* This Density -> Size decoding table is taken from Winbond
9087 density
= (flashid
>> 16) & 0xff;
9089 case 0x17: /* 8MB */
9092 case 0x18: /* 16MB */
9100 /* If we didn't recognize the FLASH part, that's no real issue: the
9101 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9102 * use a FLASH part which is at least 4MB in size and has 64KB
9103 * sectors. The unrecognized FLASH part is likely to be much larger
9104 * than 4MB, but that's all we really need.
9107 dev_warn(adap
->pdev_dev
, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9112 /* Store decoded Flash size and fall through into vetting code. */
9113 adap
->params
.sf_size
= size
;
9114 adap
->params
.sf_nsec
= size
/ SF_SEC_SIZE
;
9117 if (adap
->params
.sf_size
< FLASH_MIN_SIZE
)
9118 dev_warn(adap
->pdev_dev
, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9119 flashid
, adap
->params
.sf_size
, FLASH_MIN_SIZE
);
9124 * t4_prep_adapter - prepare SW and HW for operation
9125 * @adapter: the adapter
9127 * Initialize adapter SW state for the various HW modules, set initial
9128 * values for some adapter tunables, take PHYs out of reset, and
9129 * initialize the MDIO interface.
9131 int t4_prep_adapter(struct adapter
*adapter
)
9137 get_pci_mode(adapter
, &adapter
->params
.pci
);
9138 pl_rev
= REV_G(t4_read_reg(adapter
, PL_REV_A
));
9140 ret
= t4_get_flash_params(adapter
);
9142 dev_err(adapter
->pdev_dev
, "error %d identifying flash\n", ret
);
9146 /* Retrieve adapter's device ID
9148 pci_read_config_word(adapter
->pdev
, PCI_DEVICE_ID
, &device_id
);
9149 ver
= device_id
>> 12;
9150 adapter
->params
.chip
= 0;
9153 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T4
, pl_rev
);
9154 adapter
->params
.arch
.sge_fl_db
= DBPRIO_F
;
9155 adapter
->params
.arch
.mps_tcam_size
=
9156 NUM_MPS_CLS_SRAM_L_INSTANCES
;
9157 adapter
->params
.arch
.mps_rplc_size
= 128;
9158 adapter
->params
.arch
.nchan
= NCHAN
;
9159 adapter
->params
.arch
.pm_stats_cnt
= PM_NSTATS
;
9160 adapter
->params
.arch
.vfcount
= 128;
9161 /* Congestion map is for 4 channels so that
9162 * MPS can have 4 priority per port.
9164 adapter
->params
.arch
.cng_ch_bits_log
= 2;
9167 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T5
, pl_rev
);
9168 adapter
->params
.arch
.sge_fl_db
= DBPRIO_F
| DBTYPE_F
;
9169 adapter
->params
.arch
.mps_tcam_size
=
9170 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
9171 adapter
->params
.arch
.mps_rplc_size
= 128;
9172 adapter
->params
.arch
.nchan
= NCHAN
;
9173 adapter
->params
.arch
.pm_stats_cnt
= PM_NSTATS
;
9174 adapter
->params
.arch
.vfcount
= 128;
9175 adapter
->params
.arch
.cng_ch_bits_log
= 2;
9178 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T6
, pl_rev
);
9179 adapter
->params
.arch
.sge_fl_db
= 0;
9180 adapter
->params
.arch
.mps_tcam_size
=
9181 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
9182 adapter
->params
.arch
.mps_rplc_size
= 256;
9183 adapter
->params
.arch
.nchan
= 2;
9184 adapter
->params
.arch
.pm_stats_cnt
= T6_PM_NSTATS
;
9185 adapter
->params
.arch
.vfcount
= 256;
9186 /* Congestion map will be for 2 channels so that
9187 * MPS can have 8 priority per port.
9189 adapter
->params
.arch
.cng_ch_bits_log
= 3;
9192 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
9197 adapter
->params
.cim_la_size
= CIMLA_SIZE
;
9198 init_cong_ctrl(adapter
->params
.a_wnd
, adapter
->params
.b_wnd
);
9201 * Default port for debugging in case we can't reach FW.
9203 adapter
->params
.nports
= 1;
9204 adapter
->params
.portvec
= 1;
9205 adapter
->params
.vpd
.cclk
= 50000;
9207 /* Set PCIe completion timeout to 4 seconds. */
9208 pcie_capability_clear_and_set_word(adapter
->pdev
, PCI_EXP_DEVCTL2
,
9209 PCI_EXP_DEVCTL2_COMP_TIMEOUT
, 0xd);
9214 * t4_shutdown_adapter - shut down adapter, host & wire
9215 * @adapter: the adapter
9217 * Perform an emergency shutdown of the adapter and stop it from
9218 * continuing any further communication on the ports or DMA to the
9219 * host. This is typically used when the adapter and/or firmware
9220 * have crashed and we want to prevent any further accidental
9221 * communication with the rest of the world. This will also force
9222 * the port Link Status to go down -- if register writes work --
9223 * which should help our peers figure out that we're down.
9225 int t4_shutdown_adapter(struct adapter
*adapter
)
9229 t4_intr_disable(adapter
);
9230 t4_write_reg(adapter
, DBG_GPIO_EN_A
, 0);
9231 for_each_port(adapter
, port
) {
9232 u32 a_port_cfg
= is_t4(adapter
->params
.chip
) ?
9233 PORT_REG(port
, XGMAC_PORT_CFG_A
) :
9234 T5_PORT_REG(port
, MAC_PORT_CFG_A
);
9236 t4_write_reg(adapter
, a_port_cfg
,
9237 t4_read_reg(adapter
, a_port_cfg
)
9238 & ~SIGNAL_DET_V(1));
9240 t4_set_reg_field(adapter
, SGE_CONTROL_A
, GLOBALENABLE_F
, 0);
9246 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9247 * @adapter: the adapter
9248 * @qid: the Queue ID
9249 * @qtype: the Ingress or Egress type for @qid
9250 * @user: true if this request is for a user mode queue
9251 * @pbar2_qoffset: BAR2 Queue Offset
9252 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9254 * Returns the BAR2 SGE Queue Registers information associated with the
9255 * indicated Absolute Queue ID. These are passed back in return value
9256 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9257 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9259 * This may return an error which indicates that BAR2 SGE Queue
9260 * registers aren't available. If an error is not returned, then the
9261 * following values are returned:
9263 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9264 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9266 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9267 * require the "Inferred Queue ID" ability may be used. E.g. the
9268 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9269 * then these "Inferred Queue ID" register may not be used.
9271 int t4_bar2_sge_qregs(struct adapter
*adapter
,
9273 enum t4_bar2_qtype qtype
,
9276 unsigned int *pbar2_qid
)
9278 unsigned int page_shift
, page_size
, qpp_shift
, qpp_mask
;
9279 u64 bar2_page_offset
, bar2_qoffset
;
9280 unsigned int bar2_qid
, bar2_qid_offset
, bar2_qinferred
;
9282 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9283 if (!user
&& is_t4(adapter
->params
.chip
))
9286 /* Get our SGE Page Size parameters.
9288 page_shift
= adapter
->params
.sge
.hps
+ 10;
9289 page_size
= 1 << page_shift
;
9291 /* Get the right Queues per Page parameters for our Queue.
9293 qpp_shift
= (qtype
== T4_BAR2_QTYPE_EGRESS
9294 ? adapter
->params
.sge
.eq_qpp
9295 : adapter
->params
.sge
.iq_qpp
);
9296 qpp_mask
= (1 << qpp_shift
) - 1;
9298 /* Calculate the basics of the BAR2 SGE Queue register area:
9299 * o The BAR2 page the Queue registers will be in.
9300 * o The BAR2 Queue ID.
9301 * o The BAR2 Queue ID Offset into the BAR2 page.
9303 bar2_page_offset
= ((u64
)(qid
>> qpp_shift
) << page_shift
);
9304 bar2_qid
= qid
& qpp_mask
;
9305 bar2_qid_offset
= bar2_qid
* SGE_UDB_SIZE
;
9307 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9308 * hardware will infer the Absolute Queue ID simply from the writes to
9309 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9310 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9311 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9312 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9313 * from the BAR2 Page and BAR2 Queue ID.
9315 * One important censequence of this is that some BAR2 SGE registers
9316 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9317 * there. But other registers synthesize the SGE Queue ID purely
9318 * from the writes to the registers -- the Write Combined Doorbell
9319 * Buffer is a good example. These BAR2 SGE Registers are only
9320 * available for those BAR2 SGE Register areas where the SGE Absolute
9321 * Queue ID can be inferred from simple writes.
9323 bar2_qoffset
= bar2_page_offset
;
9324 bar2_qinferred
= (bar2_qid_offset
< page_size
);
9325 if (bar2_qinferred
) {
9326 bar2_qoffset
+= bar2_qid_offset
;
9330 *pbar2_qoffset
= bar2_qoffset
;
9331 *pbar2_qid
= bar2_qid
;
9336 * t4_init_devlog_params - initialize adapter->params.devlog
9337 * @adap: the adapter
9339 * Initialize various fields of the adapter's Firmware Device Log
9340 * Parameters structure.
9342 int t4_init_devlog_params(struct adapter
*adap
)
9344 struct devlog_params
*dparams
= &adap
->params
.devlog
;
9346 unsigned int devlog_meminfo
;
9347 struct fw_devlog_cmd devlog_cmd
;
9350 /* If we're dealing with newer firmware, the Device Log Parameters
9351 * are stored in a designated register which allows us to access the
9352 * Device Log even if we can't talk to the firmware.
9355 t4_read_reg(adap
, PCIE_FW_REG(PCIE_FW_PF_A
, PCIE_FW_PF_DEVLOG
));
9357 unsigned int nentries
, nentries128
;
9359 dparams
->memtype
= PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams
);
9360 dparams
->start
= PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams
) << 4;
9362 nentries128
= PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams
);
9363 nentries
= (nentries128
+ 1) * 128;
9364 dparams
->size
= nentries
* sizeof(struct fw_devlog_e
);
9369 /* Otherwise, ask the firmware for it's Device Log Parameters.
9371 memset(&devlog_cmd
, 0, sizeof(devlog_cmd
));
9372 devlog_cmd
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD
) |
9373 FW_CMD_REQUEST_F
| FW_CMD_READ_F
);
9374 devlog_cmd
.retval_len16
= cpu_to_be32(FW_LEN16(devlog_cmd
));
9375 ret
= t4_wr_mbox(adap
, adap
->mbox
, &devlog_cmd
, sizeof(devlog_cmd
),
9381 be32_to_cpu(devlog_cmd
.memtype_devlog_memaddr16_devlog
);
9382 dparams
->memtype
= FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo
);
9383 dparams
->start
= FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo
) << 4;
9384 dparams
->size
= be32_to_cpu(devlog_cmd
.memsize_devlog
);
9390 * t4_init_sge_params - initialize adap->params.sge
9391 * @adapter: the adapter
9393 * Initialize various fields of the adapter's SGE Parameters structure.
9395 int t4_init_sge_params(struct adapter
*adapter
)
9397 struct sge_params
*sge_params
= &adapter
->params
.sge
;
9399 unsigned int s_hps
, s_qpp
;
9401 /* Extract the SGE Page Size for our PF.
9403 hps
= t4_read_reg(adapter
, SGE_HOST_PAGE_SIZE_A
);
9404 s_hps
= (HOSTPAGESIZEPF0_S
+
9405 (HOSTPAGESIZEPF1_S
- HOSTPAGESIZEPF0_S
) * adapter
->pf
);
9406 sge_params
->hps
= ((hps
>> s_hps
) & HOSTPAGESIZEPF0_M
);
9408 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9410 s_qpp
= (QUEUESPERPAGEPF0_S
+
9411 (QUEUESPERPAGEPF1_S
- QUEUESPERPAGEPF0_S
) * adapter
->pf
);
9412 qpp
= t4_read_reg(adapter
, SGE_EGRESS_QUEUES_PER_PAGE_PF_A
);
9413 sge_params
->eq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
9414 qpp
= t4_read_reg(adapter
, SGE_INGRESS_QUEUES_PER_PAGE_PF_A
);
9415 sge_params
->iq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
9421 * t4_init_tp_params - initialize adap->params.tp
9422 * @adap: the adapter
9423 * @sleep_ok: if true we may sleep while awaiting command completion
9425 * Initialize various fields of the adapter's TP Parameters structure.
9427 int t4_init_tp_params(struct adapter
*adap
, bool sleep_ok
)
9433 v
= t4_read_reg(adap
, TP_TIMER_RESOLUTION_A
);
9434 adap
->params
.tp
.tre
= TIMERRESOLUTION_G(v
);
9435 adap
->params
.tp
.dack_re
= DELAYEDACKRESOLUTION_G(v
);
9437 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9438 for (chan
= 0; chan
< NCHAN
; chan
++)
9439 adap
->params
.tp
.tx_modq
[chan
] = chan
;
9441 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9444 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
9445 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER
) |
9446 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK
));
9448 /* Read current value */
9449 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0, 1,
9452 dev_info(adap
->pdev_dev
,
9453 "Current filter mode/mask 0x%x:0x%x\n",
9454 FW_PARAMS_PARAM_FILTER_MODE_G(val
),
9455 FW_PARAMS_PARAM_FILTER_MASK_G(val
));
9456 adap
->params
.tp
.vlan_pri_map
=
9457 FW_PARAMS_PARAM_FILTER_MODE_G(val
);
9458 adap
->params
.tp
.filter_mask
=
9459 FW_PARAMS_PARAM_FILTER_MASK_G(val
);
9461 dev_info(adap
->pdev_dev
,
9462 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9464 /* Incase of older-fw (which doesn't expose the api
9465 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9466 * the fw api) combination, fall-back to older method of reading
9467 * the filter mode from indirect-register
9469 t4_tp_pio_read(adap
, &adap
->params
.tp
.vlan_pri_map
, 1,
9470 TP_VLAN_PRI_MAP_A
, sleep_ok
);
9472 /* With the older-fw and newer-driver combination we might run
9473 * into an issue when user wants to use hash filter region but
9474 * the filter_mask is zero, in this case filter_mask validation
9475 * is tough. To avoid that we set the filter_mask same as filter
9476 * mode, which will behave exactly as the older way of ignoring
9477 * the filter mask validation.
9479 adap
->params
.tp
.filter_mask
= adap
->params
.tp
.vlan_pri_map
;
9482 t4_tp_pio_read(adap
, &adap
->params
.tp
.ingress_config
, 1,
9483 TP_INGRESS_CONFIG_A
, sleep_ok
);
9485 /* For T6, cache the adapter's compressed error vector
9486 * and passing outer header info for encapsulated packets.
9488 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) {
9489 v
= t4_read_reg(adap
, TP_OUT_CONFIG_A
);
9490 adap
->params
.tp
.rx_pkt_encap
= (v
& CRXPKTENC_F
) ? 1 : 0;
9493 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9494 * shift positions of several elements of the Compressed Filter Tuple
9495 * for this adapter which we need frequently ...
9497 adap
->params
.tp
.fcoe_shift
= t4_filter_field_shift(adap
, FCOE_F
);
9498 adap
->params
.tp
.port_shift
= t4_filter_field_shift(adap
, PORT_F
);
9499 adap
->params
.tp
.vnic_shift
= t4_filter_field_shift(adap
, VNIC_ID_F
);
9500 adap
->params
.tp
.vlan_shift
= t4_filter_field_shift(adap
, VLAN_F
);
9501 adap
->params
.tp
.tos_shift
= t4_filter_field_shift(adap
, TOS_F
);
9502 adap
->params
.tp
.protocol_shift
= t4_filter_field_shift(adap
,
9504 adap
->params
.tp
.ethertype_shift
= t4_filter_field_shift(adap
,
9506 adap
->params
.tp
.macmatch_shift
= t4_filter_field_shift(adap
,
9508 adap
->params
.tp
.matchtype_shift
= t4_filter_field_shift(adap
,
9510 adap
->params
.tp
.frag_shift
= t4_filter_field_shift(adap
,
9513 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9514 * represents the presence of an Outer VLAN instead of a VNIC ID.
9516 if ((adap
->params
.tp
.ingress_config
& VNIC_F
) == 0)
9517 adap
->params
.tp
.vnic_shift
= -1;
9519 v
= t4_read_reg(adap
, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A
);
9520 adap
->params
.tp
.hash_filter_mask
= v
;
9521 v
= t4_read_reg(adap
, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A
);
9522 adap
->params
.tp
.hash_filter_mask
|= ((u64
)v
<< 32);
9527 * t4_filter_field_shift - calculate filter field shift
9528 * @adap: the adapter
9529 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9531 * Return the shift position of a filter field within the Compressed
9532 * Filter Tuple. The filter field is specified via its selection bit
9533 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9535 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
)
9537 unsigned int filter_mode
= adap
->params
.tp
.vlan_pri_map
;
9541 if ((filter_mode
& filter_sel
) == 0)
9544 for (sel
= 1, field_shift
= 0; sel
< filter_sel
; sel
<<= 1) {
9545 switch (filter_mode
& sel
) {
9547 field_shift
+= FT_FCOE_W
;
9550 field_shift
+= FT_PORT_W
;
9553 field_shift
+= FT_VNIC_ID_W
;
9556 field_shift
+= FT_VLAN_W
;
9559 field_shift
+= FT_TOS_W
;
9562 field_shift
+= FT_PROTOCOL_W
;
9565 field_shift
+= FT_ETHERTYPE_W
;
9568 field_shift
+= FT_MACMATCH_W
;
9571 field_shift
+= FT_MPSHITTYPE_W
;
9573 case FRAGMENTATION_F
:
9574 field_shift
+= FT_FRAGMENTATION_W
;
9581 int t4_init_rss_mode(struct adapter
*adap
, int mbox
)
9584 struct fw_rss_vi_config_cmd rvc
;
9586 memset(&rvc
, 0, sizeof(rvc
));
9588 for_each_port(adap
, i
) {
9589 struct port_info
*p
= adap2pinfo(adap
, i
);
9592 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
9593 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
9594 FW_RSS_VI_CONFIG_CMD_VIID_V(p
->viid
));
9595 rvc
.retval_len16
= cpu_to_be32(FW_LEN16(rvc
));
9596 ret
= t4_wr_mbox(adap
, mbox
, &rvc
, sizeof(rvc
), &rvc
);
9599 p
->rss_mode
= be32_to_cpu(rvc
.u
.basicvirtual
.defaultq_to_udpen
);
9605 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9606 * @pi: the port_info
9607 * @mbox: mailbox to use for the FW command
9608 * @port: physical port associated with the VI
9609 * @pf: the PF owning the VI
9610 * @vf: the VF owning the VI
9611 * @mac: the MAC address of the VI
9613 * Allocates a virtual interface for the given physical port. If @mac is
9614 * not %NULL it contains the MAC address of the VI as assigned by FW.
9615 * @mac should be large enough to hold an Ethernet address.
9616 * Returns < 0 on error.
9618 int t4_init_portinfo(struct port_info
*pi
, int mbox
,
9619 int port
, int pf
, int vf
, u8 mac
[])
9621 struct adapter
*adapter
= pi
->adapter
;
9622 unsigned int fw_caps
= adapter
->params
.fw_caps_support
;
9623 struct fw_port_cmd cmd
;
9624 unsigned int rss_size
;
9625 enum fw_port_type port_type
;
9627 fw_port_cap32_t pcaps
, acaps
;
9628 u8 vivld
= 0, vin
= 0;
9631 /* If we haven't yet determined whether we're talking to Firmware
9632 * which knows the new 32-bit Port Capabilities, it's time to find
9633 * out now. This will also tell new Firmware to send us Port Status
9634 * Updates using the new 32-bit Port Capabilities version of the
9635 * Port Information message.
9637 if (fw_caps
== FW_CAPS_UNKNOWN
) {
9640 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF
) |
9641 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32
));
9643 ret
= t4_set_params(adapter
, mbox
, pf
, vf
, 1, ¶m
, &val
);
9644 fw_caps
= (ret
== 0 ? FW_CAPS32
: FW_CAPS16
);
9645 adapter
->params
.fw_caps_support
= fw_caps
;
9648 memset(&cmd
, 0, sizeof(cmd
));
9649 cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
9650 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
9651 FW_PORT_CMD_PORTID_V(port
));
9652 cmd
.action_to_len16
= cpu_to_be32(
9653 FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
9654 ? FW_PORT_ACTION_GET_PORT_INFO
9655 : FW_PORT_ACTION_GET_PORT_INFO32
) |
9657 ret
= t4_wr_mbox(pi
->adapter
, mbox
, &cmd
, sizeof(cmd
), &cmd
);
9661 /* Extract the various fields from the Port Information message.
9663 if (fw_caps
== FW_CAPS16
) {
9664 u32 lstatus
= be32_to_cpu(cmd
.u
.info
.lstatus_to_modtype
);
9666 port_type
= FW_PORT_CMD_PTYPE_G(lstatus
);
9667 mdio_addr
= ((lstatus
& FW_PORT_CMD_MDIOCAP_F
)
9668 ? FW_PORT_CMD_MDIOADDR_G(lstatus
)
9670 pcaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
.u
.info
.pcap
));
9671 acaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
.u
.info
.acap
));
9673 u32 lstatus32
= be32_to_cpu(cmd
.u
.info32
.lstatus32_to_cbllen32
);
9675 port_type
= FW_PORT_CMD_PORTTYPE32_G(lstatus32
);
9676 mdio_addr
= ((lstatus32
& FW_PORT_CMD_MDIOCAP32_F
)
9677 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32
)
9679 pcaps
= be32_to_cpu(cmd
.u
.info32
.pcaps32
);
9680 acaps
= be32_to_cpu(cmd
.u
.info32
.acaps32
);
9683 ret
= t4_alloc_vi(pi
->adapter
, mbox
, port
, pf
, vf
, 1, mac
, &rss_size
,
9691 pi
->rss_size
= rss_size
;
9692 pi
->rx_cchan
= t4_get_tp_e2c_map(pi
->adapter
, port
);
9694 /* If fw supports returning the VIN as part of FW_VI_CMD,
9695 * save the returned values.
9697 if (adapter
->params
.viid_smt_extn_support
) {
9701 /* Retrieve the values from VIID */
9702 pi
->vivld
= FW_VIID_VIVLD_G(pi
->viid
);
9703 pi
->vin
= FW_VIID_VIN_G(pi
->viid
);
9706 pi
->port_type
= port_type
;
9707 pi
->mdio_addr
= mdio_addr
;
9708 pi
->mod_type
= FW_PORT_MOD_TYPE_NA
;
9710 init_link_config(&pi
->link_cfg
, pcaps
, acaps
);
9714 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
)
9719 for_each_port(adap
, i
) {
9720 struct port_info
*pi
= adap2pinfo(adap
, i
);
9722 while ((adap
->params
.portvec
& (1 << j
)) == 0)
9725 ret
= t4_init_portinfo(pi
, mbox
, j
, pf
, vf
, addr
);
9729 memcpy(adap
->port
[i
]->dev_addr
, addr
, ETH_ALEN
);
9735 int t4_init_port_mirror(struct port_info
*pi
, u8 mbox
, u8 port
, u8 pf
, u8 vf
,
9740 ret
= t4_alloc_vi(pi
->adapter
, mbox
, port
, pf
, vf
, 1, NULL
, NULL
,
9752 * t4_read_cimq_cfg - read CIM queue configuration
9753 * @adap: the adapter
9754 * @base: holds the queue base addresses in bytes
9755 * @size: holds the queue sizes in bytes
9756 * @thres: holds the queue full thresholds in bytes
9758 * Returns the current configuration of the CIM queues, starting with
9759 * the IBQs, then the OBQs.
9761 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
)
9764 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
9765 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
9767 for (i
= 0; i
< CIM_NUM_IBQ
; i
++) {
9768 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, IBQSELECT_F
|
9770 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9771 /* value is in 256-byte units */
9772 *base
++ = CIMQBASE_G(v
) * 256;
9773 *size
++ = CIMQSIZE_G(v
) * 256;
9774 *thres
++ = QUEFULLTHRSH_G(v
) * 8; /* 8-byte unit */
9776 for (i
= 0; i
< cim_num_obq
; i
++) {
9777 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
9779 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9780 /* value is in 256-byte units */
9781 *base
++ = CIMQBASE_G(v
) * 256;
9782 *size
++ = CIMQSIZE_G(v
) * 256;
9787 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9788 * @adap: the adapter
9789 * @qid: the queue index
9790 * @data: where to store the queue contents
9791 * @n: capacity of @data in 32-bit words
9793 * Reads the contents of the selected CIM queue starting at address 0 up
9794 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9795 * error and the number of 32-bit words actually read on success.
9797 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
9799 int i
, err
, attempts
;
9801 const unsigned int nwords
= CIM_IBQ_SIZE
* 4;
9803 if (qid
> 5 || (n
& 3))
9806 addr
= qid
* nwords
;
9810 /* It might take 3-10ms before the IBQ debug read access is allowed.
9811 * Wait for 1 Sec with a delay of 1 usec.
9815 for (i
= 0; i
< n
; i
++, addr
++) {
9816 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGADDR_V(addr
) |
9818 err
= t4_wait_op_done(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGBUSY_F
, 0,
9822 *data
++ = t4_read_reg(adap
, CIM_IBQ_DBG_DATA_A
);
9824 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, 0);
9829 * t4_read_cim_obq - read the contents of a CIM outbound queue
9830 * @adap: the adapter
9831 * @qid: the queue index
9832 * @data: where to store the queue contents
9833 * @n: capacity of @data in 32-bit words
9835 * Reads the contents of the selected CIM queue starting at address 0 up
9836 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9837 * error and the number of 32-bit words actually read on success.
9839 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
9842 unsigned int addr
, v
, nwords
;
9843 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
9844 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
9846 if ((qid
> (cim_num_obq
- 1)) || (n
& 3))
9849 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
9850 QUENUMSELECT_V(qid
));
9851 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9853 addr
= CIMQBASE_G(v
) * 64; /* muliple of 256 -> muliple of 4 */
9854 nwords
= CIMQSIZE_G(v
) * 64; /* same */
9858 for (i
= 0; i
< n
; i
++, addr
++) {
9859 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGADDR_V(addr
) |
9861 err
= t4_wait_op_done(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGBUSY_F
, 0,
9865 *data
++ = t4_read_reg(adap
, CIM_OBQ_DBG_DATA_A
);
9867 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, 0);
9872 * t4_cim_read - read a block from CIM internal address space
9873 * @adap: the adapter
9874 * @addr: the start address within the CIM address space
9875 * @n: number of words to read
9876 * @valp: where to store the result
9878 * Reads a block of 4-byte words from the CIM intenal address space.
9880 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
9885 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
9888 for ( ; !ret
&& n
--; addr
+= 4) {
9889 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
);
9890 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
9893 *valp
++ = t4_read_reg(adap
, CIM_HOST_ACC_DATA_A
);
9899 * t4_cim_write - write a block into CIM internal address space
9900 * @adap: the adapter
9901 * @addr: the start address within the CIM address space
9902 * @n: number of words to write
9903 * @valp: set of values to write
9905 * Writes a block of 4-byte words into the CIM intenal address space.
9907 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
9908 const unsigned int *valp
)
9912 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
9915 for ( ; !ret
&& n
--; addr
+= 4) {
9916 t4_write_reg(adap
, CIM_HOST_ACC_DATA_A
, *valp
++);
9917 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
| HOSTWRITE_F
);
9918 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
9924 static int t4_cim_write1(struct adapter
*adap
, unsigned int addr
,
9927 return t4_cim_write(adap
, addr
, 1, &val
);
9931 * t4_cim_read_la - read CIM LA capture buffer
9932 * @adap: the adapter
9933 * @la_buf: where to store the LA data
9934 * @wrptr: the HW write pointer within the capture buffer
9936 * Reads the contents of the CIM LA buffer with the most recent entry at
9937 * the end of the returned data and with the entry at @wrptr first.
9938 * We try to leave the LA in the running state we find it in.
9940 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
)
9943 unsigned int cfg
, val
, idx
;
9945 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &cfg
);
9949 if (cfg
& UPDBGLAEN_F
) { /* LA is running, freeze it */
9950 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
, 0);
9955 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
9959 idx
= UPDBGLAWRPTR_G(val
);
9963 for (i
= 0; i
< adap
->params
.cim_la_size
; i
++) {
9964 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
9965 UPDBGLARDPTR_V(idx
) | UPDBGLARDEN_F
);
9968 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
9971 if (val
& UPDBGLARDEN_F
) {
9975 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_DATA_A
, 1, &la_buf
[i
]);
9979 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9980 * identify the 32-bit portion of the full 312-bit data
9982 if (is_t6(adap
->params
.chip
) && (idx
& 0xf) >= 9)
9983 idx
= (idx
& 0xff0) + 0x10;
9986 /* address can't exceed 0xfff */
9987 idx
&= UPDBGLARDPTR_M
;
9990 if (cfg
& UPDBGLAEN_F
) {
9991 int r
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
9992 cfg
& ~UPDBGLARDEN_F
);
10000 * t4_tp_read_la - read TP LA capture buffer
10001 * @adap: the adapter
10002 * @la_buf: where to store the LA data
10003 * @wrptr: the HW write pointer within the capture buffer
10005 * Reads the contents of the TP LA buffer with the most recent entry at
10006 * the end of the returned data and with the entry at @wrptr first.
10007 * We leave the LA in the running state we find it in.
10009 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
)
10011 bool last_incomplete
;
10012 unsigned int i
, cfg
, val
, idx
;
10014 cfg
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
) & 0xffff;
10015 if (cfg
& DBGLAENABLE_F
) /* freeze LA */
10016 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
10017 adap
->params
.tp
.la_mask
| (cfg
^ DBGLAENABLE_F
));
10019 val
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
);
10020 idx
= DBGLAWPTR_G(val
);
10021 last_incomplete
= DBGLAMODE_G(val
) >= 2 && (val
& DBGLAWHLF_F
) == 0;
10022 if (last_incomplete
)
10023 idx
= (idx
+ 1) & DBGLARPTR_M
;
10028 val
&= ~DBGLARPTR_V(DBGLARPTR_M
);
10029 val
|= adap
->params
.tp
.la_mask
;
10031 for (i
= 0; i
< TPLA_SIZE
; i
++) {
10032 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
, DBGLARPTR_V(idx
) | val
);
10033 la_buf
[i
] = t4_read_reg64(adap
, TP_DBG_LA_DATAL_A
);
10034 idx
= (idx
+ 1) & DBGLARPTR_M
;
10037 /* Wipe out last entry if it isn't valid */
10038 if (last_incomplete
)
10039 la_buf
[TPLA_SIZE
- 1] = ~0ULL;
10041 if (cfg
& DBGLAENABLE_F
) /* restore running state */
10042 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
10043 cfg
| adap
->params
.tp
.la_mask
);
10046 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10047 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10048 * state for more than the Warning Threshold then we'll issue a warning about
10049 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10050 * appears to be hung every Warning Repeat second till the situation clears.
10051 * If the situation clears, we'll note that as well.
10053 #define SGE_IDMA_WARN_THRESH 1
10054 #define SGE_IDMA_WARN_REPEAT 300
10057 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10058 * @adapter: the adapter
10059 * @idma: the adapter IDMA Monitor state
10061 * Initialize the state of an SGE Ingress DMA Monitor.
10063 void t4_idma_monitor_init(struct adapter
*adapter
,
10064 struct sge_idma_monitor_state
*idma
)
10066 /* Initialize the state variables for detecting an SGE Ingress DMA
10067 * hang. The SGE has internal counters which count up on each clock
10068 * tick whenever the SGE finds its Ingress DMA State Engines in the
10069 * same state they were on the previous clock tick. The clock used is
10070 * the Core Clock so we have a limit on the maximum "time" they can
10071 * record; typically a very small number of seconds. For instance,
10072 * with a 600MHz Core Clock, we can only count up to a bit more than
10073 * 7s. So we'll synthesize a larger counter in order to not run the
10074 * risk of having the "timers" overflow and give us the flexibility to
10075 * maintain a Hung SGE State Machine of our own which operates across
10076 * a longer time frame.
10078 idma
->idma_1s_thresh
= core_ticks_per_usec(adapter
) * 1000000; /* 1s */
10079 idma
->idma_stalled
[0] = 0;
10080 idma
->idma_stalled
[1] = 0;
10084 * t4_idma_monitor - monitor SGE Ingress DMA state
10085 * @adapter: the adapter
10086 * @idma: the adapter IDMA Monitor state
10087 * @hz: number of ticks/second
10088 * @ticks: number of ticks since the last IDMA Monitor call
10090 void t4_idma_monitor(struct adapter
*adapter
,
10091 struct sge_idma_monitor_state
*idma
,
10094 int i
, idma_same_state_cnt
[2];
10096 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10097 * are counters inside the SGE which count up on each clock when the
10098 * SGE finds its Ingress DMA State Engines in the same states they
10099 * were in the previous clock. The counters will peg out at
10100 * 0xffffffff without wrapping around so once they pass the 1s
10101 * threshold they'll stay above that till the IDMA state changes.
10103 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 13);
10104 idma_same_state_cnt
[0] = t4_read_reg(adapter
, SGE_DEBUG_DATA_HIGH_A
);
10105 idma_same_state_cnt
[1] = t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
10107 for (i
= 0; i
< 2; i
++) {
10108 u32 debug0
, debug11
;
10110 /* If the Ingress DMA Same State Counter ("timer") is less
10111 * than 1s, then we can reset our synthesized Stall Timer and
10112 * continue. If we have previously emitted warnings about a
10113 * potential stalled Ingress Queue, issue a note indicating
10114 * that the Ingress Queue has resumed forward progress.
10116 if (idma_same_state_cnt
[i
] < idma
->idma_1s_thresh
) {
10117 if (idma
->idma_stalled
[i
] >= SGE_IDMA_WARN_THRESH
* hz
)
10118 dev_warn(adapter
->pdev_dev
, "SGE idma%d, queue %u, "
10119 "resumed after %d seconds\n",
10120 i
, idma
->idma_qid
[i
],
10121 idma
->idma_stalled
[i
] / hz
);
10122 idma
->idma_stalled
[i
] = 0;
10126 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10127 * domain. The first time we get here it'll be because we
10128 * passed the 1s Threshold; each additional time it'll be
10129 * because the RX Timer Callback is being fired on its regular
10132 * If the stall is below our Potential Hung Ingress Queue
10133 * Warning Threshold, continue.
10135 if (idma
->idma_stalled
[i
] == 0) {
10136 idma
->idma_stalled
[i
] = hz
;
10137 idma
->idma_warn
[i
] = 0;
10139 idma
->idma_stalled
[i
] += ticks
;
10140 idma
->idma_warn
[i
] -= ticks
;
10143 if (idma
->idma_stalled
[i
] < SGE_IDMA_WARN_THRESH
* hz
)
10146 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10148 if (idma
->idma_warn
[i
] > 0)
10150 idma
->idma_warn
[i
] = SGE_IDMA_WARN_REPEAT
* hz
;
10152 /* Read and save the SGE IDMA State and Queue ID information.
10153 * We do this every time in case it changes across time ...
10154 * can't be too careful ...
10156 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 0);
10157 debug0
= t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
10158 idma
->idma_state
[i
] = (debug0
>> (i
* 9)) & 0x3f;
10160 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 11);
10161 debug11
= t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
10162 idma
->idma_qid
[i
] = (debug11
>> (i
* 16)) & 0xffff;
10164 dev_warn(adapter
->pdev_dev
, "SGE idma%u, queue %u, potentially stuck in "
10165 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10166 i
, idma
->idma_qid
[i
], idma
->idma_state
[i
],
10167 idma
->idma_stalled
[i
] / hz
,
10169 t4_sge_decode_idma_state(adapter
, idma
->idma_state
[i
]);
10174 * t4_load_cfg - download config file
10175 * @adap: the adapter
10176 * @cfg_data: the cfg text file to write
10177 * @size: text file size
10179 * Write the supplied config text file to the card's serial flash.
10181 int t4_load_cfg(struct adapter
*adap
, const u8
*cfg_data
, unsigned int size
)
10183 int ret
, i
, n
, cfg_addr
;
10185 unsigned int flash_cfg_start_sec
;
10186 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
10188 cfg_addr
= t4_flash_cfg_addr(adap
);
10193 flash_cfg_start_sec
= addr
/ SF_SEC_SIZE
;
10195 if (size
> FLASH_CFG_MAX_SIZE
) {
10196 dev_err(adap
->pdev_dev
, "cfg file too large, max is %u bytes\n",
10197 FLASH_CFG_MAX_SIZE
);
10201 i
= DIV_ROUND_UP(FLASH_CFG_MAX_SIZE
, /* # of sectors spanned */
10203 ret
= t4_flash_erase_sectors(adap
, flash_cfg_start_sec
,
10204 flash_cfg_start_sec
+ i
- 1);
10205 /* If size == 0 then we're simply erasing the FLASH sectors associated
10206 * with the on-adapter Firmware Configuration File.
10208 if (ret
|| size
== 0)
10211 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10212 for (i
= 0; i
< size
; i
+= SF_PAGE_SIZE
) {
10213 if ((size
- i
) < SF_PAGE_SIZE
)
10217 ret
= t4_write_flash(adap
, addr
, n
, cfg_data
);
10221 addr
+= SF_PAGE_SIZE
;
10222 cfg_data
+= SF_PAGE_SIZE
;
10227 dev_err(adap
->pdev_dev
, "config file %s failed %d\n",
10228 (size
== 0 ? "clear" : "download"), ret
);
10233 * t4_set_vf_mac - Set MAC address for the specified VF
10234 * @adapter: The adapter
10235 * @vf: one of the VFs instantiated by the specified PF
10236 * @naddr: the number of MAC addresses
10237 * @addr: the MAC address(es) to be set to the specified VF
10239 int t4_set_vf_mac_acl(struct adapter
*adapter
, unsigned int vf
,
10240 unsigned int naddr
, u8
*addr
)
10242 struct fw_acl_mac_cmd cmd
;
10244 memset(&cmd
, 0, sizeof(cmd
));
10245 cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD
) |
10248 FW_ACL_MAC_CMD_PFN_V(adapter
->pf
) |
10249 FW_ACL_MAC_CMD_VFN_V(vf
));
10251 /* Note: Do not enable the ACL */
10252 cmd
.en_to_len16
= cpu_to_be32((unsigned int)FW_LEN16(cmd
));
10255 switch (adapter
->pf
) {
10257 memcpy(cmd
.macaddr3
, addr
, sizeof(cmd
.macaddr3
));
10260 memcpy(cmd
.macaddr2
, addr
, sizeof(cmd
.macaddr2
));
10263 memcpy(cmd
.macaddr1
, addr
, sizeof(cmd
.macaddr1
));
10266 memcpy(cmd
.macaddr0
, addr
, sizeof(cmd
.macaddr0
));
10270 return t4_wr_mbox(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
), &cmd
);
10274 * t4_read_pace_tbl - read the pace table
10275 * @adap: the adapter
10276 * @pace_vals: holds the returned values
10278 * Returns the values of TP's pace table in microseconds.
10280 void t4_read_pace_tbl(struct adapter
*adap
, unsigned int pace_vals
[NTX_SCHED
])
10284 for (i
= 0; i
< NTX_SCHED
; i
++) {
10285 t4_write_reg(adap
, TP_PACE_TABLE_A
, 0xffff0000 + i
);
10286 v
= t4_read_reg(adap
, TP_PACE_TABLE_A
);
10287 pace_vals
[i
] = dack_ticks_to_usec(adap
, v
);
10292 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10293 * @adap: the adapter
10294 * @sched: the scheduler index
10295 * @kbps: the byte rate in Kbps
10296 * @ipg: the interpacket delay in tenths of nanoseconds
10297 * @sleep_ok: if true we may sleep while awaiting command completion
10299 * Return the current configuration of a HW Tx scheduler.
10301 void t4_get_tx_sched(struct adapter
*adap
, unsigned int sched
,
10302 unsigned int *kbps
, unsigned int *ipg
, bool sleep_ok
)
10304 unsigned int v
, addr
, bpt
, cpt
;
10307 addr
= TP_TX_MOD_Q1_Q0_RATE_LIMIT_A
- sched
/ 2;
10308 t4_tp_tm_pio_read(adap
, &v
, 1, addr
, sleep_ok
);
10311 bpt
= (v
>> 8) & 0xff;
10314 *kbps
= 0; /* scheduler disabled */
10316 v
= (adap
->params
.vpd
.cclk
* 1000) / cpt
; /* ticks/s */
10317 *kbps
= (v
* bpt
) / 125;
10321 addr
= TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A
- sched
/ 2;
10322 t4_tp_tm_pio_read(adap
, &v
, 1, addr
, sleep_ok
);
10326 *ipg
= (10000 * v
) / core_ticks_per_usec(adap
);
10330 /* t4_sge_ctxt_rd - read an SGE context through FW
10331 * @adap: the adapter
10332 * @mbox: mailbox to use for the FW command
10333 * @cid: the context id
10334 * @ctype: the context type
10335 * @data: where to store the context data
10337 * Issues a FW command through the given mailbox to read an SGE context.
10339 int t4_sge_ctxt_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int cid
,
10340 enum ctxt_type ctype
, u32
*data
)
10342 struct fw_ldst_cmd c
;
10345 if (ctype
== CTXT_FLM
)
10346 ret
= FW_LDST_ADDRSPC_SGE_FLMC
;
10348 ret
= FW_LDST_ADDRSPC_SGE_CONMC
;
10350 memset(&c
, 0, sizeof(c
));
10351 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
10352 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
10353 FW_LDST_CMD_ADDRSPACE_V(ret
));
10354 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
10355 c
.u
.idctxt
.physid
= cpu_to_be32(cid
);
10357 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
10359 data
[0] = be32_to_cpu(c
.u
.idctxt
.ctxt_data0
);
10360 data
[1] = be32_to_cpu(c
.u
.idctxt
.ctxt_data1
);
10361 data
[2] = be32_to_cpu(c
.u
.idctxt
.ctxt_data2
);
10362 data
[3] = be32_to_cpu(c
.u
.idctxt
.ctxt_data3
);
10363 data
[4] = be32_to_cpu(c
.u
.idctxt
.ctxt_data4
);
10364 data
[5] = be32_to_cpu(c
.u
.idctxt
.ctxt_data5
);
10370 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10371 * @adap: the adapter
10372 * @cid: the context id
10373 * @ctype: the context type
10374 * @data: where to store the context data
10376 * Reads an SGE context directly, bypassing FW. This is only for
10377 * debugging when FW is unavailable.
10379 int t4_sge_ctxt_rd_bd(struct adapter
*adap
, unsigned int cid
,
10380 enum ctxt_type ctype
, u32
*data
)
10384 t4_write_reg(adap
, SGE_CTXT_CMD_A
, CTXTQID_V(cid
) | CTXTTYPE_V(ctype
));
10385 ret
= t4_wait_op_done(adap
, SGE_CTXT_CMD_A
, BUSY_F
, 0, 3, 1);
10387 for (i
= SGE_CTXT_DATA0_A
; i
<= SGE_CTXT_DATA5_A
; i
+= 4)
10388 *data
++ = t4_read_reg(adap
, i
);
10392 int t4_sched_params(struct adapter
*adapter
, u8 type
, u8 level
, u8 mode
,
10393 u8 rateunit
, u8 ratemode
, u8 channel
, u8
class,
10394 u32 minrate
, u32 maxrate
, u16 weight
, u16 pktsize
,
10397 struct fw_sched_cmd cmd
;
10399 memset(&cmd
, 0, sizeof(cmd
));
10400 cmd
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD
) |
10403 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
10405 cmd
.u
.params
.sc
= FW_SCHED_SC_PARAMS
;
10406 cmd
.u
.params
.type
= type
;
10407 cmd
.u
.params
.level
= level
;
10408 cmd
.u
.params
.mode
= mode
;
10409 cmd
.u
.params
.ch
= channel
;
10410 cmd
.u
.params
.cl
= class;
10411 cmd
.u
.params
.unit
= rateunit
;
10412 cmd
.u
.params
.rate
= ratemode
;
10413 cmd
.u
.params
.min
= cpu_to_be32(minrate
);
10414 cmd
.u
.params
.max
= cpu_to_be32(maxrate
);
10415 cmd
.u
.params
.weight
= cpu_to_be16(weight
);
10416 cmd
.u
.params
.pktsize
= cpu_to_be16(pktsize
);
10417 cmd
.u
.params
.burstsize
= cpu_to_be16(burstsize
);
10419 return t4_wr_mbox_meat(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
),
10424 * t4_i2c_rd - read I2C data from adapter
10425 * @adap: the adapter
10426 * @mbox: mailbox to use for the FW command
10427 * @port: Port number if per-port device; <0 if not
10428 * @devid: per-port device ID or absolute device ID
10429 * @offset: byte offset into device I2C space
10430 * @len: byte length of I2C space data
10431 * @buf: buffer in which to return I2C data
10433 * Reads the I2C data from the indicated device and location.
10435 int t4_i2c_rd(struct adapter
*adap
, unsigned int mbox
, int port
,
10436 unsigned int devid
, unsigned int offset
,
10437 unsigned int len
, u8
*buf
)
10439 struct fw_ldst_cmd ldst_cmd
, ldst_rpl
;
10440 unsigned int i2c_max
= sizeof(ldst_cmd
.u
.i2c
.data
);
10443 if (len
> I2C_PAGE_SIZE
)
10446 /* Dont allow reads that spans multiple pages */
10447 if (offset
< I2C_PAGE_SIZE
&& offset
+ len
> I2C_PAGE_SIZE
)
10450 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
10451 ldst_cmd
.op_to_addrspace
=
10452 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
10455 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C
));
10456 ldst_cmd
.cycles_to_len16
= cpu_to_be32(FW_LEN16(ldst_cmd
));
10457 ldst_cmd
.u
.i2c
.pid
= (port
< 0 ? 0xff : port
);
10458 ldst_cmd
.u
.i2c
.did
= devid
;
10461 unsigned int i2c_len
= (len
< i2c_max
) ? len
: i2c_max
;
10463 ldst_cmd
.u
.i2c
.boffset
= offset
;
10464 ldst_cmd
.u
.i2c
.blen
= i2c_len
;
10466 ret
= t4_wr_mbox(adap
, mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
10471 memcpy(buf
, ldst_rpl
.u
.i2c
.data
, i2c_len
);
10481 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10482 * @adap: the adapter
10483 * @mbox: mailbox to use for the FW command
10484 * @vf: one of the VFs instantiated by the specified PF
10485 * @vlan: The vlanid to be set
10487 int t4_set_vlan_acl(struct adapter
*adap
, unsigned int mbox
, unsigned int vf
,
10490 struct fw_acl_vlan_cmd vlan_cmd
;
10491 unsigned int enable
;
10493 enable
= (vlan
? FW_ACL_VLAN_CMD_EN_F
: 0);
10494 memset(&vlan_cmd
, 0, sizeof(vlan_cmd
));
10495 vlan_cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD
) |
10499 FW_ACL_VLAN_CMD_PFN_V(adap
->pf
) |
10500 FW_ACL_VLAN_CMD_VFN_V(vf
));
10501 vlan_cmd
.en_to_len16
= cpu_to_be32(enable
| FW_LEN16(vlan_cmd
));
10502 /* Drop all packets that donot match vlan id */
10503 vlan_cmd
.dropnovlan_fm
= (enable
10504 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F
|
10505 FW_ACL_VLAN_CMD_FM_F
) : 0);
10507 vlan_cmd
.nvlan
= 1;
10508 vlan_cmd
.vlanid
[0] = cpu_to_be16(vlan
);
10511 return t4_wr_mbox(adap
, adap
->mbox
, &vlan_cmd
, sizeof(vlan_cmd
), NULL
);
10515 * modify_device_id - Modifies the device ID of the Boot BIOS image
10516 * @device_id: the device ID to write.
10517 * @boot_data: the boot image to modify.
10519 * Write the supplied device ID to the boot BIOS image.
10521 static void modify_device_id(int device_id
, u8
*boot_data
)
10523 struct cxgb4_pcir_data
*pcir_header
;
10524 struct legacy_pci_rom_hdr
*header
;
10525 u8
*cur_header
= boot_data
;
10528 /* Loop through all chained images and change the device ID's */
10530 header
= (struct legacy_pci_rom_hdr
*)cur_header
;
10531 pcir_offset
= le16_to_cpu(header
->pcir_offset
);
10532 pcir_header
= (struct cxgb4_pcir_data
*)(cur_header
+
10536 * Only modify the Device ID if code type is Legacy or HP.
10537 * 0x00: Okay to modify
10538 * 0x01: FCODE. Do not modify
10539 * 0x03: Okay to modify
10540 * 0x04-0xFF: Do not modify
10542 if (pcir_header
->code_type
== CXGB4_HDR_CODE1
) {
10547 * Modify Device ID to match current adatper
10549 pcir_header
->device_id
= cpu_to_le16(device_id
);
10552 * Set checksum temporarily to 0.
10553 * We will recalculate it later.
10555 header
->cksum
= 0x0;
10558 * Calculate and update checksum
10560 for (i
= 0; i
< (header
->size512
* 512); i
++)
10561 csum
+= cur_header
[i
];
10564 * Invert summed value to create the checksum
10565 * Writing new checksum value directly to the boot data
10567 cur_header
[7] = -csum
;
10569 } else if (pcir_header
->code_type
== CXGB4_HDR_CODE2
) {
10571 * Modify Device ID to match current adatper
10573 pcir_header
->device_id
= cpu_to_le16(device_id
);
10577 * Move header pointer up to the next image in the ROM.
10579 cur_header
+= header
->size512
* 512;
10580 } while (!(pcir_header
->indicator
& CXGB4_HDR_INDI
));
10584 * t4_load_boot - download boot flash
10585 * @adap: the adapter
10586 * @boot_data: the boot image to write
10587 * @boot_addr: offset in flash to write boot_data
10588 * @size: image size
10590 * Write the supplied boot image to the card's serial flash.
10591 * The boot image has the following sections: a 28-byte header and the
10594 int t4_load_boot(struct adapter
*adap
, u8
*boot_data
,
10595 unsigned int boot_addr
, unsigned int size
)
10597 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
10598 unsigned int boot_sector
= (boot_addr
* 1024);
10599 struct cxgb4_pci_exp_rom_header
*header
;
10600 struct cxgb4_pcir_data
*pcir_header
;
10607 * Make sure the boot image does not encroach on the firmware region
10609 if ((boot_sector
+ size
) >> 16 > FLASH_FW_START_SEC
) {
10610 dev_err(adap
->pdev_dev
, "boot image encroaching on firmware region\n");
10614 /* Get boot header */
10615 header
= (struct cxgb4_pci_exp_rom_header
*)boot_data
;
10616 pcir_offset
= le16_to_cpu(header
->pcir_offset
);
10617 /* PCIR Data Structure */
10618 pcir_header
= (struct cxgb4_pcir_data
*)&boot_data
[pcir_offset
];
10621 * Perform some primitive sanity testing to avoid accidentally
10622 * writing garbage over the boot sectors. We ought to check for
10623 * more but it's not worth it for now ...
10625 if (size
< BOOT_MIN_SIZE
|| size
> BOOT_MAX_SIZE
) {
10626 dev_err(adap
->pdev_dev
, "boot image too small/large\n");
10630 if (le16_to_cpu(header
->signature
) != BOOT_SIGNATURE
) {
10631 dev_err(adap
->pdev_dev
, "Boot image missing signature\n");
10635 /* Check PCI header signature */
10636 if (le32_to_cpu(pcir_header
->signature
) != PCIR_SIGNATURE
) {
10637 dev_err(adap
->pdev_dev
, "PCI header missing signature\n");
10641 /* Check Vendor ID matches Chelsio ID*/
10642 if (le16_to_cpu(pcir_header
->vendor_id
) != PCI_VENDOR_ID_CHELSIO
) {
10643 dev_err(adap
->pdev_dev
, "Vendor ID missing signature\n");
10648 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10649 * and Boot configuration data sections. These 3 boot sections span
10650 * sectors 0 to 7 in flash and live right before the FW image location.
10652 i
= DIV_ROUND_UP(size
? size
: FLASH_FW_START
, sf_sec_size
);
10653 ret
= t4_flash_erase_sectors(adap
, boot_sector
>> 16,
10654 (boot_sector
>> 16) + i
- 1);
10657 * If size == 0 then we're simply erasing the FLASH sectors associated
10658 * with the on-adapter option ROM file
10660 if (ret
|| size
== 0)
10662 /* Retrieve adapter's device ID */
10663 pci_read_config_word(adap
->pdev
, PCI_DEVICE_ID
, &device_id
);
10664 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10665 device_id
= device_id
& 0xf0ff;
10667 /* Check PCIE Device ID */
10668 if (le16_to_cpu(pcir_header
->device_id
) != device_id
) {
10670 * Change the device ID in the Boot BIOS image to match
10671 * the Device ID of the current adapter.
10673 modify_device_id(device_id
, boot_data
);
10677 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10678 * we finish copying the rest of the boot image. This will ensure
10679 * that the BIOS boot header will only be written if the boot image
10680 * was written in full.
10682 addr
= boot_sector
;
10683 for (size
-= SF_PAGE_SIZE
; size
; size
-= SF_PAGE_SIZE
) {
10684 addr
+= SF_PAGE_SIZE
;
10685 boot_data
+= SF_PAGE_SIZE
;
10686 ret
= t4_write_flash(adap
, addr
, SF_PAGE_SIZE
, boot_data
);
10691 ret
= t4_write_flash(adap
, boot_sector
, SF_PAGE_SIZE
,
10692 (const u8
*)header
);
10696 dev_err(adap
->pdev_dev
, "boot image load failed, error %d\n",
10702 * t4_flash_bootcfg_addr - return the address of the flash
10703 * optionrom configuration
10704 * @adapter: the adapter
10706 * Return the address within the flash where the OptionROM Configuration
10707 * is stored, or an error if the device FLASH is too small to contain
10708 * a OptionROM Configuration.
10710 static int t4_flash_bootcfg_addr(struct adapter
*adapter
)
10713 * If the device FLASH isn't large enough to hold a Firmware
10714 * Configuration File, return an error.
10716 if (adapter
->params
.sf_size
<
10717 FLASH_BOOTCFG_START
+ FLASH_BOOTCFG_MAX_SIZE
)
10720 return FLASH_BOOTCFG_START
;
10723 int t4_load_bootcfg(struct adapter
*adap
, const u8
*cfg_data
, unsigned int size
)
10725 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
10726 struct cxgb4_bootcfg_data
*header
;
10727 unsigned int flash_cfg_start_sec
;
10728 unsigned int addr
, npad
;
10729 int ret
, i
, n
, cfg_addr
;
10731 cfg_addr
= t4_flash_bootcfg_addr(adap
);
10736 flash_cfg_start_sec
= addr
/ SF_SEC_SIZE
;
10738 if (size
> FLASH_BOOTCFG_MAX_SIZE
) {
10739 dev_err(adap
->pdev_dev
, "bootcfg file too large, max is %u bytes\n",
10740 FLASH_BOOTCFG_MAX_SIZE
);
10744 header
= (struct cxgb4_bootcfg_data
*)cfg_data
;
10745 if (le16_to_cpu(header
->signature
) != BOOT_CFG_SIG
) {
10746 dev_err(adap
->pdev_dev
, "Wrong bootcfg signature\n");
10751 i
= DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE
,
10753 ret
= t4_flash_erase_sectors(adap
, flash_cfg_start_sec
,
10754 flash_cfg_start_sec
+ i
- 1);
10757 * If size == 0 then we're simply erasing the FLASH sectors associated
10758 * with the on-adapter OptionROM Configuration File.
10760 if (ret
|| size
== 0)
10763 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10764 for (i
= 0; i
< size
; i
+= SF_PAGE_SIZE
) {
10765 n
= min_t(u32
, size
- i
, SF_PAGE_SIZE
);
10767 ret
= t4_write_flash(adap
, addr
, n
, cfg_data
);
10771 addr
+= SF_PAGE_SIZE
;
10772 cfg_data
+= SF_PAGE_SIZE
;
10775 npad
= ((size
+ 4 - 1) & ~3) - size
;
10776 for (i
= 0; i
< npad
; i
++) {
10779 ret
= t4_write_flash(adap
, cfg_addr
+ size
+ i
, 1, &data
);
10786 dev_err(adap
->pdev_dev
, "boot config data %s failed %d\n",
10787 (size
== 0 ? "clear" : "download"), ret
);