2 drivers/net/ethernet/dec/tulip/media.c
4 Copyright 2000,2001 The Linux Kernel Team
5 Written/copyright 1994-2001 by Donald Becker.
7 This software may be used and distributed according to the terms
8 of the GNU General Public License, incorporated herein by reference.
10 Please submit bugs to http://bugzilla.kernel.org/ .
13 #include <linux/kernel.h>
14 #include <linux/mii.h>
15 #include <linux/delay.h>
16 #include <linux/pci.h>
20 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
21 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
22 "overclocking" issues or future 66Mhz PCI. */
23 #define mdio_delay() ioread32(mdio_addr)
25 /* Read and write the MII registers using software-generated serial
26 MDIO protocol. It is just different enough from the EEPROM protocol
27 to not share code. The maxium data clock rate is 2.5 Mhz. */
28 #define MDIO_SHIFT_CLK 0x10000
29 #define MDIO_DATA_WRITE0 0x00000
30 #define MDIO_DATA_WRITE1 0x20000
31 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
32 #define MDIO_ENB_IN 0x40000
33 #define MDIO_DATA_READ 0x80000
35 static const unsigned char comet_miireg2offset
[32] = {
36 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
37 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
40 /* MII transceiver control section.
41 Read and write the MII registers using software-generated serial
43 See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
44 or DP83840A data sheet for more details.
47 int tulip_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
49 struct tulip_private
*tp
= netdev_priv(dev
);
51 int read_cmd
= (0xf6 << 10) | ((phy_id
& 0x1f) << 5) | location
;
53 void __iomem
*ioaddr
= tp
->base_addr
;
54 void __iomem
*mdio_addr
= ioaddr
+ CSR9
;
60 if (tp
->chip_id
== COMET
&& phy_id
== 30) {
61 if (comet_miireg2offset
[location
])
62 return ioread32(ioaddr
+ comet_miireg2offset
[location
]);
66 spin_lock_irqsave(&tp
->mii_lock
, flags
);
67 if (tp
->chip_id
== LC82C168
) {
68 iowrite32(0x60020000 + (phy_id
<<23) + (location
<<18), ioaddr
+ 0xA0);
69 ioread32(ioaddr
+ 0xA0);
70 ioread32(ioaddr
+ 0xA0);
71 for (i
= 1000; i
>= 0; --i
) {
73 if ( ! ((retval
= ioread32(ioaddr
+ 0xA0)) & 0x80000000))
76 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
77 return retval
& 0xffff;
80 /* Establish sync by sending at least 32 logic ones. */
81 for (i
= 32; i
>= 0; i
--) {
82 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
, mdio_addr
);
84 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
| MDIO_SHIFT_CLK
, mdio_addr
);
87 /* Shift the read command bits out. */
88 for (i
= 15; i
>= 0; i
--) {
89 int dataval
= (read_cmd
& (1 << i
)) ? MDIO_DATA_WRITE1
: 0;
91 iowrite32(MDIO_ENB
| dataval
, mdio_addr
);
93 iowrite32(MDIO_ENB
| dataval
| MDIO_SHIFT_CLK
, mdio_addr
);
96 /* Read the two transition, 16 data, and wire-idle bits. */
97 for (i
= 19; i
> 0; i
--) {
98 iowrite32(MDIO_ENB_IN
, mdio_addr
);
100 retval
= (retval
<< 1) | ((ioread32(mdio_addr
) & MDIO_DATA_READ
) ? 1 : 0);
101 iowrite32(MDIO_ENB_IN
| MDIO_SHIFT_CLK
, mdio_addr
);
105 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
106 return (retval
>>1) & 0xffff;
109 void tulip_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
)
111 struct tulip_private
*tp
= netdev_priv(dev
);
113 int cmd
= (0x5002 << 16) | ((phy_id
& 0x1f) << 23) | (location
<<18) | (val
& 0xffff);
114 void __iomem
*ioaddr
= tp
->base_addr
;
115 void __iomem
*mdio_addr
= ioaddr
+ CSR9
;
118 if (location
& ~0x1f)
121 if (tp
->chip_id
== COMET
&& phy_id
== 30) {
122 if (comet_miireg2offset
[location
])
123 iowrite32(val
, ioaddr
+ comet_miireg2offset
[location
]);
127 spin_lock_irqsave(&tp
->mii_lock
, flags
);
128 if (tp
->chip_id
== LC82C168
) {
129 iowrite32(cmd
, ioaddr
+ 0xA0);
130 for (i
= 1000; i
>= 0; --i
) {
132 if ( ! (ioread32(ioaddr
+ 0xA0) & 0x80000000))
135 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
139 /* Establish sync by sending 32 logic ones. */
140 for (i
= 32; i
>= 0; i
--) {
141 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
, mdio_addr
);
143 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
| MDIO_SHIFT_CLK
, mdio_addr
);
146 /* Shift the command bits out. */
147 for (i
= 31; i
>= 0; i
--) {
148 int dataval
= (cmd
& (1 << i
)) ? MDIO_DATA_WRITE1
: 0;
149 iowrite32(MDIO_ENB
| dataval
, mdio_addr
);
151 iowrite32(MDIO_ENB
| dataval
| MDIO_SHIFT_CLK
, mdio_addr
);
154 /* Clear out extra bits. */
155 for (i
= 2; i
> 0; i
--) {
156 iowrite32(MDIO_ENB_IN
, mdio_addr
);
158 iowrite32(MDIO_ENB_IN
| MDIO_SHIFT_CLK
, mdio_addr
);
162 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
166 /* Set up the transceiver control registers for the selected media type. */
167 void tulip_select_media(struct net_device
*dev
, int startup
)
169 struct tulip_private
*tp
= netdev_priv(dev
);
170 void __iomem
*ioaddr
= tp
->base_addr
;
171 struct mediatable
*mtable
= tp
->mtable
;
176 struct medialeaf
*mleaf
= &mtable
->mleaf
[tp
->cur_index
];
177 unsigned char *p
= mleaf
->leafdata
;
178 switch (mleaf
->type
) {
179 case 0: /* 21140 non-MII xcvr. */
181 netdev_dbg(dev
, "Using a 21140 non-MII transceiver with control setting %02x\n",
185 iowrite32(mtable
->csr12dir
| 0x100, ioaddr
+ CSR12
);
186 iowrite32(p
[1], ioaddr
+ CSR12
);
187 new_csr6
= 0x02000000 | ((p
[2] & 0x71) << 18);
191 u32 csr13val
, csr14val
, csr15dir
, csr15val
;
192 for (i
= 0; i
< 5; i
++)
193 setup
[i
] = get_u16(&p
[i
*2 + 1]);
195 dev
->if_port
= p
[0] & MEDIA_MASK
;
196 if (tulip_media_cap
[dev
->if_port
] & MediaAlwaysFD
)
199 if (startup
&& mtable
->has_reset
) {
200 struct medialeaf
*rleaf
= &mtable
->mleaf
[mtable
->has_reset
];
201 unsigned char *rst
= rleaf
->leafdata
;
203 netdev_dbg(dev
, "Resetting the transceiver\n");
204 for (i
= 0; i
< rst
[0]; i
++)
205 iowrite32(get_u16(rst
+ 1 + (i
<<1)) << 16, ioaddr
+ CSR15
);
208 netdev_dbg(dev
, "21143 non-MII %s transceiver control %04x/%04x\n",
209 medianame
[dev
->if_port
],
211 if (p
[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
214 csr15dir
= (setup
[3]<<16) | setup
[2];
215 csr15val
= (setup
[4]<<16) | setup
[2];
216 iowrite32(0, ioaddr
+ CSR13
);
217 iowrite32(csr14val
, ioaddr
+ CSR14
);
218 iowrite32(csr15dir
, ioaddr
+ CSR15
); /* Direction */
219 iowrite32(csr15val
, ioaddr
+ CSR15
); /* Data */
220 iowrite32(csr13val
, ioaddr
+ CSR13
);
224 csr15dir
= (setup
[0]<<16) | 0x0008;
225 csr15val
= (setup
[1]<<16) | 0x0008;
226 if (dev
->if_port
<= 4)
227 csr14val
= t21142_csr14
[dev
->if_port
];
229 iowrite32(0, ioaddr
+ CSR13
);
230 iowrite32(csr14val
, ioaddr
+ CSR14
);
232 iowrite32(csr15dir
, ioaddr
+ CSR15
); /* Direction */
233 iowrite32(csr15val
, ioaddr
+ CSR15
); /* Data */
234 if (startup
) iowrite32(csr13val
, ioaddr
+ CSR13
);
237 netdev_dbg(dev
, "Setting CSR15 to %08x/%08x\n",
239 if (mleaf
->type
== 4)
240 new_csr6
= 0x82020000 | ((setup
[2] & 0x71) << 18);
242 new_csr6
= 0x82420000;
247 int init_length
= p
[1];
248 u16
*misc_info
, tmp_info
;
251 new_csr6
= 0x020E0000;
252 if (mleaf
->type
== 3) { /* 21142 */
253 u16
*init_sequence
= (u16
*)(p
+2);
254 u16
*reset_sequence
= &((u16
*)(p
+3))[init_length
];
255 int reset_length
= p
[2 + init_length
*2];
256 misc_info
= reset_sequence
+ reset_length
;
258 int timeout
= 10; /* max 1 ms */
259 for (i
= 0; i
< reset_length
; i
++)
260 iowrite32(get_u16(&reset_sequence
[i
]) << 16, ioaddr
+ CSR15
);
262 /* flush posted writes */
263 ioread32(ioaddr
+ CSR15
);
265 /* Sect 3.10.3 in DP83840A.pdf (p39) */
268 /* Section 4.2 in DP83840A.pdf (p43) */
269 /* and IEEE 802.3 "22.2.4.1.1 Reset" */
271 (tulip_mdio_read (dev
, phy_num
, MII_BMCR
) & BMCR_RESET
))
274 for (i
= 0; i
< init_length
; i
++)
275 iowrite32(get_u16(&init_sequence
[i
]) << 16, ioaddr
+ CSR15
);
277 ioread32(ioaddr
+ CSR15
); /* flush posted writes */
279 u8
*init_sequence
= p
+ 2;
280 u8
*reset_sequence
= p
+ 3 + init_length
;
281 int reset_length
= p
[2 + init_length
];
282 misc_info
= (u16
*)(reset_sequence
+ reset_length
);
284 int timeout
= 10; /* max 1 ms */
285 iowrite32(mtable
->csr12dir
| 0x100, ioaddr
+ CSR12
);
286 for (i
= 0; i
< reset_length
; i
++)
287 iowrite32(reset_sequence
[i
], ioaddr
+ CSR12
);
289 /* flush posted writes */
290 ioread32(ioaddr
+ CSR12
);
292 /* Sect 3.10.3 in DP83840A.pdf (p39) */
295 /* Section 4.2 in DP83840A.pdf (p43) */
296 /* and IEEE 802.3 "22.2.4.1.1 Reset" */
298 (tulip_mdio_read (dev
, phy_num
, MII_BMCR
) & BMCR_RESET
))
301 for (i
= 0; i
< init_length
; i
++)
302 iowrite32(init_sequence
[i
], ioaddr
+ CSR12
);
304 ioread32(ioaddr
+ CSR12
); /* flush posted writes */
307 tmp_info
= get_u16(&misc_info
[1]);
309 tp
->advertising
[phy_num
] = tmp_info
| 1;
310 if (tmp_info
&& startup
< 2) {
311 if (tp
->mii_advertise
== 0)
312 tp
->mii_advertise
= tp
->advertising
[phy_num
];
314 netdev_dbg(dev
, " Advertising %04x on MII %d\n",
317 tulip_mdio_write(dev
, tp
->phys
[phy_num
], 4, tp
->mii_advertise
);
322 new_csr6
= 0; /* FIXME */
324 if (startup
&& mtable
->has_reset
) {
325 struct medialeaf
*rleaf
= &mtable
->mleaf
[mtable
->has_reset
];
326 unsigned char *rst
= rleaf
->leafdata
;
328 netdev_dbg(dev
, "Resetting the transceiver\n");
329 for (i
= 0; i
< rst
[0]; i
++)
330 iowrite32(get_u16(rst
+ 1 + (i
<<1)) << 16, ioaddr
+ CSR15
);
336 netdev_dbg(dev
, " Invalid media table selection %d\n",
338 new_csr6
= 0x020E0000;
341 netdev_dbg(dev
, "Using media type %s, CSR12 is %02x\n",
342 medianame
[dev
->if_port
],
343 ioread32(ioaddr
+ CSR12
) & 0xff);
344 } else if (tp
->chip_id
== LC82C168
) {
345 if (startup
&& ! tp
->medialock
)
346 dev
->if_port
= tp
->mii_cnt
? 11 : 0;
348 netdev_dbg(dev
, "PNIC PHY status is %3.3x, media %s\n",
349 ioread32(ioaddr
+ 0xB8),
350 medianame
[dev
->if_port
]);
352 new_csr6
= 0x810C0000;
353 iowrite32(0x0001, ioaddr
+ CSR15
);
354 iowrite32(0x0201B07A, ioaddr
+ 0xB8);
355 } else if (startup
) {
356 /* Start with 10mbps to do autonegotiation. */
357 iowrite32(0x32, ioaddr
+ CSR12
);
358 new_csr6
= 0x00420000;
359 iowrite32(0x0001B078, ioaddr
+ 0xB8);
360 iowrite32(0x0201B078, ioaddr
+ 0xB8);
361 } else if (dev
->if_port
== 3 || dev
->if_port
== 5) {
362 iowrite32(0x33, ioaddr
+ CSR12
);
363 new_csr6
= 0x01860000;
364 /* Trigger autonegotiation. */
365 iowrite32(startup
? 0x0201F868 : 0x0001F868, ioaddr
+ 0xB8);
367 iowrite32(0x32, ioaddr
+ CSR12
);
368 new_csr6
= 0x00420000;
369 iowrite32(0x1F078, ioaddr
+ 0xB8);
371 } else { /* Unknown chip type with no media table. */
372 if (tp
->default_port
== 0)
373 dev
->if_port
= tp
->mii_cnt
? 11 : 3;
374 if (tulip_media_cap
[dev
->if_port
] & MediaIsMII
) {
375 new_csr6
= 0x020E0000;
376 } else if (tulip_media_cap
[dev
->if_port
] & MediaIsFx
) {
377 new_csr6
= 0x02860000;
379 new_csr6
= 0x03860000;
381 netdev_dbg(dev
, "No media description table, assuming %s transceiver, CSR12 %02x\n",
382 medianame
[dev
->if_port
],
383 ioread32(ioaddr
+ CSR12
));
386 tp
->csr6
= new_csr6
| (tp
->csr6
& 0xfdff) | (tp
->full_duplex
? 0x0200 : 0);
392 Check the MII negotiated duplex and change the CSR6 setting if
394 Return 0 if everything is OK.
395 Return < 0 if the transceiver is missing or has no link beat.
397 int tulip_check_duplex(struct net_device
*dev
)
399 struct tulip_private
*tp
= netdev_priv(dev
);
400 unsigned int bmsr
, lpa
, negotiated
, new_csr6
;
402 bmsr
= tulip_mdio_read(dev
, tp
->phys
[0], MII_BMSR
);
403 lpa
= tulip_mdio_read(dev
, tp
->phys
[0], MII_LPA
);
405 dev_info(&dev
->dev
, "MII status %04x, Link partner report %04x\n",
409 if ((bmsr
& BMSR_LSTATUS
) == 0) {
410 int new_bmsr
= tulip_mdio_read(dev
, tp
->phys
[0], MII_BMSR
);
411 if ((new_bmsr
& BMSR_LSTATUS
) == 0) {
414 "No link beat on the MII interface, status %04x\n",
419 negotiated
= lpa
& tp
->advertising
[0];
420 tp
->full_duplex
= mii_duplex(tp
->full_duplex_lock
, negotiated
);
424 if (negotiated
& LPA_100
) new_csr6
&= ~TxThreshold
;
425 else new_csr6
|= TxThreshold
;
426 if (tp
->full_duplex
) new_csr6
|= FullDuplex
;
427 else new_csr6
&= ~FullDuplex
;
429 if (new_csr6
!= tp
->csr6
) {
431 tulip_restart_rxtx(tp
);
435 "Setting %s-duplex based on MII#%d link partner capability of %04x\n",
436 tp
->full_duplex
? "full" : "half",
444 void tulip_find_mii(struct net_device
*dev
, int board_idx
)
446 struct tulip_private
*tp
= netdev_priv(dev
);
447 int phyn
, phy_idx
= 0;
450 unsigned int to_advert
, new_bmcr
, ane_switch
;
452 /* Find the connected MII xcvrs.
453 Doing this in open() would allow detecting external xcvrs later,
454 but takes much time. */
455 for (phyn
= 1; phyn
<= 32 && phy_idx
< ARRAY_SIZE(tp
->phys
); phyn
++) {
456 int phy
= phyn
& 0x1f;
457 int mii_status
= tulip_mdio_read (dev
, phy
, MII_BMSR
);
458 if ((mii_status
& 0x8301) == 0x8001 ||
459 ((mii_status
& BMSR_100BASE4
) == 0 &&
460 (mii_status
& 0x7800) != 0)) {
461 /* preserve Becker logic, gain indentation level */
466 mii_reg0
= tulip_mdio_read (dev
, phy
, MII_BMCR
);
467 mii_advert
= tulip_mdio_read (dev
, phy
, MII_ADVERTISE
);
470 /* if not advertising at all, gen an
471 * advertising value from the capability
474 if ((mii_advert
& ADVERTISE_ALL
) == 0) {
475 unsigned int tmpadv
= tulip_mdio_read (dev
, phy
, MII_BMSR
);
476 mii_advert
= ((tmpadv
>> 6) & 0x3e0) | 1;
479 if (tp
->mii_advertise
) {
480 tp
->advertising
[phy_idx
] =
481 to_advert
= tp
->mii_advertise
;
482 } else if (tp
->advertising
[phy_idx
]) {
483 to_advert
= tp
->advertising
[phy_idx
];
485 tp
->advertising
[phy_idx
] =
487 to_advert
= mii_advert
;
490 tp
->phys
[phy_idx
++] = phy
;
492 pr_info("tulip%d: MII transceiver #%d config %04x status %04x advertising %04x\n",
493 board_idx
, phy
, mii_reg0
, mii_status
, mii_advert
);
495 /* Fixup for DLink with miswired PHY. */
496 if (mii_advert
!= to_advert
) {
497 pr_debug("tulip%d: Advertising %04x on PHY %d, previously advertising %04x\n",
498 board_idx
, to_advert
, phy
, mii_advert
);
499 tulip_mdio_write (dev
, phy
, 4, to_advert
);
502 /* Enable autonegotiation: some boards default to off. */
503 if (tp
->default_port
== 0) {
504 new_bmcr
= mii_reg0
| BMCR_ANENABLE
;
505 if (new_bmcr
!= mii_reg0
) {
506 new_bmcr
|= BMCR_ANRESTART
;
510 /* ...or disable nway, if forcing media */
512 new_bmcr
= mii_reg0
& ~BMCR_ANENABLE
;
513 if (new_bmcr
!= mii_reg0
)
517 /* clear out bits we never want at this point */
518 new_bmcr
&= ~(BMCR_CTST
| BMCR_FULLDPLX
| BMCR_ISOLATE
|
519 BMCR_PDOWN
| BMCR_SPEED100
| BMCR_LOOPBACK
|
523 new_bmcr
|= BMCR_FULLDPLX
;
524 if (tulip_media_cap
[tp
->default_port
] & MediaIs100
)
525 new_bmcr
|= BMCR_SPEED100
;
527 if (new_bmcr
!= mii_reg0
) {
528 /* some phys need the ANE switch to
529 * happen before forced media settings
530 * will "take." However, we write the
531 * same value twice in order not to
532 * confuse the sane phys.
535 tulip_mdio_write (dev
, phy
, MII_BMCR
, new_bmcr
);
538 tulip_mdio_write (dev
, phy
, MII_BMCR
, new_bmcr
);
541 tp
->mii_cnt
= phy_idx
;
542 if (tp
->mtable
&& tp
->mtable
->has_mii
&& phy_idx
== 0) {
543 pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n",