drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
   3
   4 #ifndef __HCLGEVF_CMD_H
   5 #define __HCLGEVF_CMD_H
   6 #include <linux/io.h>
   7 #include <linux/types.h>
   8 #include "hnae3.h"
   9
  10 #define HCLGEVF_CMDQ_TX_TIMEOUT         30000
  11 #define HCLGEVF_CMDQ_RX_INVLD_B         0
  12 #define HCLGEVF_CMDQ_RX_OUTVLD_B        1
  13
  14 struct hclgevf_hw;
  15 struct hclgevf_dev;
  16
  17 struct hclgevf_desc {
  18         __le16 opcode;
  19         __le16 flag;
  20         __le16 retval;
  21         __le16 rsv;
  22         __le32 data[6];
  23 };
  24
  25 struct hclgevf_desc_cb {
  26         dma_addr_t dma;
  27         void *va;
  28         u32 length;
  29 };
  30
  31 struct hclgevf_cmq_ring {
  32         dma_addr_t desc_dma_addr;
  33         struct hclgevf_desc *desc;
  34         struct hclgevf_desc_cb *desc_cb;
  35         struct hclgevf_dev  *dev;
  36         u32 head;
  37         u32 tail;
  38
  39         u16 buf_size;
  40         u16 desc_num;
  41         int next_to_use;
  42         int next_to_clean;
  43         u8 flag;
  44         spinlock_t lock; /* Command queue lock */
  45 };
  46
  47 enum hclgevf_cmd_return_status {
  48         HCLGEVF_CMD_EXEC_SUCCESS        = 0,
  49         HCLGEVF_CMD_NO_AUTH             = 1,
  50         HCLGEVF_CMD_NOT_SUPPORTED       = 2,
  51         HCLGEVF_CMD_QUEUE_FULL          = 3,
  52         HCLGEVF_CMD_NEXT_ERR            = 4,
  53         HCLGEVF_CMD_UNEXE_ERR           = 5,
  54         HCLGEVF_CMD_PARA_ERR            = 6,
  55         HCLGEVF_CMD_RESULT_ERR          = 7,
  56         HCLGEVF_CMD_TIMEOUT             = 8,
  57         HCLGEVF_CMD_HILINK_ERR          = 9,
  58         HCLGEVF_CMD_QUEUE_ILLEGAL       = 10,
  59         HCLGEVF_CMD_INVALID             = 11,
  60 };
  61
  62 enum hclgevf_cmd_status {
  63         HCLGEVF_STATUS_SUCCESS  = 0,
  64         HCLGEVF_ERR_CSQ_FULL    = -1,
  65         HCLGEVF_ERR_CSQ_TIMEOUT = -2,
  66         HCLGEVF_ERR_CSQ_ERROR   = -3
  67 };
  68
  69 struct hclgevf_cmq {
  70         struct hclgevf_cmq_ring csq;
  71         struct hclgevf_cmq_ring crq;
  72         u16 tx_timeout; /* Tx timeout */
  73         enum hclgevf_cmd_status last_status;
  74 };
  75
  76 #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT         0
  77 #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT        1
  78 #define HCLGEVF_CMD_FLAG_NEXT_SHIFT             2
  79 #define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT         3
  80 #define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT          4
  81 #define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT         5
  82
  83 #define HCLGEVF_CMD_FLAG_IN             BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
  84 #define HCLGEVF_CMD_FLAG_OUT            BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
  85 #define HCLGEVF_CMD_FLAG_NEXT           BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
  86 #define HCLGEVF_CMD_FLAG_WR             BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
  87 #define HCLGEVF_CMD_FLAG_NO_INTR        BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
  88 #define HCLGEVF_CMD_FLAG_ERR_INTR       BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
  89
  90 enum hclgevf_opcode_type {
  91         /* Generic command */
  92         HCLGEVF_OPC_QUERY_FW_VER        = 0x0001,
  93         HCLGEVF_OPC_QUERY_VF_RSRC       = 0x0024,
  94         HCLGEVF_OPC_QUERY_DEV_SPECS     = 0x0050,
  95
  96         /* TQP command */
  97         HCLGEVF_OPC_QUERY_TX_STATUS     = 0x0B03,
  98         HCLGEVF_OPC_QUERY_RX_STATUS     = 0x0B13,
  99         HCLGEVF_OPC_CFG_COM_TQP_QUEUE   = 0x0B20,
 100         /* GRO command */
 101         HCLGEVF_OPC_GRO_GENERIC_CONFIG  = 0x0C10,
 102         /* RSS cmd */
 103         HCLGEVF_OPC_RSS_GENERIC_CONFIG  = 0x0D01,
 104         HCLGEVF_OPC_RSS_INPUT_TUPLE     = 0x0D02,
 105         HCLGEVF_OPC_RSS_INDIR_TABLE     = 0x0D07,
 106         HCLGEVF_OPC_RSS_TC_MODE         = 0x0D08,
 107         /* Mailbox cmd */
 108         HCLGEVF_OPC_MBX_VF_TO_PF        = 0x2001,
 109 };
 110
 111 #define HCLGEVF_TQP_REG_OFFSET          0x80000
 112 #define HCLGEVF_TQP_REG_SIZE            0x200
 113
 114 #define HCLGEVF_TQP_MAX_SIZE_DEV_V2     1024
 115 #define HCLGEVF_TQP_EXT_REG_OFFSET      0x100
 116
 117 struct hclgevf_tqp_map {
 118         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 119         u8 tqp_vf; /* VF id */
 120 #define HCLGEVF_TQP_MAP_TYPE_PF         0
 121 #define HCLGEVF_TQP_MAP_TYPE_VF         1
 122 #define HCLGEVF_TQP_MAP_TYPE_B          0
 123 #define HCLGEVF_TQP_MAP_EN_B            1
 124         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 125         __le16 tqp_vid; /* Virtual id in this pf/vf */
 126         u8 rsv[18];
 127 };
 128
 129 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
 130
 131 enum hclgevf_int_type {
 132         HCLGEVF_INT_TX = 0,
 133         HCLGEVF_INT_RX,
 134         HCLGEVF_INT_EVENT,
 135 };
 136
 137 struct hclgevf_ctrl_vector_chain {
 138         u8 int_vector_id;
 139         u8 int_cause_num;
 140 #define HCLGEVF_INT_TYPE_S      0
 141 #define HCLGEVF_INT_TYPE_M      0x3
 142 #define HCLGEVF_TQP_ID_S        2
 143 #define HCLGEVF_TQP_ID_M        (0x3fff << HCLGEVF_TQP_ID_S)
 144         __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
 145         u8 vfid;
 146         u8 resv;
 147 };
 148
 149 enum HCLGEVF_CAP_BITS {
 150         HCLGEVF_CAP_UDP_GSO_B,
 151         HCLGEVF_CAP_QB_B,
 152         HCLGEVF_CAP_FD_FORWARD_TC_B,
 153         HCLGEVF_CAP_PTP_B,
 154         HCLGEVF_CAP_INT_QL_B,
 155         HCLGEVF_CAP_HW_TX_CSUM_B,
 156         HCLGEVF_CAP_TX_PUSH_B,
 157         HCLGEVF_CAP_PHY_IMP_B,
 158         HCLGEVF_CAP_TQP_TXRX_INDEP_B,
 159         HCLGEVF_CAP_HW_PAD_B,
 160         HCLGEVF_CAP_STASH_B,
 161         HCLGEVF_CAP_UDP_TUNNEL_CSUM_B,
 162 };
 163
 164 #define HCLGEVF_QUERY_CAP_LENGTH                3
 165 struct hclgevf_query_version_cmd {
 166         __le32 firmware;
 167         __le32 hardware;
 168         __le32 rsv;
 169         __le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
 170 };
 171
 172 #define HCLGEVF_MSIX_OFT_ROCEE_S       0
 173 #define HCLGEVF_MSIX_OFT_ROCEE_M       (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
 174 #define HCLGEVF_VEC_NUM_S              0
 175 #define HCLGEVF_VEC_NUM_M              (0xff << HCLGEVF_VEC_NUM_S)
 176 struct hclgevf_query_res_cmd {
 177         __le16 tqp_num;
 178         __le16 reserved;
 179         __le16 msixcap_localid_ba_nic;
 180         __le16 msixcap_localid_ba_rocee;
 181         __le16 vf_intr_vector_number;
 182         __le16 rsv[7];
 183 };
 184
 185 #define HCLGEVF_GRO_EN_B               0
 186 struct hclgevf_cfg_gro_status_cmd {
 187         u8 gro_en;
 188         u8 rsv[23];
 189 };
 190
 191 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B   4
 192 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B   4
 193 #define HCLGEVF_RSS_HASH_KEY_NUM        16
 194 struct hclgevf_rss_config_cmd {
 195         u8 hash_config;
 196         u8 rsv[7];
 197         u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM];
 198 };
 199
 200 struct hclgevf_rss_input_tuple_cmd {
 201         u8 ipv4_tcp_en;
 202         u8 ipv4_udp_en;
 203         u8 ipv4_sctp_en;
 204         u8 ipv4_fragment_en;
 205         u8 ipv6_tcp_en;
 206         u8 ipv6_udp_en;
 207         u8 ipv6_sctp_en;
 208         u8 ipv6_fragment_en;
 209         u8 rsv[16];
 210 };
 211
 212 #define HCLGEVF_RSS_CFG_TBL_SIZE        16
 213
 214 struct hclgevf_rss_indirection_table_cmd {
 215         u16 start_table_index;
 216         u16 rss_set_bitmap;
 217         u8 rsv[4];
 218         u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
 219 };
 220
 221 #define HCLGEVF_RSS_TC_OFFSET_S         0
 222 #define HCLGEVF_RSS_TC_OFFSET_M         (0x3ff << HCLGEVF_RSS_TC_OFFSET_S)
 223 #define HCLGEVF_RSS_TC_SIZE_S           12
 224 #define HCLGEVF_RSS_TC_SIZE_M           (0x7 << HCLGEVF_RSS_TC_SIZE_S)
 225 #define HCLGEVF_RSS_TC_VALID_B          15
 226 #define HCLGEVF_MAX_TC_NUM              8
 227 struct hclgevf_rss_tc_mode_cmd {
 228         u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
 229         u8 rsv[8];
 230 };
 231
 232 #define HCLGEVF_LINK_STS_B      0
 233 #define HCLGEVF_LINK_STATUS     BIT(HCLGEVF_LINK_STS_B)
 234 struct hclgevf_link_status_cmd {
 235         u8 status;
 236         u8 rsv[23];
 237 };
 238
 239 #define HCLGEVF_RING_ID_MASK    0x3ff
 240 #define HCLGEVF_TQP_ENABLE_B    0
 241
 242 struct hclgevf_cfg_com_tqp_queue_cmd {
 243         __le16 tqp_id;
 244         __le16 stream_id;
 245         u8 enable;
 246         u8 rsv[19];
 247 };
 248
 249 struct hclgevf_cfg_tx_queue_pointer_cmd {
 250         __le16 tqp_id;
 251         __le16 tx_tail;
 252         __le16 tx_head;
 253         __le16 fbd_num;
 254         __le16 ring_offset;
 255         u8 rsv[14];
 256 };
 257
 258 #define HCLGEVF_TYPE_CRQ                0
 259 #define HCLGEVF_TYPE_CSQ                1
 260 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG  0x27000
 261 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG  0x27004
 262 #define HCLGEVF_NIC_CSQ_DEPTH_REG       0x27008
 263 #define HCLGEVF_NIC_CSQ_TAIL_REG        0x27010
 264 #define HCLGEVF_NIC_CSQ_HEAD_REG        0x27014
 265 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG  0x27018
 266 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG  0x2701c
 267 #define HCLGEVF_NIC_CRQ_DEPTH_REG       0x27020
 268 #define HCLGEVF_NIC_CRQ_TAIL_REG        0x27024
 269 #define HCLGEVF_NIC_CRQ_HEAD_REG        0x27028
 270
 271 /* this bit indicates that the driver is ready for hardware reset */
 272 #define HCLGEVF_NIC_SW_RST_RDY_B        16
 273 #define HCLGEVF_NIC_SW_RST_RDY          BIT(HCLGEVF_NIC_SW_RST_RDY_B)
 274
 275 #define HCLGEVF_NIC_CMQ_DESC_NUM        1024
 276 #define HCLGEVF_NIC_CMQ_DESC_NUM_S      3
 277 #define HCLGEVF_NIC_CMDQ_INT_SRC_REG    0x27100
 278
 279 #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM          4
 280
 281 struct hclgevf_dev_specs_0_cmd {
 282         __le32 rsv0;
 283         __le32 mac_entry_num;
 284         __le32 mng_entry_num;
 285         __le16 rss_ind_tbl_size;
 286         __le16 rss_key_size;
 287         __le16 int_ql_max;
 288         u8 max_non_tso_bd_num;
 289         u8 rsv1[5];
 290 };
 291
 292 #define HCLGEVF_DEF_MAX_INT_GL          0x1FE0U
 293
 294 struct hclgevf_dev_specs_1_cmd {
 295         __le32 rsv0;
 296         __le16 max_int_gl;
 297         u8 rsv1[18];
 298 };
 299
 300 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
 301 {
 302         writel(value, base + reg);
 303 }
 304
 305 static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
 306 {
 307         u8 __iomem *reg_addr = READ_ONCE(base);
 308
 309         return readl(reg_addr + reg);
 310 }
 311
 312 #define hclgevf_write_dev(a, reg, value) \
 313         hclgevf_write_reg((a)->io_base, (reg), (value))
 314 #define hclgevf_read_dev(a, reg) \
 315         hclgevf_read_reg((a)->io_base, (reg))
 316
 317 #define HCLGEVF_SEND_SYNC(flag) \
 318         ((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
 319
 320 int hclgevf_cmd_init(struct hclgevf_dev *hdev);
 321 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
 322 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
 323
 324 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
 325 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
 326                                   enum hclgevf_opcode_type opcode,
 327                                   bool is_read);
 328 #endif