drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Huawei HiNIC PCI Express Linux driver
   4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   5  */
   6
   7 #ifndef HINIC_HW_CSR_H
   8 #define HINIC_HW_CSR_H
   9
  10 /* HW interface registers */
  11 #define HINIC_CSR_FUNC_ATTR0_ADDR                       0x0
  12 #define HINIC_CSR_FUNC_ATTR1_ADDR                       0x4
  13 #define HINIC_CSR_FUNC_ATTR2_ADDR                       0x8
  14 #define HINIC_CSR_FUNC_ATTR4_ADDR                       0x10
  15 #define HINIC_CSR_FUNC_ATTR5_ADDR                       0x14
  16
  17 #define HINIC_DMA_ATTR_BASE                             0xC80
  18 #define HINIC_ELECTION_BASE                             0x4200
  19
  20 #define HINIC_DMA_ATTR_STRIDE                           0x4
  21 #define HINIC_CSR_DMA_ATTR_ADDR(idx)                    \
  22         (HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
  23
  24 #define HINIC_PPF_ELECTION_STRIDE                       0x4
  25 #define HINIC_CSR_MAX_PORTS                             4
  26
  27 #define HINIC_CSR_PPF_ELECTION_ADDR(idx)                \
  28         (HINIC_ELECTION_BASE +  (idx) * HINIC_PPF_ELECTION_STRIDE)
  29
  30 /* API CMD registers */
  31 #define HINIC_CSR_API_CMD_BASE                          0xF000
  32
  33 #define HINIC_CSR_API_CMD_STRIDE                        0x100
  34
  35 #define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)       \
  36         (HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  37
  38 #define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)       \
  39         (HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  40
  41 #define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)           \
  42         (HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  43
  44 #define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)           \
  45         (HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
  46
  47 #define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)     \
  48         (HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  49
  50 #define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)          \
  51         (HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  52
  53 #define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)            \
  54         (HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
  55
  56 #define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)           \
  57         (HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  58
  59 #define HINIC_CSR_API_CMD_STATUS_ADDR(idx)              \
  60         (HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
  61
  62 /* MSI-X registers */
  63 #define HINIC_CSR_MSIX_CTRL_BASE                        0x2000
  64 #define HINIC_CSR_MSIX_CNT_BASE                         0x2004
  65
  66 #define HINIC_CSR_MSIX_STRIDE                           0x8
  67
  68 #define HINIC_CSR_MSIX_CTRL_ADDR(idx)                   \
  69         (HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
  70
  71 #define HINIC_CSR_MSIX_CNT_ADDR(idx)                    \
  72         (HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
  73
  74 /* EQ registers */
  75 #define HINIC_AEQ_MTT_OFF_BASE_ADDR                     0x200
  76 #define HINIC_CEQ_MTT_OFF_BASE_ADDR                     0x400
  77
  78 #define HINIC_EQ_MTT_OFF_STRIDE                         0x40
  79
  80 #define HINIC_CSR_AEQ_MTT_OFF(id)                       \
  81         (HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
  82
  83 #define HINIC_CSR_CEQ_MTT_OFF(id)                       \
  84         (HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
  85
  86 #define HINIC_CSR_EQ_PAGE_OFF_STRIDE                    8
  87
  88 #define HINIC_CSR_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
  89         (HINIC_CSR_AEQ_MTT_OFF(q_id) + \
  90          (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
  91
  92 #define HINIC_CSR_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
  93         (HINIC_CSR_CEQ_MTT_OFF(q_id) +          \
  94          (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
  95
  96 #define HINIC_CSR_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
  97         (HINIC_CSR_AEQ_MTT_OFF(q_id) + \
  98          (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
  99
 100 #define HINIC_CSR_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
 101         (HINIC_CSR_CEQ_MTT_OFF(q_id) +  \
 102          (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
 103
 104 #define HINIC_AEQ_CTRL_0_ADDR_BASE                      0xE00
 105 #define HINIC_AEQ_CTRL_1_ADDR_BASE                      0xE04
 106 #define HINIC_AEQ_CONS_IDX_ADDR_BASE                    0xE08
 107 #define HINIC_AEQ_PROD_IDX_ADDR_BASE                    0xE0C
 108
 109 #define HINIC_CEQ_CTRL_0_ADDR_BASE                      0x1000
 110 #define HINIC_CEQ_CTRL_1_ADDR_BASE                      0x1004
 111 #define HINIC_CEQ_CONS_IDX_ADDR_BASE                    0x1008
 112 #define HINIC_CEQ_PROD_IDX_ADDR_BASE                    0x100C
 113
 114 #define HINIC_EQ_OFF_STRIDE                             0x80
 115
 116 #define HINIC_CSR_AEQ_CTRL_0_ADDR(idx)                  \
 117         (HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 118
 119 #define HINIC_CSR_AEQ_CTRL_1_ADDR(idx)                  \
 120         (HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 121
 122 #define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx)                \
 123         (HINIC_AEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 124
 125 #define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx)                \
 126         (HINIC_AEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 127
 128 #define HINIC_CSR_CEQ_CTRL_0_ADDR(idx)                  \
 129         (HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 130
 131 #define HINIC_CSR_CEQ_CTRL_1_ADDR(idx)                  \
 132         (HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 133
 134 #define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx)                \
 135         (HINIC_CEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 136
 137 #define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx)                \
 138         (HINIC_CEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
 139
 140 #endif