drivers/net/ethernet/intel/igc/igc.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c)  2018 Intel Corporation */
   3
   4 #ifndef _IGC_H_
   5 #define _IGC_H_
   6
   7 #include <linux/kobject.h>
   8 #include <linux/pci.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/vmalloc.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/sctp.h>
  13 #include <linux/ptp_clock_kernel.h>
  14 #include <linux/timecounter.h>
  15 #include <linux/net_tstamp.h>
  16
  17 #include "igc_hw.h"
  18
  19 void igc_ethtool_set_ops(struct net_device *);
  20
  21 /* Transmit and receive queues */
  22 #define IGC_MAX_RX_QUEUES               4
  23 #define IGC_MAX_TX_QUEUES               4
  24
  25 #define MAX_Q_VECTORS                   8
  26 #define MAX_STD_JUMBO_FRAME_SIZE        9216
  27
  28 #define MAX_ETYPE_FILTER                8
  29 #define IGC_RETA_SIZE                   128
  30
  31 enum igc_mac_filter_type {
  32         IGC_MAC_FILTER_TYPE_DST = 0,
  33         IGC_MAC_FILTER_TYPE_SRC
  34 };
  35
  36 struct igc_tx_queue_stats {
  37         u64 packets;
  38         u64 bytes;
  39         u64 restart_queue;
  40         u64 restart_queue2;
  41 };
  42
  43 struct igc_rx_queue_stats {
  44         u64 packets;
  45         u64 bytes;
  46         u64 drops;
  47         u64 csum_err;
  48         u64 alloc_failed;
  49 };
  50
  51 struct igc_rx_packet_stats {
  52         u64 ipv4_packets;      /* IPv4 headers processed */
  53         u64 ipv4e_packets;     /* IPv4E headers with extensions processed */
  54         u64 ipv6_packets;      /* IPv6 headers processed */
  55         u64 ipv6e_packets;     /* IPv6E headers with extensions processed */
  56         u64 tcp_packets;       /* TCP headers processed */
  57         u64 udp_packets;       /* UDP headers processed */
  58         u64 sctp_packets;      /* SCTP headers processed */
  59         u64 nfs_packets;       /* NFS headers processe */
  60         u64 other_packets;
  61 };
  62
  63 struct igc_ring_container {
  64         struct igc_ring *ring;          /* pointer to linked list of rings */
  65         unsigned int total_bytes;       /* total bytes processed this int */
  66         unsigned int total_packets;     /* total packets processed this int */
  67         u16 work_limit;                 /* total work allowed per interrupt */
  68         u8 count;                       /* total number of rings in vector */
  69         u8 itr;                         /* current ITR setting for ring */
  70 };
  71
  72 struct igc_ring {
  73         struct igc_q_vector *q_vector;  /* backlink to q_vector */
  74         struct net_device *netdev;      /* back pointer to net_device */
  75         struct device *dev;             /* device for dma mapping */
  76         union {                         /* array of buffer info structs */
  77                 struct igc_tx_buffer *tx_buffer_info;
  78                 struct igc_rx_buffer *rx_buffer_info;
  79         };
  80         void *desc;                     /* descriptor ring memory */
  81         unsigned long flags;            /* ring specific flags */
  82         void __iomem *tail;             /* pointer to ring tail register */
  83         dma_addr_t dma;                 /* phys address of the ring */
  84         unsigned int size;              /* length of desc. ring in bytes */
  85
  86         u16 count;                      /* number of desc. in the ring */
  87         u8 queue_index;                 /* logical index of the ring*/
  88         u8 reg_idx;                     /* physical index of the ring */
  89         bool launchtime_enable;         /* true if LaunchTime is enabled */
  90
  91         u32 start_time;
  92         u32 end_time;
  93
  94         /* everything past this point are written often */
  95         u16 next_to_clean;
  96         u16 next_to_use;
  97         u16 next_to_alloc;
  98
  99         union {
 100                 /* TX */
 101                 struct {
 102                         struct igc_tx_queue_stats tx_stats;
 103                         struct u64_stats_sync tx_syncp;
 104                         struct u64_stats_sync tx_syncp2;
 105                 };
 106                 /* RX */
 107                 struct {
 108                         struct igc_rx_queue_stats rx_stats;
 109                         struct igc_rx_packet_stats pkt_stats;
 110                         struct u64_stats_sync rx_syncp;
 111                         struct sk_buff *skb;
 112                 };
 113         };
 114 } ____cacheline_internodealigned_in_smp;
 115
 116 /* Board specific private data structure */
 117 struct igc_adapter {
 118         struct net_device *netdev;
 119
 120         struct ethtool_eee eee;
 121         u16 eee_advert;
 122
 123         unsigned long state;
 124         unsigned int flags;
 125         unsigned int num_q_vectors;
 126
 127         struct msix_entry *msix_entries;
 128
 129         /* TX */
 130         u16 tx_work_limit;
 131         u32 tx_timeout_count;
 132         int num_tx_queues;
 133         struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
 134
 135         /* RX */
 136         int num_rx_queues;
 137         struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
 138
 139         struct timer_list watchdog_timer;
 140         struct timer_list dma_err_timer;
 141         struct timer_list phy_info_timer;
 142
 143         u32 wol;
 144         u32 en_mng_pt;
 145         u16 link_speed;
 146         u16 link_duplex;
 147
 148         u8 port_num;
 149
 150         u8 __iomem *io_addr;
 151         /* Interrupt Throttle Rate */
 152         u32 rx_itr_setting;
 153         u32 tx_itr_setting;
 154
 155         struct work_struct reset_task;
 156         struct work_struct watchdog_task;
 157         struct work_struct dma_err_task;
 158         bool fc_autoneg;
 159
 160         u8 tx_timeout_factor;
 161
 162         int msg_enable;
 163         u32 max_frame_size;
 164         u32 min_frame_size;
 165
 166         ktime_t base_time;
 167         ktime_t cycle_time;
 168
 169         /* OS defined structs */
 170         struct pci_dev *pdev;
 171         /* lock for statistics */
 172         spinlock_t stats64_lock;
 173         struct rtnl_link_stats64 stats64;
 174
 175         /* structs defined in igc_hw.h */
 176         struct igc_hw hw;
 177         struct igc_hw_stats stats;
 178
 179         struct igc_q_vector *q_vector[MAX_Q_VECTORS];
 180         u32 eims_enable_mask;
 181         u32 eims_other;
 182
 183         u16 tx_ring_count;
 184         u16 rx_ring_count;
 185
 186         u32 tx_hwtstamp_timeouts;
 187         u32 tx_hwtstamp_skipped;
 188         u32 rx_hwtstamp_cleared;
 189
 190         u32 rss_queues;
 191         u32 rss_indir_tbl_init;
 192
 193         /* Any access to elements in nfc_rule_list is protected by the
 194          * nfc_rule_lock.
 195          */
 196         struct mutex nfc_rule_lock;
 197         struct list_head nfc_rule_list;
 198         unsigned int nfc_rule_count;
 199
 200         u8 rss_indir_tbl[IGC_RETA_SIZE];
 201
 202         unsigned long link_check_timeout;
 203         struct igc_info ei;
 204
 205         u32 test_icr;
 206
 207         struct ptp_clock *ptp_clock;
 208         struct ptp_clock_info ptp_caps;
 209         struct work_struct ptp_tx_work;
 210         struct sk_buff *ptp_tx_skb;
 211         struct hwtstamp_config tstamp_config;
 212         unsigned long ptp_tx_start;
 213         unsigned int ptp_flags;
 214         /* System time value lock */
 215         spinlock_t tmreg_lock;
 216         struct cyclecounter cc;
 217         struct timecounter tc;
 218         struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
 219         ktime_t ptp_reset_start; /* Reset time in clock mono */
 220 };
 221
 222 void igc_up(struct igc_adapter *adapter);
 223 void igc_down(struct igc_adapter *adapter);
 224 int igc_open(struct net_device *netdev);
 225 int igc_close(struct net_device *netdev);
 226 int igc_setup_tx_resources(struct igc_ring *ring);
 227 int igc_setup_rx_resources(struct igc_ring *ring);
 228 void igc_free_tx_resources(struct igc_ring *ring);
 229 void igc_free_rx_resources(struct igc_ring *ring);
 230 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
 231 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
 232                               const u32 max_rss_queues);
 233 int igc_reinit_queues(struct igc_adapter *adapter);
 234 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
 235 bool igc_has_link(struct igc_adapter *adapter);
 236 void igc_reset(struct igc_adapter *adapter);
 237 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
 238 void igc_update_stats(struct igc_adapter *adapter);
 239
 240 /* igc_dump declarations */
 241 void igc_rings_dump(struct igc_adapter *adapter);
 242 void igc_regs_dump(struct igc_adapter *adapter);
 243
 244 extern char igc_driver_name[];
 245
 246 #define IGC_REGS_LEN                    740
 247
 248 /* flags controlling PTP/1588 function */
 249 #define IGC_PTP_ENABLED         BIT(0)
 250
 251 /* Flags definitions */
 252 #define IGC_FLAG_HAS_MSI                BIT(0)
 253 #define IGC_FLAG_QUEUE_PAIRS            BIT(3)
 254 #define IGC_FLAG_DMAC                   BIT(4)
 255 #define IGC_FLAG_PTP                    BIT(8)
 256 #define IGC_FLAG_WOL_SUPPORTED          BIT(8)
 257 #define IGC_FLAG_NEED_LINK_UPDATE       BIT(9)
 258 #define IGC_FLAG_MEDIA_RESET            BIT(10)
 259 #define IGC_FLAG_MAS_ENABLE             BIT(12)
 260 #define IGC_FLAG_HAS_MSIX               BIT(13)
 261 #define IGC_FLAG_EEE                    BIT(14)
 262 #define IGC_FLAG_VLAN_PROMISC           BIT(15)
 263 #define IGC_FLAG_RX_LEGACY              BIT(16)
 264 #define IGC_FLAG_TSN_QBV_ENABLED        BIT(17)
 265
 266 #define IGC_FLAG_RSS_FIELD_IPV4_UDP     BIT(6)
 267 #define IGC_FLAG_RSS_FIELD_IPV6_UDP     BIT(7)
 268
 269 #define IGC_MRQC_ENABLE_RSS_MQ          0x00000002
 270 #define IGC_MRQC_RSS_FIELD_IPV4_UDP     0x00400000
 271 #define IGC_MRQC_RSS_FIELD_IPV6_UDP     0x00800000
 272
 273 /* Interrupt defines */
 274 #define IGC_START_ITR                   648 /* ~6000 ints/sec */
 275 #define IGC_4K_ITR                      980
 276 #define IGC_20K_ITR                     196
 277 #define IGC_70K_ITR                     56
 278
 279 #define IGC_DEFAULT_ITR         3 /* dynamic */
 280 #define IGC_MAX_ITR_USECS       10000
 281 #define IGC_MIN_ITR_USECS       10
 282 #define NON_Q_VECTORS           1
 283 #define MAX_MSIX_ENTRIES        10
 284
 285 /* TX/RX descriptor defines */
 286 #define IGC_DEFAULT_TXD         256
 287 #define IGC_DEFAULT_TX_WORK     128
 288 #define IGC_MIN_TXD             80
 289 #define IGC_MAX_TXD             4096
 290
 291 #define IGC_DEFAULT_RXD         256
 292 #define IGC_MIN_RXD             80
 293 #define IGC_MAX_RXD             4096
 294
 295 /* Supported Rx Buffer Sizes */
 296 #define IGC_RXBUFFER_256                256
 297 #define IGC_RXBUFFER_2048               2048
 298 #define IGC_RXBUFFER_3072               3072
 299
 300 #define AUTO_ALL_MODES          0
 301 #define IGC_RX_HDR_LEN                  IGC_RXBUFFER_256
 302
 303 /* Transmit and receive latency (for PTP timestamps) */
 304 #define IGC_I225_TX_LATENCY_10          240
 305 #define IGC_I225_TX_LATENCY_100         58
 306 #define IGC_I225_TX_LATENCY_1000        80
 307 #define IGC_I225_TX_LATENCY_2500        1325
 308 #define IGC_I225_RX_LATENCY_10          6450
 309 #define IGC_I225_RX_LATENCY_100         185
 310 #define IGC_I225_RX_LATENCY_1000        300
 311 #define IGC_I225_RX_LATENCY_2500        1485
 312
 313 /* RX and TX descriptor control thresholds.
 314  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 315  *           descriptors available in its onboard memory.
 316  *           Setting this to 0 disables RX descriptor prefetch.
 317  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 318  *           available in host memory.
 319  *           If PTHRESH is 0, this should also be 0.
 320  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 321  *           descriptors until either it has this many to write back, or the
 322  *           ITR timer expires.
 323  */
 324 #define IGC_RX_PTHRESH                  8
 325 #define IGC_RX_HTHRESH                  8
 326 #define IGC_TX_PTHRESH                  8
 327 #define IGC_TX_HTHRESH                  1
 328 #define IGC_RX_WTHRESH                  4
 329 #define IGC_TX_WTHRESH                  16
 330
 331 #define IGC_RX_DMA_ATTR \
 332         (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
 333
 334 #define IGC_TS_HDR_LEN                  16
 335
 336 #define IGC_SKB_PAD                     (NET_SKB_PAD + NET_IP_ALIGN)
 337
 338 #if (PAGE_SIZE < 8192)
 339 #define IGC_MAX_FRAME_BUILD_SKB \
 340         (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
 341 #else
 342 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
 343 #endif
 344
 345 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 346 #define IGC_RX_BUFFER_WRITE     16 /* Must be power of 2 */
 347
 348 /* VLAN info */
 349 #define IGC_TX_FLAGS_VLAN_MASK  0xffff0000
 350
 351 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
 352 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
 353                                       const u32 stat_err_bits)
 354 {
 355         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 356 }
 357
 358 enum igc_state_t {
 359         __IGC_TESTING,
 360         __IGC_RESETTING,
 361         __IGC_DOWN,
 362         __IGC_PTP_TX_IN_PROGRESS,
 363 };
 364
 365 enum igc_tx_flags {
 366         /* cmd_type flags */
 367         IGC_TX_FLAGS_VLAN       = 0x01,
 368         IGC_TX_FLAGS_TSO        = 0x02,
 369         IGC_TX_FLAGS_TSTAMP     = 0x04,
 370
 371         /* olinfo flags */
 372         IGC_TX_FLAGS_IPV4       = 0x10,
 373         IGC_TX_FLAGS_CSUM       = 0x20,
 374 };
 375
 376 enum igc_boards {
 377         board_base,
 378 };
 379
 380 /* The largest size we can write to the descriptor is 65535.  In order to
 381  * maintain a power of two alignment we have to limit ourselves to 32K.
 382  */
 383 #define IGC_MAX_TXD_PWR         15
 384 #define IGC_MAX_DATA_PER_TXD    BIT(IGC_MAX_TXD_PWR)
 385
 386 /* Tx Descriptors needed, worst case */
 387 #define TXD_USE_COUNT(S)        DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
 388 #define DESC_NEEDED     (MAX_SKB_FRAGS + 4)
 389
 390 /* wrapper around a pointer to a socket buffer,
 391  * so a DMA handle can be stored along with the buffer
 392  */
 393 struct igc_tx_buffer {
 394         union igc_adv_tx_desc *next_to_watch;
 395         unsigned long time_stamp;
 396         struct sk_buff *skb;
 397         unsigned int bytecount;
 398         u16 gso_segs;
 399         __be16 protocol;
 400
 401         DEFINE_DMA_UNMAP_ADDR(dma);
 402         DEFINE_DMA_UNMAP_LEN(len);
 403         u32 tx_flags;
 404 };
 405
 406 struct igc_rx_buffer {
 407         dma_addr_t dma;
 408         struct page *page;
 409 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
 410         __u32 page_offset;
 411 #else
 412         __u16 page_offset;
 413 #endif
 414         __u16 pagecnt_bias;
 415 };
 416
 417 struct igc_q_vector {
 418         struct igc_adapter *adapter;    /* backlink */
 419         void __iomem *itr_register;
 420         u32 eims_value;                 /* EIMS mask value */
 421
 422         u16 itr_val;
 423         u8 set_itr;
 424
 425         struct igc_ring_container rx, tx;
 426
 427         struct napi_struct napi;
 428
 429         struct rcu_head rcu;    /* to avoid race with update stats on free */
 430         char name[IFNAMSIZ + 9];
 431         struct net_device poll_dev;
 432
 433         /* for dynamic allocation of rings associated with this q_vector */
 434         struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
 435 };
 436
 437 enum igc_filter_match_flags {
 438         IGC_FILTER_FLAG_ETHER_TYPE =    0x1,
 439         IGC_FILTER_FLAG_VLAN_TCI   =    0x2,
 440         IGC_FILTER_FLAG_SRC_MAC_ADDR =  0x4,
 441         IGC_FILTER_FLAG_DST_MAC_ADDR =  0x8,
 442 };
 443
 444 struct igc_nfc_filter {
 445         u8 match_flags;
 446         u16 etype;
 447         u16 vlan_tci;
 448         u8 src_addr[ETH_ALEN];
 449         u8 dst_addr[ETH_ALEN];
 450 };
 451
 452 struct igc_nfc_rule {
 453         struct list_head list;
 454         struct igc_nfc_filter filter;
 455         u32 location;
 456         u16 action;
 457 };
 458
 459 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
 460  * based, and 8 ethertype based.
 461  */
 462 #define IGC_MAX_RXNFC_RULES             32
 463
 464 /* igc_desc_unused - calculate if we have unused descriptors */
 465 static inline u16 igc_desc_unused(const struct igc_ring *ring)
 466 {
 467         u16 ntc = ring->next_to_clean;
 468         u16 ntu = ring->next_to_use;
 469
 470         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 471 }
 472
 473 static inline s32 igc_get_phy_info(struct igc_hw *hw)
 474 {
 475         if (hw->phy.ops.get_phy_info)
 476                 return hw->phy.ops.get_phy_info(hw);
 477
 478         return 0;
 479 }
 480
 481 static inline s32 igc_reset_phy(struct igc_hw *hw)
 482 {
 483         if (hw->phy.ops.reset)
 484                 return hw->phy.ops.reset(hw);
 485
 486         return 0;
 487 }
 488
 489 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
 490 {
 491         return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 492 }
 493
 494 enum igc_ring_flags_t {
 495         IGC_RING_FLAG_RX_3K_BUFFER,
 496         IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
 497         IGC_RING_FLAG_RX_SCTP_CSUM,
 498         IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
 499         IGC_RING_FLAG_TX_CTX_IDX,
 500         IGC_RING_FLAG_TX_DETECT_HANG
 501 };
 502
 503 #define ring_uses_large_buffer(ring) \
 504         test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
 505
 506 #define ring_uses_build_skb(ring) \
 507         test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
 508
 509 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
 510 {
 511 #if (PAGE_SIZE < 8192)
 512         if (ring_uses_large_buffer(ring))
 513                 return IGC_RXBUFFER_3072;
 514
 515         if (ring_uses_build_skb(ring))
 516                 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
 517 #endif
 518         return IGC_RXBUFFER_2048;
 519 }
 520
 521 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
 522 {
 523 #if (PAGE_SIZE < 8192)
 524         if (ring_uses_large_buffer(ring))
 525                 return 1;
 526 #endif
 527         return 0;
 528 }
 529
 530 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
 531 {
 532         if (hw->phy.ops.read_reg)
 533                 return hw->phy.ops.read_reg(hw, offset, data);
 534
 535         return 0;
 536 }
 537
 538 void igc_reinit_locked(struct igc_adapter *);
 539 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
 540                                       u32 location);
 541 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
 542 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
 543
 544 void igc_ptp_init(struct igc_adapter *adapter);
 545 void igc_ptp_reset(struct igc_adapter *adapter);
 546 void igc_ptp_suspend(struct igc_adapter *adapter);
 547 void igc_ptp_stop(struct igc_adapter *adapter);
 548 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va,
 549                          struct sk_buff *skb);
 550 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
 551 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
 552 void igc_ptp_tx_hang(struct igc_adapter *adapter);
 553 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
 554
 555 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
 556
 557 #define IGC_TXD_DCMD    (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
 558
 559 #define IGC_RX_DESC(R, i)       \
 560         (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
 561 #define IGC_TX_DESC(R, i)       \
 562         (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
 563 #define IGC_TX_CTXTDESC(R, i)   \
 564         (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
 565
 566 #endif /* _IGC_H_ */