1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2008 Intel Corporation. */
7 #define IXGB_EEPROM_SIZE 64 /* Size in words */
10 #define EEPROM_READ_OPCODE 0x6 /* EEPROM read opcode */
11 #define EEPROM_WRITE_OPCODE 0x5 /* EEPROM write opcode */
12 #define EEPROM_ERASE_OPCODE 0x7 /* EEPROM erase opcode */
13 #define EEPROM_EWEN_OPCODE 0x13 /* EEPROM erase/write enable */
14 #define EEPROM_EWDS_OPCODE 0x10 /* EEPROM erase/write disable */
16 /* EEPROM MAP (Word Offsets) */
17 #define EEPROM_IA_1_2_REG 0x0000
18 #define EEPROM_IA_3_4_REG 0x0001
19 #define EEPROM_IA_5_6_REG 0x0002
20 #define EEPROM_COMPATIBILITY_REG 0x0003
21 #define EEPROM_PBA_1_2_REG 0x0008
22 #define EEPROM_PBA_3_4_REG 0x0009
23 #define EEPROM_INIT_CONTROL1_REG 0x000A
24 #define EEPROM_SUBSYS_ID_REG 0x000B
25 #define EEPROM_SUBVEND_ID_REG 0x000C
26 #define EEPROM_DEVICE_ID_REG 0x000D
27 #define EEPROM_VENDOR_ID_REG 0x000E
28 #define EEPROM_INIT_CONTROL2_REG 0x000F
29 #define EEPROM_SWDPINS_REG 0x0020
30 #define EEPROM_CIRCUIT_CTRL_REG 0x0021
31 #define EEPROM_D0_D3_POWER_REG 0x0022
32 #define EEPROM_FLASH_VERSION 0x0032
33 #define EEPROM_CHECKSUM_REG 0x003F
35 /* Mask bits for fields in Word 0x0a of the EEPROM */
37 #define EEPROM_ICW1_SIGNATURE_MASK 0xC000
38 #define EEPROM_ICW1_SIGNATURE_VALID 0x4000
39 #define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000
41 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
42 #define EEPROM_SUM 0xBABA
44 /* EEPROM Map Sizes (Byte Counts) */
47 /* EEPROM Map defines (WORD OFFSETS)*/
49 /* EEPROM structure */
50 struct ixgb_ee_map_type
{
51 u8 mac_addr
[ETH_ALEN
];
55 __le16 init_ctrl_reg_1
;
60 __le16 init_ctrl_reg_2
;
61 __le16 oem_reserved
[16];
63 __le16 circuit_ctrl_reg
;
70 /* EEPROM Functions */
71 u16
ixgb_read_eeprom(struct ixgb_hw
*hw
, u16 reg
);
73 bool ixgb_validate_eeprom_checksum(struct ixgb_hw
*hw
);
75 void ixgb_update_eeprom_checksum(struct ixgb_hw
*hw
);
77 void ixgb_write_eeprom(struct ixgb_hw
*hw
, u16 reg
, u16 data
);
79 #endif /* IXGB_EE_H */