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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
blob90e6111ce534dba7f16de983549ade748890124c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
4 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 *
6 * Based on the 64360 driver from:
7 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
8 * Rabeeh Khoury <rabeeh@marvell.com>
9 *
10 * Copyright (C) 2003 PMC-Sierra, Inc.,
11 * written by Manish Lachwani
12 *
13 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 *
15 * Copyright (C) 2004-2006 MontaVista Software, Inc.
16 * Dale Farnsworth <dale@farnsworth.org>
17 *
18 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
19 * <sjhill@realitydiluted.com>
20 *
21 * Copyright (C) 2007-2008 Marvell Semiconductor
22 * Lennert Buytenhek <buytenh@marvell.com>
23 *
24 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 */
26
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28
29 #include <linux/init.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/in.h>
32 #include <linux/ip.h>
33 #include <net/tso.h>
34 #include <linux/tcp.h>
35 #include <linux/udp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/delay.h>
38 #include <linux/ethtool.h>
39 #include <linux/platform_device.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/phy.h>
45 #include <linux/mv643xx_eth.h>
46 #include <linux/io.h>
47 #include <linux/interrupt.h>
48 #include <linux/types.h>
49 #include <linux/slab.h>
50 #include <linux/clk.h>
51 #include <linux/of.h>
52 #include <linux/of_irq.h>
53 #include <linux/of_net.h>
54 #include <linux/of_mdio.h>
55
56 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
57 static char mv643xx_eth_driver_version[] = "1.4";
58
59
60 /*
61 * Registers shared between all ports.
62 */
63 #define PHY_ADDR 0x0000
64 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
65 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
66 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
67 #define WINDOW_BAR_ENABLE 0x0290
68 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
69
70 /*
71 * Main per-port registers. These live at offset 0x0400 for
72 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
73 */
74 #define PORT_CONFIG 0x0000
75 #define UNICAST_PROMISCUOUS_MODE 0x00000001
76 #define PORT_CONFIG_EXT 0x0004
77 #define MAC_ADDR_LOW 0x0014
78 #define MAC_ADDR_HIGH 0x0018
79 #define SDMA_CONFIG 0x001c
80 #define TX_BURST_SIZE_16_64BIT 0x01000000
81 #define TX_BURST_SIZE_4_64BIT 0x00800000
82 #define BLM_TX_NO_SWAP 0x00000020
83 #define BLM_RX_NO_SWAP 0x00000010
84 #define RX_BURST_SIZE_16_64BIT 0x00000008
85 #define RX_BURST_SIZE_4_64BIT 0x00000004
86 #define PORT_SERIAL_CONTROL 0x003c
87 #define SET_MII_SPEED_TO_100 0x01000000
88 #define SET_GMII_SPEED_TO_1000 0x00800000
89 #define SET_FULL_DUPLEX_MODE 0x00200000
90 #define MAX_RX_PACKET_9700BYTE 0x000a0000
91 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
92 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
93 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
94 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
95 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
96 #define FORCE_LINK_PASS 0x00000002
97 #define SERIAL_PORT_ENABLE 0x00000001
98 #define PORT_STATUS 0x0044
99 #define TX_FIFO_EMPTY 0x00000400
100 #define TX_IN_PROGRESS 0x00000080
101 #define PORT_SPEED_MASK 0x00000030
102 #define PORT_SPEED_1000 0x00000010
103 #define PORT_SPEED_100 0x00000020
104 #define PORT_SPEED_10 0x00000000
105 #define FLOW_CONTROL_ENABLED 0x00000008
106 #define FULL_DUPLEX 0x00000004
107 #define LINK_UP 0x00000002
108 #define TXQ_COMMAND 0x0048
109 #define TXQ_FIX_PRIO_CONF 0x004c
110 #define PORT_SERIAL_CONTROL1 0x004c
111 #define CLK125_BYPASS_EN 0x00000010
112 #define TX_BW_RATE 0x0050
113 #define TX_BW_MTU 0x0058
114 #define TX_BW_BURST 0x005c
115 #define INT_CAUSE 0x0060
116 #define INT_TX_END 0x07f80000
117 #define INT_TX_END_0 0x00080000
118 #define INT_RX 0x000003fc
119 #define INT_RX_0 0x00000004
120 #define INT_EXT 0x00000002
121 #define INT_CAUSE_EXT 0x0064
122 #define INT_EXT_LINK_PHY 0x00110000
123 #define INT_EXT_TX 0x000000ff
124 #define INT_MASK 0x0068
125 #define INT_MASK_EXT 0x006c
126 #define TX_FIFO_URGENT_THRESHOLD 0x0074
127 #define RX_DISCARD_FRAME_CNT 0x0084
128 #define RX_OVERRUN_FRAME_CNT 0x0088
129 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
130 #define TX_BW_RATE_MOVED 0x00e0
131 #define TX_BW_MTU_MOVED 0x00e8
132 #define TX_BW_BURST_MOVED 0x00ec
133 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
134 #define RXQ_COMMAND 0x0280
135 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
136 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
137 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
138 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
139
140 /*
141 * Misc per-port registers.
142 */
143 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
144 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
145 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
146 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
147
148
149 /*
150 * SDMA configuration register default value.
151 */
152 #if defined(__BIG_ENDIAN)
153 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
154 (RX_BURST_SIZE_4_64BIT | \
155 TX_BURST_SIZE_4_64BIT)
156 #elif defined(__LITTLE_ENDIAN)
157 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
158 (RX_BURST_SIZE_4_64BIT | \
159 BLM_RX_NO_SWAP | \
160 BLM_TX_NO_SWAP | \
161 TX_BURST_SIZE_4_64BIT)
162 #else
163 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
164 #endif
165
166
167 /*
168 * Misc definitions.
169 */
170 #define DEFAULT_RX_QUEUE_SIZE 128
171 #define DEFAULT_TX_QUEUE_SIZE 512
172 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
173
174 /* Max number of allowed TCP segments for software TSO */
175 #define MV643XX_MAX_TSO_SEGS 100
176 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
177
178 #define IS_TSO_HEADER(txq, addr) \
179 ((addr >= txq->tso_hdrs_dma) && \
180 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
181
182 #define DESC_DMA_MAP_SINGLE 0
183 #define DESC_DMA_MAP_PAGE 1
184
185 /*
186 * RX/TX descriptors.
187 */
188 #if defined(__BIG_ENDIAN)
189 struct rx_desc {
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
195 };
196
197 struct tx_desc {
198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
203 };
204 #elif defined(__LITTLE_ENDIAN)
205 struct rx_desc {
206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
211 };
212
213 struct tx_desc {
214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
219 };
220 #else
221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
222 #endif
223
224 /* RX & TX descriptor command */
225 #define BUFFER_OWNED_BY_DMA 0x80000000
226
227 /* RX & TX descriptor status */
228 #define ERROR_SUMMARY 0x00000001
229
230 /* RX descriptor status */
231 #define LAYER_4_CHECKSUM_OK 0x40000000
232 #define RX_ENABLE_INTERRUPT 0x20000000
233 #define RX_FIRST_DESC 0x08000000
234 #define RX_LAST_DESC 0x04000000
235 #define RX_IP_HDR_OK 0x02000000
236 #define RX_PKT_IS_IPV4 0x01000000
237 #define RX_PKT_IS_ETHERNETV2 0x00800000
238 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
239 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
240 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
241
242 /* TX descriptor command */
243 #define TX_ENABLE_INTERRUPT 0x00800000
244 #define GEN_CRC 0x00400000
245 #define TX_FIRST_DESC 0x00200000
246 #define TX_LAST_DESC 0x00100000
247 #define ZERO_PADDING 0x00080000
248 #define GEN_IP_V4_CHECKSUM 0x00040000
249 #define GEN_TCP_UDP_CHECKSUM 0x00020000
250 #define UDP_FRAME 0x00010000
251 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
252 #define GEN_TCP_UDP_CHK_FULL 0x00000400
253 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
254
255 #define TX_IHL_SHIFT 11
256
257
258 /* global *******************************************************************/
259 struct mv643xx_eth_shared_private {
260 /*
261 * Ethernet controller base address.
262 */
263 void __iomem *base;
264
265 /*
266 * Per-port MBUS window access register value.
267 */
268 u32 win_protect;
269
270 /*
271 * Hardware-specific parameters.
272 */
273 int extended_rx_coal_limit;
274 int tx_bw_control;
275 int tx_csum_limit;
276 struct clk *clk;
277 };
278
279 #define TX_BW_CONTROL_ABSENT 0
280 #define TX_BW_CONTROL_OLD_LAYOUT 1
281 #define TX_BW_CONTROL_NEW_LAYOUT 2
282
283 static int mv643xx_eth_open(struct net_device *dev);
284 static int mv643xx_eth_stop(struct net_device *dev);
285
286
287 /* per-port *****************************************************************/
288 struct mib_counters {
289 u64 good_octets_received;
290 u32 bad_octets_received;
291 u32 internal_mac_transmit_err;
292 u32 good_frames_received;
293 u32 bad_frames_received;
294 u32 broadcast_frames_received;
295 u32 multicast_frames_received;
296 u32 frames_64_octets;
297 u32 frames_65_to_127_octets;
298 u32 frames_128_to_255_octets;
299 u32 frames_256_to_511_octets;
300 u32 frames_512_to_1023_octets;
301 u32 frames_1024_to_max_octets;
302 u64 good_octets_sent;
303 u32 good_frames_sent;
304 u32 excessive_collision;
305 u32 multicast_frames_sent;
306 u32 broadcast_frames_sent;
307 u32 unrec_mac_control_received;
308 u32 fc_sent;
309 u32 good_fc_received;
310 u32 bad_fc_received;
311 u32 undersize_received;
312 u32 fragments_received;
313 u32 oversize_received;
314 u32 jabber_received;
315 u32 mac_receive_error;
316 u32 bad_crc_event;
317 u32 collision;
318 u32 late_collision;
319 /* Non MIB hardware counters */
320 u32 rx_discard;
321 u32 rx_overrun;
322 };
323
324 struct rx_queue {
325 int index;
326
327 int rx_ring_size;
328
329 int rx_desc_count;
330 int rx_curr_desc;
331 int rx_used_desc;
332
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
337 };
338
339 struct tx_queue {
340 int index;
341
342 int tx_ring_size;
343
344 int tx_desc_count;
345 int tx_curr_desc;
346 int tx_used_desc;
347
348 int tx_stop_threshold;
349 int tx_wake_threshold;
350
351 char *tso_hdrs;
352 dma_addr_t tso_hdrs_dma;
353
354 struct tx_desc *tx_desc_area;
355 char *tx_desc_mapping; /* array to track the type of the dma mapping */
356 dma_addr_t tx_desc_dma;
357 int tx_desc_area_size;
358
359 struct sk_buff_head tx_skb;
360
361 unsigned long tx_packets;
362 unsigned long tx_bytes;
363 unsigned long tx_dropped;
364 };
365
366 struct mv643xx_eth_private {
367 struct mv643xx_eth_shared_private *shared;
368 void __iomem *base;
369 int port_num;
370
371 struct net_device *dev;
372
373 struct timer_list mib_counters_timer;
374 spinlock_t mib_counters_lock;
375 struct mib_counters mib_counters;
376
377 struct work_struct tx_timeout_task;
378
379 struct napi_struct napi;
380 u32 int_mask;
381 u8 oom;
382 u8 work_link;
383 u8 work_tx;
384 u8 work_tx_end;
385 u8 work_rx;
386 u8 work_rx_refill;
387
388 int skb_size;
389
390 /*
391 * RX state.
392 */
393 int rx_ring_size;
394 unsigned long rx_desc_sram_addr;
395 int rx_desc_sram_size;
396 int rxq_count;
397 struct timer_list rx_oom;
398 struct rx_queue rxq[8];
399
400 /*
401 * TX state.
402 */
403 int tx_ring_size;
404 unsigned long tx_desc_sram_addr;
405 int tx_desc_sram_size;
406 int txq_count;
407 struct tx_queue txq[8];
408
409 /*
410 * Hardware-specific parameters.
411 */
412 struct clk *clk;
413 unsigned int t_clk;
414 };
415
416
417 /* port register accessors **************************************************/
418 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
419 {
420 return readl(mp->shared->base + offset);
421 }
422
423 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
424 {
425 return readl(mp->base + offset);
426 }
427
428 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
429 {
430 writel(data, mp->shared->base + offset);
431 }
432
433 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
434 {
435 writel(data, mp->base + offset);
436 }
437
438
439 /* rxq/txq helper functions *************************************************/
440 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
441 {
442 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
443 }
444
445 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
446 {
447 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
448 }
449
450 static void rxq_enable(struct rx_queue *rxq)
451 {
452 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
453 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
454 }
455
456 static void rxq_disable(struct rx_queue *rxq)
457 {
458 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
459 u8 mask = 1 << rxq->index;
460
461 wrlp(mp, RXQ_COMMAND, mask << 8);
462 while (rdlp(mp, RXQ_COMMAND) & mask)
463 udelay(10);
464 }
465
466 static void txq_reset_hw_ptr(struct tx_queue *txq)
467 {
468 struct mv643xx_eth_private *mp = txq_to_mp(txq);
469 u32 addr;
470
471 addr = (u32)txq->tx_desc_dma;
472 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
473 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
474 }
475
476 static void txq_enable(struct tx_queue *txq)
477 {
478 struct mv643xx_eth_private *mp = txq_to_mp(txq);
479 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
480 }
481
482 static void txq_disable(struct tx_queue *txq)
483 {
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 u8 mask = 1 << txq->index;
486
487 wrlp(mp, TXQ_COMMAND, mask << 8);
488 while (rdlp(mp, TXQ_COMMAND) & mask)
489 udelay(10);
490 }
491
492 static void txq_maybe_wake(struct tx_queue *txq)
493 {
494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
496
497 if (netif_tx_queue_stopped(nq)) {
498 __netif_tx_lock(nq, smp_processor_id());
499 if (txq->tx_desc_count <= txq->tx_wake_threshold)
500 netif_tx_wake_queue(nq);
501 __netif_tx_unlock(nq);
502 }
503 }
504
505 static int rxq_process(struct rx_queue *rxq, int budget)
506 {
507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
508 struct net_device_stats *stats = &mp->dev->stats;
509 int rx;
510
511 rx = 0;
512 while (rx < budget && rxq->rx_desc_count) {
513 struct rx_desc *rx_desc;
514 unsigned int cmd_sts;
515 struct sk_buff *skb;
516 u16 byte_cnt;
517
518 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
519
520 cmd_sts = rx_desc->cmd_sts;
521 if (cmd_sts & BUFFER_OWNED_BY_DMA)
522 break;
523 rmb();
524
525 skb = rxq->rx_skb[rxq->rx_curr_desc];
526 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
527
528 rxq->rx_curr_desc++;
529 if (rxq->rx_curr_desc == rxq->rx_ring_size)
530 rxq->rx_curr_desc = 0;
531
532 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
533 rx_desc->buf_size, DMA_FROM_DEVICE);
534 rxq->rx_desc_count--;
535 rx++;
536
537 mp->work_rx_refill |= 1 << rxq->index;
538
539 byte_cnt = rx_desc->byte_cnt;
540
541 /*
542 * Update statistics.
543 *
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
548 */
549 stats->rx_packets++;
550 stats->rx_bytes += byte_cnt - 2;
551
552 /*
553 * In case we received a packet without first / last bits
554 * on, or the error summary bit is set, the packet needs
555 * to be dropped.
556 */
557 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
558 != (RX_FIRST_DESC | RX_LAST_DESC))
559 goto err;
560
561 /*
562 * The -4 is for the CRC in the trailer of the
563 * received packet
564 */
565 skb_put(skb, byte_cnt - 2 - 4);
566
567 if (cmd_sts & LAYER_4_CHECKSUM_OK)
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
569 skb->protocol = eth_type_trans(skb, mp->dev);
570
571 napi_gro_receive(&mp->napi, skb);
572
573 continue;
574
575 err:
576 stats->rx_dropped++;
577
578 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
579 (RX_FIRST_DESC | RX_LAST_DESC)) {
580 if (net_ratelimit())
581 netdev_err(mp->dev,
582 "received packet spanning multiple descriptors\n");
583 }
584
585 if (cmd_sts & ERROR_SUMMARY)
586 stats->rx_errors++;
587
588 dev_kfree_skb(skb);
589 }
590
591 if (rx < budget)
592 mp->work_rx &= ~(1 << rxq->index);
593
594 return rx;
595 }
596
597 static int rxq_refill(struct rx_queue *rxq, int budget)
598 {
599 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
600 int refilled;
601
602 refilled = 0;
603 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
604 struct sk_buff *skb;
605 int rx;
606 struct rx_desc *rx_desc;
607 int size;
608
609 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
610
611 if (skb == NULL) {
612 mp->oom = 1;
613 goto oom;
614 }
615
616 if (SKB_DMA_REALIGN)
617 skb_reserve(skb, SKB_DMA_REALIGN);
618
619 refilled++;
620 rxq->rx_desc_count++;
621
622 rx = rxq->rx_used_desc++;
623 if (rxq->rx_used_desc == rxq->rx_ring_size)
624 rxq->rx_used_desc = 0;
625
626 rx_desc = rxq->rx_desc_area + rx;
627
628 size = skb_end_pointer(skb) - skb->data;
629 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
630 skb->data, size,
631 DMA_FROM_DEVICE);
632 rx_desc->buf_size = size;
633 rxq->rx_skb[rx] = skb;
634 wmb();
635 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
636 wmb();
637
638 /*
639 * The hardware automatically prepends 2 bytes of
640 * dummy data to each received packet, so that the
641 * IP header ends up 16-byte aligned.
642 */
643 skb_reserve(skb, 2);
644 }
645
646 if (refilled < budget)
647 mp->work_rx_refill &= ~(1 << rxq->index);
648
649 oom:
650 return refilled;
651 }
652
653
654 /* tx ***********************************************************************/
655 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
656 {
657 int frag;
658
659 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
660 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
661
662 if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7)
663 return 1;
664 }
665
666 return 0;
667 }
668
669 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
670 u16 *l4i_chk, u32 *command, int length)
671 {
672 int ret;
673 u32 cmd = 0;
674
675 if (skb->ip_summed == CHECKSUM_PARTIAL) {
676 int hdr_len;
677 int tag_bytes;
678
679 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
680 skb->protocol != htons(ETH_P_8021Q));
681
682 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
683 tag_bytes = hdr_len - ETH_HLEN;
684
685 if (length - hdr_len > mp->shared->tx_csum_limit ||
686 unlikely(tag_bytes & ~12)) {
687 ret = skb_checksum_help(skb);
688 if (!ret)
689 goto no_csum;
690 return ret;
691 }
692
693 if (tag_bytes & 4)
694 cmd |= MAC_HDR_EXTRA_4_BYTES;
695 if (tag_bytes & 8)
696 cmd |= MAC_HDR_EXTRA_8_BYTES;
697
698 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
699 GEN_IP_V4_CHECKSUM |
700 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
701
702 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
703 * it seems we don't need to pass the initial checksum. */
704 switch (ip_hdr(skb)->protocol) {
705 case IPPROTO_UDP:
706 cmd |= UDP_FRAME;
707 *l4i_chk = 0;
708 break;
709 case IPPROTO_TCP:
710 *l4i_chk = 0;
711 break;
712 default:
713 WARN(1, "protocol not supported");
714 }
715 } else {
716 no_csum:
717 /* Errata BTS #50, IHL must be 5 if no HW checksum */
718 cmd |= 5 << TX_IHL_SHIFT;
719 }
720 *command = cmd;
721 return 0;
722 }
723
724 static inline int
725 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
726 struct sk_buff *skb, char *data, int length,
727 bool last_tcp, bool is_last)
728 {
729 int tx_index;
730 u32 cmd_sts;
731 struct tx_desc *desc;
732
733 tx_index = txq->tx_curr_desc++;
734 if (txq->tx_curr_desc == txq->tx_ring_size)
735 txq->tx_curr_desc = 0;
736 desc = &txq->tx_desc_area[tx_index];
737 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
738
739 desc->l4i_chk = 0;
740 desc->byte_cnt = length;
741
742 if (length <= 8 && (uintptr_t)data & 0x7) {
743 /* Copy unaligned small data fragment to TSO header data area */
744 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
745 data, length);
746 desc->buf_ptr = txq->tso_hdrs_dma
747 + tx_index * TSO_HEADER_SIZE;
748 } else {
749 /* Alignment is okay, map buffer and hand off to hardware */
750 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
751 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
752 length, DMA_TO_DEVICE);
753 if (unlikely(dma_mapping_error(dev->dev.parent,
754 desc->buf_ptr))) {
755 WARN(1, "dma_map_single failed!\n");
756 return -ENOMEM;
757 }
758 }
759
760 cmd_sts = BUFFER_OWNED_BY_DMA;
761 if (last_tcp) {
762 /* last descriptor in the TCP packet */
763 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
764 /* last descriptor in SKB */
765 if (is_last)
766 cmd_sts |= TX_ENABLE_INTERRUPT;
767 }
768 desc->cmd_sts = cmd_sts;
769 return 0;
770 }
771
772 static inline void
773 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
774 u32 *first_cmd_sts, bool first_desc)
775 {
776 struct mv643xx_eth_private *mp = txq_to_mp(txq);
777 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
778 int tx_index;
779 struct tx_desc *desc;
780 int ret;
781 u32 cmd_csum = 0;
782 u16 l4i_chk = 0;
783 u32 cmd_sts;
784
785 tx_index = txq->tx_curr_desc;
786 desc = &txq->tx_desc_area[tx_index];
787
788 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
789 if (ret)
790 WARN(1, "failed to prepare checksum!");
791
792 /* Should we set this? Can't use the value from skb_tx_csum()
793 * as it's not the correct initial L4 checksum to use. */
794 desc->l4i_chk = 0;
795
796 desc->byte_cnt = hdr_len;
797 desc->buf_ptr = txq->tso_hdrs_dma +
798 txq->tx_curr_desc * TSO_HEADER_SIZE;
799 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
800 GEN_CRC;
801
802 /* Defer updating the first command descriptor until all
803 * following descriptors have been written.
804 */
805 if (first_desc)
806 *first_cmd_sts = cmd_sts;
807 else
808 desc->cmd_sts = cmd_sts;
809
810 txq->tx_curr_desc++;
811 if (txq->tx_curr_desc == txq->tx_ring_size)
812 txq->tx_curr_desc = 0;
813 }
814
815 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
816 struct net_device *dev)
817 {
818 struct mv643xx_eth_private *mp = txq_to_mp(txq);
819 int hdr_len, total_len, data_left, ret;
820 int desc_count = 0;
821 struct tso_t tso;
822 struct tx_desc *first_tx_desc;
823 u32 first_cmd_sts = 0;
824
825 /* Count needed descriptors */
826 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
827 netdev_dbg(dev, "not enough descriptors for TSO!\n");
828 return -EBUSY;
829 }
830
831 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
832
833 /* Initialize the TSO handler, and prepare the first payload */
834 hdr_len = tso_start(skb, &tso);
835
836 total_len = skb->len - hdr_len;
837 while (total_len > 0) {
838 bool first_desc = (desc_count == 0);
839 char *hdr;
840
841 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
842 total_len -= data_left;
843 desc_count++;
844
845 /* prepare packet headers: MAC + IP + TCP */
846 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
847 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
848 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
849 first_desc);
850
851 while (data_left > 0) {
852 int size;
853 desc_count++;
854
855 size = min_t(int, tso.size, data_left);
856 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
857 size == data_left,
858 total_len == 0);
859 if (ret)
860 goto err_release;
861 data_left -= size;
862 tso_build_data(skb, &tso, size);
863 }
864 }
865
866 __skb_queue_tail(&txq->tx_skb, skb);
867 skb_tx_timestamp(skb);
868
869 /* ensure all other descriptors are written before first cmd_sts */
870 wmb();
871 first_tx_desc->cmd_sts = first_cmd_sts;
872
873 /* clear TX_END status */
874 mp->work_tx_end &= ~(1 << txq->index);
875
876 /* ensure all descriptors are written before poking hardware */
877 wmb();
878 txq_enable(txq);
879 txq->tx_desc_count += desc_count;
880 return 0;
881 err_release:
882 /* TODO: Release all used data descriptors; header descriptors must not
883 * be DMA-unmapped.
884 */
885 return ret;
886 }
887
888 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
889 {
890 struct mv643xx_eth_private *mp = txq_to_mp(txq);
891 int nr_frags = skb_shinfo(skb)->nr_frags;
892 int frag;
893
894 for (frag = 0; frag < nr_frags; frag++) {
895 skb_frag_t *this_frag;
896 int tx_index;
897 struct tx_desc *desc;
898
899 this_frag = &skb_shinfo(skb)->frags[frag];
900 tx_index = txq->tx_curr_desc++;
901 if (txq->tx_curr_desc == txq->tx_ring_size)
902 txq->tx_curr_desc = 0;
903 desc = &txq->tx_desc_area[tx_index];
904 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
905
906 /*
907 * The last fragment will generate an interrupt
908 * which will free the skb on TX completion.
909 */
910 if (frag == nr_frags - 1) {
911 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
912 ZERO_PADDING | TX_LAST_DESC |
913 TX_ENABLE_INTERRUPT;
914 } else {
915 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
916 }
917
918 desc->l4i_chk = 0;
919 desc->byte_cnt = skb_frag_size(this_frag);
920 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
921 this_frag, 0, desc->byte_cnt,
922 DMA_TO_DEVICE);
923 }
924 }
925
926 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
927 struct net_device *dev)
928 {
929 struct mv643xx_eth_private *mp = txq_to_mp(txq);
930 int nr_frags = skb_shinfo(skb)->nr_frags;
931 int tx_index;
932 struct tx_desc *desc;
933 u32 cmd_sts;
934 u16 l4i_chk;
935 int length, ret;
936
937 cmd_sts = 0;
938 l4i_chk = 0;
939
940 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
941 if (net_ratelimit())
942 netdev_err(dev, "tx queue full?!\n");
943 return -EBUSY;
944 }
945
946 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
947 if (ret)
948 return ret;
949 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
950
951 tx_index = txq->tx_curr_desc++;
952 if (txq->tx_curr_desc == txq->tx_ring_size)
953 txq->tx_curr_desc = 0;
954 desc = &txq->tx_desc_area[tx_index];
955 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
956
957 if (nr_frags) {
958 txq_submit_frag_skb(txq, skb);
959 length = skb_headlen(skb);
960 } else {
961 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
962 length = skb->len;
963 }
964
965 desc->l4i_chk = l4i_chk;
966 desc->byte_cnt = length;
967 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
968 length, DMA_TO_DEVICE);
969
970 __skb_queue_tail(&txq->tx_skb, skb);
971
972 skb_tx_timestamp(skb);
973
974 /* ensure all other descriptors are written before first cmd_sts */
975 wmb();
976 desc->cmd_sts = cmd_sts;
977
978 /* clear TX_END status */
979 mp->work_tx_end &= ~(1 << txq->index);
980
981 /* ensure all descriptors are written before poking hardware */
982 wmb();
983 txq_enable(txq);
984
985 txq->tx_desc_count += nr_frags + 1;
986
987 return 0;
988 }
989
990 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
991 {
992 struct mv643xx_eth_private *mp = netdev_priv(dev);
993 int length, queue, ret;
994 struct tx_queue *txq;
995 struct netdev_queue *nq;
996
997 queue = skb_get_queue_mapping(skb);
998 txq = mp->txq + queue;
999 nq = netdev_get_tx_queue(dev, queue);
1000
1001 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1002 netdev_printk(KERN_DEBUG, dev,
1003 "failed to linearize skb with tiny unaligned fragment\n");
1004 return NETDEV_TX_BUSY;
1005 }
1006
1007 length = skb->len;
1008
1009 if (skb_is_gso(skb))
1010 ret = txq_submit_tso(txq, skb, dev);
1011 else
1012 ret = txq_submit_skb(txq, skb, dev);
1013 if (!ret) {
1014 txq->tx_bytes += length;
1015 txq->tx_packets++;
1016
1017 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1018 netif_tx_stop_queue(nq);
1019 } else {
1020 txq->tx_dropped++;
1021 dev_kfree_skb_any(skb);
1022 }
1023
1024 return NETDEV_TX_OK;
1025 }
1026
1027
1028 /* tx napi ******************************************************************/
1029 static void txq_kick(struct tx_queue *txq)
1030 {
1031 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1032 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1033 u32 hw_desc_ptr;
1034 u32 expected_ptr;
1035
1036 __netif_tx_lock(nq, smp_processor_id());
1037
1038 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1039 goto out;
1040
1041 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1042 expected_ptr = (u32)txq->tx_desc_dma +
1043 txq->tx_curr_desc * sizeof(struct tx_desc);
1044
1045 if (hw_desc_ptr != expected_ptr)
1046 txq_enable(txq);
1047
1048 out:
1049 __netif_tx_unlock(nq);
1050
1051 mp->work_tx_end &= ~(1 << txq->index);
1052 }
1053
1054 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1055 {
1056 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1057 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1058 int reclaimed;
1059
1060 __netif_tx_lock_bh(nq);
1061
1062 reclaimed = 0;
1063 while (reclaimed < budget && txq->tx_desc_count > 0) {
1064 int tx_index;
1065 struct tx_desc *desc;
1066 u32 cmd_sts;
1067 char desc_dma_map;
1068
1069 tx_index = txq->tx_used_desc;
1070 desc = &txq->tx_desc_area[tx_index];
1071 desc_dma_map = txq->tx_desc_mapping[tx_index];
1072
1073 cmd_sts = desc->cmd_sts;
1074
1075 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1076 if (!force)
1077 break;
1078 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1079 }
1080
1081 txq->tx_used_desc = tx_index + 1;
1082 if (txq->tx_used_desc == txq->tx_ring_size)
1083 txq->tx_used_desc = 0;
1084
1085 reclaimed++;
1086 txq->tx_desc_count--;
1087
1088 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1089
1090 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1091 dma_unmap_page(mp->dev->dev.parent,
1092 desc->buf_ptr,
1093 desc->byte_cnt,
1094 DMA_TO_DEVICE);
1095 else
1096 dma_unmap_single(mp->dev->dev.parent,
1097 desc->buf_ptr,
1098 desc->byte_cnt,
1099 DMA_TO_DEVICE);
1100 }
1101
1102 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1103 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1104
1105 if (!WARN_ON(!skb))
1106 dev_consume_skb_any(skb);
1107 }
1108
1109 if (cmd_sts & ERROR_SUMMARY) {
1110 netdev_info(mp->dev, "tx error\n");
1111 mp->dev->stats.tx_errors++;
1112 }
1113
1114 }
1115
1116 __netif_tx_unlock_bh(nq);
1117
1118 if (reclaimed < budget)
1119 mp->work_tx &= ~(1 << txq->index);
1120
1121 return reclaimed;
1122 }
1123
1124
1125 /* tx rate control **********************************************************/
1126 /*
1127 * Set total maximum TX rate (shared by all TX queues for this port)
1128 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1129 */
1130 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1131 {
1132 int token_rate;
1133 int mtu;
1134 int bucket_size;
1135
1136 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1137 if (token_rate > 1023)
1138 token_rate = 1023;
1139
1140 mtu = (mp->dev->mtu + 255) >> 8;
1141 if (mtu > 63)
1142 mtu = 63;
1143
1144 bucket_size = (burst + 255) >> 8;
1145 if (bucket_size > 65535)
1146 bucket_size = 65535;
1147
1148 switch (mp->shared->tx_bw_control) {
1149 case TX_BW_CONTROL_OLD_LAYOUT:
1150 wrlp(mp, TX_BW_RATE, token_rate);
1151 wrlp(mp, TX_BW_MTU, mtu);
1152 wrlp(mp, TX_BW_BURST, bucket_size);
1153 break;
1154 case TX_BW_CONTROL_NEW_LAYOUT:
1155 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1156 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1157 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1158 break;
1159 }
1160 }
1161
1162 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1163 {
1164 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1165 int token_rate;
1166 int bucket_size;
1167
1168 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1169 if (token_rate > 1023)
1170 token_rate = 1023;
1171
1172 bucket_size = (burst + 255) >> 8;
1173 if (bucket_size > 65535)
1174 bucket_size = 65535;
1175
1176 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1177 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1178 }
1179
1180 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1181 {
1182 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1183 int off;
1184 u32 val;
1185
1186 /*
1187 * Turn on fixed priority mode.
1188 */
1189 off = 0;
1190 switch (mp->shared->tx_bw_control) {
1191 case TX_BW_CONTROL_OLD_LAYOUT:
1192 off = TXQ_FIX_PRIO_CONF;
1193 break;
1194 case TX_BW_CONTROL_NEW_LAYOUT:
1195 off = TXQ_FIX_PRIO_CONF_MOVED;
1196 break;
1197 }
1198
1199 if (off) {
1200 val = rdlp(mp, off);
1201 val |= 1 << txq->index;
1202 wrlp(mp, off, val);
1203 }
1204 }
1205
1206
1207 /* mii management interface *************************************************/
1208 static void mv643xx_eth_adjust_link(struct net_device *dev)
1209 {
1210 struct mv643xx_eth_private *mp = netdev_priv(dev);
1211 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1212 u32 autoneg_disable = FORCE_LINK_PASS |
1213 DISABLE_AUTO_NEG_SPEED_GMII |
1214 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1215 DISABLE_AUTO_NEG_FOR_DUPLEX;
1216
1217 if (dev->phydev->autoneg == AUTONEG_ENABLE) {
1218 /* enable auto negotiation */
1219 pscr &= ~autoneg_disable;
1220 goto out_write;
1221 }
1222
1223 pscr |= autoneg_disable;
1224
1225 if (dev->phydev->speed == SPEED_1000) {
1226 /* force gigabit, half duplex not supported */
1227 pscr |= SET_GMII_SPEED_TO_1000;
1228 pscr |= SET_FULL_DUPLEX_MODE;
1229 goto out_write;
1230 }
1231
1232 pscr &= ~SET_GMII_SPEED_TO_1000;
1233
1234 if (dev->phydev->speed == SPEED_100)
1235 pscr |= SET_MII_SPEED_TO_100;
1236 else
1237 pscr &= ~SET_MII_SPEED_TO_100;
1238
1239 if (dev->phydev->duplex == DUPLEX_FULL)
1240 pscr |= SET_FULL_DUPLEX_MODE;
1241 else
1242 pscr &= ~SET_FULL_DUPLEX_MODE;
1243
1244 out_write:
1245 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1246 }
1247
1248 /* statistics ***************************************************************/
1249 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1250 {
1251 struct mv643xx_eth_private *mp = netdev_priv(dev);
1252 struct net_device_stats *stats = &dev->stats;
1253 unsigned long tx_packets = 0;
1254 unsigned long tx_bytes = 0;
1255 unsigned long tx_dropped = 0;
1256 int i;
1257
1258 for (i = 0; i < mp->txq_count; i++) {
1259 struct tx_queue *txq = mp->txq + i;
1260
1261 tx_packets += txq->tx_packets;
1262 tx_bytes += txq->tx_bytes;
1263 tx_dropped += txq->tx_dropped;
1264 }
1265
1266 stats->tx_packets = tx_packets;
1267 stats->tx_bytes = tx_bytes;
1268 stats->tx_dropped = tx_dropped;
1269
1270 return stats;
1271 }
1272
1273 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1274 {
1275 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1276 }
1277
1278 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1279 {
1280 int i;
1281
1282 for (i = 0; i < 0x80; i += 4)
1283 mib_read(mp, i);
1284
1285 /* Clear non MIB hw counters also */
1286 rdlp(mp, RX_DISCARD_FRAME_CNT);
1287 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1288 }
1289
1290 static void mib_counters_update(struct mv643xx_eth_private *mp)
1291 {
1292 struct mib_counters *p = &mp->mib_counters;
1293
1294 spin_lock_bh(&mp->mib_counters_lock);
1295 p->good_octets_received += mib_read(mp, 0x00);
1296 p->bad_octets_received += mib_read(mp, 0x08);
1297 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1298 p->good_frames_received += mib_read(mp, 0x10);
1299 p->bad_frames_received += mib_read(mp, 0x14);
1300 p->broadcast_frames_received += mib_read(mp, 0x18);
1301 p->multicast_frames_received += mib_read(mp, 0x1c);
1302 p->frames_64_octets += mib_read(mp, 0x20);
1303 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1304 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1305 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1306 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1307 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1308 p->good_octets_sent += mib_read(mp, 0x38);
1309 p->good_frames_sent += mib_read(mp, 0x40);
1310 p->excessive_collision += mib_read(mp, 0x44);
1311 p->multicast_frames_sent += mib_read(mp, 0x48);
1312 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1313 p->unrec_mac_control_received += mib_read(mp, 0x50);
1314 p->fc_sent += mib_read(mp, 0x54);
1315 p->good_fc_received += mib_read(mp, 0x58);
1316 p->bad_fc_received += mib_read(mp, 0x5c);
1317 p->undersize_received += mib_read(mp, 0x60);
1318 p->fragments_received += mib_read(mp, 0x64);
1319 p->oversize_received += mib_read(mp, 0x68);
1320 p->jabber_received += mib_read(mp, 0x6c);
1321 p->mac_receive_error += mib_read(mp, 0x70);
1322 p->bad_crc_event += mib_read(mp, 0x74);
1323 p->collision += mib_read(mp, 0x78);
1324 p->late_collision += mib_read(mp, 0x7c);
1325 /* Non MIB hardware counters */
1326 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1327 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1328 spin_unlock_bh(&mp->mib_counters_lock);
1329 }
1330
1331 static void mib_counters_timer_wrapper(struct timer_list *t)
1332 {
1333 struct mv643xx_eth_private *mp = from_timer(mp, t, mib_counters_timer);
1334 mib_counters_update(mp);
1335 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1336 }
1337
1338
1339 /* interrupt coalescing *****************************************************/
1340 /*
1341 * Hardware coalescing parameters are set in units of 64 t_clk
1342 * cycles. I.e.:
1343 *
1344 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1345 *
1346 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1347 *
1348 * In the ->set*() methods, we round the computed register value
1349 * to the nearest integer.
1350 */
1351 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1352 {
1353 u32 val = rdlp(mp, SDMA_CONFIG);
1354 u64 temp;
1355
1356 if (mp->shared->extended_rx_coal_limit)
1357 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1358 else
1359 temp = (val & 0x003fff00) >> 8;
1360
1361 temp *= 64000000;
1362 temp += mp->t_clk / 2;
1363 do_div(temp, mp->t_clk);
1364
1365 return (unsigned int)temp;
1366 }
1367
1368 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1369 {
1370 u64 temp;
1371 u32 val;
1372
1373 temp = (u64)usec * mp->t_clk;
1374 temp += 31999999;
1375 do_div(temp, 64000000);
1376
1377 val = rdlp(mp, SDMA_CONFIG);
1378 if (mp->shared->extended_rx_coal_limit) {
1379 if (temp > 0xffff)
1380 temp = 0xffff;
1381 val &= ~0x023fff80;
1382 val |= (temp & 0x8000) << 10;
1383 val |= (temp & 0x7fff) << 7;
1384 } else {
1385 if (temp > 0x3fff)
1386 temp = 0x3fff;
1387 val &= ~0x003fff00;
1388 val |= (temp & 0x3fff) << 8;
1389 }
1390 wrlp(mp, SDMA_CONFIG, val);
1391 }
1392
1393 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1394 {
1395 u64 temp;
1396
1397 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1398 temp *= 64000000;
1399 temp += mp->t_clk / 2;
1400 do_div(temp, mp->t_clk);
1401
1402 return (unsigned int)temp;
1403 }
1404
1405 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1406 {
1407 u64 temp;
1408
1409 temp = (u64)usec * mp->t_clk;
1410 temp += 31999999;
1411 do_div(temp, 64000000);
1412
1413 if (temp > 0x3fff)
1414 temp = 0x3fff;
1415
1416 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1417 }
1418
1419
1420 /* ethtool ******************************************************************/
1421 struct mv643xx_eth_stats {
1422 char stat_string[ETH_GSTRING_LEN];
1423 int sizeof_stat;
1424 int netdev_off;
1425 int mp_off;
1426 };
1427
1428 #define SSTAT(m) \
1429 { #m, sizeof_field(struct net_device_stats, m), \
1430 offsetof(struct net_device, stats.m), -1 }
1431
1432 #define MIBSTAT(m) \
1433 { #m, sizeof_field(struct mib_counters, m), \
1434 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1435
1436 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1437 SSTAT(rx_packets),
1438 SSTAT(tx_packets),
1439 SSTAT(rx_bytes),
1440 SSTAT(tx_bytes),
1441 SSTAT(rx_errors),
1442 SSTAT(tx_errors),
1443 SSTAT(rx_dropped),
1444 SSTAT(tx_dropped),
1445 MIBSTAT(good_octets_received),
1446 MIBSTAT(bad_octets_received),
1447 MIBSTAT(internal_mac_transmit_err),
1448 MIBSTAT(good_frames_received),
1449 MIBSTAT(bad_frames_received),
1450 MIBSTAT(broadcast_frames_received),
1451 MIBSTAT(multicast_frames_received),
1452 MIBSTAT(frames_64_octets),
1453 MIBSTAT(frames_65_to_127_octets),
1454 MIBSTAT(frames_128_to_255_octets),
1455 MIBSTAT(frames_256_to_511_octets),
1456 MIBSTAT(frames_512_to_1023_octets),
1457 MIBSTAT(frames_1024_to_max_octets),
1458 MIBSTAT(good_octets_sent),
1459 MIBSTAT(good_frames_sent),
1460 MIBSTAT(excessive_collision),
1461 MIBSTAT(multicast_frames_sent),
1462 MIBSTAT(broadcast_frames_sent),
1463 MIBSTAT(unrec_mac_control_received),
1464 MIBSTAT(fc_sent),
1465 MIBSTAT(good_fc_received),
1466 MIBSTAT(bad_fc_received),
1467 MIBSTAT(undersize_received),
1468 MIBSTAT(fragments_received),
1469 MIBSTAT(oversize_received),
1470 MIBSTAT(jabber_received),
1471 MIBSTAT(mac_receive_error),
1472 MIBSTAT(bad_crc_event),
1473 MIBSTAT(collision),
1474 MIBSTAT(late_collision),
1475 MIBSTAT(rx_discard),
1476 MIBSTAT(rx_overrun),
1477 };
1478
1479 static int
1480 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1481 struct ethtool_link_ksettings *cmd)
1482 {
1483 struct net_device *dev = mp->dev;
1484
1485 phy_ethtool_ksettings_get(dev->phydev, cmd);
1486
1487 /*
1488 * The MAC does not support 1000baseT_Half.
1489 */
1490 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1491 cmd->link_modes.supported);
1492 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1493 cmd->link_modes.advertising);
1494
1495 return 0;
1496 }
1497
1498 static int
1499 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1500 struct ethtool_link_ksettings *cmd)
1501 {
1502 u32 port_status;
1503 u32 supported, advertising;
1504
1505 port_status = rdlp(mp, PORT_STATUS);
1506
1507 supported = SUPPORTED_MII;
1508 advertising = ADVERTISED_MII;
1509 switch (port_status & PORT_SPEED_MASK) {
1510 case PORT_SPEED_10:
1511 cmd->base.speed = SPEED_10;
1512 break;
1513 case PORT_SPEED_100:
1514 cmd->base.speed = SPEED_100;
1515 break;
1516 case PORT_SPEED_1000:
1517 cmd->base.speed = SPEED_1000;
1518 break;
1519 default:
1520 cmd->base.speed = -1;
1521 break;
1522 }
1523 cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1524 DUPLEX_FULL : DUPLEX_HALF;
1525 cmd->base.port = PORT_MII;
1526 cmd->base.phy_address = 0;
1527 cmd->base.autoneg = AUTONEG_DISABLE;
1528
1529 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1530 supported);
1531 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1532 advertising);
1533
1534 return 0;
1535 }
1536
1537 static void
1538 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1539 {
1540 wol->supported = 0;
1541 wol->wolopts = 0;
1542 if (dev->phydev)
1543 phy_ethtool_get_wol(dev->phydev, wol);
1544 }
1545
1546 static int
1547 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1548 {
1549 int err;
1550
1551 if (!dev->phydev)
1552 return -EOPNOTSUPP;
1553
1554 err = phy_ethtool_set_wol(dev->phydev, wol);
1555 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1556 * this debugging hint is useful to have.
1557 */
1558 if (err == -EOPNOTSUPP)
1559 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1560 return err;
1561 }
1562
1563 static int
1564 mv643xx_eth_get_link_ksettings(struct net_device *dev,
1565 struct ethtool_link_ksettings *cmd)
1566 {
1567 struct mv643xx_eth_private *mp = netdev_priv(dev);
1568
1569 if (dev->phydev)
1570 return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
1571 else
1572 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
1573 }
1574
1575 static int
1576 mv643xx_eth_set_link_ksettings(struct net_device *dev,
1577 const struct ethtool_link_ksettings *cmd)
1578 {
1579 struct ethtool_link_ksettings c = *cmd;
1580 u32 advertising;
1581 int ret;
1582
1583 if (!dev->phydev)
1584 return -EINVAL;
1585
1586 /*
1587 * The MAC does not support 1000baseT_Half.
1588 */
1589 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1590 c.link_modes.advertising);
1591 advertising &= ~ADVERTISED_1000baseT_Half;
1592 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1593 advertising);
1594
1595 ret = phy_ethtool_ksettings_set(dev->phydev, &c);
1596 if (!ret)
1597 mv643xx_eth_adjust_link(dev);
1598 return ret;
1599 }
1600
1601 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1602 struct ethtool_drvinfo *drvinfo)
1603 {
1604 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1605 sizeof(drvinfo->driver));
1606 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1607 sizeof(drvinfo->version));
1608 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1609 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1610 }
1611
1612 static int
1613 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1614 {
1615 struct mv643xx_eth_private *mp = netdev_priv(dev);
1616
1617 ec->rx_coalesce_usecs = get_rx_coal(mp);
1618 ec->tx_coalesce_usecs = get_tx_coal(mp);
1619
1620 return 0;
1621 }
1622
1623 static int
1624 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1625 {
1626 struct mv643xx_eth_private *mp = netdev_priv(dev);
1627
1628 set_rx_coal(mp, ec->rx_coalesce_usecs);
1629 set_tx_coal(mp, ec->tx_coalesce_usecs);
1630
1631 return 0;
1632 }
1633
1634 static void
1635 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1636 {
1637 struct mv643xx_eth_private *mp = netdev_priv(dev);
1638
1639 er->rx_max_pending = 4096;
1640 er->tx_max_pending = 4096;
1641
1642 er->rx_pending = mp->rx_ring_size;
1643 er->tx_pending = mp->tx_ring_size;
1644 }
1645
1646 static int
1647 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1648 {
1649 struct mv643xx_eth_private *mp = netdev_priv(dev);
1650
1651 if (er->rx_mini_pending || er->rx_jumbo_pending)
1652 return -EINVAL;
1653
1654 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1655 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1656 MV643XX_MAX_SKB_DESCS * 2, 4096);
1657 if (mp->tx_ring_size != er->tx_pending)
1658 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1659 mp->tx_ring_size, er->tx_pending);
1660
1661 if (netif_running(dev)) {
1662 mv643xx_eth_stop(dev);
1663 if (mv643xx_eth_open(dev)) {
1664 netdev_err(dev,
1665 "fatal error on re-opening device after ring param change\n");
1666 return -ENOMEM;
1667 }
1668 }
1669
1670 return 0;
1671 }
1672
1673
1674 static int
1675 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1676 {
1677 struct mv643xx_eth_private *mp = netdev_priv(dev);
1678 bool rx_csum = features & NETIF_F_RXCSUM;
1679
1680 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1681
1682 return 0;
1683 }
1684
1685 static void mv643xx_eth_get_strings(struct net_device *dev,
1686 uint32_t stringset, uint8_t *data)
1687 {
1688 int i;
1689
1690 if (stringset == ETH_SS_STATS) {
1691 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1692 memcpy(data + i * ETH_GSTRING_LEN,
1693 mv643xx_eth_stats[i].stat_string,
1694 ETH_GSTRING_LEN);
1695 }
1696 }
1697 }
1698
1699 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1700 struct ethtool_stats *stats,
1701 uint64_t *data)
1702 {
1703 struct mv643xx_eth_private *mp = netdev_priv(dev);
1704 int i;
1705
1706 mv643xx_eth_get_stats(dev);
1707 mib_counters_update(mp);
1708
1709 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1710 const struct mv643xx_eth_stats *stat;
1711 void *p;
1712
1713 stat = mv643xx_eth_stats + i;
1714
1715 if (stat->netdev_off >= 0)
1716 p = ((void *)mp->dev) + stat->netdev_off;
1717 else
1718 p = ((void *)mp) + stat->mp_off;
1719
1720 data[i] = (stat->sizeof_stat == 8) ?
1721 *(uint64_t *)p : *(uint32_t *)p;
1722 }
1723 }
1724
1725 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1726 {
1727 if (sset == ETH_SS_STATS)
1728 return ARRAY_SIZE(mv643xx_eth_stats);
1729
1730 return -EOPNOTSUPP;
1731 }
1732
1733 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1734 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
1735 .get_drvinfo = mv643xx_eth_get_drvinfo,
1736 .nway_reset = phy_ethtool_nway_reset,
1737 .get_link = ethtool_op_get_link,
1738 .get_coalesce = mv643xx_eth_get_coalesce,
1739 .set_coalesce = mv643xx_eth_set_coalesce,
1740 .get_ringparam = mv643xx_eth_get_ringparam,
1741 .set_ringparam = mv643xx_eth_set_ringparam,
1742 .get_strings = mv643xx_eth_get_strings,
1743 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1744 .get_sset_count = mv643xx_eth_get_sset_count,
1745 .get_ts_info = ethtool_op_get_ts_info,
1746 .get_wol = mv643xx_eth_get_wol,
1747 .set_wol = mv643xx_eth_set_wol,
1748 .get_link_ksettings = mv643xx_eth_get_link_ksettings,
1749 .set_link_ksettings = mv643xx_eth_set_link_ksettings,
1750 };
1751
1752
1753 /* address handling *********************************************************/
1754 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1755 {
1756 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1757 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1758
1759 addr[0] = (mac_h >> 24) & 0xff;
1760 addr[1] = (mac_h >> 16) & 0xff;
1761 addr[2] = (mac_h >> 8) & 0xff;
1762 addr[3] = mac_h & 0xff;
1763 addr[4] = (mac_l >> 8) & 0xff;
1764 addr[5] = mac_l & 0xff;
1765 }
1766
1767 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1768 {
1769 wrlp(mp, MAC_ADDR_HIGH,
1770 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1771 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1772 }
1773
1774 static u32 uc_addr_filter_mask(struct net_device *dev)
1775 {
1776 struct netdev_hw_addr *ha;
1777 u32 nibbles;
1778
1779 if (dev->flags & IFF_PROMISC)
1780 return 0;
1781
1782 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1783 netdev_for_each_uc_addr(ha, dev) {
1784 if (memcmp(dev->dev_addr, ha->addr, 5))
1785 return 0;
1786 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1787 return 0;
1788
1789 nibbles |= 1 << (ha->addr[5] & 0x0f);
1790 }
1791
1792 return nibbles;
1793 }
1794
1795 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1796 {
1797 struct mv643xx_eth_private *mp = netdev_priv(dev);
1798 u32 port_config;
1799 u32 nibbles;
1800 int i;
1801
1802 uc_addr_set(mp, dev->dev_addr);
1803
1804 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1805
1806 nibbles = uc_addr_filter_mask(dev);
1807 if (!nibbles) {
1808 port_config |= UNICAST_PROMISCUOUS_MODE;
1809 nibbles = 0xffff;
1810 }
1811
1812 for (i = 0; i < 16; i += 4) {
1813 int off = UNICAST_TABLE(mp->port_num) + i;
1814 u32 v;
1815
1816 v = 0;
1817 if (nibbles & 1)
1818 v |= 0x00000001;
1819 if (nibbles & 2)
1820 v |= 0x00000100;
1821 if (nibbles & 4)
1822 v |= 0x00010000;
1823 if (nibbles & 8)
1824 v |= 0x01000000;
1825 nibbles >>= 4;
1826
1827 wrl(mp, off, v);
1828 }
1829
1830 wrlp(mp, PORT_CONFIG, port_config);
1831 }
1832
1833 static int addr_crc(unsigned char *addr)
1834 {
1835 int crc = 0;
1836 int i;
1837
1838 for (i = 0; i < 6; i++) {
1839 int j;
1840
1841 crc = (crc ^ addr[i]) << 8;
1842 for (j = 7; j >= 0; j--) {
1843 if (crc & (0x100 << j))
1844 crc ^= 0x107 << j;
1845 }
1846 }
1847
1848 return crc;
1849 }
1850
1851 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1852 {
1853 struct mv643xx_eth_private *mp = netdev_priv(dev);
1854 u32 *mc_spec;
1855 u32 *mc_other;
1856 struct netdev_hw_addr *ha;
1857 int i;
1858
1859 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1860 goto promiscuous;
1861
1862 /* Allocate both mc_spec and mc_other tables */
1863 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1864 if (!mc_spec)
1865 goto promiscuous;
1866 mc_other = &mc_spec[64];
1867
1868 netdev_for_each_mc_addr(ha, dev) {
1869 u8 *a = ha->addr;
1870 u32 *table;
1871 u8 entry;
1872
1873 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1874 table = mc_spec;
1875 entry = a[5];
1876 } else {
1877 table = mc_other;
1878 entry = addr_crc(a);
1879 }
1880
1881 table[entry >> 2] |= 1 << (8 * (entry & 3));
1882 }
1883
1884 for (i = 0; i < 64; i++) {
1885 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1886 mc_spec[i]);
1887 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1888 mc_other[i]);
1889 }
1890
1891 kfree(mc_spec);
1892 return;
1893
1894 promiscuous:
1895 for (i = 0; i < 64; i++) {
1896 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1897 0x01010101u);
1898 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1899 0x01010101u);
1900 }
1901 }
1902
1903 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1904 {
1905 mv643xx_eth_program_unicast_filter(dev);
1906 mv643xx_eth_program_multicast_filter(dev);
1907 }
1908
1909 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1910 {
1911 struct sockaddr *sa = addr;
1912
1913 if (!is_valid_ether_addr(sa->sa_data))
1914 return -EADDRNOTAVAIL;
1915
1916 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1917
1918 netif_addr_lock_bh(dev);
1919 mv643xx_eth_program_unicast_filter(dev);
1920 netif_addr_unlock_bh(dev);
1921
1922 return 0;
1923 }
1924
1925
1926 /* rx/tx queue initialisation ***********************************************/
1927 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1928 {
1929 struct rx_queue *rxq = mp->rxq + index;
1930 struct rx_desc *rx_desc;
1931 int size;
1932 int i;
1933
1934 rxq->index = index;
1935
1936 rxq->rx_ring_size = mp->rx_ring_size;
1937
1938 rxq->rx_desc_count = 0;
1939 rxq->rx_curr_desc = 0;
1940 rxq->rx_used_desc = 0;
1941
1942 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1943
1944 if (index == 0 && size <= mp->rx_desc_sram_size) {
1945 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1946 mp->rx_desc_sram_size);
1947 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1948 } else {
1949 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1950 size, &rxq->rx_desc_dma,
1951 GFP_KERNEL);
1952 }
1953
1954 if (rxq->rx_desc_area == NULL) {
1955 netdev_err(mp->dev,
1956 "can't allocate rx ring (%d bytes)\n", size);
1957 goto out;
1958 }
1959 memset(rxq->rx_desc_area, 0, size);
1960
1961 rxq->rx_desc_area_size = size;
1962 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1963 GFP_KERNEL);
1964 if (rxq->rx_skb == NULL)
1965 goto out_free;
1966
1967 rx_desc = rxq->rx_desc_area;
1968 for (i = 0; i < rxq->rx_ring_size; i++) {
1969 int nexti;
1970
1971 nexti = i + 1;
1972 if (nexti == rxq->rx_ring_size)
1973 nexti = 0;
1974
1975 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1976 nexti * sizeof(struct rx_desc);
1977 }
1978
1979 return 0;
1980
1981
1982 out_free:
1983 if (index == 0 && size <= mp->rx_desc_sram_size)
1984 iounmap(rxq->rx_desc_area);
1985 else
1986 dma_free_coherent(mp->dev->dev.parent, size,
1987 rxq->rx_desc_area,
1988 rxq->rx_desc_dma);
1989
1990 out:
1991 return -ENOMEM;
1992 }
1993
1994 static void rxq_deinit(struct rx_queue *rxq)
1995 {
1996 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1997 int i;
1998
1999 rxq_disable(rxq);
2000
2001 for (i = 0; i < rxq->rx_ring_size; i++) {
2002 if (rxq->rx_skb[i]) {
2003 dev_consume_skb_any(rxq->rx_skb[i]);
2004 rxq->rx_desc_count--;
2005 }
2006 }
2007
2008 if (rxq->rx_desc_count) {
2009 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2010 rxq->rx_desc_count);
2011 }
2012
2013 if (rxq->index == 0 &&
2014 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2015 iounmap(rxq->rx_desc_area);
2016 else
2017 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2018 rxq->rx_desc_area, rxq->rx_desc_dma);
2019
2020 kfree(rxq->rx_skb);
2021 }
2022
2023 static int txq_init(struct mv643xx_eth_private *mp, int index)
2024 {
2025 struct tx_queue *txq = mp->txq + index;
2026 struct tx_desc *tx_desc;
2027 int size;
2028 int ret;
2029 int i;
2030
2031 txq->index = index;
2032
2033 txq->tx_ring_size = mp->tx_ring_size;
2034
2035 /* A queue must always have room for at least one skb.
2036 * Therefore, stop the queue when the free entries reaches
2037 * the maximum number of descriptors per skb.
2038 */
2039 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2040 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2041
2042 txq->tx_desc_count = 0;
2043 txq->tx_curr_desc = 0;
2044 txq->tx_used_desc = 0;
2045
2046 size = txq->tx_ring_size * sizeof(struct tx_desc);
2047
2048 if (index == 0 && size <= mp->tx_desc_sram_size) {
2049 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2050 mp->tx_desc_sram_size);
2051 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2052 } else {
2053 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2054 size, &txq->tx_desc_dma,
2055 GFP_KERNEL);
2056 }
2057
2058 if (txq->tx_desc_area == NULL) {
2059 netdev_err(mp->dev,
2060 "can't allocate tx ring (%d bytes)\n", size);
2061 return -ENOMEM;
2062 }
2063 memset(txq->tx_desc_area, 0, size);
2064
2065 txq->tx_desc_area_size = size;
2066
2067 tx_desc = txq->tx_desc_area;
2068 for (i = 0; i < txq->tx_ring_size; i++) {
2069 struct tx_desc *txd = tx_desc + i;
2070 int nexti;
2071
2072 nexti = i + 1;
2073 if (nexti == txq->tx_ring_size)
2074 nexti = 0;
2075
2076 txd->cmd_sts = 0;
2077 txd->next_desc_ptr = txq->tx_desc_dma +
2078 nexti * sizeof(struct tx_desc);
2079 }
2080
2081 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2082 GFP_KERNEL);
2083 if (!txq->tx_desc_mapping) {
2084 ret = -ENOMEM;
2085 goto err_free_desc_area;
2086 }
2087
2088 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2089 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2090 txq->tx_ring_size * TSO_HEADER_SIZE,
2091 &txq->tso_hdrs_dma, GFP_KERNEL);
2092 if (txq->tso_hdrs == NULL) {
2093 ret = -ENOMEM;
2094 goto err_free_desc_mapping;
2095 }
2096 skb_queue_head_init(&txq->tx_skb);
2097
2098 return 0;
2099
2100 err_free_desc_mapping:
2101 kfree(txq->tx_desc_mapping);
2102 err_free_desc_area:
2103 if (index == 0 && size <= mp->tx_desc_sram_size)
2104 iounmap(txq->tx_desc_area);
2105 else
2106 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2107 txq->tx_desc_area, txq->tx_desc_dma);
2108 return ret;
2109 }
2110
2111 static void txq_deinit(struct tx_queue *txq)
2112 {
2113 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2114
2115 txq_disable(txq);
2116 txq_reclaim(txq, txq->tx_ring_size, 1);
2117
2118 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2119
2120 if (txq->index == 0 &&
2121 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2122 iounmap(txq->tx_desc_area);
2123 else
2124 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2125 txq->tx_desc_area, txq->tx_desc_dma);
2126 kfree(txq->tx_desc_mapping);
2127
2128 if (txq->tso_hdrs)
2129 dma_free_coherent(mp->dev->dev.parent,
2130 txq->tx_ring_size * TSO_HEADER_SIZE,
2131 txq->tso_hdrs, txq->tso_hdrs_dma);
2132 }
2133
2134
2135 /* netdev ops and related ***************************************************/
2136 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2137 {
2138 u32 int_cause;
2139 u32 int_cause_ext;
2140
2141 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2142 if (int_cause == 0)
2143 return 0;
2144
2145 int_cause_ext = 0;
2146 if (int_cause & INT_EXT) {
2147 int_cause &= ~INT_EXT;
2148 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2149 }
2150
2151 if (int_cause) {
2152 wrlp(mp, INT_CAUSE, ~int_cause);
2153 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2154 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2155 mp->work_rx |= (int_cause & INT_RX) >> 2;
2156 }
2157
2158 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2159 if (int_cause_ext) {
2160 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2161 if (int_cause_ext & INT_EXT_LINK_PHY)
2162 mp->work_link = 1;
2163 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2164 }
2165
2166 return 1;
2167 }
2168
2169 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2170 {
2171 struct net_device *dev = (struct net_device *)dev_id;
2172 struct mv643xx_eth_private *mp = netdev_priv(dev);
2173
2174 if (unlikely(!mv643xx_eth_collect_events(mp)))
2175 return IRQ_NONE;
2176
2177 wrlp(mp, INT_MASK, 0);
2178 napi_schedule(&mp->napi);
2179
2180 return IRQ_HANDLED;
2181 }
2182
2183 static void handle_link_event(struct mv643xx_eth_private *mp)
2184 {
2185 struct net_device *dev = mp->dev;
2186 u32 port_status;
2187 int speed;
2188 int duplex;
2189 int fc;
2190
2191 port_status = rdlp(mp, PORT_STATUS);
2192 if (!(port_status & LINK_UP)) {
2193 if (netif_carrier_ok(dev)) {
2194 int i;
2195
2196 netdev_info(dev, "link down\n");
2197
2198 netif_carrier_off(dev);
2199
2200 for (i = 0; i < mp->txq_count; i++) {
2201 struct tx_queue *txq = mp->txq + i;
2202
2203 txq_reclaim(txq, txq->tx_ring_size, 1);
2204 txq_reset_hw_ptr(txq);
2205 }
2206 }
2207 return;
2208 }
2209
2210 switch (port_status & PORT_SPEED_MASK) {
2211 case PORT_SPEED_10:
2212 speed = 10;
2213 break;
2214 case PORT_SPEED_100:
2215 speed = 100;
2216 break;
2217 case PORT_SPEED_1000:
2218 speed = 1000;
2219 break;
2220 default:
2221 speed = -1;
2222 break;
2223 }
2224 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2225 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2226
2227 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2228 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2229
2230 if (!netif_carrier_ok(dev))
2231 netif_carrier_on(dev);
2232 }
2233
2234 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2235 {
2236 struct mv643xx_eth_private *mp;
2237 int work_done;
2238
2239 mp = container_of(napi, struct mv643xx_eth_private, napi);
2240
2241 if (unlikely(mp->oom)) {
2242 mp->oom = 0;
2243 del_timer(&mp->rx_oom);
2244 }
2245
2246 work_done = 0;
2247 while (work_done < budget) {
2248 u8 queue_mask;
2249 int queue;
2250 int work_tbd;
2251
2252 if (mp->work_link) {
2253 mp->work_link = 0;
2254 handle_link_event(mp);
2255 work_done++;
2256 continue;
2257 }
2258
2259 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2260 if (likely(!mp->oom))
2261 queue_mask |= mp->work_rx_refill;
2262
2263 if (!queue_mask) {
2264 if (mv643xx_eth_collect_events(mp))
2265 continue;
2266 break;
2267 }
2268
2269 queue = fls(queue_mask) - 1;
2270 queue_mask = 1 << queue;
2271
2272 work_tbd = budget - work_done;
2273 if (work_tbd > 16)
2274 work_tbd = 16;
2275
2276 if (mp->work_tx_end & queue_mask) {
2277 txq_kick(mp->txq + queue);
2278 } else if (mp->work_tx & queue_mask) {
2279 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2280 txq_maybe_wake(mp->txq + queue);
2281 } else if (mp->work_rx & queue_mask) {
2282 work_done += rxq_process(mp->rxq + queue, work_tbd);
2283 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2284 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2285 } else {
2286 BUG();
2287 }
2288 }
2289
2290 if (work_done < budget) {
2291 if (mp->oom)
2292 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2293 napi_complete_done(napi, work_done);
2294 wrlp(mp, INT_MASK, mp->int_mask);
2295 }
2296
2297 return work_done;
2298 }
2299
2300 static inline void oom_timer_wrapper(struct timer_list *t)
2301 {
2302 struct mv643xx_eth_private *mp = from_timer(mp, t, rx_oom);
2303
2304 napi_schedule(&mp->napi);
2305 }
2306
2307 static void port_start(struct mv643xx_eth_private *mp)
2308 {
2309 struct net_device *dev = mp->dev;
2310 u32 pscr;
2311 int i;
2312
2313 /*
2314 * Perform PHY reset, if there is a PHY.
2315 */
2316 if (dev->phydev) {
2317 struct ethtool_link_ksettings cmd;
2318
2319 mv643xx_eth_get_link_ksettings(dev, &cmd);
2320 phy_init_hw(dev->phydev);
2321 mv643xx_eth_set_link_ksettings(
2322 dev, (const struct ethtool_link_ksettings *)&cmd);
2323 phy_start(dev->phydev);
2324 }
2325
2326 /*
2327 * Configure basic link parameters.
2328 */
2329 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2330
2331 pscr |= SERIAL_PORT_ENABLE;
2332 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2333
2334 pscr |= DO_NOT_FORCE_LINK_FAIL;
2335 if (!dev->phydev)
2336 pscr |= FORCE_LINK_PASS;
2337 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2338
2339 /*
2340 * Configure TX path and queues.
2341 */
2342 tx_set_rate(mp, 1000000000, 16777216);
2343 for (i = 0; i < mp->txq_count; i++) {
2344 struct tx_queue *txq = mp->txq + i;
2345
2346 txq_reset_hw_ptr(txq);
2347 txq_set_rate(txq, 1000000000, 16777216);
2348 txq_set_fixed_prio_mode(txq);
2349 }
2350
2351 /*
2352 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2353 * frames to RX queue #0, and include the pseudo-header when
2354 * calculating receive checksums.
2355 */
2356 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2357
2358 /*
2359 * Treat BPDUs as normal multicasts, and disable partition mode.
2360 */
2361 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2362
2363 /*
2364 * Add configured unicast addresses to address filter table.
2365 */
2366 mv643xx_eth_program_unicast_filter(mp->dev);
2367
2368 /*
2369 * Enable the receive queues.
2370 */
2371 for (i = 0; i < mp->rxq_count; i++) {
2372 struct rx_queue *rxq = mp->rxq + i;
2373 u32 addr;
2374
2375 addr = (u32)rxq->rx_desc_dma;
2376 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2377 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2378
2379 rxq_enable(rxq);
2380 }
2381 }
2382
2383 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2384 {
2385 int skb_size;
2386
2387 /*
2388 * Reserve 2+14 bytes for an ethernet header (the hardware
2389 * automatically prepends 2 bytes of dummy data to each
2390 * received packet), 16 bytes for up to four VLAN tags, and
2391 * 4 bytes for the trailing FCS -- 36 bytes total.
2392 */
2393 skb_size = mp->dev->mtu + 36;
2394
2395 /*
2396 * Make sure that the skb size is a multiple of 8 bytes, as
2397 * the lower three bits of the receive descriptor's buffer
2398 * size field are ignored by the hardware.
2399 */
2400 mp->skb_size = (skb_size + 7) & ~7;
2401
2402 /*
2403 * If NET_SKB_PAD is smaller than a cache line,
2404 * netdev_alloc_skb() will cause skb->data to be misaligned
2405 * to a cache line boundary. If this is the case, include
2406 * some extra space to allow re-aligning the data area.
2407 */
2408 mp->skb_size += SKB_DMA_REALIGN;
2409 }
2410
2411 static int mv643xx_eth_open(struct net_device *dev)
2412 {
2413 struct mv643xx_eth_private *mp = netdev_priv(dev);
2414 int err;
2415 int i;
2416
2417 wrlp(mp, INT_CAUSE, 0);
2418 wrlp(mp, INT_CAUSE_EXT, 0);
2419 rdlp(mp, INT_CAUSE_EXT);
2420
2421 err = request_irq(dev->irq, mv643xx_eth_irq,
2422 IRQF_SHARED, dev->name, dev);
2423 if (err) {
2424 netdev_err(dev, "can't assign irq\n");
2425 return -EAGAIN;
2426 }
2427
2428 mv643xx_eth_recalc_skb_size(mp);
2429
2430 napi_enable(&mp->napi);
2431
2432 mp->int_mask = INT_EXT;
2433
2434 for (i = 0; i < mp->rxq_count; i++) {
2435 err = rxq_init(mp, i);
2436 if (err) {
2437 while (--i >= 0)
2438 rxq_deinit(mp->rxq + i);
2439 goto out;
2440 }
2441
2442 rxq_refill(mp->rxq + i, INT_MAX);
2443 mp->int_mask |= INT_RX_0 << i;
2444 }
2445
2446 if (mp->oom) {
2447 mp->rx_oom.expires = jiffies + (HZ / 10);
2448 add_timer(&mp->rx_oom);
2449 }
2450
2451 for (i = 0; i < mp->txq_count; i++) {
2452 err = txq_init(mp, i);
2453 if (err) {
2454 while (--i >= 0)
2455 txq_deinit(mp->txq + i);
2456 goto out_free;
2457 }
2458 mp->int_mask |= INT_TX_END_0 << i;
2459 }
2460
2461 add_timer(&mp->mib_counters_timer);
2462 port_start(mp);
2463
2464 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2465 wrlp(mp, INT_MASK, mp->int_mask);
2466
2467 return 0;
2468
2469
2470 out_free:
2471 for (i = 0; i < mp->rxq_count; i++)
2472 rxq_deinit(mp->rxq + i);
2473 out:
2474 free_irq(dev->irq, dev);
2475
2476 return err;
2477 }
2478
2479 static void port_reset(struct mv643xx_eth_private *mp)
2480 {
2481 unsigned int data;
2482 int i;
2483
2484 for (i = 0; i < mp->rxq_count; i++)
2485 rxq_disable(mp->rxq + i);
2486 for (i = 0; i < mp->txq_count; i++)
2487 txq_disable(mp->txq + i);
2488
2489 while (1) {
2490 u32 ps = rdlp(mp, PORT_STATUS);
2491
2492 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2493 break;
2494 udelay(10);
2495 }
2496
2497 /* Reset the Enable bit in the Configuration Register */
2498 data = rdlp(mp, PORT_SERIAL_CONTROL);
2499 data &= ~(SERIAL_PORT_ENABLE |
2500 DO_NOT_FORCE_LINK_FAIL |
2501 FORCE_LINK_PASS);
2502 wrlp(mp, PORT_SERIAL_CONTROL, data);
2503 }
2504
2505 static int mv643xx_eth_stop(struct net_device *dev)
2506 {
2507 struct mv643xx_eth_private *mp = netdev_priv(dev);
2508 int i;
2509
2510 wrlp(mp, INT_MASK_EXT, 0x00000000);
2511 wrlp(mp, INT_MASK, 0x00000000);
2512 rdlp(mp, INT_MASK);
2513
2514 napi_disable(&mp->napi);
2515
2516 del_timer_sync(&mp->rx_oom);
2517
2518 netif_carrier_off(dev);
2519 if (dev->phydev)
2520 phy_stop(dev->phydev);
2521 free_irq(dev->irq, dev);
2522
2523 port_reset(mp);
2524 mv643xx_eth_get_stats(dev);
2525 mib_counters_update(mp);
2526 del_timer_sync(&mp->mib_counters_timer);
2527
2528 for (i = 0; i < mp->rxq_count; i++)
2529 rxq_deinit(mp->rxq + i);
2530 for (i = 0; i < mp->txq_count; i++)
2531 txq_deinit(mp->txq + i);
2532
2533 return 0;
2534 }
2535
2536 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2537 {
2538 int ret;
2539
2540 if (!dev->phydev)
2541 return -ENOTSUPP;
2542
2543 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
2544 if (!ret)
2545 mv643xx_eth_adjust_link(dev);
2546 return ret;
2547 }
2548
2549 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2550 {
2551 struct mv643xx_eth_private *mp = netdev_priv(dev);
2552
2553 dev->mtu = new_mtu;
2554 mv643xx_eth_recalc_skb_size(mp);
2555 tx_set_rate(mp, 1000000000, 16777216);
2556
2557 if (!netif_running(dev))
2558 return 0;
2559
2560 /*
2561 * Stop and then re-open the interface. This will allocate RX
2562 * skbs of the new MTU.
2563 * There is a possible danger that the open will not succeed,
2564 * due to memory being full.
2565 */
2566 mv643xx_eth_stop(dev);
2567 if (mv643xx_eth_open(dev)) {
2568 netdev_err(dev,
2569 "fatal error on re-opening device after MTU change\n");
2570 }
2571
2572 return 0;
2573 }
2574
2575 static void tx_timeout_task(struct work_struct *ugly)
2576 {
2577 struct mv643xx_eth_private *mp;
2578
2579 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2580 if (netif_running(mp->dev)) {
2581 netif_tx_stop_all_queues(mp->dev);
2582 port_reset(mp);
2583 port_start(mp);
2584 netif_tx_wake_all_queues(mp->dev);
2585 }
2586 }
2587
2588 static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue)
2589 {
2590 struct mv643xx_eth_private *mp = netdev_priv(dev);
2591
2592 netdev_info(dev, "tx timeout\n");
2593
2594 schedule_work(&mp->tx_timeout_task);
2595 }
2596
2597 #ifdef CONFIG_NET_POLL_CONTROLLER
2598 static void mv643xx_eth_netpoll(struct net_device *dev)
2599 {
2600 struct mv643xx_eth_private *mp = netdev_priv(dev);
2601
2602 wrlp(mp, INT_MASK, 0x00000000);
2603 rdlp(mp, INT_MASK);
2604
2605 mv643xx_eth_irq(dev->irq, dev);
2606
2607 wrlp(mp, INT_MASK, mp->int_mask);
2608 }
2609 #endif
2610
2611
2612 /* platform glue ************************************************************/
2613 static void
2614 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2615 const struct mbus_dram_target_info *dram)
2616 {
2617 void __iomem *base = msp->base;
2618 u32 win_enable;
2619 u32 win_protect;
2620 int i;
2621
2622 for (i = 0; i < 6; i++) {
2623 writel(0, base + WINDOW_BASE(i));
2624 writel(0, base + WINDOW_SIZE(i));
2625 if (i < 4)
2626 writel(0, base + WINDOW_REMAP_HIGH(i));
2627 }
2628
2629 win_enable = 0x3f;
2630 win_protect = 0;
2631
2632 for (i = 0; i < dram->num_cs; i++) {
2633 const struct mbus_dram_window *cs = dram->cs + i;
2634
2635 writel((cs->base & 0xffff0000) |
2636 (cs->mbus_attr << 8) |
2637 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2638 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2639
2640 win_enable &= ~(1 << i);
2641 win_protect |= 3 << (2 * i);
2642 }
2643
2644 writel(win_enable, base + WINDOW_BAR_ENABLE);
2645 msp->win_protect = win_protect;
2646 }
2647
2648 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2649 {
2650 /*
2651 * Check whether we have a 14-bit coal limit field in bits
2652 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2653 * SDMA config register.
2654 */
2655 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2656 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2657 msp->extended_rx_coal_limit = 1;
2658 else
2659 msp->extended_rx_coal_limit = 0;
2660
2661 /*
2662 * Check whether the MAC supports TX rate control, and if
2663 * yes, whether its associated registers are in the old or
2664 * the new place.
2665 */
2666 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2667 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2668 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2669 } else {
2670 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2671 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2672 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2673 else
2674 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2675 }
2676 }
2677
2678 #if defined(CONFIG_OF)
2679 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2680 { .compatible = "marvell,orion-eth", },
2681 { .compatible = "marvell,kirkwood-eth", },
2682 { }
2683 };
2684 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2685 #endif
2686
2687 #if defined(CONFIG_OF_IRQ) && !defined(CONFIG_MV64X60)
2688 #define mv643xx_eth_property(_np, _name, _v) \
2689 do { \
2690 u32 tmp; \
2691 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2692 _v = tmp; \
2693 } while (0)
2694
2695 static struct platform_device *port_platdev[3];
2696
2697 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2698 struct device_node *pnp)
2699 {
2700 struct platform_device *ppdev;
2701 struct mv643xx_eth_platform_data ppd;
2702 struct resource res;
2703 const char *mac_addr;
2704 int ret;
2705 int dev_num = 0;
2706
2707 memset(&ppd, 0, sizeof(ppd));
2708 ppd.shared = pdev;
2709
2710 memset(&res, 0, sizeof(res));
2711 if (of_irq_to_resource(pnp, 0, &res) <= 0) {
2712 dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp);
2713 return -EINVAL;
2714 }
2715
2716 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2717 dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp);
2718 return -EINVAL;
2719 }
2720
2721 if (ppd.port_number >= 3) {
2722 dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp);
2723 return -EINVAL;
2724 }
2725
2726 while (dev_num < 3 && port_platdev[dev_num])
2727 dev_num++;
2728
2729 if (dev_num == 3) {
2730 dev_err(&pdev->dev, "too many ports registered\n");
2731 return -EINVAL;
2732 }
2733
2734 mac_addr = of_get_mac_address(pnp);
2735 if (!IS_ERR(mac_addr))
2736 ether_addr_copy(ppd.mac_addr, mac_addr);
2737
2738 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2739 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2740 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2741 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2742 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2743 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2744
2745 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2746 if (!ppd.phy_node) {
2747 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2748 of_property_read_u32(pnp, "speed", &ppd.speed);
2749 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2750 }
2751
2752 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2753 if (!ppdev)
2754 return -ENOMEM;
2755 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2756 ppdev->dev.of_node = pnp;
2757
2758 ret = platform_device_add_resources(ppdev, &res, 1);
2759 if (ret)
2760 goto port_err;
2761
2762 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2763 if (ret)
2764 goto port_err;
2765
2766 ret = platform_device_add(ppdev);
2767 if (ret)
2768 goto port_err;
2769
2770 port_platdev[dev_num] = ppdev;
2771
2772 return 0;
2773
2774 port_err:
2775 platform_device_put(ppdev);
2776 return ret;
2777 }
2778
2779 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2780 {
2781 struct mv643xx_eth_shared_platform_data *pd;
2782 struct device_node *pnp, *np = pdev->dev.of_node;
2783 int ret;
2784
2785 /* bail out if not registered from DT */
2786 if (!np)
2787 return 0;
2788
2789 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2790 if (!pd)
2791 return -ENOMEM;
2792 pdev->dev.platform_data = pd;
2793
2794 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2795
2796 for_each_available_child_of_node(np, pnp) {
2797 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2798 if (ret) {
2799 of_node_put(pnp);
2800 return ret;
2801 }
2802 }
2803 return 0;
2804 }
2805
2806 static void mv643xx_eth_shared_of_remove(void)
2807 {
2808 int n;
2809
2810 for (n = 0; n < 3; n++) {
2811 platform_device_del(port_platdev[n]);
2812 port_platdev[n] = NULL;
2813 }
2814 }
2815 #else
2816 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2817 {
2818 return 0;
2819 }
2820
2821 static inline void mv643xx_eth_shared_of_remove(void)
2822 {
2823 }
2824 #endif
2825
2826 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2827 {
2828 static int mv643xx_eth_version_printed;
2829 struct mv643xx_eth_shared_platform_data *pd;
2830 struct mv643xx_eth_shared_private *msp;
2831 const struct mbus_dram_target_info *dram;
2832 struct resource *res;
2833 int ret;
2834
2835 if (!mv643xx_eth_version_printed++)
2836 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2837 mv643xx_eth_driver_version);
2838
2839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2840 if (res == NULL)
2841 return -EINVAL;
2842
2843 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2844 if (msp == NULL)
2845 return -ENOMEM;
2846 platform_set_drvdata(pdev, msp);
2847
2848 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2849 if (msp->base == NULL)
2850 return -ENOMEM;
2851
2852 msp->clk = devm_clk_get(&pdev->dev, NULL);
2853 if (!IS_ERR(msp->clk))
2854 clk_prepare_enable(msp->clk);
2855
2856 /*
2857 * (Re-)program MBUS remapping windows if we are asked to.
2858 */
2859 dram = mv_mbus_dram_info();
2860 if (dram)
2861 mv643xx_eth_conf_mbus_windows(msp, dram);
2862
2863 ret = mv643xx_eth_shared_of_probe(pdev);
2864 if (ret)
2865 goto err_put_clk;
2866 pd = dev_get_platdata(&pdev->dev);
2867
2868 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2869 pd->tx_csum_limit : 9 * 1024;
2870 infer_hw_params(msp);
2871
2872 return 0;
2873
2874 err_put_clk:
2875 if (!IS_ERR(msp->clk))
2876 clk_disable_unprepare(msp->clk);
2877 return ret;
2878 }
2879
2880 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2881 {
2882 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2883
2884 mv643xx_eth_shared_of_remove();
2885 if (!IS_ERR(msp->clk))
2886 clk_disable_unprepare(msp->clk);
2887 return 0;
2888 }
2889
2890 static struct platform_driver mv643xx_eth_shared_driver = {
2891 .probe = mv643xx_eth_shared_probe,
2892 .remove = mv643xx_eth_shared_remove,
2893 .driver = {
2894 .name = MV643XX_ETH_SHARED_NAME,
2895 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2896 },
2897 };
2898
2899 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2900 {
2901 int addr_shift = 5 * mp->port_num;
2902 u32 data;
2903
2904 data = rdl(mp, PHY_ADDR);
2905 data &= ~(0x1f << addr_shift);
2906 data |= (phy_addr & 0x1f) << addr_shift;
2907 wrl(mp, PHY_ADDR, data);
2908 }
2909
2910 static int phy_addr_get(struct mv643xx_eth_private *mp)
2911 {
2912 unsigned int data;
2913
2914 data = rdl(mp, PHY_ADDR);
2915
2916 return (data >> (5 * mp->port_num)) & 0x1f;
2917 }
2918
2919 static void set_params(struct mv643xx_eth_private *mp,
2920 struct mv643xx_eth_platform_data *pd)
2921 {
2922 struct net_device *dev = mp->dev;
2923 unsigned int tx_ring_size;
2924
2925 if (is_valid_ether_addr(pd->mac_addr))
2926 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2927 else
2928 uc_addr_get(mp, dev->dev_addr);
2929
2930 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2931 if (pd->rx_queue_size)
2932 mp->rx_ring_size = pd->rx_queue_size;
2933 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2934 mp->rx_desc_sram_size = pd->rx_sram_size;
2935
2936 mp->rxq_count = pd->rx_queue_count ? : 1;
2937
2938 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2939 if (pd->tx_queue_size)
2940 tx_ring_size = pd->tx_queue_size;
2941
2942 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2943 MV643XX_MAX_SKB_DESCS * 2, 4096);
2944 if (mp->tx_ring_size != tx_ring_size)
2945 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2946 mp->tx_ring_size, tx_ring_size);
2947
2948 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2949 mp->tx_desc_sram_size = pd->tx_sram_size;
2950
2951 mp->txq_count = pd->tx_queue_count ? : 1;
2952 }
2953
2954 static int get_phy_mode(struct mv643xx_eth_private *mp)
2955 {
2956 struct device *dev = mp->dev->dev.parent;
2957 phy_interface_t iface;
2958 int err;
2959
2960 if (dev->of_node)
2961 err = of_get_phy_mode(dev->of_node, &iface);
2962
2963 /* Historical default if unspecified. We could also read/write
2964 * the interface state in the PSC1
2965 */
2966 if (!dev->of_node || err)
2967 iface = PHY_INTERFACE_MODE_GMII;
2968 return iface;
2969 }
2970
2971 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2972 int phy_addr)
2973 {
2974 struct phy_device *phydev;
2975 int start;
2976 int num;
2977 int i;
2978 char phy_id[MII_BUS_ID_SIZE + 3];
2979
2980 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2981 start = phy_addr_get(mp) & 0x1f;
2982 num = 32;
2983 } else {
2984 start = phy_addr & 0x1f;
2985 num = 1;
2986 }
2987
2988 /* Attempt to connect to the PHY using orion-mdio */
2989 phydev = ERR_PTR(-ENODEV);
2990 for (i = 0; i < num; i++) {
2991 int addr = (start + i) & 0x1f;
2992
2993 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2994 "orion-mdio-mii", addr);
2995
2996 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2997 get_phy_mode(mp));
2998 if (!IS_ERR(phydev)) {
2999 phy_addr_set(mp, addr);
3000 break;
3001 }
3002 }
3003
3004 return phydev;
3005 }
3006
3007 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3008 {
3009 struct net_device *dev = mp->dev;
3010 struct phy_device *phy = dev->phydev;
3011
3012 if (speed == 0) {
3013 phy->autoneg = AUTONEG_ENABLE;
3014 phy->speed = 0;
3015 phy->duplex = 0;
3016 linkmode_copy(phy->advertising, phy->supported);
3017 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3018 phy->advertising);
3019 } else {
3020 phy->autoneg = AUTONEG_DISABLE;
3021 linkmode_zero(phy->advertising);
3022 phy->speed = speed;
3023 phy->duplex = duplex;
3024 }
3025 phy_start_aneg(phy);
3026 }
3027
3028 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3029 {
3030 struct net_device *dev = mp->dev;
3031 u32 pscr;
3032
3033 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3034 if (pscr & SERIAL_PORT_ENABLE) {
3035 pscr &= ~SERIAL_PORT_ENABLE;
3036 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3037 }
3038
3039 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3040 if (!dev->phydev) {
3041 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3042 if (speed == SPEED_1000)
3043 pscr |= SET_GMII_SPEED_TO_1000;
3044 else if (speed == SPEED_100)
3045 pscr |= SET_MII_SPEED_TO_100;
3046
3047 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3048
3049 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3050 if (duplex == DUPLEX_FULL)
3051 pscr |= SET_FULL_DUPLEX_MODE;
3052 }
3053
3054 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3055 }
3056
3057 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3058 .ndo_open = mv643xx_eth_open,
3059 .ndo_stop = mv643xx_eth_stop,
3060 .ndo_start_xmit = mv643xx_eth_xmit,
3061 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3062 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3063 .ndo_validate_addr = eth_validate_addr,
3064 .ndo_do_ioctl = mv643xx_eth_ioctl,
3065 .ndo_change_mtu = mv643xx_eth_change_mtu,
3066 .ndo_set_features = mv643xx_eth_set_features,
3067 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3068 .ndo_get_stats = mv643xx_eth_get_stats,
3069 #ifdef CONFIG_NET_POLL_CONTROLLER
3070 .ndo_poll_controller = mv643xx_eth_netpoll,
3071 #endif
3072 };
3073
3074 static int mv643xx_eth_probe(struct platform_device *pdev)
3075 {
3076 struct mv643xx_eth_platform_data *pd;
3077 struct mv643xx_eth_private *mp;
3078 struct net_device *dev;
3079 struct phy_device *phydev = NULL;
3080 struct resource *res;
3081 int err;
3082
3083 pd = dev_get_platdata(&pdev->dev);
3084 if (pd == NULL) {
3085 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3086 return -ENODEV;
3087 }
3088
3089 if (pd->shared == NULL) {
3090 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3091 return -ENODEV;
3092 }
3093
3094 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3095 if (!dev)
3096 return -ENOMEM;
3097
3098 SET_NETDEV_DEV(dev, &pdev->dev);
3099 mp = netdev_priv(dev);
3100 platform_set_drvdata(pdev, mp);
3101
3102 mp->shared = platform_get_drvdata(pd->shared);
3103 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3104 mp->port_num = pd->port_number;
3105
3106 mp->dev = dev;
3107
3108 /* Kirkwood resets some registers on gated clocks. Especially
3109 * CLK125_BYPASS_EN must be cleared but is not available on
3110 * all other SoCs/System Controllers using this driver.
3111 */
3112 if (of_device_is_compatible(pdev->dev.of_node,
3113 "marvell,kirkwood-eth-port"))
3114 wrlp(mp, PORT_SERIAL_CONTROL1,
3115 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3116
3117 /*
3118 * Start with a default rate, and if there is a clock, allow
3119 * it to override the default.
3120 */
3121 mp->t_clk = 133000000;
3122 mp->clk = devm_clk_get(&pdev->dev, NULL);
3123 if (!IS_ERR(mp->clk)) {
3124 clk_prepare_enable(mp->clk);
3125 mp->t_clk = clk_get_rate(mp->clk);
3126 } else if (!IS_ERR(mp->shared->clk)) {
3127 mp->t_clk = clk_get_rate(mp->shared->clk);
3128 }
3129
3130 set_params(mp, pd);
3131 netif_set_real_num_tx_queues(dev, mp->txq_count);
3132 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3133
3134 err = 0;
3135 if (pd->phy_node) {
3136 phydev = of_phy_connect(mp->dev, pd->phy_node,
3137 mv643xx_eth_adjust_link, 0,
3138 get_phy_mode(mp));
3139 if (!phydev)
3140 err = -ENODEV;
3141 else
3142 phy_addr_set(mp, phydev->mdio.addr);
3143 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3144 phydev = phy_scan(mp, pd->phy_addr);
3145
3146 if (IS_ERR(phydev))
3147 err = PTR_ERR(phydev);
3148 else
3149 phy_init(mp, pd->speed, pd->duplex);
3150 }
3151 if (err == -ENODEV) {
3152 err = -EPROBE_DEFER;
3153 goto out;
3154 }
3155 if (err)
3156 goto out;
3157
3158 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3159
3160 init_pscr(mp, pd->speed, pd->duplex);
3161
3162
3163 mib_counters_clear(mp);
3164
3165 timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0);
3166 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3167
3168 spin_lock_init(&mp->mib_counters_lock);
3169
3170 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3171
3172 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3173
3174 timer_setup(&mp->rx_oom, oom_timer_wrapper, 0);
3175
3176
3177 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3178 BUG_ON(!res);
3179 dev->irq = res->start;
3180
3181 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3182
3183 dev->watchdog_timeo = 2 * HZ;
3184 dev->base_addr = 0;
3185
3186 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3187 dev->vlan_features = dev->features;
3188
3189 dev->features |= NETIF_F_RXCSUM;
3190 dev->hw_features = dev->features;
3191
3192 dev->priv_flags |= IFF_UNICAST_FLT;
3193 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3194
3195 /* MTU range: 64 - 9500 */
3196 dev->min_mtu = 64;
3197 dev->max_mtu = 9500;
3198
3199 if (mp->shared->win_protect)
3200 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3201
3202 netif_carrier_off(dev);
3203
3204 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3205
3206 set_rx_coal(mp, 250);
3207 set_tx_coal(mp, 0);
3208
3209 err = register_netdev(dev);
3210 if (err)
3211 goto out;
3212
3213 netdev_notice(dev, "port %d with MAC address %pM\n",
3214 mp->port_num, dev->dev_addr);
3215
3216 if (mp->tx_desc_sram_size > 0)
3217 netdev_notice(dev, "configured with sram\n");
3218
3219 return 0;
3220
3221 out:
3222 if (!IS_ERR(mp->clk))
3223 clk_disable_unprepare(mp->clk);
3224 free_netdev(dev);
3225
3226 return err;
3227 }
3228
3229 static int mv643xx_eth_remove(struct platform_device *pdev)
3230 {
3231 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3232 struct net_device *dev = mp->dev;
3233
3234 unregister_netdev(mp->dev);
3235 if (dev->phydev)
3236 phy_disconnect(dev->phydev);
3237 cancel_work_sync(&mp->tx_timeout_task);
3238
3239 if (!IS_ERR(mp->clk))
3240 clk_disable_unprepare(mp->clk);
3241
3242 free_netdev(mp->dev);
3243
3244 return 0;
3245 }
3246
3247 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3248 {
3249 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3250
3251 /* Mask all interrupts on ethernet port */
3252 wrlp(mp, INT_MASK, 0);
3253 rdlp(mp, INT_MASK);
3254
3255 if (netif_running(mp->dev))
3256 port_reset(mp);
3257 }
3258
3259 static struct platform_driver mv643xx_eth_driver = {
3260 .probe = mv643xx_eth_probe,
3261 .remove = mv643xx_eth_remove,
3262 .shutdown = mv643xx_eth_shutdown,
3263 .driver = {
3264 .name = MV643XX_ETH_NAME,
3265 },
3266 };
3267
3268 static struct platform_driver * const drivers[] = {
3269 &mv643xx_eth_shared_driver,
3270 &mv643xx_eth_driver,
3271 };
3272
3273 static int __init mv643xx_eth_init_module(void)
3274 {
3275 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3276 }
3277 module_init(mv643xx_eth_init_module);
3278
3279 static void __exit mv643xx_eth_cleanup_module(void)
3280 {
3281 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3282 }
3283 module_exit(mv643xx_eth_cleanup_module);
3284
3285 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3286 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3287 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3288 MODULE_LICENSE("GPL");
3289 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3290 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux with added FPC-III support