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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / mvpp2 / mvpp2_main.c
blob4b1808acef5812a934aeed1b44a804bd4fdb9bb2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/platform_device.h>
15 #include <linux/skbuff.h>
16 #include <linux/inetdevice.h>
17 #include <linux/mbus.h>
18 #include <linux/module.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpumask.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/phy.h>
29 #include <linux/phylink.h>
30 #include <linux/phy/phy.h>
31 #include <linux/ptp_classify.h>
32 #include <linux/clk.h>
33 #include <linux/hrtimer.h>
34 #include <linux/ktime.h>
35 #include <linux/regmap.h>
36 #include <uapi/linux/ppp_defs.h>
37 #include <net/ip.h>
38 #include <net/ipv6.h>
39 #include <net/tso.h>
40 #include <linux/bpf_trace.h>
41
42 #include "mvpp2.h"
43 #include "mvpp2_prs.h"
44 #include "mvpp2_cls.h"
45
46 enum mvpp2_bm_pool_log_num {
47 MVPP2_BM_SHORT,
48 MVPP2_BM_LONG,
49 MVPP2_BM_JUMBO,
50 MVPP2_BM_POOLS_NUM
51 };
52
53 static struct {
54 int pkt_size;
55 int buf_num;
56 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
57
58 /* The prototype is added here to be used in start_dev when using ACPI. This
59 * will be removed once phylink is used for all modes (dt+ACPI).
60 */
61 static void mvpp2_acpi_start(struct mvpp2_port *port);
62
63 /* Queue modes */
64 #define MVPP2_QDIST_SINGLE_MODE 0
65 #define MVPP2_QDIST_MULTI_MODE 1
66
67 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
68
69 module_param(queue_mode, int, 0444);
70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
71
72 /* Utility/helper methods */
73
74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
75 {
76 writel(data, priv->swth_base[0] + offset);
77 }
78
79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
80 {
81 return readl(priv->swth_base[0] + offset);
82 }
83
84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
85 {
86 return readl_relaxed(priv->swth_base[0] + offset);
87 }
88
89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
90 {
91 return cpu % priv->nthreads;
92 }
93
94 static struct page_pool *
95 mvpp2_create_page_pool(struct device *dev, int num, int len,
96 enum dma_data_direction dma_dir)
97 {
98 struct page_pool_params pp_params = {
99 /* internal DMA mapping in page_pool */
100 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
101 .pool_size = num,
102 .nid = NUMA_NO_NODE,
103 .dev = dev,
104 .dma_dir = dma_dir,
105 .offset = MVPP2_SKB_HEADROOM,
106 .max_len = len,
107 };
108
109 return page_pool_create(&pp_params);
110 }
111
112 /* These accessors should be used to access:
113 *
114 * - per-thread registers, where each thread has its own copy of the
115 * register.
116 *
117 * MVPP2_BM_VIRT_ALLOC_REG
118 * MVPP2_BM_ADDR_HIGH_ALLOC
119 * MVPP22_BM_ADDR_HIGH_RLS_REG
120 * MVPP2_BM_VIRT_RLS_REG
121 * MVPP2_ISR_RX_TX_CAUSE_REG
122 * MVPP2_ISR_RX_TX_MASK_REG
123 * MVPP2_TXQ_NUM_REG
124 * MVPP2_AGGR_TXQ_UPDATE_REG
125 * MVPP2_TXQ_RSVD_REQ_REG
126 * MVPP2_TXQ_RSVD_RSLT_REG
127 * MVPP2_TXQ_SENT_REG
128 * MVPP2_RXQ_NUM_REG
129 *
130 * - global registers that must be accessed through a specific thread
131 * window, because they are related to an access to a per-thread
132 * register
133 *
134 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
135 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
136 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
137 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
138 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
139 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
140 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
141 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
142 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
143 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
144 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
145 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
146 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
147 */
148 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
149 u32 offset, u32 data)
150 {
151 writel(data, priv->swth_base[thread] + offset);
152 }
153
154 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
155 u32 offset)
156 {
157 return readl(priv->swth_base[thread] + offset);
158 }
159
160 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
161 u32 offset, u32 data)
162 {
163 writel_relaxed(data, priv->swth_base[thread] + offset);
164 }
165
166 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
167 u32 offset)
168 {
169 return readl_relaxed(priv->swth_base[thread] + offset);
170 }
171
172 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
173 struct mvpp2_tx_desc *tx_desc)
174 {
175 if (port->priv->hw_version == MVPP21)
176 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
177 else
178 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
179 MVPP2_DESC_DMA_MASK;
180 }
181
182 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
183 struct mvpp2_tx_desc *tx_desc,
184 dma_addr_t dma_addr)
185 {
186 dma_addr_t addr, offset;
187
188 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
189 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
190
191 if (port->priv->hw_version == MVPP21) {
192 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
193 tx_desc->pp21.packet_offset = offset;
194 } else {
195 __le64 val = cpu_to_le64(addr);
196
197 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
198 tx_desc->pp22.buf_dma_addr_ptp |= val;
199 tx_desc->pp22.packet_offset = offset;
200 }
201 }
202
203 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
204 struct mvpp2_tx_desc *tx_desc)
205 {
206 if (port->priv->hw_version == MVPP21)
207 return le16_to_cpu(tx_desc->pp21.data_size);
208 else
209 return le16_to_cpu(tx_desc->pp22.data_size);
210 }
211
212 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
213 struct mvpp2_tx_desc *tx_desc,
214 size_t size)
215 {
216 if (port->priv->hw_version == MVPP21)
217 tx_desc->pp21.data_size = cpu_to_le16(size);
218 else
219 tx_desc->pp22.data_size = cpu_to_le16(size);
220 }
221
222 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
223 struct mvpp2_tx_desc *tx_desc,
224 unsigned int txq)
225 {
226 if (port->priv->hw_version == MVPP21)
227 tx_desc->pp21.phys_txq = txq;
228 else
229 tx_desc->pp22.phys_txq = txq;
230 }
231
232 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
233 struct mvpp2_tx_desc *tx_desc,
234 unsigned int command)
235 {
236 if (port->priv->hw_version == MVPP21)
237 tx_desc->pp21.command = cpu_to_le32(command);
238 else
239 tx_desc->pp22.command = cpu_to_le32(command);
240 }
241
242 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
243 struct mvpp2_tx_desc *tx_desc)
244 {
245 if (port->priv->hw_version == MVPP21)
246 return tx_desc->pp21.packet_offset;
247 else
248 return tx_desc->pp22.packet_offset;
249 }
250
251 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
252 struct mvpp2_rx_desc *rx_desc)
253 {
254 if (port->priv->hw_version == MVPP21)
255 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
256 else
257 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
258 MVPP2_DESC_DMA_MASK;
259 }
260
261 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
262 struct mvpp2_rx_desc *rx_desc)
263 {
264 if (port->priv->hw_version == MVPP21)
265 return le32_to_cpu(rx_desc->pp21.buf_cookie);
266 else
267 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
268 MVPP2_DESC_DMA_MASK;
269 }
270
271 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
272 struct mvpp2_rx_desc *rx_desc)
273 {
274 if (port->priv->hw_version == MVPP21)
275 return le16_to_cpu(rx_desc->pp21.data_size);
276 else
277 return le16_to_cpu(rx_desc->pp22.data_size);
278 }
279
280 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
281 struct mvpp2_rx_desc *rx_desc)
282 {
283 if (port->priv->hw_version == MVPP21)
284 return le32_to_cpu(rx_desc->pp21.status);
285 else
286 return le32_to_cpu(rx_desc->pp22.status);
287 }
288
289 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
290 {
291 txq_pcpu->txq_get_index++;
292 if (txq_pcpu->txq_get_index == txq_pcpu->size)
293 txq_pcpu->txq_get_index = 0;
294 }
295
296 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
297 struct mvpp2_txq_pcpu *txq_pcpu,
298 void *data,
299 struct mvpp2_tx_desc *tx_desc,
300 enum mvpp2_tx_buf_type buf_type)
301 {
302 struct mvpp2_txq_pcpu_buf *tx_buf =
303 txq_pcpu->buffs + txq_pcpu->txq_put_index;
304 tx_buf->type = buf_type;
305 if (buf_type == MVPP2_TYPE_SKB)
306 tx_buf->skb = data;
307 else
308 tx_buf->xdpf = data;
309 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
310 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
311 mvpp2_txdesc_offset_get(port, tx_desc);
312 txq_pcpu->txq_put_index++;
313 if (txq_pcpu->txq_put_index == txq_pcpu->size)
314 txq_pcpu->txq_put_index = 0;
315 }
316
317 /* Get number of maximum RXQ */
318 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
319 {
320 unsigned int nrxqs;
321
322 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
323 return 1;
324
325 /* According to the PPv2.2 datasheet and our experiments on
326 * PPv2.1, RX queues have an allocation granularity of 4 (when
327 * more than a single one on PPv2.2).
328 * Round up to nearest multiple of 4.
329 */
330 nrxqs = (num_possible_cpus() + 3) & ~0x3;
331 if (nrxqs > MVPP2_PORT_MAX_RXQ)
332 nrxqs = MVPP2_PORT_MAX_RXQ;
333
334 return nrxqs;
335 }
336
337 /* Get number of physical egress port */
338 static inline int mvpp2_egress_port(struct mvpp2_port *port)
339 {
340 return MVPP2_MAX_TCONT + port->id;
341 }
342
343 /* Get number of physical TXQ */
344 static inline int mvpp2_txq_phys(int port, int txq)
345 {
346 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
347 }
348
349 /* Returns a struct page if page_pool is set, otherwise a buffer */
350 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
351 struct page_pool *page_pool)
352 {
353 if (page_pool)
354 return page_pool_dev_alloc_pages(page_pool);
355
356 if (likely(pool->frag_size <= PAGE_SIZE))
357 return netdev_alloc_frag(pool->frag_size);
358
359 return kmalloc(pool->frag_size, GFP_ATOMIC);
360 }
361
362 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
363 struct page_pool *page_pool, void *data)
364 {
365 if (page_pool)
366 page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
367 else if (likely(pool->frag_size <= PAGE_SIZE))
368 skb_free_frag(data);
369 else
370 kfree(data);
371 }
372
373 /* Buffer Manager configuration routines */
374
375 /* Create pool */
376 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
377 struct mvpp2_bm_pool *bm_pool, int size)
378 {
379 u32 val;
380
381 /* Number of buffer pointers must be a multiple of 16, as per
382 * hardware constraints
383 */
384 if (!IS_ALIGNED(size, 16))
385 return -EINVAL;
386
387 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
388 * bytes per buffer pointer
389 */
390 if (priv->hw_version == MVPP21)
391 bm_pool->size_bytes = 2 * sizeof(u32) * size;
392 else
393 bm_pool->size_bytes = 2 * sizeof(u64) * size;
394
395 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
396 &bm_pool->dma_addr,
397 GFP_KERNEL);
398 if (!bm_pool->virt_addr)
399 return -ENOMEM;
400
401 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
402 MVPP2_BM_POOL_PTR_ALIGN)) {
403 dma_free_coherent(dev, bm_pool->size_bytes,
404 bm_pool->virt_addr, bm_pool->dma_addr);
405 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
406 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
407 return -ENOMEM;
408 }
409
410 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
411 lower_32_bits(bm_pool->dma_addr));
412 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
413
414 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
415 val |= MVPP2_BM_START_MASK;
416 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
417
418 bm_pool->size = size;
419 bm_pool->pkt_size = 0;
420 bm_pool->buf_num = 0;
421
422 return 0;
423 }
424
425 /* Set pool buffer size */
426 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
427 struct mvpp2_bm_pool *bm_pool,
428 int buf_size)
429 {
430 u32 val;
431
432 bm_pool->buf_size = buf_size;
433
434 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
435 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
436 }
437
438 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
439 struct mvpp2_bm_pool *bm_pool,
440 dma_addr_t *dma_addr,
441 phys_addr_t *phys_addr)
442 {
443 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
444
445 *dma_addr = mvpp2_thread_read(priv, thread,
446 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
447 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
448
449 if (priv->hw_version == MVPP22) {
450 u32 val;
451 u32 dma_addr_highbits, phys_addr_highbits;
452
453 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
454 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
455 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
456 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
457
458 if (sizeof(dma_addr_t) == 8)
459 *dma_addr |= (u64)dma_addr_highbits << 32;
460
461 if (sizeof(phys_addr_t) == 8)
462 *phys_addr |= (u64)phys_addr_highbits << 32;
463 }
464
465 put_cpu();
466 }
467
468 /* Free all buffers from the pool */
469 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
470 struct mvpp2_bm_pool *bm_pool, int buf_num)
471 {
472 struct page_pool *pp = NULL;
473 int i;
474
475 if (buf_num > bm_pool->buf_num) {
476 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
477 bm_pool->id, buf_num);
478 buf_num = bm_pool->buf_num;
479 }
480
481 if (priv->percpu_pools)
482 pp = priv->page_pool[bm_pool->id];
483
484 for (i = 0; i < buf_num; i++) {
485 dma_addr_t buf_dma_addr;
486 phys_addr_t buf_phys_addr;
487 void *data;
488
489 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
490 &buf_dma_addr, &buf_phys_addr);
491
492 if (!pp)
493 dma_unmap_single(dev, buf_dma_addr,
494 bm_pool->buf_size, DMA_FROM_DEVICE);
495
496 data = (void *)phys_to_virt(buf_phys_addr);
497 if (!data)
498 break;
499
500 mvpp2_frag_free(bm_pool, pp, data);
501 }
502
503 /* Update BM driver with number of buffers removed from pool */
504 bm_pool->buf_num -= i;
505 }
506
507 /* Check number of buffers in BM pool */
508 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
509 {
510 int buf_num = 0;
511
512 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
513 MVPP22_BM_POOL_PTRS_NUM_MASK;
514 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
515 MVPP2_BM_BPPI_PTR_NUM_MASK;
516
517 /* HW has one buffer ready which is not reflected in the counters */
518 if (buf_num)
519 buf_num += 1;
520
521 return buf_num;
522 }
523
524 /* Cleanup pool */
525 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
526 struct mvpp2_bm_pool *bm_pool)
527 {
528 int buf_num;
529 u32 val;
530
531 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
532 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
533
534 /* Check buffer counters after free */
535 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
536 if (buf_num) {
537 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
538 bm_pool->id, bm_pool->buf_num);
539 return 0;
540 }
541
542 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
543 val |= MVPP2_BM_STOP_MASK;
544 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
545
546 if (priv->percpu_pools) {
547 page_pool_destroy(priv->page_pool[bm_pool->id]);
548 priv->page_pool[bm_pool->id] = NULL;
549 }
550
551 dma_free_coherent(dev, bm_pool->size_bytes,
552 bm_pool->virt_addr,
553 bm_pool->dma_addr);
554 return 0;
555 }
556
557 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
558 {
559 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
560 struct mvpp2_bm_pool *bm_pool;
561
562 if (priv->percpu_pools)
563 poolnum = mvpp2_get_nrxqs(priv) * 2;
564
565 /* Create all pools with maximum size */
566 size = MVPP2_BM_POOL_SIZE_MAX;
567 for (i = 0; i < poolnum; i++) {
568 bm_pool = &priv->bm_pools[i];
569 bm_pool->id = i;
570 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
571 if (err)
572 goto err_unroll_pools;
573 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
574 }
575 return 0;
576
577 err_unroll_pools:
578 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
579 for (i = i - 1; i >= 0; i--)
580 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
581 return err;
582 }
583
584 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
585 {
586 enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
587 int i, err, poolnum = MVPP2_BM_POOLS_NUM;
588 struct mvpp2_port *port;
589
590 if (priv->percpu_pools) {
591 for (i = 0; i < priv->port_count; i++) {
592 port = priv->port_list[i];
593 if (port->xdp_prog) {
594 dma_dir = DMA_BIDIRECTIONAL;
595 break;
596 }
597 }
598
599 poolnum = mvpp2_get_nrxqs(priv) * 2;
600 for (i = 0; i < poolnum; i++) {
601 /* the pool in use */
602 int pn = i / (poolnum / 2);
603
604 priv->page_pool[i] =
605 mvpp2_create_page_pool(dev,
606 mvpp2_pools[pn].buf_num,
607 mvpp2_pools[pn].pkt_size,
608 dma_dir);
609 if (IS_ERR(priv->page_pool[i])) {
610 int j;
611
612 for (j = 0; j < i; j++) {
613 page_pool_destroy(priv->page_pool[j]);
614 priv->page_pool[j] = NULL;
615 }
616 return PTR_ERR(priv->page_pool[i]);
617 }
618 }
619 }
620
621 dev_info(dev, "using %d %s buffers\n", poolnum,
622 priv->percpu_pools ? "per-cpu" : "shared");
623
624 for (i = 0; i < poolnum; i++) {
625 /* Mask BM all interrupts */
626 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
627 /* Clear BM cause register */
628 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
629 }
630
631 /* Allocate and initialize BM pools */
632 priv->bm_pools = devm_kcalloc(dev, poolnum,
633 sizeof(*priv->bm_pools), GFP_KERNEL);
634 if (!priv->bm_pools)
635 return -ENOMEM;
636
637 err = mvpp2_bm_pools_init(dev, priv);
638 if (err < 0)
639 return err;
640 return 0;
641 }
642
643 static void mvpp2_setup_bm_pool(void)
644 {
645 /* Short pool */
646 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
647 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
648
649 /* Long pool */
650 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
651 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
652
653 /* Jumbo pool */
654 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
655 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
656 }
657
658 /* Attach long pool to rxq */
659 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
660 int lrxq, int long_pool)
661 {
662 u32 val, mask;
663 int prxq;
664
665 /* Get queue physical ID */
666 prxq = port->rxqs[lrxq]->id;
667
668 if (port->priv->hw_version == MVPP21)
669 mask = MVPP21_RXQ_POOL_LONG_MASK;
670 else
671 mask = MVPP22_RXQ_POOL_LONG_MASK;
672
673 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
674 val &= ~mask;
675 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
676 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
677 }
678
679 /* Attach short pool to rxq */
680 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
681 int lrxq, int short_pool)
682 {
683 u32 val, mask;
684 int prxq;
685
686 /* Get queue physical ID */
687 prxq = port->rxqs[lrxq]->id;
688
689 if (port->priv->hw_version == MVPP21)
690 mask = MVPP21_RXQ_POOL_SHORT_MASK;
691 else
692 mask = MVPP22_RXQ_POOL_SHORT_MASK;
693
694 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
695 val &= ~mask;
696 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
697 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
698 }
699
700 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
701 struct mvpp2_bm_pool *bm_pool,
702 struct page_pool *page_pool,
703 dma_addr_t *buf_dma_addr,
704 phys_addr_t *buf_phys_addr,
705 gfp_t gfp_mask)
706 {
707 dma_addr_t dma_addr;
708 struct page *page;
709 void *data;
710
711 data = mvpp2_frag_alloc(bm_pool, page_pool);
712 if (!data)
713 return NULL;
714
715 if (page_pool) {
716 page = (struct page *)data;
717 dma_addr = page_pool_get_dma_addr(page);
718 data = page_to_virt(page);
719 } else {
720 dma_addr = dma_map_single(port->dev->dev.parent, data,
721 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
722 DMA_FROM_DEVICE);
723 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
724 mvpp2_frag_free(bm_pool, NULL, data);
725 return NULL;
726 }
727 }
728 *buf_dma_addr = dma_addr;
729 *buf_phys_addr = virt_to_phys(data);
730
731 return data;
732 }
733
734 /* Release buffer to BM */
735 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
736 dma_addr_t buf_dma_addr,
737 phys_addr_t buf_phys_addr)
738 {
739 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
740 unsigned long flags = 0;
741
742 if (test_bit(thread, &port->priv->lock_map))
743 spin_lock_irqsave(&port->bm_lock[thread], flags);
744
745 if (port->priv->hw_version == MVPP22) {
746 u32 val = 0;
747
748 if (sizeof(dma_addr_t) == 8)
749 val |= upper_32_bits(buf_dma_addr) &
750 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
751
752 if (sizeof(phys_addr_t) == 8)
753 val |= (upper_32_bits(buf_phys_addr)
754 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
755 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
756
757 mvpp2_thread_write_relaxed(port->priv, thread,
758 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
759 }
760
761 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
762 * returned in the "cookie" field of the RX
763 * descriptor. Instead of storing the virtual address, we
764 * store the physical address
765 */
766 mvpp2_thread_write_relaxed(port->priv, thread,
767 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
768 mvpp2_thread_write_relaxed(port->priv, thread,
769 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
770
771 if (test_bit(thread, &port->priv->lock_map))
772 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
773
774 put_cpu();
775 }
776
777 /* Allocate buffers for the pool */
778 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
779 struct mvpp2_bm_pool *bm_pool, int buf_num)
780 {
781 int i, buf_size, total_size;
782 dma_addr_t dma_addr;
783 phys_addr_t phys_addr;
784 struct page_pool *pp = NULL;
785 void *buf;
786
787 if (port->priv->percpu_pools &&
788 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
789 netdev_err(port->dev,
790 "attempted to use jumbo frames with per-cpu pools");
791 return 0;
792 }
793
794 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
795 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
796
797 if (buf_num < 0 ||
798 (buf_num + bm_pool->buf_num > bm_pool->size)) {
799 netdev_err(port->dev,
800 "cannot allocate %d buffers for pool %d\n",
801 buf_num, bm_pool->id);
802 return 0;
803 }
804
805 if (port->priv->percpu_pools)
806 pp = port->priv->page_pool[bm_pool->id];
807 for (i = 0; i < buf_num; i++) {
808 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
809 &phys_addr, GFP_KERNEL);
810 if (!buf)
811 break;
812
813 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
814 phys_addr);
815 }
816
817 /* Update BM driver with number of buffers added to pool */
818 bm_pool->buf_num += i;
819
820 netdev_dbg(port->dev,
821 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
822 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
823
824 netdev_dbg(port->dev,
825 "pool %d: %d of %d buffers added\n",
826 bm_pool->id, i, buf_num);
827 return i;
828 }
829
830 /* Notify the driver that BM pool is being used as specific type and return the
831 * pool pointer on success
832 */
833 static struct mvpp2_bm_pool *
834 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
835 {
836 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
837 int num;
838
839 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
840 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
841 netdev_err(port->dev, "Invalid pool %d\n", pool);
842 return NULL;
843 }
844
845 /* Allocate buffers in case BM pool is used as long pool, but packet
846 * size doesn't match MTU or BM pool hasn't being used yet
847 */
848 if (new_pool->pkt_size == 0) {
849 int pkts_num;
850
851 /* Set default buffer number or free all the buffers in case
852 * the pool is not empty
853 */
854 pkts_num = new_pool->buf_num;
855 if (pkts_num == 0) {
856 if (port->priv->percpu_pools) {
857 if (pool < port->nrxqs)
858 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
859 else
860 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
861 } else {
862 pkts_num = mvpp2_pools[pool].buf_num;
863 }
864 } else {
865 mvpp2_bm_bufs_free(port->dev->dev.parent,
866 port->priv, new_pool, pkts_num);
867 }
868
869 new_pool->pkt_size = pkt_size;
870 new_pool->frag_size =
871 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
872 MVPP2_SKB_SHINFO_SIZE;
873
874 /* Allocate buffers for this pool */
875 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
876 if (num != pkts_num) {
877 WARN(1, "pool %d: %d of %d allocated\n",
878 new_pool->id, num, pkts_num);
879 return NULL;
880 }
881 }
882
883 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
884 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
885
886 return new_pool;
887 }
888
889 static struct mvpp2_bm_pool *
890 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
891 unsigned int pool, int pkt_size)
892 {
893 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
894 int num;
895
896 if (pool > port->nrxqs * 2) {
897 netdev_err(port->dev, "Invalid pool %d\n", pool);
898 return NULL;
899 }
900
901 /* Allocate buffers in case BM pool is used as long pool, but packet
902 * size doesn't match MTU or BM pool hasn't being used yet
903 */
904 if (new_pool->pkt_size == 0) {
905 int pkts_num;
906
907 /* Set default buffer number or free all the buffers in case
908 * the pool is not empty
909 */
910 pkts_num = new_pool->buf_num;
911 if (pkts_num == 0)
912 pkts_num = mvpp2_pools[type].buf_num;
913 else
914 mvpp2_bm_bufs_free(port->dev->dev.parent,
915 port->priv, new_pool, pkts_num);
916
917 new_pool->pkt_size = pkt_size;
918 new_pool->frag_size =
919 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
920 MVPP2_SKB_SHINFO_SIZE;
921
922 /* Allocate buffers for this pool */
923 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
924 if (num != pkts_num) {
925 WARN(1, "pool %d: %d of %d allocated\n",
926 new_pool->id, num, pkts_num);
927 return NULL;
928 }
929 }
930
931 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
932 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
933
934 return new_pool;
935 }
936
937 /* Initialize pools for swf, shared buffers variant */
938 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
939 {
940 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
941 int rxq;
942
943 /* If port pkt_size is higher than 1518B:
944 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
945 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
946 */
947 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
948 long_log_pool = MVPP2_BM_JUMBO;
949 short_log_pool = MVPP2_BM_LONG;
950 } else {
951 long_log_pool = MVPP2_BM_LONG;
952 short_log_pool = MVPP2_BM_SHORT;
953 }
954
955 if (!port->pool_long) {
956 port->pool_long =
957 mvpp2_bm_pool_use(port, long_log_pool,
958 mvpp2_pools[long_log_pool].pkt_size);
959 if (!port->pool_long)
960 return -ENOMEM;
961
962 port->pool_long->port_map |= BIT(port->id);
963
964 for (rxq = 0; rxq < port->nrxqs; rxq++)
965 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
966 }
967
968 if (!port->pool_short) {
969 port->pool_short =
970 mvpp2_bm_pool_use(port, short_log_pool,
971 mvpp2_pools[short_log_pool].pkt_size);
972 if (!port->pool_short)
973 return -ENOMEM;
974
975 port->pool_short->port_map |= BIT(port->id);
976
977 for (rxq = 0; rxq < port->nrxqs; rxq++)
978 mvpp2_rxq_short_pool_set(port, rxq,
979 port->pool_short->id);
980 }
981
982 return 0;
983 }
984
985 /* Initialize pools for swf, percpu buffers variant */
986 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
987 {
988 struct mvpp2_bm_pool *bm_pool;
989 int i;
990
991 for (i = 0; i < port->nrxqs; i++) {
992 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
993 mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
994 if (!bm_pool)
995 return -ENOMEM;
996
997 bm_pool->port_map |= BIT(port->id);
998 mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
999 }
1000
1001 for (i = 0; i < port->nrxqs; i++) {
1002 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1003 mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1004 if (!bm_pool)
1005 return -ENOMEM;
1006
1007 bm_pool->port_map |= BIT(port->id);
1008 mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1009 }
1010
1011 port->pool_long = NULL;
1012 port->pool_short = NULL;
1013
1014 return 0;
1015 }
1016
1017 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1018 {
1019 if (port->priv->percpu_pools)
1020 return mvpp2_swf_bm_pool_init_percpu(port);
1021 else
1022 return mvpp2_swf_bm_pool_init_shared(port);
1023 }
1024
1025 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1026 enum mvpp2_bm_pool_log_num new_long_pool)
1027 {
1028 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1029
1030 /* Update L4 checksum when jumbo enable/disable on port.
1031 * Only port 0 supports hardware checksum offload due to
1032 * the Tx FIFO size limitation.
1033 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1034 * has 7 bits, so the maximum L3 offset is 128.
1035 */
1036 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1037 port->dev->features &= ~csums;
1038 port->dev->hw_features &= ~csums;
1039 } else {
1040 port->dev->features |= csums;
1041 port->dev->hw_features |= csums;
1042 }
1043 }
1044
1045 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1046 {
1047 struct mvpp2_port *port = netdev_priv(dev);
1048 enum mvpp2_bm_pool_log_num new_long_pool;
1049 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1050
1051 if (port->priv->percpu_pools)
1052 goto out_set;
1053
1054 /* If port MTU is higher than 1518B:
1055 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1056 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1057 */
1058 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1059 new_long_pool = MVPP2_BM_JUMBO;
1060 else
1061 new_long_pool = MVPP2_BM_LONG;
1062
1063 if (new_long_pool != port->pool_long->id) {
1064 /* Remove port from old short & long pool */
1065 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1066 port->pool_long->pkt_size);
1067 port->pool_long->port_map &= ~BIT(port->id);
1068 port->pool_long = NULL;
1069
1070 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1071 port->pool_short->pkt_size);
1072 port->pool_short->port_map &= ~BIT(port->id);
1073 port->pool_short = NULL;
1074
1075 port->pkt_size = pkt_size;
1076
1077 /* Add port to new short & long pool */
1078 mvpp2_swf_bm_pool_init(port);
1079
1080 mvpp2_set_hw_csum(port, new_long_pool);
1081 }
1082
1083 out_set:
1084 dev->mtu = mtu;
1085 dev->wanted_features = dev->features;
1086
1087 netdev_update_features(dev);
1088 return 0;
1089 }
1090
1091 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1092 {
1093 int i, sw_thread_mask = 0;
1094
1095 for (i = 0; i < port->nqvecs; i++)
1096 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1097
1098 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1099 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1100 }
1101
1102 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1103 {
1104 int i, sw_thread_mask = 0;
1105
1106 for (i = 0; i < port->nqvecs; i++)
1107 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1108
1109 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1110 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1111 }
1112
1113 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1114 {
1115 struct mvpp2_port *port = qvec->port;
1116
1117 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1118 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1119 }
1120
1121 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1122 {
1123 struct mvpp2_port *port = qvec->port;
1124
1125 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1126 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1127 }
1128
1129 /* Mask the current thread's Rx/Tx interrupts
1130 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1131 * using smp_processor_id() is OK.
1132 */
1133 static void mvpp2_interrupts_mask(void *arg)
1134 {
1135 struct mvpp2_port *port = arg;
1136
1137 /* If the thread isn't used, don't do anything */
1138 if (smp_processor_id() > port->priv->nthreads)
1139 return;
1140
1141 mvpp2_thread_write(port->priv,
1142 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1143 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1144 }
1145
1146 /* Unmask the current thread's Rx/Tx interrupts.
1147 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1148 * using smp_processor_id() is OK.
1149 */
1150 static void mvpp2_interrupts_unmask(void *arg)
1151 {
1152 struct mvpp2_port *port = arg;
1153 u32 val;
1154
1155 /* If the thread isn't used, don't do anything */
1156 if (smp_processor_id() > port->priv->nthreads)
1157 return;
1158
1159 val = MVPP2_CAUSE_MISC_SUM_MASK |
1160 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1161 if (port->has_tx_irqs)
1162 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1163
1164 mvpp2_thread_write(port->priv,
1165 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1166 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1167 }
1168
1169 static void
1170 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1171 {
1172 u32 val;
1173 int i;
1174
1175 if (port->priv->hw_version != MVPP22)
1176 return;
1177
1178 if (mask)
1179 val = 0;
1180 else
1181 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1182
1183 for (i = 0; i < port->nqvecs; i++) {
1184 struct mvpp2_queue_vector *v = port->qvecs + i;
1185
1186 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1187 continue;
1188
1189 mvpp2_thread_write(port->priv, v->sw_thread_id,
1190 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1191 }
1192 }
1193
1194 /* Only GOP port 0 has an XLG MAC */
1195 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1196 {
1197 return port->gop_id == 0;
1198 }
1199
1200 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1201 {
1202 return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
1203 }
1204
1205 /* Port configuration routines */
1206 static bool mvpp2_is_xlg(phy_interface_t interface)
1207 {
1208 return interface == PHY_INTERFACE_MODE_10GBASER ||
1209 interface == PHY_INTERFACE_MODE_XAUI;
1210 }
1211
1212 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1213 {
1214 u32 old, val;
1215
1216 old = val = readl(ptr);
1217 val &= ~mask;
1218 val |= set;
1219 if (old != val)
1220 writel(val, ptr);
1221 }
1222
1223 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1224 {
1225 struct mvpp2 *priv = port->priv;
1226 u32 val;
1227
1228 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1229 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1230 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1231
1232 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1233 if (port->gop_id == 2)
1234 val |= GENCONF_CTRL0_PORT0_RGMII;
1235 else if (port->gop_id == 3)
1236 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
1237 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1238 }
1239
1240 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1241 {
1242 struct mvpp2 *priv = port->priv;
1243 u32 val;
1244
1245 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1246 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1247 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1248 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1249
1250 if (port->gop_id > 1) {
1251 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1252 if (port->gop_id == 2)
1253 val &= ~GENCONF_CTRL0_PORT0_RGMII;
1254 else if (port->gop_id == 3)
1255 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1256 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1257 }
1258 }
1259
1260 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1261 {
1262 struct mvpp2 *priv = port->priv;
1263 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1264 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1265 u32 val;
1266
1267 val = readl(xpcs + MVPP22_XPCS_CFG0);
1268 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1269 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1270 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1271 writel(val, xpcs + MVPP22_XPCS_CFG0);
1272
1273 val = readl(mpcs + MVPP22_MPCS_CTRL);
1274 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1275 writel(val, mpcs + MVPP22_MPCS_CTRL);
1276
1277 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1278 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1279 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1280 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1281 }
1282
1283 static int mvpp22_gop_init(struct mvpp2_port *port)
1284 {
1285 struct mvpp2 *priv = port->priv;
1286 u32 val;
1287
1288 if (!priv->sysctrl_base)
1289 return 0;
1290
1291 switch (port->phy_interface) {
1292 case PHY_INTERFACE_MODE_RGMII:
1293 case PHY_INTERFACE_MODE_RGMII_ID:
1294 case PHY_INTERFACE_MODE_RGMII_RXID:
1295 case PHY_INTERFACE_MODE_RGMII_TXID:
1296 if (!mvpp2_port_supports_rgmii(port))
1297 goto invalid_conf;
1298 mvpp22_gop_init_rgmii(port);
1299 break;
1300 case PHY_INTERFACE_MODE_SGMII:
1301 case PHY_INTERFACE_MODE_1000BASEX:
1302 case PHY_INTERFACE_MODE_2500BASEX:
1303 mvpp22_gop_init_sgmii(port);
1304 break;
1305 case PHY_INTERFACE_MODE_10GBASER:
1306 if (!mvpp2_port_supports_xlg(port))
1307 goto invalid_conf;
1308 mvpp22_gop_init_10gkr(port);
1309 break;
1310 default:
1311 goto unsupported_conf;
1312 }
1313
1314 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1315 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1316 GENCONF_PORT_CTRL1_EN(port->gop_id);
1317 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1318
1319 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1320 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1321 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1322
1323 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1324 val |= GENCONF_SOFT_RESET1_GOP;
1325 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1326
1327 unsupported_conf:
1328 return 0;
1329
1330 invalid_conf:
1331 netdev_err(port->dev, "Invalid port configuration\n");
1332 return -EINVAL;
1333 }
1334
1335 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1336 {
1337 u32 val;
1338
1339 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1340 phy_interface_mode_is_8023z(port->phy_interface) ||
1341 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1342 /* Enable the GMAC link status irq for this port */
1343 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1344 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1345 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1346 }
1347
1348 if (mvpp2_port_supports_xlg(port)) {
1349 /* Enable the XLG/GIG irqs for this port */
1350 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1351 if (mvpp2_is_xlg(port->phy_interface))
1352 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1353 else
1354 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1355 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1356 }
1357 }
1358
1359 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1360 {
1361 u32 val;
1362
1363 if (mvpp2_port_supports_xlg(port)) {
1364 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1365 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1366 MVPP22_XLG_EXT_INT_MASK_GIG);
1367 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1368 }
1369
1370 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1371 phy_interface_mode_is_8023z(port->phy_interface) ||
1372 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1373 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1374 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1375 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1376 }
1377 }
1378
1379 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1380 {
1381 u32 val;
1382
1383 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
1384 MVPP22_GMAC_INT_SUM_MASK_PTP,
1385 MVPP22_GMAC_INT_SUM_MASK_PTP);
1386
1387 if (port->phylink ||
1388 phy_interface_mode_is_rgmii(port->phy_interface) ||
1389 phy_interface_mode_is_8023z(port->phy_interface) ||
1390 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1391 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1392 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1393 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1394 }
1395
1396 if (mvpp2_port_supports_xlg(port)) {
1397 val = readl(port->base + MVPP22_XLG_INT_MASK);
1398 val |= MVPP22_XLG_INT_MASK_LINK;
1399 writel(val, port->base + MVPP22_XLG_INT_MASK);
1400
1401 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
1402 MVPP22_XLG_EXT_INT_MASK_PTP,
1403 MVPP22_XLG_EXT_INT_MASK_PTP);
1404 }
1405
1406 mvpp22_gop_unmask_irq(port);
1407 }
1408
1409 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1410 *
1411 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1412 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1413 * differ.
1414 *
1415 * The COMPHY configures the serdes lanes regardless of the actual use of the
1416 * lanes by the physical layer. This is why configurations like
1417 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1418 */
1419 static int mvpp22_comphy_init(struct mvpp2_port *port)
1420 {
1421 int ret;
1422
1423 if (!port->comphy)
1424 return 0;
1425
1426 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1427 port->phy_interface);
1428 if (ret)
1429 return ret;
1430
1431 return phy_power_on(port->comphy);
1432 }
1433
1434 static void mvpp2_port_enable(struct mvpp2_port *port)
1435 {
1436 u32 val;
1437
1438 if (mvpp2_port_supports_xlg(port) &&
1439 mvpp2_is_xlg(port->phy_interface)) {
1440 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1441 val |= MVPP22_XLG_CTRL0_PORT_EN;
1442 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1443 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1444 } else {
1445 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1446 val |= MVPP2_GMAC_PORT_EN_MASK;
1447 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1448 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1449 }
1450 }
1451
1452 static void mvpp2_port_disable(struct mvpp2_port *port)
1453 {
1454 u32 val;
1455
1456 if (mvpp2_port_supports_xlg(port) &&
1457 mvpp2_is_xlg(port->phy_interface)) {
1458 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1459 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1460 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1461 }
1462
1463 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1464 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1465 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1466 }
1467
1468 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1469 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1470 {
1471 u32 val;
1472
1473 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1474 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1475 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1476 }
1477
1478 /* Configure loopback port */
1479 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1480 const struct phylink_link_state *state)
1481 {
1482 u32 val;
1483
1484 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1485
1486 if (state->speed == 1000)
1487 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1488 else
1489 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1490
1491 if (phy_interface_mode_is_8023z(state->interface) ||
1492 state->interface == PHY_INTERFACE_MODE_SGMII)
1493 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1494 else
1495 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1496
1497 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1498 }
1499
1500 enum {
1501 ETHTOOL_XDP_REDIRECT,
1502 ETHTOOL_XDP_PASS,
1503 ETHTOOL_XDP_DROP,
1504 ETHTOOL_XDP_TX,
1505 ETHTOOL_XDP_TX_ERR,
1506 ETHTOOL_XDP_XMIT,
1507 ETHTOOL_XDP_XMIT_ERR,
1508 };
1509
1510 struct mvpp2_ethtool_counter {
1511 unsigned int offset;
1512 const char string[ETH_GSTRING_LEN];
1513 bool reg_is_64b;
1514 };
1515
1516 static u64 mvpp2_read_count(struct mvpp2_port *port,
1517 const struct mvpp2_ethtool_counter *counter)
1518 {
1519 u64 val;
1520
1521 val = readl(port->stats_base + counter->offset);
1522 if (counter->reg_is_64b)
1523 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1524
1525 return val;
1526 }
1527
1528 /* Some counters are accessed indirectly by first writing an index to
1529 * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1530 * register we access, it can be a hit counter for some classification tables,
1531 * a counter specific to a rxq, a txq or a buffer pool.
1532 */
1533 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1534 {
1535 mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1536 return mvpp2_read(priv, reg);
1537 }
1538
1539 /* Due to the fact that software statistics and hardware statistics are, by
1540 * design, incremented at different moments in the chain of packet processing,
1541 * it is very likely that incoming packets could have been dropped after being
1542 * counted by hardware but before reaching software statistics (most probably
1543 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1544 * are added in between as well as TSO skb will be split and header bytes added.
1545 * Hence, statistics gathered from userspace with ifconfig (software) and
1546 * ethtool (hardware) cannot be compared.
1547 */
1548 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1549 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1550 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1551 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1552 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1553 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1554 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1555 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1556 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1557 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1558 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1559 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1560 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1561 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1562 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1563 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1564 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1565 { MVPP2_MIB_FC_SENT, "fc_sent" },
1566 { MVPP2_MIB_FC_RCVD, "fc_received" },
1567 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1568 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1569 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1570 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1571 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1572 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1573 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1574 { MVPP2_MIB_COLLISION, "collision" },
1575 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1576 };
1577
1578 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1579 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1580 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1581 };
1582
1583 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1584 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1585 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1586 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1587 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1588 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1589 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1590 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1591 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1592 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1593 };
1594
1595 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1596 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1597 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1598 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1599 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1600 };
1601
1602 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1603 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1604 { ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1605 { ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1606 { ETHTOOL_XDP_TX, "rx_xdp_tx", },
1607 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1608 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1609 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1610 };
1611
1612 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1613 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1614 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1615 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1616 ARRAY_SIZE(mvpp2_ethtool_xdp))
1617
1618 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1619 u8 *data)
1620 {
1621 struct mvpp2_port *port = netdev_priv(netdev);
1622 int i, q;
1623
1624 if (sset != ETH_SS_STATS)
1625 return;
1626
1627 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1628 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1629 ETH_GSTRING_LEN);
1630 data += ETH_GSTRING_LEN;
1631 }
1632
1633 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1634 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1635 ETH_GSTRING_LEN);
1636 data += ETH_GSTRING_LEN;
1637 }
1638
1639 for (q = 0; q < port->ntxqs; q++) {
1640 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1641 snprintf(data, ETH_GSTRING_LEN,
1642 mvpp2_ethtool_txq_regs[i].string, q);
1643 data += ETH_GSTRING_LEN;
1644 }
1645 }
1646
1647 for (q = 0; q < port->nrxqs; q++) {
1648 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1649 snprintf(data, ETH_GSTRING_LEN,
1650 mvpp2_ethtool_rxq_regs[i].string,
1651 q);
1652 data += ETH_GSTRING_LEN;
1653 }
1654 }
1655
1656 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
1657 strscpy(data, mvpp2_ethtool_xdp[i].string,
1658 ETH_GSTRING_LEN);
1659 data += ETH_GSTRING_LEN;
1660 }
1661 }
1662
1663 static void
1664 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
1665 {
1666 unsigned int start;
1667 unsigned int cpu;
1668
1669 /* Gather XDP Statistics */
1670 for_each_possible_cpu(cpu) {
1671 struct mvpp2_pcpu_stats *cpu_stats;
1672 u64 xdp_redirect;
1673 u64 xdp_pass;
1674 u64 xdp_drop;
1675 u64 xdp_xmit;
1676 u64 xdp_xmit_err;
1677 u64 xdp_tx;
1678 u64 xdp_tx_err;
1679
1680 cpu_stats = per_cpu_ptr(port->stats, cpu);
1681 do {
1682 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
1683 xdp_redirect = cpu_stats->xdp_redirect;
1684 xdp_pass = cpu_stats->xdp_pass;
1685 xdp_drop = cpu_stats->xdp_drop;
1686 xdp_xmit = cpu_stats->xdp_xmit;
1687 xdp_xmit_err = cpu_stats->xdp_xmit_err;
1688 xdp_tx = cpu_stats->xdp_tx;
1689 xdp_tx_err = cpu_stats->xdp_tx_err;
1690 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
1691
1692 xdp_stats->xdp_redirect += xdp_redirect;
1693 xdp_stats->xdp_pass += xdp_pass;
1694 xdp_stats->xdp_drop += xdp_drop;
1695 xdp_stats->xdp_xmit += xdp_xmit;
1696 xdp_stats->xdp_xmit_err += xdp_xmit_err;
1697 xdp_stats->xdp_tx += xdp_tx;
1698 xdp_stats->xdp_tx_err += xdp_tx_err;
1699 }
1700 }
1701
1702 static void mvpp2_read_stats(struct mvpp2_port *port)
1703 {
1704 struct mvpp2_pcpu_stats xdp_stats = {};
1705 const struct mvpp2_ethtool_counter *s;
1706 u64 *pstats;
1707 int i, q;
1708
1709 pstats = port->ethtool_stats;
1710
1711 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
1712 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
1713
1714 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
1715 *pstats++ += mvpp2_read(port->priv,
1716 mvpp2_ethtool_port_regs[i].offset +
1717 4 * port->id);
1718
1719 for (q = 0; q < port->ntxqs; q++)
1720 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
1721 *pstats++ += mvpp2_read_index(port->priv,
1722 MVPP22_CTRS_TX_CTR(port->id, q),
1723 mvpp2_ethtool_txq_regs[i].offset);
1724
1725 /* Rxqs are numbered from 0 from the user standpoint, but not from the
1726 * driver's. We need to add the port->first_rxq offset.
1727 */
1728 for (q = 0; q < port->nrxqs; q++)
1729 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
1730 *pstats++ += mvpp2_read_index(port->priv,
1731 port->first_rxq + q,
1732 mvpp2_ethtool_rxq_regs[i].offset);
1733
1734 /* Gather XDP Statistics */
1735 mvpp2_get_xdp_stats(port, &xdp_stats);
1736
1737 for (i = 0, s = mvpp2_ethtool_xdp;
1738 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
1739 s++, i++) {
1740 switch (s->offset) {
1741 case ETHTOOL_XDP_REDIRECT:
1742 *pstats++ = xdp_stats.xdp_redirect;
1743 break;
1744 case ETHTOOL_XDP_PASS:
1745 *pstats++ = xdp_stats.xdp_pass;
1746 break;
1747 case ETHTOOL_XDP_DROP:
1748 *pstats++ = xdp_stats.xdp_drop;
1749 break;
1750 case ETHTOOL_XDP_TX:
1751 *pstats++ = xdp_stats.xdp_tx;
1752 break;
1753 case ETHTOOL_XDP_TX_ERR:
1754 *pstats++ = xdp_stats.xdp_tx_err;
1755 break;
1756 case ETHTOOL_XDP_XMIT:
1757 *pstats++ = xdp_stats.xdp_xmit;
1758 break;
1759 case ETHTOOL_XDP_XMIT_ERR:
1760 *pstats++ = xdp_stats.xdp_xmit_err;
1761 break;
1762 }
1763 }
1764 }
1765
1766 static void mvpp2_gather_hw_statistics(struct work_struct *work)
1767 {
1768 struct delayed_work *del_work = to_delayed_work(work);
1769 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1770 stats_work);
1771
1772 mutex_lock(&port->gather_stats_lock);
1773
1774 mvpp2_read_stats(port);
1775
1776 /* No need to read again the counters right after this function if it
1777 * was called asynchronously by the user (ie. use of ethtool).
1778 */
1779 cancel_delayed_work(&port->stats_work);
1780 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
1781 MVPP2_MIB_COUNTERS_STATS_DELAY);
1782
1783 mutex_unlock(&port->gather_stats_lock);
1784 }
1785
1786 static void mvpp2_ethtool_get_stats(struct net_device *dev,
1787 struct ethtool_stats *stats, u64 *data)
1788 {
1789 struct mvpp2_port *port = netdev_priv(dev);
1790
1791 /* Update statistics for the given port, then take the lock to avoid
1792 * concurrent accesses on the ethtool_stats structure during its copy.
1793 */
1794 mvpp2_gather_hw_statistics(&port->stats_work.work);
1795
1796 mutex_lock(&port->gather_stats_lock);
1797 memcpy(data, port->ethtool_stats,
1798 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
1799 mutex_unlock(&port->gather_stats_lock);
1800 }
1801
1802 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1803 {
1804 struct mvpp2_port *port = netdev_priv(dev);
1805
1806 if (sset == ETH_SS_STATS)
1807 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
1808
1809 return -EOPNOTSUPP;
1810 }
1811
1812 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
1813 {
1814 u32 val;
1815
1816 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
1817 MVPP2_GMAC_PORT_RESET_MASK;
1818 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1819
1820 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
1821 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
1822 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1823 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1824 }
1825 }
1826
1827 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
1828 {
1829 struct mvpp2 *priv = port->priv;
1830 void __iomem *mpcs, *xpcs;
1831 u32 val;
1832
1833 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1834 return;
1835
1836 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1837 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1838
1839 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1840 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1841 val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
1842 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1843
1844 val = readl(xpcs + MVPP22_XPCS_CFG0);
1845 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1846 }
1847
1848 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
1849 {
1850 struct mvpp2 *priv = port->priv;
1851 void __iomem *mpcs, *xpcs;
1852 u32 val;
1853
1854 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1855 return;
1856
1857 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1858 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1859
1860 switch (port->phy_interface) {
1861 case PHY_INTERFACE_MODE_10GBASER:
1862 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1863 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
1864 MAC_CLK_RESET_SD_TX;
1865 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1866 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1867 break;
1868 case PHY_INTERFACE_MODE_XAUI:
1869 case PHY_INTERFACE_MODE_RXAUI:
1870 val = readl(xpcs + MVPP22_XPCS_CFG0);
1871 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1872 break;
1873 default:
1874 break;
1875 }
1876 }
1877
1878 /* Change maximum receive size of the port */
1879 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1880 {
1881 u32 val;
1882
1883 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1884 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1885 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1886 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1887 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1888 }
1889
1890 /* Change maximum receive size of the port */
1891 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1892 {
1893 u32 val;
1894
1895 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1896 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1897 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1898 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
1899 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1900 }
1901
1902 /* Set defaults to the MVPP2 port */
1903 static void mvpp2_defaults_set(struct mvpp2_port *port)
1904 {
1905 int tx_port_num, val, queue, lrxq;
1906
1907 if (port->priv->hw_version == MVPP21) {
1908 /* Update TX FIFO MIN Threshold */
1909 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1910 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1911 /* Min. TX threshold must be less than minimal packet length */
1912 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1913 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1914 }
1915
1916 /* Disable Legacy WRR, Disable EJP, Release from reset */
1917 tx_port_num = mvpp2_egress_port(port);
1918 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1919 tx_port_num);
1920 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1921
1922 /* Set TXQ scheduling to Round-Robin */
1923 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1924
1925 /* Close bandwidth for all queues */
1926 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
1927 mvpp2_write(port->priv,
1928 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
1929
1930 /* Set refill period to 1 usec, refill tokens
1931 * and bucket size to maximum
1932 */
1933 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1934 port->priv->tclk / USEC_PER_SEC);
1935 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1936 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1937 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1938 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1939 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1940 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1941 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1942
1943 /* Set MaximumLowLatencyPacketSize value to 256 */
1944 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1945 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1946 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1947
1948 /* Enable Rx cache snoop */
1949 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1950 queue = port->rxqs[lrxq]->id;
1951 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1952 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1953 MVPP2_SNOOP_BUF_HDR_MASK;
1954 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1955 }
1956
1957 /* At default, mask all interrupts to all present cpus */
1958 mvpp2_interrupts_disable(port);
1959 }
1960
1961 /* Enable/disable receiving packets */
1962 static void mvpp2_ingress_enable(struct mvpp2_port *port)
1963 {
1964 u32 val;
1965 int lrxq, queue;
1966
1967 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1968 queue = port->rxqs[lrxq]->id;
1969 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1970 val &= ~MVPP2_RXQ_DISABLE_MASK;
1971 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1972 }
1973 }
1974
1975 static void mvpp2_ingress_disable(struct mvpp2_port *port)
1976 {
1977 u32 val;
1978 int lrxq, queue;
1979
1980 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1981 queue = port->rxqs[lrxq]->id;
1982 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1983 val |= MVPP2_RXQ_DISABLE_MASK;
1984 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1985 }
1986 }
1987
1988 /* Enable transmit via physical egress queue
1989 * - HW starts take descriptors from DRAM
1990 */
1991 static void mvpp2_egress_enable(struct mvpp2_port *port)
1992 {
1993 u32 qmap;
1994 int queue;
1995 int tx_port_num = mvpp2_egress_port(port);
1996
1997 /* Enable all initialized TXs. */
1998 qmap = 0;
1999 for (queue = 0; queue < port->ntxqs; queue++) {
2000 struct mvpp2_tx_queue *txq = port->txqs[queue];
2001
2002 if (txq->descs)
2003 qmap |= (1 << queue);
2004 }
2005
2006 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2007 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2008 }
2009
2010 /* Disable transmit via physical egress queue
2011 * - HW doesn't take descriptors from DRAM
2012 */
2013 static void mvpp2_egress_disable(struct mvpp2_port *port)
2014 {
2015 u32 reg_data;
2016 int delay;
2017 int tx_port_num = mvpp2_egress_port(port);
2018
2019 /* Issue stop command for active channels only */
2020 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2021 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2022 MVPP2_TXP_SCHED_ENQ_MASK;
2023 if (reg_data != 0)
2024 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2025 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2026
2027 /* Wait for all Tx activity to terminate. */
2028 delay = 0;
2029 do {
2030 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2031 netdev_warn(port->dev,
2032 "Tx stop timed out, status=0x%08x\n",
2033 reg_data);
2034 break;
2035 }
2036 mdelay(1);
2037 delay++;
2038
2039 /* Check port TX Command register that all
2040 * Tx queues are stopped
2041 */
2042 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2043 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2044 }
2045
2046 /* Rx descriptors helper methods */
2047
2048 /* Get number of Rx descriptors occupied by received packets */
2049 static inline int
2050 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2051 {
2052 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2053
2054 return val & MVPP2_RXQ_OCCUPIED_MASK;
2055 }
2056
2057 /* Update Rx queue status with the number of occupied and available
2058 * Rx descriptor slots.
2059 */
2060 static inline void
2061 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2062 int used_count, int free_count)
2063 {
2064 /* Decrement the number of used descriptors and increment count
2065 * increment the number of free descriptors.
2066 */
2067 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2068
2069 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2070 }
2071
2072 /* Get pointer to next RX descriptor to be processed by SW */
2073 static inline struct mvpp2_rx_desc *
2074 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2075 {
2076 int rx_desc = rxq->next_desc_to_proc;
2077
2078 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2079 prefetch(rxq->descs + rxq->next_desc_to_proc);
2080 return rxq->descs + rx_desc;
2081 }
2082
2083 /* Set rx queue offset */
2084 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2085 int prxq, int offset)
2086 {
2087 u32 val;
2088
2089 /* Convert offset from bytes to units of 32 bytes */
2090 offset = offset >> 5;
2091
2092 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2093 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2094
2095 /* Offset is in */
2096 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2097 MVPP2_RXQ_PACKET_OFFSET_MASK);
2098
2099 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2100 }
2101
2102 /* Tx descriptors helper methods */
2103
2104 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2105 static struct mvpp2_tx_desc *
2106 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2107 {
2108 int tx_desc = txq->next_desc_to_proc;
2109
2110 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2111 return txq->descs + tx_desc;
2112 }
2113
2114 /* Update HW with number of aggregated Tx descriptors to be sent
2115 *
2116 * Called only from mvpp2_tx(), so migration is disabled, using
2117 * smp_processor_id() is OK.
2118 */
2119 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2120 {
2121 /* aggregated access - relevant TXQ number is written in TX desc */
2122 mvpp2_thread_write(port->priv,
2123 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2124 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2125 }
2126
2127 /* Check if there are enough free descriptors in aggregated txq.
2128 * If not, update the number of occupied descriptors and repeat the check.
2129 *
2130 * Called only from mvpp2_tx(), so migration is disabled, using
2131 * smp_processor_id() is OK.
2132 */
2133 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2134 struct mvpp2_tx_queue *aggr_txq, int num)
2135 {
2136 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2137 /* Update number of occupied aggregated Tx descriptors */
2138 unsigned int thread =
2139 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2140 u32 val = mvpp2_read_relaxed(port->priv,
2141 MVPP2_AGGR_TXQ_STATUS_REG(thread));
2142
2143 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2144
2145 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2146 return -ENOMEM;
2147 }
2148 return 0;
2149 }
2150
2151 /* Reserved Tx descriptors allocation request
2152 *
2153 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2154 * only by mvpp2_tx(), so migration is disabled, using
2155 * smp_processor_id() is OK.
2156 */
2157 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2158 struct mvpp2_tx_queue *txq, int num)
2159 {
2160 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2161 struct mvpp2 *priv = port->priv;
2162 u32 val;
2163
2164 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2165 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2166
2167 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2168
2169 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2170 }
2171
2172 /* Check if there are enough reserved descriptors for transmission.
2173 * If not, request chunk of reserved descriptors and check again.
2174 */
2175 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2176 struct mvpp2_tx_queue *txq,
2177 struct mvpp2_txq_pcpu *txq_pcpu,
2178 int num)
2179 {
2180 int req, desc_count;
2181 unsigned int thread;
2182
2183 if (txq_pcpu->reserved_num >= num)
2184 return 0;
2185
2186 /* Not enough descriptors reserved! Update the reserved descriptor
2187 * count and check again.
2188 */
2189
2190 desc_count = 0;
2191 /* Compute total of used descriptors */
2192 for (thread = 0; thread < port->priv->nthreads; thread++) {
2193 struct mvpp2_txq_pcpu *txq_pcpu_aux;
2194
2195 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2196 desc_count += txq_pcpu_aux->count;
2197 desc_count += txq_pcpu_aux->reserved_num;
2198 }
2199
2200 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2201 desc_count += req;
2202
2203 if (desc_count >
2204 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2205 return -ENOMEM;
2206
2207 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2208
2209 /* OK, the descriptor could have been updated: check again. */
2210 if (txq_pcpu->reserved_num < num)
2211 return -ENOMEM;
2212 return 0;
2213 }
2214
2215 /* Release the last allocated Tx descriptor. Useful to handle DMA
2216 * mapping failures in the Tx path.
2217 */
2218 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2219 {
2220 if (txq->next_desc_to_proc == 0)
2221 txq->next_desc_to_proc = txq->last_desc - 1;
2222 else
2223 txq->next_desc_to_proc--;
2224 }
2225
2226 /* Set Tx descriptors fields relevant for CSUM calculation */
2227 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2228 int ip_hdr_len, int l4_proto)
2229 {
2230 u32 command;
2231
2232 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2233 * G_L4_chk, L4_type required only for checksum calculation
2234 */
2235 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2236 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2237 command |= MVPP2_TXD_IP_CSUM_DISABLE;
2238
2239 if (l3_proto == htons(ETH_P_IP)) {
2240 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
2241 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
2242 } else {
2243 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
2244 }
2245
2246 if (l4_proto == IPPROTO_TCP) {
2247 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
2248 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2249 } else if (l4_proto == IPPROTO_UDP) {
2250 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
2251 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2252 } else {
2253 command |= MVPP2_TXD_L4_CSUM_NOT;
2254 }
2255
2256 return command;
2257 }
2258
2259 /* Get number of sent descriptors and decrement counter.
2260 * The number of sent descriptors is returned.
2261 * Per-thread access
2262 *
2263 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2264 * (migration disabled) and from the TX completion tasklet (migration
2265 * disabled) so using smp_processor_id() is OK.
2266 */
2267 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2268 struct mvpp2_tx_queue *txq)
2269 {
2270 u32 val;
2271
2272 /* Reading status reg resets transmitted descriptor counter */
2273 val = mvpp2_thread_read_relaxed(port->priv,
2274 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2275 MVPP2_TXQ_SENT_REG(txq->id));
2276
2277 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2278 MVPP2_TRANSMITTED_COUNT_OFFSET;
2279 }
2280
2281 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2282 * disabled, therefore using smp_processor_id() is OK.
2283 */
2284 static void mvpp2_txq_sent_counter_clear(void *arg)
2285 {
2286 struct mvpp2_port *port = arg;
2287 int queue;
2288
2289 /* If the thread isn't used, don't do anything */
2290 if (smp_processor_id() > port->priv->nthreads)
2291 return;
2292
2293 for (queue = 0; queue < port->ntxqs; queue++) {
2294 int id = port->txqs[queue]->id;
2295
2296 mvpp2_thread_read(port->priv,
2297 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2298 MVPP2_TXQ_SENT_REG(id));
2299 }
2300 }
2301
2302 /* Set max sizes for Tx queues */
2303 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2304 {
2305 u32 val, size, mtu;
2306 int txq, tx_port_num;
2307
2308 mtu = port->pkt_size * 8;
2309 if (mtu > MVPP2_TXP_MTU_MAX)
2310 mtu = MVPP2_TXP_MTU_MAX;
2311
2312 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2313 mtu = 3 * mtu;
2314
2315 /* Indirect access to registers */
2316 tx_port_num = mvpp2_egress_port(port);
2317 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2318
2319 /* Set MTU */
2320 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2321 val &= ~MVPP2_TXP_MTU_MAX;
2322 val |= mtu;
2323 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2324
2325 /* TXP token size and all TXQs token size must be larger that MTU */
2326 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2327 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2328 if (size < mtu) {
2329 size = mtu;
2330 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2331 val |= size;
2332 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2333 }
2334
2335 for (txq = 0; txq < port->ntxqs; txq++) {
2336 val = mvpp2_read(port->priv,
2337 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2338 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2339
2340 if (size < mtu) {
2341 size = mtu;
2342 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2343 val |= size;
2344 mvpp2_write(port->priv,
2345 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2346 val);
2347 }
2348 }
2349 }
2350
2351 /* Set the number of packets that will be received before Rx interrupt
2352 * will be generated by HW.
2353 */
2354 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2355 struct mvpp2_rx_queue *rxq)
2356 {
2357 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2358
2359 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2360 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2361
2362 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2363 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2364 rxq->pkts_coal);
2365
2366 put_cpu();
2367 }
2368
2369 /* For some reason in the LSP this is done on each CPU. Why ? */
2370 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2371 struct mvpp2_tx_queue *txq)
2372 {
2373 unsigned int thread;
2374 u32 val;
2375
2376 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2377 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2378
2379 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2380 /* PKT-coalescing registers are per-queue + per-thread */
2381 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2382 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2383 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2384 }
2385 }
2386
2387 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2388 {
2389 u64 tmp = (u64)clk_hz * usec;
2390
2391 do_div(tmp, USEC_PER_SEC);
2392
2393 return tmp > U32_MAX ? U32_MAX : tmp;
2394 }
2395
2396 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2397 {
2398 u64 tmp = (u64)cycles * USEC_PER_SEC;
2399
2400 do_div(tmp, clk_hz);
2401
2402 return tmp > U32_MAX ? U32_MAX : tmp;
2403 }
2404
2405 /* Set the time delay in usec before Rx interrupt */
2406 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2407 struct mvpp2_rx_queue *rxq)
2408 {
2409 unsigned long freq = port->priv->tclk;
2410 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2411
2412 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2413 rxq->time_coal =
2414 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2415
2416 /* re-evaluate to get actual register value */
2417 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2418 }
2419
2420 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2421 }
2422
2423 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2424 {
2425 unsigned long freq = port->priv->tclk;
2426 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2427
2428 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2429 port->tx_time_coal =
2430 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2431
2432 /* re-evaluate to get actual register value */
2433 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2434 }
2435
2436 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2437 }
2438
2439 /* Free Tx queue skbuffs */
2440 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2441 struct mvpp2_tx_queue *txq,
2442 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2443 {
2444 struct xdp_frame_bulk bq;
2445 int i;
2446
2447 xdp_frame_bulk_init(&bq);
2448
2449 rcu_read_lock(); /* need for xdp_return_frame_bulk */
2450
2451 for (i = 0; i < num; i++) {
2452 struct mvpp2_txq_pcpu_buf *tx_buf =
2453 txq_pcpu->buffs + txq_pcpu->txq_get_index;
2454
2455 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2456 tx_buf->type != MVPP2_TYPE_XDP_TX)
2457 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2458 tx_buf->size, DMA_TO_DEVICE);
2459 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2460 dev_kfree_skb_any(tx_buf->skb);
2461 else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2462 tx_buf->type == MVPP2_TYPE_XDP_NDO)
2463 xdp_return_frame_bulk(tx_buf->xdpf, &bq);
2464
2465 mvpp2_txq_inc_get(txq_pcpu);
2466 }
2467 xdp_flush_frame_bulk(&bq);
2468
2469 rcu_read_unlock();
2470 }
2471
2472 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2473 u32 cause)
2474 {
2475 int queue = fls(cause) - 1;
2476
2477 return port->rxqs[queue];
2478 }
2479
2480 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2481 u32 cause)
2482 {
2483 int queue = fls(cause) - 1;
2484
2485 return port->txqs[queue];
2486 }
2487
2488 /* Handle end of transmission */
2489 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2490 struct mvpp2_txq_pcpu *txq_pcpu)
2491 {
2492 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2493 int tx_done;
2494
2495 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2496 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2497
2498 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2499 if (!tx_done)
2500 return;
2501 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2502
2503 txq_pcpu->count -= tx_done;
2504
2505 if (netif_tx_queue_stopped(nq))
2506 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2507 netif_tx_wake_queue(nq);
2508 }
2509
2510 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2511 unsigned int thread)
2512 {
2513 struct mvpp2_tx_queue *txq;
2514 struct mvpp2_txq_pcpu *txq_pcpu;
2515 unsigned int tx_todo = 0;
2516
2517 while (cause) {
2518 txq = mvpp2_get_tx_queue(port, cause);
2519 if (!txq)
2520 break;
2521
2522 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2523
2524 if (txq_pcpu->count) {
2525 mvpp2_txq_done(port, txq, txq_pcpu);
2526 tx_todo += txq_pcpu->count;
2527 }
2528
2529 cause &= ~(1 << txq->log_id);
2530 }
2531 return tx_todo;
2532 }
2533
2534 /* Rx/Tx queue initialization/cleanup methods */
2535
2536 /* Allocate and initialize descriptors for aggr TXQ */
2537 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2538 struct mvpp2_tx_queue *aggr_txq,
2539 unsigned int thread, struct mvpp2 *priv)
2540 {
2541 u32 txq_dma;
2542
2543 /* Allocate memory for TX descriptors */
2544 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2545 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2546 &aggr_txq->descs_dma, GFP_KERNEL);
2547 if (!aggr_txq->descs)
2548 return -ENOMEM;
2549
2550 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2551
2552 /* Aggr TXQ no reset WA */
2553 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2554 MVPP2_AGGR_TXQ_INDEX_REG(thread));
2555
2556 /* Set Tx descriptors queue starting address indirect
2557 * access
2558 */
2559 if (priv->hw_version == MVPP21)
2560 txq_dma = aggr_txq->descs_dma;
2561 else
2562 txq_dma = aggr_txq->descs_dma >>
2563 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2564
2565 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2566 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2567 MVPP2_AGGR_TXQ_SIZE);
2568
2569 return 0;
2570 }
2571
2572 /* Create a specified Rx queue */
2573 static int mvpp2_rxq_init(struct mvpp2_port *port,
2574 struct mvpp2_rx_queue *rxq)
2575 {
2576 struct mvpp2 *priv = port->priv;
2577 unsigned int thread;
2578 u32 rxq_dma;
2579 int err;
2580
2581 rxq->size = port->rx_ring_size;
2582
2583 /* Allocate memory for RX descriptors */
2584 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2585 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2586 &rxq->descs_dma, GFP_KERNEL);
2587 if (!rxq->descs)
2588 return -ENOMEM;
2589
2590 rxq->last_desc = rxq->size - 1;
2591
2592 /* Zero occupied and non-occupied counters - direct access */
2593 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2594
2595 /* Set Rx descriptors queue starting address - indirect access */
2596 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2597 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2598 if (port->priv->hw_version == MVPP21)
2599 rxq_dma = rxq->descs_dma;
2600 else
2601 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2602 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2603 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2604 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2605 put_cpu();
2606
2607 /* Set Offset */
2608 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2609
2610 /* Set coalescing pkts and time */
2611 mvpp2_rx_pkts_coal_set(port, rxq);
2612 mvpp2_rx_time_coal_set(port, rxq);
2613
2614 /* Add number of descriptors ready for receiving packets */
2615 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2616
2617 if (priv->percpu_pools) {
2618 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id, 0);
2619 if (err < 0)
2620 goto err_free_dma;
2621
2622 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id, 0);
2623 if (err < 0)
2624 goto err_unregister_rxq_short;
2625
2626 /* Every RXQ has a pool for short and another for long packets */
2627 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
2628 MEM_TYPE_PAGE_POOL,
2629 priv->page_pool[rxq->logic_rxq]);
2630 if (err < 0)
2631 goto err_unregister_rxq_long;
2632
2633 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
2634 MEM_TYPE_PAGE_POOL,
2635 priv->page_pool[rxq->logic_rxq +
2636 port->nrxqs]);
2637 if (err < 0)
2638 goto err_unregister_mem_rxq_short;
2639 }
2640
2641 return 0;
2642
2643 err_unregister_mem_rxq_short:
2644 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
2645 err_unregister_rxq_long:
2646 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2647 err_unregister_rxq_short:
2648 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2649 err_free_dma:
2650 dma_free_coherent(port->dev->dev.parent,
2651 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2652 rxq->descs, rxq->descs_dma);
2653 return err;
2654 }
2655
2656 /* Push packets received by the RXQ to BM pool */
2657 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2658 struct mvpp2_rx_queue *rxq)
2659 {
2660 int rx_received, i;
2661
2662 rx_received = mvpp2_rxq_received(port, rxq->id);
2663 if (!rx_received)
2664 return;
2665
2666 for (i = 0; i < rx_received; i++) {
2667 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2668 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2669 int pool;
2670
2671 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2672 MVPP2_RXD_BM_POOL_ID_OFFS;
2673
2674 mvpp2_bm_pool_put(port, pool,
2675 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2676 mvpp2_rxdesc_cookie_get(port, rx_desc));
2677 }
2678 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2679 }
2680
2681 /* Cleanup Rx queue */
2682 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2683 struct mvpp2_rx_queue *rxq)
2684 {
2685 unsigned int thread;
2686
2687 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
2688 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2689
2690 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
2691 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2692
2693 mvpp2_rxq_drop_pkts(port, rxq);
2694
2695 if (rxq->descs)
2696 dma_free_coherent(port->dev->dev.parent,
2697 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2698 rxq->descs,
2699 rxq->descs_dma);
2700
2701 rxq->descs = NULL;
2702 rxq->last_desc = 0;
2703 rxq->next_desc_to_proc = 0;
2704 rxq->descs_dma = 0;
2705
2706 /* Clear Rx descriptors queue starting address and size;
2707 * free descriptor number
2708 */
2709 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2710 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2711 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2712 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2713 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
2714 put_cpu();
2715 }
2716
2717 /* Create and initialize a Tx queue */
2718 static int mvpp2_txq_init(struct mvpp2_port *port,
2719 struct mvpp2_tx_queue *txq)
2720 {
2721 u32 val;
2722 unsigned int thread;
2723 int desc, desc_per_txq, tx_port_num;
2724 struct mvpp2_txq_pcpu *txq_pcpu;
2725
2726 txq->size = port->tx_ring_size;
2727
2728 /* Allocate memory for Tx descriptors */
2729 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2730 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2731 &txq->descs_dma, GFP_KERNEL);
2732 if (!txq->descs)
2733 return -ENOMEM;
2734
2735 txq->last_desc = txq->size - 1;
2736
2737 /* Set Tx descriptors queue starting address - indirect access */
2738 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2739 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2740 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
2741 txq->descs_dma);
2742 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
2743 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2744 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2745 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
2746 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2747 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
2748 val &= ~MVPP2_TXQ_PENDING_MASK;
2749 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
2750
2751 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2752 * for each existing TXQ.
2753 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
2754 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
2755 */
2756 desc_per_txq = 16;
2757 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2758 (txq->log_id * desc_per_txq);
2759
2760 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
2761 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2762 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
2763 put_cpu();
2764
2765 /* WRR / EJP configuration - indirect access */
2766 tx_port_num = mvpp2_egress_port(port);
2767 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2768
2769 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2770 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2771 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2772 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2773 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2774
2775 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2776 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2777 val);
2778
2779 for (thread = 0; thread < port->priv->nthreads; thread++) {
2780 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2781 txq_pcpu->size = txq->size;
2782 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2783 sizeof(*txq_pcpu->buffs),
2784 GFP_KERNEL);
2785 if (!txq_pcpu->buffs)
2786 return -ENOMEM;
2787
2788 txq_pcpu->count = 0;
2789 txq_pcpu->reserved_num = 0;
2790 txq_pcpu->txq_put_index = 0;
2791 txq_pcpu->txq_get_index = 0;
2792 txq_pcpu->tso_headers = NULL;
2793
2794 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2795 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2796
2797 txq_pcpu->tso_headers =
2798 dma_alloc_coherent(port->dev->dev.parent,
2799 txq_pcpu->size * TSO_HEADER_SIZE,
2800 &txq_pcpu->tso_headers_dma,
2801 GFP_KERNEL);
2802 if (!txq_pcpu->tso_headers)
2803 return -ENOMEM;
2804 }
2805
2806 return 0;
2807 }
2808
2809 /* Free allocated TXQ resources */
2810 static void mvpp2_txq_deinit(struct mvpp2_port *port,
2811 struct mvpp2_tx_queue *txq)
2812 {
2813 struct mvpp2_txq_pcpu *txq_pcpu;
2814 unsigned int thread;
2815
2816 for (thread = 0; thread < port->priv->nthreads; thread++) {
2817 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2818 kfree(txq_pcpu->buffs);
2819
2820 if (txq_pcpu->tso_headers)
2821 dma_free_coherent(port->dev->dev.parent,
2822 txq_pcpu->size * TSO_HEADER_SIZE,
2823 txq_pcpu->tso_headers,
2824 txq_pcpu->tso_headers_dma);
2825
2826 txq_pcpu->tso_headers = NULL;
2827 }
2828
2829 if (txq->descs)
2830 dma_free_coherent(port->dev->dev.parent,
2831 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2832 txq->descs, txq->descs_dma);
2833
2834 txq->descs = NULL;
2835 txq->last_desc = 0;
2836 txq->next_desc_to_proc = 0;
2837 txq->descs_dma = 0;
2838
2839 /* Set minimum bandwidth for disabled TXQs */
2840 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
2841
2842 /* Set Tx descriptors queue starting address and size */
2843 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2844 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2845 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2846 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
2847 put_cpu();
2848 }
2849
2850 /* Cleanup Tx ports */
2851 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2852 {
2853 struct mvpp2_txq_pcpu *txq_pcpu;
2854 int delay, pending;
2855 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2856 u32 val;
2857
2858 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2859 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
2860 val |= MVPP2_TXQ_DRAIN_EN_MASK;
2861 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2862
2863 /* The napi queue has been stopped so wait for all packets
2864 * to be transmitted.
2865 */
2866 delay = 0;
2867 do {
2868 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2869 netdev_warn(port->dev,
2870 "port %d: cleaning queue %d timed out\n",
2871 port->id, txq->log_id);
2872 break;
2873 }
2874 mdelay(1);
2875 delay++;
2876
2877 pending = mvpp2_thread_read(port->priv, thread,
2878 MVPP2_TXQ_PENDING_REG);
2879 pending &= MVPP2_TXQ_PENDING_MASK;
2880 } while (pending);
2881
2882 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
2883 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2884 put_cpu();
2885
2886 for (thread = 0; thread < port->priv->nthreads; thread++) {
2887 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2888
2889 /* Release all packets */
2890 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2891
2892 /* Reset queue */
2893 txq_pcpu->count = 0;
2894 txq_pcpu->txq_put_index = 0;
2895 txq_pcpu->txq_get_index = 0;
2896 }
2897 }
2898
2899 /* Cleanup all Tx queues */
2900 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2901 {
2902 struct mvpp2_tx_queue *txq;
2903 int queue;
2904 u32 val;
2905
2906 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2907
2908 /* Reset Tx ports and delete Tx queues */
2909 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2910 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2911
2912 for (queue = 0; queue < port->ntxqs; queue++) {
2913 txq = port->txqs[queue];
2914 mvpp2_txq_clean(port, txq);
2915 mvpp2_txq_deinit(port, txq);
2916 }
2917
2918 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2919
2920 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2921 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2922 }
2923
2924 /* Cleanup all Rx queues */
2925 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2926 {
2927 int queue;
2928
2929 for (queue = 0; queue < port->nrxqs; queue++)
2930 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2931 }
2932
2933 /* Init all Rx queues for port */
2934 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2935 {
2936 int queue, err;
2937
2938 for (queue = 0; queue < port->nrxqs; queue++) {
2939 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2940 if (err)
2941 goto err_cleanup;
2942 }
2943 return 0;
2944
2945 err_cleanup:
2946 mvpp2_cleanup_rxqs(port);
2947 return err;
2948 }
2949
2950 /* Init all tx queues for port */
2951 static int mvpp2_setup_txqs(struct mvpp2_port *port)
2952 {
2953 struct mvpp2_tx_queue *txq;
2954 int queue, err;
2955
2956 for (queue = 0; queue < port->ntxqs; queue++) {
2957 txq = port->txqs[queue];
2958 err = mvpp2_txq_init(port, txq);
2959 if (err)
2960 goto err_cleanup;
2961
2962 /* Assign this queue to a CPU */
2963 if (queue < num_possible_cpus())
2964 netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
2965 }
2966
2967 if (port->has_tx_irqs) {
2968 mvpp2_tx_time_coal_set(port);
2969 for (queue = 0; queue < port->ntxqs; queue++) {
2970 txq = port->txqs[queue];
2971 mvpp2_tx_pkts_coal_set(port, txq);
2972 }
2973 }
2974
2975 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2976 return 0;
2977
2978 err_cleanup:
2979 mvpp2_cleanup_txqs(port);
2980 return err;
2981 }
2982
2983 /* The callback for per-port interrupt */
2984 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2985 {
2986 struct mvpp2_queue_vector *qv = dev_id;
2987
2988 mvpp2_qvec_interrupt_disable(qv);
2989
2990 napi_schedule(&qv->napi);
2991
2992 return IRQ_HANDLED;
2993 }
2994
2995 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
2996 {
2997 struct skb_shared_hwtstamps shhwtstamps;
2998 struct mvpp2_hwtstamp_queue *queue;
2999 struct sk_buff *skb;
3000 void __iomem *ptp_q;
3001 unsigned int id;
3002 u32 r0, r1, r2;
3003
3004 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3005 if (nq)
3006 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
3007
3008 queue = &port->tx_hwtstamp_queue[nq];
3009
3010 while (1) {
3011 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
3012 if (!r0)
3013 break;
3014
3015 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
3016 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
3017
3018 id = (r0 >> 1) & 31;
3019
3020 skb = queue->skb[id];
3021 queue->skb[id] = NULL;
3022 if (skb) {
3023 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
3024
3025 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
3026 skb_tstamp_tx(skb, &shhwtstamps);
3027 dev_kfree_skb_any(skb);
3028 }
3029 }
3030 }
3031
3032 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
3033 {
3034 void __iomem *ptp;
3035 u32 val;
3036
3037 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3038 val = readl(ptp + MVPP22_PTP_INT_CAUSE);
3039 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
3040 mvpp2_isr_handle_ptp_queue(port, 0);
3041 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
3042 mvpp2_isr_handle_ptp_queue(port, 1);
3043 }
3044
3045 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
3046 {
3047 struct net_device *dev = port->dev;
3048
3049 if (port->phylink) {
3050 phylink_mac_change(port->phylink, link);
3051 return;
3052 }
3053
3054 if (!netif_running(dev))
3055 return;
3056
3057 if (link) {
3058 mvpp2_interrupts_enable(port);
3059
3060 mvpp2_egress_enable(port);
3061 mvpp2_ingress_enable(port);
3062 netif_carrier_on(dev);
3063 netif_tx_wake_all_queues(dev);
3064 } else {
3065 netif_tx_stop_all_queues(dev);
3066 netif_carrier_off(dev);
3067 mvpp2_ingress_disable(port);
3068 mvpp2_egress_disable(port);
3069
3070 mvpp2_interrupts_disable(port);
3071 }
3072 }
3073
3074 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
3075 {
3076 bool link;
3077 u32 val;
3078
3079 val = readl(port->base + MVPP22_XLG_INT_STAT);
3080 if (val & MVPP22_XLG_INT_STAT_LINK) {
3081 val = readl(port->base + MVPP22_XLG_STATUS);
3082 link = (val & MVPP22_XLG_STATUS_LINK_UP);
3083 mvpp2_isr_handle_link(port, link);
3084 }
3085 }
3086
3087 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
3088 {
3089 bool link;
3090 u32 val;
3091
3092 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3093 phy_interface_mode_is_8023z(port->phy_interface) ||
3094 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3095 val = readl(port->base + MVPP22_GMAC_INT_STAT);
3096 if (val & MVPP22_GMAC_INT_STAT_LINK) {
3097 val = readl(port->base + MVPP2_GMAC_STATUS0);
3098 link = (val & MVPP2_GMAC_STATUS0_LINK_UP);
3099 mvpp2_isr_handle_link(port, link);
3100 }
3101 }
3102 }
3103
3104 /* Per-port interrupt for link status changes */
3105 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
3106 {
3107 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
3108 u32 val;
3109
3110 mvpp22_gop_mask_irq(port);
3111
3112 if (mvpp2_port_supports_xlg(port) &&
3113 mvpp2_is_xlg(port->phy_interface)) {
3114 /* Check the external status register */
3115 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
3116 if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
3117 mvpp2_isr_handle_xlg(port);
3118 if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
3119 mvpp2_isr_handle_ptp(port);
3120 } else {
3121 /* If it's not the XLG, we must be using the GMAC.
3122 * Check the summary status.
3123 */
3124 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
3125 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
3126 mvpp2_isr_handle_gmac_internal(port);
3127 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
3128 mvpp2_isr_handle_ptp(port);
3129 }
3130
3131 mvpp22_gop_unmask_irq(port);
3132 return IRQ_HANDLED;
3133 }
3134
3135 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3136 {
3137 struct net_device *dev;
3138 struct mvpp2_port *port;
3139 struct mvpp2_port_pcpu *port_pcpu;
3140 unsigned int tx_todo, cause;
3141
3142 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3143 dev = port_pcpu->dev;
3144
3145 if (!netif_running(dev))
3146 return HRTIMER_NORESTART;
3147
3148 port_pcpu->timer_scheduled = false;
3149 port = netdev_priv(dev);
3150
3151 /* Process all the Tx queues */
3152 cause = (1 << port->ntxqs) - 1;
3153 tx_todo = mvpp2_tx_done(port, cause,
3154 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3155
3156 /* Set the timer in case not all the packets were processed */
3157 if (tx_todo && !port_pcpu->timer_scheduled) {
3158 port_pcpu->timer_scheduled = true;
3159 hrtimer_forward_now(&port_pcpu->tx_done_timer,
3160 MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3161
3162 return HRTIMER_RESTART;
3163 }
3164 return HRTIMER_NORESTART;
3165 }
3166
3167 /* Main RX/TX processing routines */
3168
3169 /* Display more error info */
3170 static void mvpp2_rx_error(struct mvpp2_port *port,
3171 struct mvpp2_rx_desc *rx_desc)
3172 {
3173 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3174 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3175 char *err_str = NULL;
3176
3177 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3178 case MVPP2_RXD_ERR_CRC:
3179 err_str = "crc";
3180 break;
3181 case MVPP2_RXD_ERR_OVERRUN:
3182 err_str = "overrun";
3183 break;
3184 case MVPP2_RXD_ERR_RESOURCE:
3185 err_str = "resource";
3186 break;
3187 }
3188 if (err_str && net_ratelimit())
3189 netdev_err(port->dev,
3190 "bad rx status %08x (%s error), size=%zu\n",
3191 status, err_str, sz);
3192 }
3193
3194 /* Handle RX checksum offload */
3195 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
3196 struct sk_buff *skb)
3197 {
3198 if (((status & MVPP2_RXD_L3_IP4) &&
3199 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3200 (status & MVPP2_RXD_L3_IP6))
3201 if (((status & MVPP2_RXD_L4_UDP) ||
3202 (status & MVPP2_RXD_L4_TCP)) &&
3203 (status & MVPP2_RXD_L4_CSUM_OK)) {
3204 skb->csum = 0;
3205 skb->ip_summed = CHECKSUM_UNNECESSARY;
3206 return;
3207 }
3208
3209 skb->ip_summed = CHECKSUM_NONE;
3210 }
3211
3212 /* Allocate a new skb and add it to BM pool */
3213 static int mvpp2_rx_refill(struct mvpp2_port *port,
3214 struct mvpp2_bm_pool *bm_pool,
3215 struct page_pool *page_pool, int pool)
3216 {
3217 dma_addr_t dma_addr;
3218 phys_addr_t phys_addr;
3219 void *buf;
3220
3221 buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3222 &dma_addr, &phys_addr, GFP_ATOMIC);
3223 if (!buf)
3224 return -ENOMEM;
3225
3226 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3227
3228 return 0;
3229 }
3230
3231 /* Handle tx checksum */
3232 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3233 {
3234 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3235 int ip_hdr_len = 0;
3236 u8 l4_proto;
3237 __be16 l3_proto = vlan_get_protocol(skb);
3238
3239 if (l3_proto == htons(ETH_P_IP)) {
3240 struct iphdr *ip4h = ip_hdr(skb);
3241
3242 /* Calculate IPv4 checksum and L4 checksum */
3243 ip_hdr_len = ip4h->ihl;
3244 l4_proto = ip4h->protocol;
3245 } else if (l3_proto == htons(ETH_P_IPV6)) {
3246 struct ipv6hdr *ip6h = ipv6_hdr(skb);
3247
3248 /* Read l4_protocol from one of IPv6 extra headers */
3249 if (skb_network_header_len(skb) > 0)
3250 ip_hdr_len = (skb_network_header_len(skb) >> 2);
3251 l4_proto = ip6h->nexthdr;
3252 } else {
3253 return MVPP2_TXD_L4_CSUM_NOT;
3254 }
3255
3256 return mvpp2_txq_desc_csum(skb_network_offset(skb),
3257 l3_proto, ip_hdr_len, l4_proto);
3258 }
3259
3260 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3261 }
3262
3263 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3264 {
3265 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3266 struct mvpp2_tx_queue *aggr_txq;
3267 struct mvpp2_txq_pcpu *txq_pcpu;
3268 struct mvpp2_tx_queue *txq;
3269 struct netdev_queue *nq;
3270
3271 txq = port->txqs[txq_id];
3272 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3273 nq = netdev_get_tx_queue(port->dev, txq_id);
3274 aggr_txq = &port->priv->aggr_txqs[thread];
3275
3276 txq_pcpu->reserved_num -= nxmit;
3277 txq_pcpu->count += nxmit;
3278 aggr_txq->count += nxmit;
3279
3280 /* Enable transmit */
3281 wmb();
3282 mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3283
3284 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3285 netif_tx_stop_queue(nq);
3286
3287 /* Finalize TX processing */
3288 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3289 mvpp2_txq_done(port, txq, txq_pcpu);
3290 }
3291
3292 static int
3293 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3294 struct xdp_frame *xdpf, bool dma_map)
3295 {
3296 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3297 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3298 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3299 enum mvpp2_tx_buf_type buf_type;
3300 struct mvpp2_txq_pcpu *txq_pcpu;
3301 struct mvpp2_tx_queue *aggr_txq;
3302 struct mvpp2_tx_desc *tx_desc;
3303 struct mvpp2_tx_queue *txq;
3304 int ret = MVPP2_XDP_TX;
3305 dma_addr_t dma_addr;
3306
3307 txq = port->txqs[txq_id];
3308 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3309 aggr_txq = &port->priv->aggr_txqs[thread];
3310
3311 /* Check number of available descriptors */
3312 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3313 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3314 ret = MVPP2_XDP_DROPPED;
3315 goto out;
3316 }
3317
3318 /* Get a descriptor for the first part of the packet */
3319 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3320 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3321 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3322
3323 if (dma_map) {
3324 /* XDP_REDIRECT or AF_XDP */
3325 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3326 xdpf->len, DMA_TO_DEVICE);
3327
3328 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3329 mvpp2_txq_desc_put(txq);
3330 ret = MVPP2_XDP_DROPPED;
3331 goto out;
3332 }
3333
3334 buf_type = MVPP2_TYPE_XDP_NDO;
3335 } else {
3336 /* XDP_TX */
3337 struct page *page = virt_to_page(xdpf->data);
3338
3339 dma_addr = page_pool_get_dma_addr(page) +
3340 sizeof(*xdpf) + xdpf->headroom;
3341 dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3342 xdpf->len, DMA_BIDIRECTIONAL);
3343
3344 buf_type = MVPP2_TYPE_XDP_TX;
3345 }
3346
3347 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3348
3349 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3350 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3351
3352 out:
3353 return ret;
3354 }
3355
3356 static int
3357 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3358 {
3359 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3360 struct xdp_frame *xdpf;
3361 u16 txq_id;
3362 int ret;
3363
3364 xdpf = xdp_convert_buff_to_frame(xdp);
3365 if (unlikely(!xdpf))
3366 return MVPP2_XDP_DROPPED;
3367
3368 /* The first of the TX queues are used for XPS,
3369 * the second half for XDP_TX
3370 */
3371 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3372
3373 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3374 if (ret == MVPP2_XDP_TX) {
3375 u64_stats_update_begin(&stats->syncp);
3376 stats->tx_bytes += xdpf->len;
3377 stats->tx_packets++;
3378 stats->xdp_tx++;
3379 u64_stats_update_end(&stats->syncp);
3380
3381 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3382 } else {
3383 u64_stats_update_begin(&stats->syncp);
3384 stats->xdp_tx_err++;
3385 u64_stats_update_end(&stats->syncp);
3386 }
3387
3388 return ret;
3389 }
3390
3391 static int
3392 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3393 struct xdp_frame **frames, u32 flags)
3394 {
3395 struct mvpp2_port *port = netdev_priv(dev);
3396 int i, nxmit_byte = 0, nxmit = num_frame;
3397 struct mvpp2_pcpu_stats *stats;
3398 u16 txq_id;
3399 u32 ret;
3400
3401 if (unlikely(test_bit(0, &port->state)))
3402 return -ENETDOWN;
3403
3404 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3405 return -EINVAL;
3406
3407 /* The first of the TX queues are used for XPS,
3408 * the second half for XDP_TX
3409 */
3410 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3411
3412 for (i = 0; i < num_frame; i++) {
3413 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3414 if (ret == MVPP2_XDP_TX) {
3415 nxmit_byte += frames[i]->len;
3416 } else {
3417 xdp_return_frame_rx_napi(frames[i]);
3418 nxmit--;
3419 }
3420 }
3421
3422 if (likely(nxmit > 0))
3423 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3424
3425 stats = this_cpu_ptr(port->stats);
3426 u64_stats_update_begin(&stats->syncp);
3427 stats->tx_bytes += nxmit_byte;
3428 stats->tx_packets += nxmit;
3429 stats->xdp_xmit += nxmit;
3430 stats->xdp_xmit_err += num_frame - nxmit;
3431 u64_stats_update_end(&stats->syncp);
3432
3433 return nxmit;
3434 }
3435
3436 static int
3437 mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq,
3438 struct bpf_prog *prog, struct xdp_buff *xdp,
3439 struct page_pool *pp, struct mvpp2_pcpu_stats *stats)
3440 {
3441 unsigned int len, sync, err;
3442 struct page *page;
3443 u32 ret, act;
3444
3445 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3446 act = bpf_prog_run_xdp(prog, xdp);
3447
3448 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3449 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3450 sync = max(sync, len);
3451
3452 switch (act) {
3453 case XDP_PASS:
3454 stats->xdp_pass++;
3455 ret = MVPP2_XDP_PASS;
3456 break;
3457 case XDP_REDIRECT:
3458 err = xdp_do_redirect(port->dev, xdp, prog);
3459 if (unlikely(err)) {
3460 ret = MVPP2_XDP_DROPPED;
3461 page = virt_to_head_page(xdp->data);
3462 page_pool_put_page(pp, page, sync, true);
3463 } else {
3464 ret = MVPP2_XDP_REDIR;
3465 stats->xdp_redirect++;
3466 }
3467 break;
3468 case XDP_TX:
3469 ret = mvpp2_xdp_xmit_back(port, xdp);
3470 if (ret != MVPP2_XDP_TX) {
3471 page = virt_to_head_page(xdp->data);
3472 page_pool_put_page(pp, page, sync, true);
3473 }
3474 break;
3475 default:
3476 bpf_warn_invalid_xdp_action(act);
3477 fallthrough;
3478 case XDP_ABORTED:
3479 trace_xdp_exception(port->dev, prog, act);
3480 fallthrough;
3481 case XDP_DROP:
3482 page = virt_to_head_page(xdp->data);
3483 page_pool_put_page(pp, page, sync, true);
3484 ret = MVPP2_XDP_DROPPED;
3485 stats->xdp_drop++;
3486 break;
3487 }
3488
3489 return ret;
3490 }
3491
3492 /* Main rx processing */
3493 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3494 int rx_todo, struct mvpp2_rx_queue *rxq)
3495 {
3496 struct net_device *dev = port->dev;
3497 struct mvpp2_pcpu_stats ps = {};
3498 enum dma_data_direction dma_dir;
3499 struct bpf_prog *xdp_prog;
3500 struct xdp_buff xdp;
3501 int rx_received;
3502 int rx_done = 0;
3503 u32 xdp_ret = 0;
3504
3505 rcu_read_lock();
3506
3507 xdp_prog = READ_ONCE(port->xdp_prog);
3508
3509 /* Get number of received packets and clamp the to-do */
3510 rx_received = mvpp2_rxq_received(port, rxq->id);
3511 if (rx_todo > rx_received)
3512 rx_todo = rx_received;
3513
3514 while (rx_done < rx_todo) {
3515 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3516 struct mvpp2_bm_pool *bm_pool;
3517 struct page_pool *pp = NULL;
3518 struct sk_buff *skb;
3519 unsigned int frag_size;
3520 dma_addr_t dma_addr;
3521 phys_addr_t phys_addr;
3522 u32 rx_status, timestamp;
3523 int pool, rx_bytes, err, ret;
3524 void *data;
3525
3526 rx_done++;
3527 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3528 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3529 rx_bytes -= MVPP2_MH_SIZE;
3530 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3531 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3532 data = (void *)phys_to_virt(phys_addr);
3533
3534 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3535 MVPP2_RXD_BM_POOL_ID_OFFS;
3536 bm_pool = &port->priv->bm_pools[pool];
3537
3538 /* In case of an error, release the requested buffer pointer
3539 * to the Buffer Manager. This request process is controlled
3540 * by the hardware, and the information about the buffer is
3541 * comprised by the RX descriptor.
3542 */
3543 if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3544 goto err_drop_frame;
3545
3546 if (port->priv->percpu_pools) {
3547 pp = port->priv->page_pool[pool];
3548 dma_dir = page_pool_get_dma_dir(pp);
3549 } else {
3550 dma_dir = DMA_FROM_DEVICE;
3551 }
3552
3553 dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3554 rx_bytes + MVPP2_MH_SIZE,
3555 dma_dir);
3556
3557 /* Prefetch header */
3558 prefetch(data);
3559
3560 if (bm_pool->frag_size > PAGE_SIZE)
3561 frag_size = 0;
3562 else
3563 frag_size = bm_pool->frag_size;
3564
3565 if (xdp_prog) {
3566 xdp.data_hard_start = data;
3567 xdp.data = data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM;
3568 xdp.data_end = xdp.data + rx_bytes;
3569 xdp.frame_sz = PAGE_SIZE;
3570
3571 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3572 xdp.rxq = &rxq->xdp_rxq_short;
3573 else
3574 xdp.rxq = &rxq->xdp_rxq_long;
3575
3576 xdp_set_data_meta_invalid(&xdp);
3577
3578 ret = mvpp2_run_xdp(port, rxq, xdp_prog, &xdp, pp, &ps);
3579
3580 if (ret) {
3581 xdp_ret |= ret;
3582 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3583 if (err) {
3584 netdev_err(port->dev, "failed to refill BM pools\n");
3585 goto err_drop_frame;
3586 }
3587
3588 ps.rx_packets++;
3589 ps.rx_bytes += rx_bytes;
3590 continue;
3591 }
3592 }
3593
3594 skb = build_skb(data, frag_size);
3595 if (!skb) {
3596 netdev_warn(port->dev, "skb build failed\n");
3597 goto err_drop_frame;
3598 }
3599
3600 /* If we have RX hardware timestamping enabled, grab the
3601 * timestamp from the queue and convert.
3602 */
3603 if (mvpp22_rx_hwtstamping(port)) {
3604 timestamp = le32_to_cpu(rx_desc->pp22.timestamp);
3605 mvpp22_tai_tstamp(port->priv->tai, timestamp,
3606 skb_hwtstamps(skb));
3607 }
3608
3609 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3610 if (err) {
3611 netdev_err(port->dev, "failed to refill BM pools\n");
3612 dev_kfree_skb_any(skb);
3613 goto err_drop_frame;
3614 }
3615
3616 if (pp)
3617 page_pool_release_page(pp, virt_to_page(data));
3618 else
3619 dma_unmap_single_attrs(dev->dev.parent, dma_addr,
3620 bm_pool->buf_size, DMA_FROM_DEVICE,
3621 DMA_ATTR_SKIP_CPU_SYNC);
3622
3623 ps.rx_packets++;
3624 ps.rx_bytes += rx_bytes;
3625
3626 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
3627 skb_put(skb, rx_bytes);
3628 skb->protocol = eth_type_trans(skb, dev);
3629 mvpp2_rx_csum(port, rx_status, skb);
3630
3631 napi_gro_receive(napi, skb);
3632 continue;
3633
3634 err_drop_frame:
3635 dev->stats.rx_errors++;
3636 mvpp2_rx_error(port, rx_desc);
3637 /* Return the buffer to the pool */
3638 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3639 }
3640
3641 rcu_read_unlock();
3642
3643 if (xdp_ret & MVPP2_XDP_REDIR)
3644 xdp_do_flush_map();
3645
3646 if (ps.rx_packets) {
3647 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3648
3649 u64_stats_update_begin(&stats->syncp);
3650 stats->rx_packets += ps.rx_packets;
3651 stats->rx_bytes += ps.rx_bytes;
3652 /* xdp */
3653 stats->xdp_redirect += ps.xdp_redirect;
3654 stats->xdp_pass += ps.xdp_pass;
3655 stats->xdp_drop += ps.xdp_drop;
3656 u64_stats_update_end(&stats->syncp);
3657 }
3658
3659 /* Update Rx queue management counters */
3660 wmb();
3661 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
3662
3663 return rx_todo;
3664 }
3665
3666 static inline void
3667 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3668 struct mvpp2_tx_desc *desc)
3669 {
3670 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3671 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3672
3673 dma_addr_t buf_dma_addr =
3674 mvpp2_txdesc_dma_addr_get(port, desc);
3675 size_t buf_sz =
3676 mvpp2_txdesc_size_get(port, desc);
3677 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
3678 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
3679 buf_sz, DMA_TO_DEVICE);
3680 mvpp2_txq_desc_put(txq);
3681 }
3682
3683 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
3684 struct mvpp2_tx_desc *desc)
3685 {
3686 /* We only need to clear the low bits */
3687 if (port->priv->hw_version != MVPP21)
3688 desc->pp22.ptp_descriptor &=
3689 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
3690 }
3691
3692 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
3693 struct mvpp2_tx_desc *tx_desc,
3694 struct sk_buff *skb)
3695 {
3696 struct mvpp2_hwtstamp_queue *queue;
3697 unsigned int mtype, type, i;
3698 struct ptp_header *hdr;
3699 u64 ptpdesc;
3700
3701 if (port->priv->hw_version == MVPP21 ||
3702 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
3703 return false;
3704
3705 type = ptp_classify_raw(skb);
3706 if (!type)
3707 return false;
3708
3709 hdr = ptp_parse_header(skb, type);
3710 if (!hdr)
3711 return false;
3712
3713 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3714
3715 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
3716 MVPP22_PTP_ACTION_CAPTURE;
3717 queue = &port->tx_hwtstamp_queue[0];
3718
3719 switch (type & PTP_CLASS_VMASK) {
3720 case PTP_CLASS_V1:
3721 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
3722 break;
3723
3724 case PTP_CLASS_V2:
3725 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
3726 mtype = hdr->tsmt & 15;
3727 /* Direct PTP Sync messages to queue 1 */
3728 if (mtype == 0) {
3729 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
3730 queue = &port->tx_hwtstamp_queue[1];
3731 }
3732 break;
3733 }
3734
3735 /* Take a reference on the skb and insert into our queue */
3736 i = queue->next;
3737 queue->next = (i + 1) & 31;
3738 if (queue->skb[i])
3739 dev_kfree_skb_any(queue->skb[i]);
3740 queue->skb[i] = skb_get(skb);
3741
3742 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
3743
3744 /*
3745 * 3:0 - PTPAction
3746 * 6:4 - PTPPacketFormat
3747 * 7 - PTP_CF_WraparoundCheckEn
3748 * 9:8 - IngressTimestampSeconds[1:0]
3749 * 10 - Reserved
3750 * 11 - MACTimestampingEn
3751 * 17:12 - PTP_TimestampQueueEntryID[5:0]
3752 * 18 - PTPTimestampQueueSelect
3753 * 19 - UDPChecksumUpdateEn
3754 * 27:20 - TimestampOffset
3755 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
3756 * NTPTs, Y.1731 - L3 to timestamp entry
3757 * 35:28 - UDP Checksum Offset
3758 *
3759 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
3760 */
3761 tx_desc->pp22.ptp_descriptor &=
3762 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
3763 tx_desc->pp22.ptp_descriptor |=
3764 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
3765 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
3766 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
3767
3768 return true;
3769 }
3770
3771 /* Handle tx fragmentation processing */
3772 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
3773 struct mvpp2_tx_queue *aggr_txq,
3774 struct mvpp2_tx_queue *txq)
3775 {
3776 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3777 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3778 struct mvpp2_tx_desc *tx_desc;
3779 int i;
3780 dma_addr_t buf_dma_addr;
3781
3782 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3783 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3784 void *addr = skb_frag_address(frag);
3785
3786 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3787 mvpp2_txdesc_clear_ptp(port, tx_desc);
3788 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3789 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
3790
3791 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
3792 skb_frag_size(frag),
3793 DMA_TO_DEVICE);
3794 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
3795 mvpp2_txq_desc_put(txq);
3796 goto cleanup;
3797 }
3798
3799 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3800
3801 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
3802 /* Last descriptor */
3803 mvpp2_txdesc_cmd_set(port, tx_desc,
3804 MVPP2_TXD_L_DESC);
3805 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
3806 } else {
3807 /* Descriptor in the middle: Not First, Not Last */
3808 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3809 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3810 }
3811 }
3812
3813 return 0;
3814 cleanup:
3815 /* Release all descriptors that were used to map fragments of
3816 * this packet, as well as the corresponding DMA mappings
3817 */
3818 for (i = i - 1; i >= 0; i--) {
3819 tx_desc = txq->descs + i;
3820 tx_desc_unmap_put(port, txq, tx_desc);
3821 }
3822
3823 return -ENOMEM;
3824 }
3825
3826 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
3827 struct net_device *dev,
3828 struct mvpp2_tx_queue *txq,
3829 struct mvpp2_tx_queue *aggr_txq,
3830 struct mvpp2_txq_pcpu *txq_pcpu,
3831 int hdr_sz)
3832 {
3833 struct mvpp2_port *port = netdev_priv(dev);
3834 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3835 dma_addr_t addr;
3836
3837 mvpp2_txdesc_clear_ptp(port, tx_desc);
3838 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3839 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
3840
3841 addr = txq_pcpu->tso_headers_dma +
3842 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
3843 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
3844
3845 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
3846 MVPP2_TXD_F_DESC |
3847 MVPP2_TXD_PADDING_DISABLE);
3848 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3849 }
3850
3851 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
3852 struct net_device *dev, struct tso_t *tso,
3853 struct mvpp2_tx_queue *txq,
3854 struct mvpp2_tx_queue *aggr_txq,
3855 struct mvpp2_txq_pcpu *txq_pcpu,
3856 int sz, bool left, bool last)
3857 {
3858 struct mvpp2_port *port = netdev_priv(dev);
3859 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3860 dma_addr_t buf_dma_addr;
3861
3862 mvpp2_txdesc_clear_ptp(port, tx_desc);
3863 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3864 mvpp2_txdesc_size_set(port, tx_desc, sz);
3865
3866 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
3867 DMA_TO_DEVICE);
3868 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3869 mvpp2_txq_desc_put(txq);
3870 return -ENOMEM;
3871 }
3872
3873 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3874
3875 if (!left) {
3876 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
3877 if (last) {
3878 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
3879 return 0;
3880 }
3881 } else {
3882 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3883 }
3884
3885 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3886 return 0;
3887 }
3888
3889 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
3890 struct mvpp2_tx_queue *txq,
3891 struct mvpp2_tx_queue *aggr_txq,
3892 struct mvpp2_txq_pcpu *txq_pcpu)
3893 {
3894 struct mvpp2_port *port = netdev_priv(dev);
3895 int hdr_sz, i, len, descs = 0;
3896 struct tso_t tso;
3897
3898 /* Check number of available descriptors */
3899 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
3900 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
3901 tso_count_descs(skb)))
3902 return 0;
3903
3904 hdr_sz = tso_start(skb, &tso);
3905
3906 len = skb->len - hdr_sz;
3907 while (len > 0) {
3908 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
3909 char *hdr = txq_pcpu->tso_headers +
3910 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
3911
3912 len -= left;
3913 descs++;
3914
3915 tso_build_hdr(skb, hdr, &tso, left, len == 0);
3916 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
3917
3918 while (left > 0) {
3919 int sz = min_t(int, tso.size, left);
3920 left -= sz;
3921 descs++;
3922
3923 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
3924 txq_pcpu, sz, left, len == 0))
3925 goto release;
3926 tso_build_data(skb, &tso, sz);
3927 }
3928 }
3929
3930 return descs;
3931
3932 release:
3933 for (i = descs - 1; i >= 0; i--) {
3934 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
3935 tx_desc_unmap_put(port, txq, tx_desc);
3936 }
3937 return 0;
3938 }
3939
3940 /* Main tx processing */
3941 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
3942 {
3943 struct mvpp2_port *port = netdev_priv(dev);
3944 struct mvpp2_tx_queue *txq, *aggr_txq;
3945 struct mvpp2_txq_pcpu *txq_pcpu;
3946 struct mvpp2_tx_desc *tx_desc;
3947 dma_addr_t buf_dma_addr;
3948 unsigned long flags = 0;
3949 unsigned int thread;
3950 int frags = 0;
3951 u16 txq_id;
3952 u32 tx_cmd;
3953
3954 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3955
3956 txq_id = skb_get_queue_mapping(skb);
3957 txq = port->txqs[txq_id];
3958 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3959 aggr_txq = &port->priv->aggr_txqs[thread];
3960
3961 if (test_bit(thread, &port->priv->lock_map))
3962 spin_lock_irqsave(&port->tx_lock[thread], flags);
3963
3964 if (skb_is_gso(skb)) {
3965 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
3966 goto out;
3967 }
3968 frags = skb_shinfo(skb)->nr_frags + 1;
3969
3970 /* Check number of available descriptors */
3971 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
3972 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
3973 frags = 0;
3974 goto out;
3975 }
3976
3977 /* Get a descriptor for the first part of the packet */
3978 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3979 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
3980 !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
3981 mvpp2_txdesc_clear_ptp(port, tx_desc);
3982 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3983 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3984
3985 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
3986 skb_headlen(skb), DMA_TO_DEVICE);
3987 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3988 mvpp2_txq_desc_put(txq);
3989 frags = 0;
3990 goto out;
3991 }
3992
3993 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3994
3995 tx_cmd = mvpp2_skb_tx_csum(port, skb);
3996
3997 if (frags == 1) {
3998 /* First and Last descriptor */
3999 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
4000 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4001 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4002 } else {
4003 /* First but not Last */
4004 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
4005 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4006 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4007
4008 /* Continue with other skb fragments */
4009 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
4010 tx_desc_unmap_put(port, txq, tx_desc);
4011 frags = 0;
4012 }
4013 }
4014
4015 out:
4016 if (frags > 0) {
4017 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
4018 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
4019
4020 txq_pcpu->reserved_num -= frags;
4021 txq_pcpu->count += frags;
4022 aggr_txq->count += frags;
4023
4024 /* Enable transmit */
4025 wmb();
4026 mvpp2_aggr_txq_pend_desc_add(port, frags);
4027
4028 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
4029 netif_tx_stop_queue(nq);
4030
4031 u64_stats_update_begin(&stats->syncp);
4032 stats->tx_packets++;
4033 stats->tx_bytes += skb->len;
4034 u64_stats_update_end(&stats->syncp);
4035 } else {
4036 dev->stats.tx_dropped++;
4037 dev_kfree_skb_any(skb);
4038 }
4039
4040 /* Finalize TX processing */
4041 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
4042 mvpp2_txq_done(port, txq, txq_pcpu);
4043
4044 /* Set the timer in case not all frags were processed */
4045 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
4046 txq_pcpu->count > 0) {
4047 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
4048
4049 if (!port_pcpu->timer_scheduled) {
4050 port_pcpu->timer_scheduled = true;
4051 hrtimer_start(&port_pcpu->tx_done_timer,
4052 MVPP2_TXDONE_HRTIMER_PERIOD_NS,
4053 HRTIMER_MODE_REL_PINNED_SOFT);
4054 }
4055 }
4056
4057 if (test_bit(thread, &port->priv->lock_map))
4058 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
4059
4060 return NETDEV_TX_OK;
4061 }
4062
4063 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
4064 {
4065 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
4066 netdev_err(dev, "FCS error\n");
4067 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
4068 netdev_err(dev, "rx fifo overrun error\n");
4069 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
4070 netdev_err(dev, "tx fifo underrun error\n");
4071 }
4072
4073 static int mvpp2_poll(struct napi_struct *napi, int budget)
4074 {
4075 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
4076 int rx_done = 0;
4077 struct mvpp2_port *port = netdev_priv(napi->dev);
4078 struct mvpp2_queue_vector *qv;
4079 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4080
4081 qv = container_of(napi, struct mvpp2_queue_vector, napi);
4082
4083 /* Rx/Tx cause register
4084 *
4085 * Bits 0-15: each bit indicates received packets on the Rx queue
4086 * (bit 0 is for Rx queue 0).
4087 *
4088 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
4089 * (bit 16 is for Tx queue 0).
4090 *
4091 * Each CPU has its own Rx/Tx cause register
4092 */
4093 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
4094 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4095
4096 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4097 if (cause_misc) {
4098 mvpp2_cause_error(port->dev, cause_misc);
4099
4100 /* Clear the cause register */
4101 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
4102 mvpp2_thread_write(port->priv, thread,
4103 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
4104 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
4105 }
4106
4107 if (port->has_tx_irqs) {
4108 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4109 if (cause_tx) {
4110 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
4111 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
4112 }
4113 }
4114
4115 /* Process RX packets */
4116 cause_rx = cause_rx_tx &
4117 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
4118 cause_rx <<= qv->first_rxq;
4119 cause_rx |= qv->pending_cause_rx;
4120 while (cause_rx && budget > 0) {
4121 int count;
4122 struct mvpp2_rx_queue *rxq;
4123
4124 rxq = mvpp2_get_rx_queue(port, cause_rx);
4125 if (!rxq)
4126 break;
4127
4128 count = mvpp2_rx(port, napi, budget, rxq);
4129 rx_done += count;
4130 budget -= count;
4131 if (budget > 0) {
4132 /* Clear the bit associated to this Rx queue
4133 * so that next iteration will continue from
4134 * the next Rx queue.
4135 */
4136 cause_rx &= ~(1 << rxq->logic_rxq);
4137 }
4138 }
4139
4140 if (budget > 0) {
4141 cause_rx = 0;
4142 napi_complete_done(napi, rx_done);
4143
4144 mvpp2_qvec_interrupt_enable(qv);
4145 }
4146 qv->pending_cause_rx = cause_rx;
4147 return rx_done;
4148 }
4149
4150 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
4151 {
4152 u32 ctrl3;
4153
4154 /* Set the GMAC & XLG MAC in reset */
4155 mvpp2_mac_reset_assert(port);
4156
4157 /* Set the MPCS and XPCS in reset */
4158 mvpp22_pcs_reset_assert(port);
4159
4160 /* comphy reconfiguration */
4161 mvpp22_comphy_init(port);
4162
4163 /* gop reconfiguration */
4164 mvpp22_gop_init(port);
4165
4166 mvpp22_pcs_reset_deassert(port);
4167
4168 if (mvpp2_port_supports_xlg(port)) {
4169 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
4170 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4171
4172 if (mvpp2_is_xlg(port->phy_interface))
4173 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
4174 else
4175 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
4176
4177 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
4178 }
4179
4180 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface))
4181 mvpp2_xlg_max_rx_size_set(port);
4182 else
4183 mvpp2_gmac_max_rx_size_set(port);
4184 }
4185
4186 /* Set hw internals when starting port */
4187 static void mvpp2_start_dev(struct mvpp2_port *port)
4188 {
4189 int i;
4190
4191 mvpp2_txp_max_tx_size_set(port);
4192
4193 for (i = 0; i < port->nqvecs; i++)
4194 napi_enable(&port->qvecs[i].napi);
4195
4196 /* Enable interrupts on all threads */
4197 mvpp2_interrupts_enable(port);
4198
4199 if (port->priv->hw_version == MVPP22)
4200 mvpp22_mode_reconfigure(port);
4201
4202 if (port->phylink) {
4203 phylink_start(port->phylink);
4204 } else {
4205 mvpp2_acpi_start(port);
4206 }
4207
4208 netif_tx_start_all_queues(port->dev);
4209
4210 clear_bit(0, &port->state);
4211 }
4212
4213 /* Set hw internals when stopping port */
4214 static void mvpp2_stop_dev(struct mvpp2_port *port)
4215 {
4216 int i;
4217
4218 set_bit(0, &port->state);
4219
4220 /* Disable interrupts on all threads */
4221 mvpp2_interrupts_disable(port);
4222
4223 for (i = 0; i < port->nqvecs; i++)
4224 napi_disable(&port->qvecs[i].napi);
4225
4226 if (port->phylink)
4227 phylink_stop(port->phylink);
4228 phy_power_off(port->comphy);
4229 }
4230
4231 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4232 struct ethtool_ringparam *ring)
4233 {
4234 u16 new_rx_pending = ring->rx_pending;
4235 u16 new_tx_pending = ring->tx_pending;
4236
4237 if (ring->rx_pending == 0 || ring->tx_pending == 0)
4238 return -EINVAL;
4239
4240 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4241 new_rx_pending = MVPP2_MAX_RXD_MAX;
4242 else if (!IS_ALIGNED(ring->rx_pending, 16))
4243 new_rx_pending = ALIGN(ring->rx_pending, 16);
4244
4245 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4246 new_tx_pending = MVPP2_MAX_TXD_MAX;
4247 else if (!IS_ALIGNED(ring->tx_pending, 32))
4248 new_tx_pending = ALIGN(ring->tx_pending, 32);
4249
4250 /* The Tx ring size cannot be smaller than the minimum number of
4251 * descriptors needed for TSO.
4252 */
4253 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4254 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4255
4256 if (ring->rx_pending != new_rx_pending) {
4257 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4258 ring->rx_pending, new_rx_pending);
4259 ring->rx_pending = new_rx_pending;
4260 }
4261
4262 if (ring->tx_pending != new_tx_pending) {
4263 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4264 ring->tx_pending, new_tx_pending);
4265 ring->tx_pending = new_tx_pending;
4266 }
4267
4268 return 0;
4269 }
4270
4271 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4272 {
4273 u32 mac_addr_l, mac_addr_m, mac_addr_h;
4274
4275 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4276 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4277 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4278 addr[0] = (mac_addr_h >> 24) & 0xFF;
4279 addr[1] = (mac_addr_h >> 16) & 0xFF;
4280 addr[2] = (mac_addr_h >> 8) & 0xFF;
4281 addr[3] = mac_addr_h & 0xFF;
4282 addr[4] = mac_addr_m & 0xFF;
4283 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4284 }
4285
4286 static int mvpp2_irqs_init(struct mvpp2_port *port)
4287 {
4288 int err, i;
4289
4290 for (i = 0; i < port->nqvecs; i++) {
4291 struct mvpp2_queue_vector *qv = port->qvecs + i;
4292
4293 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4294 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4295 if (!qv->mask) {
4296 err = -ENOMEM;
4297 goto err;
4298 }
4299
4300 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4301 }
4302
4303 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4304 if (err)
4305 goto err;
4306
4307 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4308 unsigned int cpu;
4309
4310 for_each_present_cpu(cpu) {
4311 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4312 qv->sw_thread_id)
4313 cpumask_set_cpu(cpu, qv->mask);
4314 }
4315
4316 irq_set_affinity_hint(qv->irq, qv->mask);
4317 }
4318 }
4319
4320 return 0;
4321 err:
4322 for (i = 0; i < port->nqvecs; i++) {
4323 struct mvpp2_queue_vector *qv = port->qvecs + i;
4324
4325 irq_set_affinity_hint(qv->irq, NULL);
4326 kfree(qv->mask);
4327 qv->mask = NULL;
4328 free_irq(qv->irq, qv);
4329 }
4330
4331 return err;
4332 }
4333
4334 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4335 {
4336 int i;
4337
4338 for (i = 0; i < port->nqvecs; i++) {
4339 struct mvpp2_queue_vector *qv = port->qvecs + i;
4340
4341 irq_set_affinity_hint(qv->irq, NULL);
4342 kfree(qv->mask);
4343 qv->mask = NULL;
4344 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4345 free_irq(qv->irq, qv);
4346 }
4347 }
4348
4349 static bool mvpp22_rss_is_supported(void)
4350 {
4351 return queue_mode == MVPP2_QDIST_MULTI_MODE;
4352 }
4353
4354 static int mvpp2_open(struct net_device *dev)
4355 {
4356 struct mvpp2_port *port = netdev_priv(dev);
4357 struct mvpp2 *priv = port->priv;
4358 unsigned char mac_bcast[ETH_ALEN] = {
4359 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4360 bool valid = false;
4361 int err;
4362
4363 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4364 if (err) {
4365 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4366 return err;
4367 }
4368 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4369 if (err) {
4370 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4371 return err;
4372 }
4373 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4374 if (err) {
4375 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4376 return err;
4377 }
4378 err = mvpp2_prs_def_flow(port);
4379 if (err) {
4380 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4381 return err;
4382 }
4383
4384 /* Allocate the Rx/Tx queues */
4385 err = mvpp2_setup_rxqs(port);
4386 if (err) {
4387 netdev_err(port->dev, "cannot allocate Rx queues\n");
4388 return err;
4389 }
4390
4391 err = mvpp2_setup_txqs(port);
4392 if (err) {
4393 netdev_err(port->dev, "cannot allocate Tx queues\n");
4394 goto err_cleanup_rxqs;
4395 }
4396
4397 err = mvpp2_irqs_init(port);
4398 if (err) {
4399 netdev_err(port->dev, "cannot init IRQs\n");
4400 goto err_cleanup_txqs;
4401 }
4402
4403 /* Phylink isn't supported yet in ACPI mode */
4404 if (port->of_node) {
4405 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
4406 if (err) {
4407 netdev_err(port->dev, "could not attach PHY (%d)\n",
4408 err);
4409 goto err_free_irq;
4410 }
4411
4412 valid = true;
4413 }
4414
4415 if (priv->hw_version == MVPP22 && port->port_irq) {
4416 err = request_irq(port->port_irq, mvpp2_port_isr, 0,
4417 dev->name, port);
4418 if (err) {
4419 netdev_err(port->dev,
4420 "cannot request port link/ptp IRQ %d\n",
4421 port->port_irq);
4422 goto err_free_irq;
4423 }
4424
4425 mvpp22_gop_setup_irq(port);
4426
4427 /* In default link is down */
4428 netif_carrier_off(port->dev);
4429
4430 valid = true;
4431 } else {
4432 port->port_irq = 0;
4433 }
4434
4435 if (!valid) {
4436 netdev_err(port->dev,
4437 "invalid configuration: no dt or link IRQ");
4438 err = -ENOENT;
4439 goto err_free_irq;
4440 }
4441
4442 /* Unmask interrupts on all CPUs */
4443 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4444 mvpp2_shared_interrupt_mask_unmask(port, false);
4445
4446 mvpp2_start_dev(port);
4447
4448 /* Start hardware statistics gathering */
4449 queue_delayed_work(priv->stats_queue, &port->stats_work,
4450 MVPP2_MIB_COUNTERS_STATS_DELAY);
4451
4452 return 0;
4453
4454 err_free_irq:
4455 mvpp2_irqs_deinit(port);
4456 err_cleanup_txqs:
4457 mvpp2_cleanup_txqs(port);
4458 err_cleanup_rxqs:
4459 mvpp2_cleanup_rxqs(port);
4460 return err;
4461 }
4462
4463 static int mvpp2_stop(struct net_device *dev)
4464 {
4465 struct mvpp2_port *port = netdev_priv(dev);
4466 struct mvpp2_port_pcpu *port_pcpu;
4467 unsigned int thread;
4468
4469 mvpp2_stop_dev(port);
4470
4471 /* Mask interrupts on all threads */
4472 on_each_cpu(mvpp2_interrupts_mask, port, 1);
4473 mvpp2_shared_interrupt_mask_unmask(port, true);
4474
4475 if (port->phylink)
4476 phylink_disconnect_phy(port->phylink);
4477 if (port->port_irq)
4478 free_irq(port->port_irq, port);
4479
4480 mvpp2_irqs_deinit(port);
4481 if (!port->has_tx_irqs) {
4482 for (thread = 0; thread < port->priv->nthreads; thread++) {
4483 port_pcpu = per_cpu_ptr(port->pcpu, thread);
4484
4485 hrtimer_cancel(&port_pcpu->tx_done_timer);
4486 port_pcpu->timer_scheduled = false;
4487 }
4488 }
4489 mvpp2_cleanup_rxqs(port);
4490 mvpp2_cleanup_txqs(port);
4491
4492 cancel_delayed_work_sync(&port->stats_work);
4493
4494 mvpp2_mac_reset_assert(port);
4495 mvpp22_pcs_reset_assert(port);
4496
4497 return 0;
4498 }
4499
4500 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4501 struct netdev_hw_addr_list *list)
4502 {
4503 struct netdev_hw_addr *ha;
4504 int ret;
4505
4506 netdev_hw_addr_list_for_each(ha, list) {
4507 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4508 if (ret)
4509 return ret;
4510 }
4511
4512 return 0;
4513 }
4514
4515 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4516 {
4517 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4518 mvpp2_prs_vid_enable_filtering(port);
4519 else
4520 mvpp2_prs_vid_disable_filtering(port);
4521
4522 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4523 MVPP2_PRS_L2_UNI_CAST, enable);
4524
4525 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4526 MVPP2_PRS_L2_MULTI_CAST, enable);
4527 }
4528
4529 static void mvpp2_set_rx_mode(struct net_device *dev)
4530 {
4531 struct mvpp2_port *port = netdev_priv(dev);
4532
4533 /* Clear the whole UC and MC list */
4534 mvpp2_prs_mac_del_all(port);
4535
4536 if (dev->flags & IFF_PROMISC) {
4537 mvpp2_set_rx_promisc(port, true);
4538 return;
4539 }
4540
4541 mvpp2_set_rx_promisc(port, false);
4542
4543 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4544 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4545 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4546 MVPP2_PRS_L2_UNI_CAST, true);
4547
4548 if (dev->flags & IFF_ALLMULTI) {
4549 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4550 MVPP2_PRS_L2_MULTI_CAST, true);
4551 return;
4552 }
4553
4554 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4555 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4556 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4557 MVPP2_PRS_L2_MULTI_CAST, true);
4558 }
4559
4560 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4561 {
4562 const struct sockaddr *addr = p;
4563 int err;
4564
4565 if (!is_valid_ether_addr(addr->sa_data))
4566 return -EADDRNOTAVAIL;
4567
4568 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4569 if (err) {
4570 /* Reconfigure parser accept the original MAC address */
4571 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4572 netdev_err(dev, "failed to change MAC address\n");
4573 }
4574 return err;
4575 }
4576
4577 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4578 * then bring up again all ports.
4579 */
4580 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4581 {
4582 int numbufs = MVPP2_BM_POOLS_NUM, i;
4583 struct mvpp2_port *port = NULL;
4584 bool status[MVPP2_MAX_PORTS];
4585
4586 for (i = 0; i < priv->port_count; i++) {
4587 port = priv->port_list[i];
4588 status[i] = netif_running(port->dev);
4589 if (status[i])
4590 mvpp2_stop(port->dev);
4591 }
4592
4593 /* nrxqs is the same for all ports */
4594 if (priv->percpu_pools)
4595 numbufs = port->nrxqs * 2;
4596
4597 for (i = 0; i < numbufs; i++)
4598 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
4599
4600 devm_kfree(port->dev->dev.parent, priv->bm_pools);
4601 priv->percpu_pools = percpu;
4602 mvpp2_bm_init(port->dev->dev.parent, priv);
4603
4604 for (i = 0; i < priv->port_count; i++) {
4605 port = priv->port_list[i];
4606 mvpp2_swf_bm_pool_init(port);
4607 if (status[i])
4608 mvpp2_open(port->dev);
4609 }
4610
4611 return 0;
4612 }
4613
4614 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
4615 {
4616 struct mvpp2_port *port = netdev_priv(dev);
4617 bool running = netif_running(dev);
4618 struct mvpp2 *priv = port->priv;
4619 int err;
4620
4621 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
4622 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
4623 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
4624 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
4625 }
4626
4627 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
4628 if (port->xdp_prog) {
4629 netdev_err(dev, "Jumbo frames are not supported with XDP\n");
4630 return -EINVAL;
4631 }
4632 if (priv->percpu_pools) {
4633 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
4634 mvpp2_bm_switch_buffers(priv, false);
4635 }
4636 } else {
4637 bool jumbo = false;
4638 int i;
4639
4640 for (i = 0; i < priv->port_count; i++)
4641 if (priv->port_list[i] != port &&
4642 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
4643 MVPP2_BM_LONG_PKT_SIZE) {
4644 jumbo = true;
4645 break;
4646 }
4647
4648 /* No port is using jumbo frames */
4649 if (!jumbo) {
4650 dev_info(port->dev->dev.parent,
4651 "all ports have a low MTU, switching to per-cpu buffers");
4652 mvpp2_bm_switch_buffers(priv, true);
4653 }
4654 }
4655
4656 if (running)
4657 mvpp2_stop_dev(port);
4658
4659 err = mvpp2_bm_update_mtu(dev, mtu);
4660 if (err) {
4661 netdev_err(dev, "failed to change MTU\n");
4662 /* Reconfigure BM to the original MTU */
4663 mvpp2_bm_update_mtu(dev, dev->mtu);
4664 } else {
4665 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
4666 }
4667
4668 if (running) {
4669 mvpp2_start_dev(port);
4670 mvpp2_egress_enable(port);
4671 mvpp2_ingress_enable(port);
4672 }
4673
4674 return err;
4675 }
4676
4677 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
4678 {
4679 enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
4680 struct mvpp2 *priv = port->priv;
4681 int err = -1, i;
4682
4683 if (!priv->percpu_pools)
4684 return err;
4685
4686 if (!priv->page_pool[0])
4687 return -ENOMEM;
4688
4689 for (i = 0; i < priv->port_count; i++) {
4690 port = priv->port_list[i];
4691 if (port->xdp_prog) {
4692 dma_dir = DMA_BIDIRECTIONAL;
4693 break;
4694 }
4695 }
4696
4697 /* All pools are equal in terms of DMA direction */
4698 if (priv->page_pool[0]->p.dma_dir != dma_dir)
4699 err = mvpp2_bm_switch_buffers(priv, true);
4700
4701 return err;
4702 }
4703
4704 static void
4705 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4706 {
4707 struct mvpp2_port *port = netdev_priv(dev);
4708 unsigned int start;
4709 unsigned int cpu;
4710
4711 for_each_possible_cpu(cpu) {
4712 struct mvpp2_pcpu_stats *cpu_stats;
4713 u64 rx_packets;
4714 u64 rx_bytes;
4715 u64 tx_packets;
4716 u64 tx_bytes;
4717
4718 cpu_stats = per_cpu_ptr(port->stats, cpu);
4719 do {
4720 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
4721 rx_packets = cpu_stats->rx_packets;
4722 rx_bytes = cpu_stats->rx_bytes;
4723 tx_packets = cpu_stats->tx_packets;
4724 tx_bytes = cpu_stats->tx_bytes;
4725 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
4726
4727 stats->rx_packets += rx_packets;
4728 stats->rx_bytes += rx_bytes;
4729 stats->tx_packets += tx_packets;
4730 stats->tx_bytes += tx_bytes;
4731 }
4732
4733 stats->rx_errors = dev->stats.rx_errors;
4734 stats->rx_dropped = dev->stats.rx_dropped;
4735 stats->tx_dropped = dev->stats.tx_dropped;
4736 }
4737
4738 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
4739 {
4740 struct hwtstamp_config config;
4741 void __iomem *ptp;
4742 u32 gcr, int_mask;
4743
4744 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4745 return -EFAULT;
4746
4747 if (config.flags)
4748 return -EINVAL;
4749
4750 if (config.tx_type != HWTSTAMP_TX_OFF &&
4751 config.tx_type != HWTSTAMP_TX_ON)
4752 return -ERANGE;
4753
4754 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
4755
4756 int_mask = gcr = 0;
4757 if (config.tx_type != HWTSTAMP_TX_OFF) {
4758 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
4759 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
4760 MVPP22_PTP_INT_MASK_QUEUE0;
4761 }
4762
4763 /* It seems we must also release the TX reset when enabling the TSU */
4764 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
4765 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
4766 MVPP22_PTP_GCR_TX_RESET;
4767
4768 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
4769 mvpp22_tai_start(port->priv->tai);
4770
4771 if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
4772 config.rx_filter = HWTSTAMP_FILTER_ALL;
4773 mvpp2_modify(ptp + MVPP22_PTP_GCR,
4774 MVPP22_PTP_GCR_RX_RESET |
4775 MVPP22_PTP_GCR_TX_RESET |
4776 MVPP22_PTP_GCR_TSU_ENABLE, gcr);
4777 port->rx_hwtstamp = true;
4778 } else {
4779 port->rx_hwtstamp = false;
4780 mvpp2_modify(ptp + MVPP22_PTP_GCR,
4781 MVPP22_PTP_GCR_RX_RESET |
4782 MVPP22_PTP_GCR_TX_RESET |
4783 MVPP22_PTP_GCR_TSU_ENABLE, gcr);
4784 }
4785
4786 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
4787 MVPP22_PTP_INT_MASK_QUEUE1 |
4788 MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
4789
4790 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
4791 mvpp22_tai_stop(port->priv->tai);
4792
4793 port->tx_hwtstamp_type = config.tx_type;
4794
4795 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
4796 return -EFAULT;
4797
4798 return 0;
4799 }
4800
4801 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
4802 {
4803 struct hwtstamp_config config;
4804
4805 memset(&config, 0, sizeof(config));
4806
4807 config.tx_type = port->tx_hwtstamp_type;
4808 config.rx_filter = port->rx_hwtstamp ?
4809 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
4810
4811 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
4812 return -EFAULT;
4813
4814 return 0;
4815 }
4816
4817 static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
4818 struct ethtool_ts_info *info)
4819 {
4820 struct mvpp2_port *port = netdev_priv(dev);
4821
4822 if (!port->hwtstamp)
4823 return -EOPNOTSUPP;
4824
4825 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai);
4826 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
4827 SOF_TIMESTAMPING_RX_SOFTWARE |
4828 SOF_TIMESTAMPING_SOFTWARE |
4829 SOF_TIMESTAMPING_TX_HARDWARE |
4830 SOF_TIMESTAMPING_RX_HARDWARE |
4831 SOF_TIMESTAMPING_RAW_HARDWARE;
4832 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
4833 BIT(HWTSTAMP_TX_ON);
4834 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
4835 BIT(HWTSTAMP_FILTER_ALL);
4836
4837 return 0;
4838 }
4839
4840 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4841 {
4842 struct mvpp2_port *port = netdev_priv(dev);
4843
4844 switch (cmd) {
4845 case SIOCSHWTSTAMP:
4846 if (port->hwtstamp)
4847 return mvpp2_set_ts_config(port, ifr);
4848 break;
4849
4850 case SIOCGHWTSTAMP:
4851 if (port->hwtstamp)
4852 return mvpp2_get_ts_config(port, ifr);
4853 break;
4854 }
4855
4856 if (!port->phylink)
4857 return -ENOTSUPP;
4858
4859 return phylink_mii_ioctl(port->phylink, ifr, cmd);
4860 }
4861
4862 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4863 {
4864 struct mvpp2_port *port = netdev_priv(dev);
4865 int ret;
4866
4867 ret = mvpp2_prs_vid_entry_add(port, vid);
4868 if (ret)
4869 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
4870 MVPP2_PRS_VLAN_FILT_MAX - 1);
4871 return ret;
4872 }
4873
4874 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4875 {
4876 struct mvpp2_port *port = netdev_priv(dev);
4877
4878 mvpp2_prs_vid_entry_remove(port, vid);
4879 return 0;
4880 }
4881
4882 static int mvpp2_set_features(struct net_device *dev,
4883 netdev_features_t features)
4884 {
4885 netdev_features_t changed = dev->features ^ features;
4886 struct mvpp2_port *port = netdev_priv(dev);
4887
4888 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
4889 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
4890 mvpp2_prs_vid_enable_filtering(port);
4891 } else {
4892 /* Invalidate all registered VID filters for this
4893 * port
4894 */
4895 mvpp2_prs_vid_remove_all(port);
4896
4897 mvpp2_prs_vid_disable_filtering(port);
4898 }
4899 }
4900
4901 if (changed & NETIF_F_RXHASH) {
4902 if (features & NETIF_F_RXHASH)
4903 mvpp22_port_rss_enable(port);
4904 else
4905 mvpp22_port_rss_disable(port);
4906 }
4907
4908 return 0;
4909 }
4910
4911 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
4912 {
4913 struct bpf_prog *prog = bpf->prog, *old_prog;
4914 bool running = netif_running(port->dev);
4915 bool reset = !prog != !port->xdp_prog;
4916
4917 if (port->dev->mtu > ETH_DATA_LEN) {
4918 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled");
4919 return -EOPNOTSUPP;
4920 }
4921
4922 if (!port->priv->percpu_pools) {
4923 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
4924 return -EOPNOTSUPP;
4925 }
4926
4927 if (port->ntxqs < num_possible_cpus() * 2) {
4928 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
4929 return -EOPNOTSUPP;
4930 }
4931
4932 /* device is up and bpf is added/removed, must setup the RX queues */
4933 if (running && reset)
4934 mvpp2_stop(port->dev);
4935
4936 old_prog = xchg(&port->xdp_prog, prog);
4937 if (old_prog)
4938 bpf_prog_put(old_prog);
4939
4940 /* bpf is just replaced, RXQ and MTU are already setup */
4941 if (!reset)
4942 return 0;
4943
4944 /* device was up, restore the link */
4945 if (running)
4946 mvpp2_open(port->dev);
4947
4948 /* Check Page Pool DMA Direction */
4949 mvpp2_check_pagepool_dma(port);
4950
4951 return 0;
4952 }
4953
4954 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4955 {
4956 struct mvpp2_port *port = netdev_priv(dev);
4957
4958 switch (xdp->command) {
4959 case XDP_SETUP_PROG:
4960 return mvpp2_xdp_setup(port, xdp);
4961 default:
4962 return -EINVAL;
4963 }
4964 }
4965
4966 /* Ethtool methods */
4967
4968 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
4969 {
4970 struct mvpp2_port *port = netdev_priv(dev);
4971
4972 if (!port->phylink)
4973 return -ENOTSUPP;
4974
4975 return phylink_ethtool_nway_reset(port->phylink);
4976 }
4977
4978 /* Set interrupt coalescing for ethtools */
4979 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
4980 struct ethtool_coalesce *c)
4981 {
4982 struct mvpp2_port *port = netdev_priv(dev);
4983 int queue;
4984
4985 for (queue = 0; queue < port->nrxqs; queue++) {
4986 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4987
4988 rxq->time_coal = c->rx_coalesce_usecs;
4989 rxq->pkts_coal = c->rx_max_coalesced_frames;
4990 mvpp2_rx_pkts_coal_set(port, rxq);
4991 mvpp2_rx_time_coal_set(port, rxq);
4992 }
4993
4994 if (port->has_tx_irqs) {
4995 port->tx_time_coal = c->tx_coalesce_usecs;
4996 mvpp2_tx_time_coal_set(port);
4997 }
4998
4999 for (queue = 0; queue < port->ntxqs; queue++) {
5000 struct mvpp2_tx_queue *txq = port->txqs[queue];
5001
5002 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5003
5004 if (port->has_tx_irqs)
5005 mvpp2_tx_pkts_coal_set(port, txq);
5006 }
5007
5008 return 0;
5009 }
5010
5011 /* get coalescing for ethtools */
5012 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
5013 struct ethtool_coalesce *c)
5014 {
5015 struct mvpp2_port *port = netdev_priv(dev);
5016
5017 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
5018 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5019 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5020 c->tx_coalesce_usecs = port->tx_time_coal;
5021 return 0;
5022 }
5023
5024 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5025 struct ethtool_drvinfo *drvinfo)
5026 {
5027 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5028 sizeof(drvinfo->driver));
5029 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5030 sizeof(drvinfo->version));
5031 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
5032 sizeof(drvinfo->bus_info));
5033 }
5034
5035 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
5036 struct ethtool_ringparam *ring)
5037 {
5038 struct mvpp2_port *port = netdev_priv(dev);
5039
5040 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
5041 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
5042 ring->rx_pending = port->rx_ring_size;
5043 ring->tx_pending = port->tx_ring_size;
5044 }
5045
5046 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
5047 struct ethtool_ringparam *ring)
5048 {
5049 struct mvpp2_port *port = netdev_priv(dev);
5050 u16 prev_rx_ring_size = port->rx_ring_size;
5051 u16 prev_tx_ring_size = port->tx_ring_size;
5052 int err;
5053
5054 err = mvpp2_check_ringparam_valid(dev, ring);
5055 if (err)
5056 return err;
5057
5058 if (!netif_running(dev)) {
5059 port->rx_ring_size = ring->rx_pending;
5060 port->tx_ring_size = ring->tx_pending;
5061 return 0;
5062 }
5063
5064 /* The interface is running, so we have to force a
5065 * reallocation of the queues
5066 */
5067 mvpp2_stop_dev(port);
5068 mvpp2_cleanup_rxqs(port);
5069 mvpp2_cleanup_txqs(port);
5070
5071 port->rx_ring_size = ring->rx_pending;
5072 port->tx_ring_size = ring->tx_pending;
5073
5074 err = mvpp2_setup_rxqs(port);
5075 if (err) {
5076 /* Reallocate Rx queues with the original ring size */
5077 port->rx_ring_size = prev_rx_ring_size;
5078 ring->rx_pending = prev_rx_ring_size;
5079 err = mvpp2_setup_rxqs(port);
5080 if (err)
5081 goto err_out;
5082 }
5083 err = mvpp2_setup_txqs(port);
5084 if (err) {
5085 /* Reallocate Tx queues with the original ring size */
5086 port->tx_ring_size = prev_tx_ring_size;
5087 ring->tx_pending = prev_tx_ring_size;
5088 err = mvpp2_setup_txqs(port);
5089 if (err)
5090 goto err_clean_rxqs;
5091 }
5092
5093 mvpp2_start_dev(port);
5094 mvpp2_egress_enable(port);
5095 mvpp2_ingress_enable(port);
5096
5097 return 0;
5098
5099 err_clean_rxqs:
5100 mvpp2_cleanup_rxqs(port);
5101 err_out:
5102 netdev_err(dev, "failed to change ring parameters");
5103 return err;
5104 }
5105
5106 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
5107 struct ethtool_pauseparam *pause)
5108 {
5109 struct mvpp2_port *port = netdev_priv(dev);
5110
5111 if (!port->phylink)
5112 return;
5113
5114 phylink_ethtool_get_pauseparam(port->phylink, pause);
5115 }
5116
5117 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
5118 struct ethtool_pauseparam *pause)
5119 {
5120 struct mvpp2_port *port = netdev_priv(dev);
5121
5122 if (!port->phylink)
5123 return -ENOTSUPP;
5124
5125 return phylink_ethtool_set_pauseparam(port->phylink, pause);
5126 }
5127
5128 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
5129 struct ethtool_link_ksettings *cmd)
5130 {
5131 struct mvpp2_port *port = netdev_priv(dev);
5132
5133 if (!port->phylink)
5134 return -ENOTSUPP;
5135
5136 return phylink_ethtool_ksettings_get(port->phylink, cmd);
5137 }
5138
5139 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
5140 const struct ethtool_link_ksettings *cmd)
5141 {
5142 struct mvpp2_port *port = netdev_priv(dev);
5143
5144 if (!port->phylink)
5145 return -ENOTSUPP;
5146
5147 return phylink_ethtool_ksettings_set(port->phylink, cmd);
5148 }
5149
5150 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
5151 struct ethtool_rxnfc *info, u32 *rules)
5152 {
5153 struct mvpp2_port *port = netdev_priv(dev);
5154 int ret = 0, i, loc = 0;
5155
5156 if (!mvpp22_rss_is_supported())
5157 return -EOPNOTSUPP;
5158
5159 switch (info->cmd) {
5160 case ETHTOOL_GRXFH:
5161 ret = mvpp2_ethtool_rxfh_get(port, info);
5162 break;
5163 case ETHTOOL_GRXRINGS:
5164 info->data = port->nrxqs;
5165 break;
5166 case ETHTOOL_GRXCLSRLCNT:
5167 info->rule_cnt = port->n_rfs_rules;
5168 break;
5169 case ETHTOOL_GRXCLSRULE:
5170 ret = mvpp2_ethtool_cls_rule_get(port, info);
5171 break;
5172 case ETHTOOL_GRXCLSRLALL:
5173 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
5174 if (port->rfs_rules[i])
5175 rules[loc++] = i;
5176 }
5177 break;
5178 default:
5179 return -ENOTSUPP;
5180 }
5181
5182 return ret;
5183 }
5184
5185 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
5186 struct ethtool_rxnfc *info)
5187 {
5188 struct mvpp2_port *port = netdev_priv(dev);
5189 int ret = 0;
5190
5191 if (!mvpp22_rss_is_supported())
5192 return -EOPNOTSUPP;
5193
5194 switch (info->cmd) {
5195 case ETHTOOL_SRXFH:
5196 ret = mvpp2_ethtool_rxfh_set(port, info);
5197 break;
5198 case ETHTOOL_SRXCLSRLINS:
5199 ret = mvpp2_ethtool_cls_rule_ins(port, info);
5200 break;
5201 case ETHTOOL_SRXCLSRLDEL:
5202 ret = mvpp2_ethtool_cls_rule_del(port, info);
5203 break;
5204 default:
5205 return -EOPNOTSUPP;
5206 }
5207 return ret;
5208 }
5209
5210 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
5211 {
5212 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
5213 }
5214
5215 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5216 u8 *hfunc)
5217 {
5218 struct mvpp2_port *port = netdev_priv(dev);
5219 int ret = 0;
5220
5221 if (!mvpp22_rss_is_supported())
5222 return -EOPNOTSUPP;
5223
5224 if (indir)
5225 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
5226
5227 if (hfunc)
5228 *hfunc = ETH_RSS_HASH_CRC32;
5229
5230 return ret;
5231 }
5232
5233 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5234 const u8 *key, const u8 hfunc)
5235 {
5236 struct mvpp2_port *port = netdev_priv(dev);
5237 int ret = 0;
5238
5239 if (!mvpp22_rss_is_supported())
5240 return -EOPNOTSUPP;
5241
5242 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5243 return -EOPNOTSUPP;
5244
5245 if (key)
5246 return -EOPNOTSUPP;
5247
5248 if (indir)
5249 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
5250
5251 return ret;
5252 }
5253
5254 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
5255 u8 *key, u8 *hfunc, u32 rss_context)
5256 {
5257 struct mvpp2_port *port = netdev_priv(dev);
5258 int ret = 0;
5259
5260 if (!mvpp22_rss_is_supported())
5261 return -EOPNOTSUPP;
5262 if (rss_context >= MVPP22_N_RSS_TABLES)
5263 return -EINVAL;
5264
5265 if (hfunc)
5266 *hfunc = ETH_RSS_HASH_CRC32;
5267
5268 if (indir)
5269 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
5270
5271 return ret;
5272 }
5273
5274 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
5275 const u32 *indir, const u8 *key,
5276 const u8 hfunc, u32 *rss_context,
5277 bool delete)
5278 {
5279 struct mvpp2_port *port = netdev_priv(dev);
5280 int ret;
5281
5282 if (!mvpp22_rss_is_supported())
5283 return -EOPNOTSUPP;
5284
5285 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5286 return -EOPNOTSUPP;
5287
5288 if (key)
5289 return -EOPNOTSUPP;
5290
5291 if (delete)
5292 return mvpp22_port_rss_ctx_delete(port, *rss_context);
5293
5294 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
5295 ret = mvpp22_port_rss_ctx_create(port, rss_context);
5296 if (ret)
5297 return ret;
5298 }
5299
5300 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5301 }
5302 /* Device ops */
5303
5304 static const struct net_device_ops mvpp2_netdev_ops = {
5305 .ndo_open = mvpp2_open,
5306 .ndo_stop = mvpp2_stop,
5307 .ndo_start_xmit = mvpp2_tx,
5308 .ndo_set_rx_mode = mvpp2_set_rx_mode,
5309 .ndo_set_mac_address = mvpp2_set_mac_address,
5310 .ndo_change_mtu = mvpp2_change_mtu,
5311 .ndo_get_stats64 = mvpp2_get_stats64,
5312 .ndo_do_ioctl = mvpp2_ioctl,
5313 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
5314 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
5315 .ndo_set_features = mvpp2_set_features,
5316 .ndo_bpf = mvpp2_xdp,
5317 .ndo_xdp_xmit = mvpp2_xdp_xmit,
5318 };
5319
5320 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5321 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5322 ETHTOOL_COALESCE_MAX_FRAMES,
5323 .nway_reset = mvpp2_ethtool_nway_reset,
5324 .get_link = ethtool_op_get_link,
5325 .get_ts_info = mvpp2_ethtool_get_ts_info,
5326 .set_coalesce = mvpp2_ethtool_set_coalesce,
5327 .get_coalesce = mvpp2_ethtool_get_coalesce,
5328 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
5329 .get_ringparam = mvpp2_ethtool_get_ringparam,
5330 .set_ringparam = mvpp2_ethtool_set_ringparam,
5331 .get_strings = mvpp2_ethtool_get_strings,
5332 .get_ethtool_stats = mvpp2_ethtool_get_stats,
5333 .get_sset_count = mvpp2_ethtool_get_sset_count,
5334 .get_pauseparam = mvpp2_ethtool_get_pause_param,
5335 .set_pauseparam = mvpp2_ethtool_set_pause_param,
5336 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
5337 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
5338 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
5339 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
5340 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
5341 .get_rxfh = mvpp2_ethtool_get_rxfh,
5342 .set_rxfh = mvpp2_ethtool_set_rxfh,
5343 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context,
5344 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context,
5345 };
5346
5347 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5348 * had a single IRQ defined per-port.
5349 */
5350 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5351 struct device_node *port_node)
5352 {
5353 struct mvpp2_queue_vector *v = &port->qvecs[0];
5354
5355 v->first_rxq = 0;
5356 v->nrxqs = port->nrxqs;
5357 v->type = MVPP2_QUEUE_VECTOR_SHARED;
5358 v->sw_thread_id = 0;
5359 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5360 v->port = port;
5361 v->irq = irq_of_parse_and_map(port_node, 0);
5362 if (v->irq <= 0)
5363 return -EINVAL;
5364 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5365 NAPI_POLL_WEIGHT);
5366
5367 port->nqvecs = 1;
5368
5369 return 0;
5370 }
5371
5372 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5373 struct device_node *port_node)
5374 {
5375 struct mvpp2 *priv = port->priv;
5376 struct mvpp2_queue_vector *v;
5377 int i, ret;
5378
5379 switch (queue_mode) {
5380 case MVPP2_QDIST_SINGLE_MODE:
5381 port->nqvecs = priv->nthreads + 1;
5382 break;
5383 case MVPP2_QDIST_MULTI_MODE:
5384 port->nqvecs = priv->nthreads;
5385 break;
5386 }
5387
5388 for (i = 0; i < port->nqvecs; i++) {
5389 char irqname[16];
5390
5391 v = port->qvecs + i;
5392
5393 v->port = port;
5394 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5395 v->sw_thread_id = i;
5396 v->sw_thread_mask = BIT(i);
5397
5398 if (port->flags & MVPP2_F_DT_COMPAT)
5399 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5400 else
5401 snprintf(irqname, sizeof(irqname), "hif%d", i);
5402
5403 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5404 v->first_rxq = i;
5405 v->nrxqs = 1;
5406 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5407 i == (port->nqvecs - 1)) {
5408 v->first_rxq = 0;
5409 v->nrxqs = port->nrxqs;
5410 v->type = MVPP2_QUEUE_VECTOR_SHARED;
5411
5412 if (port->flags & MVPP2_F_DT_COMPAT)
5413 strncpy(irqname, "rx-shared", sizeof(irqname));
5414 }
5415
5416 if (port_node)
5417 v->irq = of_irq_get_byname(port_node, irqname);
5418 else
5419 v->irq = fwnode_irq_get(port->fwnode, i);
5420 if (v->irq <= 0) {
5421 ret = -EINVAL;
5422 goto err;
5423 }
5424
5425 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5426 NAPI_POLL_WEIGHT);
5427 }
5428
5429 return 0;
5430
5431 err:
5432 for (i = 0; i < port->nqvecs; i++)
5433 irq_dispose_mapping(port->qvecs[i].irq);
5434 return ret;
5435 }
5436
5437 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5438 struct device_node *port_node)
5439 {
5440 if (port->has_tx_irqs)
5441 return mvpp2_multi_queue_vectors_init(port, port_node);
5442 else
5443 return mvpp2_simple_queue_vectors_init(port, port_node);
5444 }
5445
5446 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5447 {
5448 int i;
5449
5450 for (i = 0; i < port->nqvecs; i++)
5451 irq_dispose_mapping(port->qvecs[i].irq);
5452 }
5453
5454 /* Configure Rx queue group interrupt for this port */
5455 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5456 {
5457 struct mvpp2 *priv = port->priv;
5458 u32 val;
5459 int i;
5460
5461 if (priv->hw_version == MVPP21) {
5462 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5463 port->nrxqs);
5464 return;
5465 }
5466
5467 /* Handle the more complicated PPv2.2 case */
5468 for (i = 0; i < port->nqvecs; i++) {
5469 struct mvpp2_queue_vector *qv = port->qvecs + i;
5470
5471 if (!qv->nrxqs)
5472 continue;
5473
5474 val = qv->sw_thread_id;
5475 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5476 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5477
5478 val = qv->first_rxq;
5479 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5480 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5481 }
5482 }
5483
5484 /* Initialize port HW */
5485 static int mvpp2_port_init(struct mvpp2_port *port)
5486 {
5487 struct device *dev = port->dev->dev.parent;
5488 struct mvpp2 *priv = port->priv;
5489 struct mvpp2_txq_pcpu *txq_pcpu;
5490 unsigned int thread;
5491 int queue, err, val;
5492
5493 /* Checks for hardware constraints */
5494 if (port->first_rxq + port->nrxqs >
5495 MVPP2_MAX_PORTS * priv->max_port_rxqs)
5496 return -EINVAL;
5497
5498 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5499 return -EINVAL;
5500
5501 /* Disable port */
5502 mvpp2_egress_disable(port);
5503 mvpp2_port_disable(port);
5504
5505 if (mvpp2_is_xlg(port->phy_interface)) {
5506 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5507 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5508 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5509 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5510 } else {
5511 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5512 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5513 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5514 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5515 }
5516
5517 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5518
5519 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5520 GFP_KERNEL);
5521 if (!port->txqs)
5522 return -ENOMEM;
5523
5524 /* Associate physical Tx queues to this port and initialize.
5525 * The mapping is predefined.
5526 */
5527 for (queue = 0; queue < port->ntxqs; queue++) {
5528 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5529 struct mvpp2_tx_queue *txq;
5530
5531 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5532 if (!txq) {
5533 err = -ENOMEM;
5534 goto err_free_percpu;
5535 }
5536
5537 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5538 if (!txq->pcpu) {
5539 err = -ENOMEM;
5540 goto err_free_percpu;
5541 }
5542
5543 txq->id = queue_phy_id;
5544 txq->log_id = queue;
5545 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5546 for (thread = 0; thread < priv->nthreads; thread++) {
5547 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5548 txq_pcpu->thread = thread;
5549 }
5550
5551 port->txqs[queue] = txq;
5552 }
5553
5554 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
5555 GFP_KERNEL);
5556 if (!port->rxqs) {
5557 err = -ENOMEM;
5558 goto err_free_percpu;
5559 }
5560
5561 /* Allocate and initialize Rx queue for this port */
5562 for (queue = 0; queue < port->nrxqs; queue++) {
5563 struct mvpp2_rx_queue *rxq;
5564
5565 /* Map physical Rx queue to port's logical Rx queue */
5566 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
5567 if (!rxq) {
5568 err = -ENOMEM;
5569 goto err_free_percpu;
5570 }
5571 /* Map this Rx queue to a physical queue */
5572 rxq->id = port->first_rxq + queue;
5573 rxq->port = port->id;
5574 rxq->logic_rxq = queue;
5575
5576 port->rxqs[queue] = rxq;
5577 }
5578
5579 mvpp2_rx_irqs_setup(port);
5580
5581 /* Create Rx descriptor rings */
5582 for (queue = 0; queue < port->nrxqs; queue++) {
5583 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5584
5585 rxq->size = port->rx_ring_size;
5586 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
5587 rxq->time_coal = MVPP2_RX_COAL_USEC;
5588 }
5589
5590 mvpp2_ingress_disable(port);
5591
5592 /* Port default configuration */
5593 mvpp2_defaults_set(port);
5594
5595 /* Port's classifier configuration */
5596 mvpp2_cls_oversize_rxq_set(port);
5597 mvpp2_cls_port_config(port);
5598
5599 if (mvpp22_rss_is_supported())
5600 mvpp22_port_rss_init(port);
5601
5602 /* Provide an initial Rx packet size */
5603 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
5604
5605 /* Initialize pools for swf */
5606 err = mvpp2_swf_bm_pool_init(port);
5607 if (err)
5608 goto err_free_percpu;
5609
5610 /* Clear all port stats */
5611 mvpp2_read_stats(port);
5612 memset(port->ethtool_stats, 0,
5613 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
5614
5615 return 0;
5616
5617 err_free_percpu:
5618 for (queue = 0; queue < port->ntxqs; queue++) {
5619 if (!port->txqs[queue])
5620 continue;
5621 free_percpu(port->txqs[queue]->pcpu);
5622 }
5623 return err;
5624 }
5625
5626 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
5627 unsigned long *flags)
5628 {
5629 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
5630 "tx-cpu3" };
5631 int i;
5632
5633 for (i = 0; i < 5; i++)
5634 if (of_property_match_string(port_node, "interrupt-names",
5635 irqs[i]) < 0)
5636 return false;
5637
5638 *flags |= MVPP2_F_DT_COMPAT;
5639 return true;
5640 }
5641
5642 /* Checks if the port dt description has the required Tx interrupts:
5643 * - PPv2.1: there are no such interrupts.
5644 * - PPv2.2:
5645 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
5646 * - The new ones have: "hifX" with X in [0..8]
5647 *
5648 * All those variants are supported to keep the backward compatibility.
5649 */
5650 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
5651 struct device_node *port_node,
5652 unsigned long *flags)
5653 {
5654 char name[5];
5655 int i;
5656
5657 /* ACPI */
5658 if (!port_node)
5659 return true;
5660
5661 if (priv->hw_version == MVPP21)
5662 return false;
5663
5664 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
5665 return true;
5666
5667 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5668 snprintf(name, 5, "hif%d", i);
5669 if (of_property_match_string(port_node, "interrupt-names",
5670 name) < 0)
5671 return false;
5672 }
5673
5674 return true;
5675 }
5676
5677 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
5678 struct fwnode_handle *fwnode,
5679 char **mac_from)
5680 {
5681 struct mvpp2_port *port = netdev_priv(dev);
5682 char hw_mac_addr[ETH_ALEN] = {0};
5683 char fw_mac_addr[ETH_ALEN];
5684
5685 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
5686 *mac_from = "firmware node";
5687 ether_addr_copy(dev->dev_addr, fw_mac_addr);
5688 return;
5689 }
5690
5691 if (priv->hw_version == MVPP21) {
5692 mvpp21_get_mac_address(port, hw_mac_addr);
5693 if (is_valid_ether_addr(hw_mac_addr)) {
5694 *mac_from = "hardware";
5695 ether_addr_copy(dev->dev_addr, hw_mac_addr);
5696 return;
5697 }
5698 }
5699
5700 *mac_from = "random";
5701 eth_hw_addr_random(dev);
5702 }
5703
5704 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
5705 {
5706 return container_of(config, struct mvpp2_port, phylink_config);
5707 }
5708
5709 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs)
5710 {
5711 return container_of(pcs, struct mvpp2_port, phylink_pcs);
5712 }
5713
5714 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
5715 struct phylink_link_state *state)
5716 {
5717 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
5718 u32 val;
5719
5720 state->speed = SPEED_10000;
5721 state->duplex = 1;
5722 state->an_complete = 1;
5723
5724 val = readl(port->base + MVPP22_XLG_STATUS);
5725 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
5726
5727 state->pause = 0;
5728 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5729 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
5730 state->pause |= MLO_PAUSE_TX;
5731 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
5732 state->pause |= MLO_PAUSE_RX;
5733 }
5734
5735 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs,
5736 unsigned int mode,
5737 phy_interface_t interface,
5738 const unsigned long *advertising,
5739 bool permit_pause_to_mac)
5740 {
5741 return 0;
5742 }
5743
5744 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
5745 .pcs_get_state = mvpp2_xlg_pcs_get_state,
5746 .pcs_config = mvpp2_xlg_pcs_config,
5747 };
5748
5749 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
5750 struct phylink_link_state *state)
5751 {
5752 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
5753 u32 val;
5754
5755 val = readl(port->base + MVPP2_GMAC_STATUS0);
5756
5757 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
5758 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
5759 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
5760
5761 switch (port->phy_interface) {
5762 case PHY_INTERFACE_MODE_1000BASEX:
5763 state->speed = SPEED_1000;
5764 break;
5765 case PHY_INTERFACE_MODE_2500BASEX:
5766 state->speed = SPEED_2500;
5767 break;
5768 default:
5769 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
5770 state->speed = SPEED_1000;
5771 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
5772 state->speed = SPEED_100;
5773 else
5774 state->speed = SPEED_10;
5775 }
5776
5777 state->pause = 0;
5778 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
5779 state->pause |= MLO_PAUSE_RX;
5780 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
5781 state->pause |= MLO_PAUSE_TX;
5782 }
5783
5784 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
5785 phy_interface_t interface,
5786 const unsigned long *advertising,
5787 bool permit_pause_to_mac)
5788 {
5789 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
5790 u32 mask, val, an, old_an, changed;
5791
5792 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
5793 MVPP2_GMAC_IN_BAND_AUTONEG |
5794 MVPP2_GMAC_AN_SPEED_EN |
5795 MVPP2_GMAC_FLOW_CTRL_AUTONEG |
5796 MVPP2_GMAC_AN_DUPLEX_EN;
5797
5798 if (phylink_autoneg_inband(mode)) {
5799 mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
5800 MVPP2_GMAC_CONFIG_GMII_SPEED |
5801 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
5802 val = MVPP2_GMAC_IN_BAND_AUTONEG;
5803
5804 if (interface == PHY_INTERFACE_MODE_SGMII) {
5805 /* SGMII mode receives the speed and duplex from PHY */
5806 val |= MVPP2_GMAC_AN_SPEED_EN |
5807 MVPP2_GMAC_AN_DUPLEX_EN;
5808 } else {
5809 /* 802.3z mode has fixed speed and duplex */
5810 val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
5811 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
5812
5813 /* The FLOW_CTRL_AUTONEG bit selects either the hardware
5814 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG
5815 * manually controls the GMAC pause modes.
5816 */
5817 if (permit_pause_to_mac)
5818 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
5819
5820 /* Configure advertisement bits */
5821 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
5822 if (phylink_test(advertising, Pause))
5823 val |= MVPP2_GMAC_FC_ADV_EN;
5824 if (phylink_test(advertising, Asym_Pause))
5825 val |= MVPP2_GMAC_FC_ADV_ASM_EN;
5826 }
5827 } else {
5828 val = 0;
5829 }
5830
5831 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5832 an = (an & ~mask) | val;
5833 changed = an ^ old_an;
5834 if (changed)
5835 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5836
5837 /* We are only interested in the advertisement bits changing */
5838 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
5839 }
5840
5841 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
5842 {
5843 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
5844 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5845
5846 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
5847 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5848 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
5849 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5850 }
5851
5852 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
5853 .pcs_get_state = mvpp2_gmac_pcs_get_state,
5854 .pcs_config = mvpp2_gmac_pcs_config,
5855 .pcs_an_restart = mvpp2_gmac_pcs_an_restart,
5856 };
5857
5858 static void mvpp2_phylink_validate(struct phylink_config *config,
5859 unsigned long *supported,
5860 struct phylink_link_state *state)
5861 {
5862 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5863 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
5864
5865 /* Invalid combinations */
5866 switch (state->interface) {
5867 case PHY_INTERFACE_MODE_10GBASER:
5868 case PHY_INTERFACE_MODE_XAUI:
5869 if (!mvpp2_port_supports_xlg(port))
5870 goto empty_set;
5871 break;
5872 case PHY_INTERFACE_MODE_RGMII:
5873 case PHY_INTERFACE_MODE_RGMII_ID:
5874 case PHY_INTERFACE_MODE_RGMII_RXID:
5875 case PHY_INTERFACE_MODE_RGMII_TXID:
5876 if (!mvpp2_port_supports_rgmii(port))
5877 goto empty_set;
5878 break;
5879 default:
5880 break;
5881 }
5882
5883 phylink_set(mask, Autoneg);
5884 phylink_set_port_modes(mask);
5885 phylink_set(mask, Pause);
5886 phylink_set(mask, Asym_Pause);
5887
5888 switch (state->interface) {
5889 case PHY_INTERFACE_MODE_10GBASER:
5890 case PHY_INTERFACE_MODE_XAUI:
5891 case PHY_INTERFACE_MODE_NA:
5892 if (mvpp2_port_supports_xlg(port)) {
5893 phylink_set(mask, 10000baseT_Full);
5894 phylink_set(mask, 10000baseCR_Full);
5895 phylink_set(mask, 10000baseSR_Full);
5896 phylink_set(mask, 10000baseLR_Full);
5897 phylink_set(mask, 10000baseLRM_Full);
5898 phylink_set(mask, 10000baseER_Full);
5899 phylink_set(mask, 10000baseKR_Full);
5900 }
5901 if (state->interface != PHY_INTERFACE_MODE_NA)
5902 break;
5903 fallthrough;
5904 case PHY_INTERFACE_MODE_RGMII:
5905 case PHY_INTERFACE_MODE_RGMII_ID:
5906 case PHY_INTERFACE_MODE_RGMII_RXID:
5907 case PHY_INTERFACE_MODE_RGMII_TXID:
5908 case PHY_INTERFACE_MODE_SGMII:
5909 phylink_set(mask, 10baseT_Half);
5910 phylink_set(mask, 10baseT_Full);
5911 phylink_set(mask, 100baseT_Half);
5912 phylink_set(mask, 100baseT_Full);
5913 phylink_set(mask, 1000baseT_Full);
5914 phylink_set(mask, 1000baseX_Full);
5915 if (state->interface != PHY_INTERFACE_MODE_NA)
5916 break;
5917 fallthrough;
5918 case PHY_INTERFACE_MODE_1000BASEX:
5919 case PHY_INTERFACE_MODE_2500BASEX:
5920 if (port->comphy ||
5921 state->interface != PHY_INTERFACE_MODE_2500BASEX) {
5922 phylink_set(mask, 1000baseT_Full);
5923 phylink_set(mask, 1000baseX_Full);
5924 }
5925 if (port->comphy ||
5926 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
5927 phylink_set(mask, 2500baseT_Full);
5928 phylink_set(mask, 2500baseX_Full);
5929 }
5930 break;
5931 default:
5932 goto empty_set;
5933 }
5934
5935 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
5936 bitmap_and(state->advertising, state->advertising, mask,
5937 __ETHTOOL_LINK_MODE_MASK_NBITS);
5938
5939 phylink_helper_basex_speed(state);
5940 return;
5941
5942 empty_set:
5943 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
5944 }
5945
5946 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
5947 const struct phylink_link_state *state)
5948 {
5949 u32 val;
5950
5951 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
5952 MVPP22_XLG_CTRL0_MAC_RESET_DIS,
5953 MVPP22_XLG_CTRL0_MAC_RESET_DIS);
5954 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
5955 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
5956 MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
5957 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
5958 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
5959
5960 /* Wait for reset to deassert */
5961 do {
5962 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5963 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
5964 }
5965
5966 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
5967 const struct phylink_link_state *state)
5968 {
5969 u32 old_ctrl0, ctrl0;
5970 u32 old_ctrl2, ctrl2;
5971 u32 old_ctrl4, ctrl4;
5972
5973 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
5974 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
5975 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
5976
5977 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
5978 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
5979
5980 /* Configure port type */
5981 if (phy_interface_mode_is_8023z(state->interface)) {
5982 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
5983 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
5984 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
5985 MVPP22_CTRL4_DP_CLK_SEL |
5986 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
5987 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
5988 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
5989 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
5990 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
5991 MVPP22_CTRL4_DP_CLK_SEL |
5992 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
5993 } else if (phy_interface_mode_is_rgmii(state->interface)) {
5994 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
5995 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
5996 MVPP22_CTRL4_SYNC_BYPASS_DIS |
5997 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
5998 }
5999
6000 /* Configure negotiation style */
6001 if (!phylink_autoneg_inband(mode)) {
6002 /* Phy or fixed speed - no in-band AN, nothing to do, leave the
6003 * configured speed, duplex and flow control as-is.
6004 */
6005 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6006 /* SGMII in-band mode receives the speed and duplex from
6007 * the PHY. Flow control information is not received. */
6008 } else if (phy_interface_mode_is_8023z(state->interface)) {
6009 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
6010 * they negotiate duplex: they are always operating with a fixed
6011 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
6012 * speed and full duplex here.
6013 */
6014 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
6015 }
6016
6017 if (old_ctrl0 != ctrl0)
6018 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
6019 if (old_ctrl2 != ctrl2)
6020 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
6021 if (old_ctrl4 != ctrl4)
6022 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
6023 }
6024
6025 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
6026 phy_interface_t interface)
6027 {
6028 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6029
6030 /* Check for invalid configuration */
6031 if (mvpp2_is_xlg(interface) && port->gop_id != 0) {
6032 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
6033 return -EINVAL;
6034 }
6035
6036 if (port->phy_interface != interface ||
6037 phylink_autoneg_inband(mode)) {
6038 /* Force the link down when changing the interface or if in
6039 * in-band mode to ensure we do not change the configuration
6040 * while the hardware is indicating link is up. We force both
6041 * XLG and GMAC down to ensure that they're both in a known
6042 * state.
6043 */
6044 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6045 MVPP2_GMAC_FORCE_LINK_PASS |
6046 MVPP2_GMAC_FORCE_LINK_DOWN,
6047 MVPP2_GMAC_FORCE_LINK_DOWN);
6048
6049 if (mvpp2_port_supports_xlg(port))
6050 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6051 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6052 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN,
6053 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN);
6054 }
6055
6056 /* Make sure the port is disabled when reconfiguring the mode */
6057 mvpp2_port_disable(port);
6058
6059 if (port->phy_interface != interface) {
6060 /* Place GMAC into reset */
6061 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6062 MVPP2_GMAC_PORT_RESET_MASK,
6063 MVPP2_GMAC_PORT_RESET_MASK);
6064
6065 if (port->priv->hw_version == MVPP22) {
6066 mvpp22_gop_mask_irq(port);
6067
6068 phy_power_off(port->comphy);
6069 }
6070 }
6071
6072 /* Select the appropriate PCS operations depending on the
6073 * configured interface mode. We will only switch to a mode
6074 * that the validate() checks have already passed.
6075 */
6076 if (mvpp2_is_xlg(interface))
6077 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops;
6078 else
6079 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops;
6080
6081 return 0;
6082 }
6083
6084 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
6085 phy_interface_t interface)
6086 {
6087 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6088 int ret;
6089
6090 ret = mvpp2__mac_prepare(config, mode, interface);
6091 if (ret == 0)
6092 phylink_set_pcs(port->phylink, &port->phylink_pcs);
6093
6094 return ret;
6095 }
6096
6097 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
6098 const struct phylink_link_state *state)
6099 {
6100 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6101
6102 /* mac (re)configuration */
6103 if (mvpp2_is_xlg(state->interface))
6104 mvpp2_xlg_config(port, mode, state);
6105 else if (phy_interface_mode_is_rgmii(state->interface) ||
6106 phy_interface_mode_is_8023z(state->interface) ||
6107 state->interface == PHY_INTERFACE_MODE_SGMII)
6108 mvpp2_gmac_config(port, mode, state);
6109
6110 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
6111 mvpp2_port_loopback_set(port, state);
6112 }
6113
6114 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
6115 phy_interface_t interface)
6116 {
6117 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6118
6119 if (port->priv->hw_version == MVPP22 &&
6120 port->phy_interface != interface) {
6121 port->phy_interface = interface;
6122
6123 /* Reconfigure the serdes lanes */
6124 mvpp22_mode_reconfigure(port);
6125
6126 /* Unmask interrupts */
6127 mvpp22_gop_unmask_irq(port);
6128 }
6129
6130 if (!mvpp2_is_xlg(interface)) {
6131 /* Release GMAC reset and wait */
6132 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6133 MVPP2_GMAC_PORT_RESET_MASK, 0);
6134
6135 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
6136 MVPP2_GMAC_PORT_RESET_MASK)
6137 continue;
6138 }
6139
6140 mvpp2_port_enable(port);
6141
6142 /* Allow the link to come up if in in-band mode, otherwise the
6143 * link is forced via mac_link_down()/mac_link_up()
6144 */
6145 if (phylink_autoneg_inband(mode)) {
6146 if (mvpp2_is_xlg(interface))
6147 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6148 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6149 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0);
6150 else
6151 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6152 MVPP2_GMAC_FORCE_LINK_PASS |
6153 MVPP2_GMAC_FORCE_LINK_DOWN, 0);
6154 }
6155
6156 return 0;
6157 }
6158
6159 static void mvpp2_mac_link_up(struct phylink_config *config,
6160 struct phy_device *phy,
6161 unsigned int mode, phy_interface_t interface,
6162 int speed, int duplex,
6163 bool tx_pause, bool rx_pause)
6164 {
6165 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6166 u32 val;
6167
6168 if (mvpp2_is_xlg(interface)) {
6169 if (!phylink_autoneg_inband(mode)) {
6170 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6171 if (tx_pause)
6172 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
6173 if (rx_pause)
6174 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
6175
6176 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6177 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
6178 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6179 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
6180 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
6181 }
6182 } else {
6183 if (!phylink_autoneg_inband(mode)) {
6184 val = MVPP2_GMAC_FORCE_LINK_PASS;
6185
6186 if (speed == SPEED_1000 || speed == SPEED_2500)
6187 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
6188 else if (speed == SPEED_100)
6189 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
6190
6191 if (duplex == DUPLEX_FULL)
6192 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6193
6194 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6195 MVPP2_GMAC_FORCE_LINK_DOWN |
6196 MVPP2_GMAC_FORCE_LINK_PASS |
6197 MVPP2_GMAC_CONFIG_MII_SPEED |
6198 MVPP2_GMAC_CONFIG_GMII_SPEED |
6199 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
6200 }
6201
6202 /* We can always update the flow control enable bits;
6203 * these will only be effective if flow control AN
6204 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
6205 */
6206 val = 0;
6207 if (tx_pause)
6208 val |= MVPP22_CTRL4_TX_FC_EN;
6209 if (rx_pause)
6210 val |= MVPP22_CTRL4_RX_FC_EN;
6211
6212 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
6213 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
6214 val);
6215 }
6216
6217 mvpp2_port_enable(port);
6218
6219 mvpp2_egress_enable(port);
6220 mvpp2_ingress_enable(port);
6221 netif_tx_wake_all_queues(port->dev);
6222 }
6223
6224 static void mvpp2_mac_link_down(struct phylink_config *config,
6225 unsigned int mode, phy_interface_t interface)
6226 {
6227 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6228 u32 val;
6229
6230 if (!phylink_autoneg_inband(mode)) {
6231 if (mvpp2_is_xlg(interface)) {
6232 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6233 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6234 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
6235 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
6236 } else {
6237 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6238 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
6239 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
6240 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6241 }
6242 }
6243
6244 netif_tx_stop_all_queues(port->dev);
6245 mvpp2_egress_disable(port);
6246 mvpp2_ingress_disable(port);
6247
6248 mvpp2_port_disable(port);
6249 }
6250
6251 static const struct phylink_mac_ops mvpp2_phylink_ops = {
6252 .validate = mvpp2_phylink_validate,
6253 .mac_prepare = mvpp2_mac_prepare,
6254 .mac_config = mvpp2_mac_config,
6255 .mac_finish = mvpp2_mac_finish,
6256 .mac_link_up = mvpp2_mac_link_up,
6257 .mac_link_down = mvpp2_mac_link_down,
6258 };
6259
6260 /* Work-around for ACPI */
6261 static void mvpp2_acpi_start(struct mvpp2_port *port)
6262 {
6263 /* Phylink isn't used as of now for ACPI, so the MAC has to be
6264 * configured manually when the interface is started. This will
6265 * be removed as soon as the phylink ACPI support lands in.
6266 */
6267 struct phylink_link_state state = {
6268 .interface = port->phy_interface,
6269 };
6270 mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND,
6271 port->phy_interface);
6272 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
6273 port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
6274 port->phy_interface,
6275 state.advertising, false);
6276 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
6277 port->phy_interface);
6278 mvpp2_mac_link_up(&port->phylink_config, NULL,
6279 MLO_AN_INBAND, port->phy_interface,
6280 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
6281 }
6282
6283 /* Ports initialization */
6284 static int mvpp2_port_probe(struct platform_device *pdev,
6285 struct fwnode_handle *port_fwnode,
6286 struct mvpp2 *priv)
6287 {
6288 struct phy *comphy = NULL;
6289 struct mvpp2_port *port;
6290 struct mvpp2_port_pcpu *port_pcpu;
6291 struct device_node *port_node = to_of_node(port_fwnode);
6292 netdev_features_t features;
6293 struct net_device *dev;
6294 struct phylink *phylink;
6295 char *mac_from = "";
6296 unsigned int ntxqs, nrxqs, thread;
6297 unsigned long flags = 0;
6298 bool has_tx_irqs;
6299 u32 id;
6300 int phy_mode;
6301 int err, i;
6302
6303 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
6304 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
6305 dev_err(&pdev->dev,
6306 "not enough IRQs to support multi queue mode\n");
6307 return -EINVAL;
6308 }
6309
6310 ntxqs = MVPP2_MAX_TXQ;
6311 nrxqs = mvpp2_get_nrxqs(priv);
6312
6313 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
6314 if (!dev)
6315 return -ENOMEM;
6316
6317 phy_mode = fwnode_get_phy_mode(port_fwnode);
6318 if (phy_mode < 0) {
6319 dev_err(&pdev->dev, "incorrect phy mode\n");
6320 err = phy_mode;
6321 goto err_free_netdev;
6322 }
6323
6324 /*
6325 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
6326 * Existing usage of 10GBASE-KR is not correct; no backplane
6327 * negotiation is done, and this driver does not actually support
6328 * 10GBASE-KR.
6329 */
6330 if (phy_mode == PHY_INTERFACE_MODE_10GKR)
6331 phy_mode = PHY_INTERFACE_MODE_10GBASER;
6332
6333 if (port_node) {
6334 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
6335 if (IS_ERR(comphy)) {
6336 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
6337 err = -EPROBE_DEFER;
6338 goto err_free_netdev;
6339 }
6340 comphy = NULL;
6341 }
6342 }
6343
6344 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
6345 err = -EINVAL;
6346 dev_err(&pdev->dev, "missing port-id value\n");
6347 goto err_free_netdev;
6348 }
6349
6350 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
6351 dev->watchdog_timeo = 5 * HZ;
6352 dev->netdev_ops = &mvpp2_netdev_ops;
6353 dev->ethtool_ops = &mvpp2_eth_tool_ops;
6354
6355 port = netdev_priv(dev);
6356 port->dev = dev;
6357 port->fwnode = port_fwnode;
6358 port->has_phy = !!of_find_property(port_node, "phy", NULL);
6359 port->ntxqs = ntxqs;
6360 port->nrxqs = nrxqs;
6361 port->priv = priv;
6362 port->has_tx_irqs = has_tx_irqs;
6363 port->flags = flags;
6364
6365 err = mvpp2_queue_vectors_init(port, port_node);
6366 if (err)
6367 goto err_free_netdev;
6368
6369 if (port_node)
6370 port->port_irq = of_irq_get_byname(port_node, "link");
6371 else
6372 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
6373 if (port->port_irq == -EPROBE_DEFER) {
6374 err = -EPROBE_DEFER;
6375 goto err_deinit_qvecs;
6376 }
6377 if (port->port_irq <= 0)
6378 /* the link irq is optional */
6379 port->port_irq = 0;
6380
6381 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
6382 port->flags |= MVPP2_F_LOOPBACK;
6383
6384 port->id = id;
6385 if (priv->hw_version == MVPP21)
6386 port->first_rxq = port->id * port->nrxqs;
6387 else
6388 port->first_rxq = port->id * priv->max_port_rxqs;
6389
6390 port->of_node = port_node;
6391 port->phy_interface = phy_mode;
6392 port->comphy = comphy;
6393
6394 if (priv->hw_version == MVPP21) {
6395 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
6396 if (IS_ERR(port->base)) {
6397 err = PTR_ERR(port->base);
6398 goto err_free_irq;
6399 }
6400
6401 port->stats_base = port->priv->lms_base +
6402 MVPP21_MIB_COUNTERS_OFFSET +
6403 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
6404 } else {
6405 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
6406 &port->gop_id)) {
6407 err = -EINVAL;
6408 dev_err(&pdev->dev, "missing gop-port-id value\n");
6409 goto err_deinit_qvecs;
6410 }
6411
6412 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
6413 port->stats_base = port->priv->iface_base +
6414 MVPP22_MIB_COUNTERS_OFFSET +
6415 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
6416
6417 /* We may want a property to describe whether we should use
6418 * MAC hardware timestamping.
6419 */
6420 if (priv->tai)
6421 port->hwtstamp = true;
6422 }
6423
6424 /* Alloc per-cpu and ethtool stats */
6425 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6426 if (!port->stats) {
6427 err = -ENOMEM;
6428 goto err_free_irq;
6429 }
6430
6431 port->ethtool_stats = devm_kcalloc(&pdev->dev,
6432 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
6433 sizeof(u64), GFP_KERNEL);
6434 if (!port->ethtool_stats) {
6435 err = -ENOMEM;
6436 goto err_free_stats;
6437 }
6438
6439 mutex_init(&port->gather_stats_lock);
6440 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6441
6442 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6443
6444 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6445 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6446 SET_NETDEV_DEV(dev, &pdev->dev);
6447
6448 err = mvpp2_port_init(port);
6449 if (err < 0) {
6450 dev_err(&pdev->dev, "failed to init port %d\n", id);
6451 goto err_free_stats;
6452 }
6453
6454 mvpp2_port_periodic_xon_disable(port);
6455
6456 mvpp2_mac_reset_assert(port);
6457 mvpp22_pcs_reset_assert(port);
6458
6459 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6460 if (!port->pcpu) {
6461 err = -ENOMEM;
6462 goto err_free_txq_pcpu;
6463 }
6464
6465 if (!port->has_tx_irqs) {
6466 for (thread = 0; thread < priv->nthreads; thread++) {
6467 port_pcpu = per_cpu_ptr(port->pcpu, thread);
6468
6469 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6470 HRTIMER_MODE_REL_PINNED_SOFT);
6471 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6472 port_pcpu->timer_scheduled = false;
6473 port_pcpu->dev = dev;
6474 }
6475 }
6476
6477 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6478 NETIF_F_TSO;
6479 dev->features = features | NETIF_F_RXCSUM;
6480 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6481 NETIF_F_HW_VLAN_CTAG_FILTER;
6482
6483 if (mvpp22_rss_is_supported()) {
6484 dev->hw_features |= NETIF_F_RXHASH;
6485 dev->features |= NETIF_F_NTUPLE;
6486 }
6487
6488 if (!port->priv->percpu_pools)
6489 mvpp2_set_hw_csum(port, port->pool_long->id);
6490
6491 dev->vlan_features |= features;
6492 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
6493 dev->priv_flags |= IFF_UNICAST_FLT;
6494
6495 /* MTU range: 68 - 9704 */
6496 dev->min_mtu = ETH_MIN_MTU;
6497 /* 9704 == 9728 - 20 and rounding to 8 */
6498 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6499 dev->dev.of_node = port_node;
6500
6501 /* Phylink isn't used w/ ACPI as of now */
6502 if (port_node) {
6503 port->phylink_config.dev = &dev->dev;
6504 port->phylink_config.type = PHYLINK_NETDEV;
6505
6506 phylink = phylink_create(&port->phylink_config, port_fwnode,
6507 phy_mode, &mvpp2_phylink_ops);
6508 if (IS_ERR(phylink)) {
6509 err = PTR_ERR(phylink);
6510 goto err_free_port_pcpu;
6511 }
6512 port->phylink = phylink;
6513 } else {
6514 port->phylink = NULL;
6515 }
6516
6517 /* Cycle the comphy to power it down, saving 270mW per port -
6518 * don't worry about an error powering it up. When the comphy
6519 * driver does this, we can remove this code.
6520 */
6521 if (port->comphy) {
6522 err = mvpp22_comphy_init(port);
6523 if (err == 0)
6524 phy_power_off(port->comphy);
6525 }
6526
6527 err = register_netdev(dev);
6528 if (err < 0) {
6529 dev_err(&pdev->dev, "failed to register netdev\n");
6530 goto err_phylink;
6531 }
6532 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6533
6534 priv->port_list[priv->port_count++] = port;
6535
6536 return 0;
6537
6538 err_phylink:
6539 if (port->phylink)
6540 phylink_destroy(port->phylink);
6541 err_free_port_pcpu:
6542 free_percpu(port->pcpu);
6543 err_free_txq_pcpu:
6544 for (i = 0; i < port->ntxqs; i++)
6545 free_percpu(port->txqs[i]->pcpu);
6546 err_free_stats:
6547 free_percpu(port->stats);
6548 err_free_irq:
6549 if (port->port_irq)
6550 irq_dispose_mapping(port->port_irq);
6551 err_deinit_qvecs:
6552 mvpp2_queue_vectors_deinit(port);
6553 err_free_netdev:
6554 free_netdev(dev);
6555 return err;
6556 }
6557
6558 /* Ports removal routine */
6559 static void mvpp2_port_remove(struct mvpp2_port *port)
6560 {
6561 int i;
6562
6563 unregister_netdev(port->dev);
6564 if (port->phylink)
6565 phylink_destroy(port->phylink);
6566 free_percpu(port->pcpu);
6567 free_percpu(port->stats);
6568 for (i = 0; i < port->ntxqs; i++)
6569 free_percpu(port->txqs[i]->pcpu);
6570 mvpp2_queue_vectors_deinit(port);
6571 if (port->port_irq)
6572 irq_dispose_mapping(port->port_irq);
6573 free_netdev(port->dev);
6574 }
6575
6576 /* Initialize decoding windows */
6577 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
6578 struct mvpp2 *priv)
6579 {
6580 u32 win_enable;
6581 int i;
6582
6583 for (i = 0; i < 6; i++) {
6584 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
6585 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
6586
6587 if (i < 4)
6588 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
6589 }
6590
6591 win_enable = 0;
6592
6593 for (i = 0; i < dram->num_cs; i++) {
6594 const struct mbus_dram_window *cs = dram->cs + i;
6595
6596 mvpp2_write(priv, MVPP2_WIN_BASE(i),
6597 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
6598 dram->mbus_dram_target_id);
6599
6600 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
6601 (cs->size - 1) & 0xffff0000);
6602
6603 win_enable |= (1 << i);
6604 }
6605
6606 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
6607 }
6608
6609 /* Initialize Rx FIFO's */
6610 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
6611 {
6612 int port;
6613
6614 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
6615 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
6616 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
6617 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
6618 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
6619 }
6620
6621 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6622 MVPP2_RX_FIFO_PORT_MIN_PKT);
6623 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6624 }
6625
6626 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
6627 {
6628 int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size);
6629
6630 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);
6631 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
6632 }
6633
6634 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2.
6635 * 4kB fixed space must be assigned for the loopback port.
6636 * Redistribute remaining avialable 44kB space among all active ports.
6637 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
6638 * SGMII link.
6639 */
6640 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
6641 {
6642 int remaining_ports_count;
6643 unsigned long port_map;
6644 int size_remainder;
6645 int port, size;
6646
6647 /* The loopback requires fixed 4kB of the FIFO space assignment. */
6648 mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
6649 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
6650 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
6651
6652 /* Set RX FIFO size to 0 for inactive ports. */
6653 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
6654 mvpp22_rx_fifo_set_hw(priv, port, 0);
6655
6656 /* Assign remaining RX FIFO space among all active ports. */
6657 size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB;
6658 remaining_ports_count = hweight_long(port_map);
6659
6660 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
6661 if (remaining_ports_count == 1)
6662 size = size_remainder;
6663 else if (port == 0)
6664 size = max(size_remainder / remaining_ports_count,
6665 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
6666 else if (port == 1)
6667 size = max(size_remainder / remaining_ports_count,
6668 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
6669 else
6670 size = size_remainder / remaining_ports_count;
6671
6672 size_remainder -= size;
6673 remaining_ports_count--;
6674
6675 mvpp22_rx_fifo_set_hw(priv, port, size);
6676 }
6677
6678 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6679 MVPP2_RX_FIFO_PORT_MIN_PKT);
6680 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6681 }
6682
6683 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
6684 {
6685 int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
6686
6687 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
6688 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
6689 }
6690
6691 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2.
6692 * 3kB fixed space must be assigned for the loopback port.
6693 * Redistribute remaining avialable 16kB space among all active ports.
6694 * The 10G interface should use 10kB (which is maximum possible size
6695 * per single port).
6696 */
6697 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
6698 {
6699 int remaining_ports_count;
6700 unsigned long port_map;
6701 int size_remainder;
6702 int port, size;
6703
6704 /* The loopback requires fixed 3kB of the FIFO space assignment. */
6705 mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
6706 MVPP22_TX_FIFO_DATA_SIZE_3KB);
6707 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
6708
6709 /* Set TX FIFO size to 0 for inactive ports. */
6710 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
6711 mvpp22_tx_fifo_set_hw(priv, port, 0);
6712
6713 /* Assign remaining TX FIFO space among all active ports. */
6714 size_remainder = MVPP22_TX_FIFO_DATA_SIZE_16KB;
6715 remaining_ports_count = hweight_long(port_map);
6716
6717 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
6718 if (remaining_ports_count == 1)
6719 size = min(size_remainder,
6720 MVPP22_TX_FIFO_DATA_SIZE_10KB);
6721 else if (port == 0)
6722 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
6723 else
6724 size = size_remainder / remaining_ports_count;
6725
6726 size_remainder -= size;
6727 remaining_ports_count--;
6728
6729 mvpp22_tx_fifo_set_hw(priv, port, size);
6730 }
6731 }
6732
6733 static void mvpp2_axi_init(struct mvpp2 *priv)
6734 {
6735 u32 val, rdval, wrval;
6736
6737 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
6738
6739 /* AXI Bridge Configuration */
6740
6741 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
6742 << MVPP22_AXI_ATTR_CACHE_OFFS;
6743 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6744 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
6745
6746 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
6747 << MVPP22_AXI_ATTR_CACHE_OFFS;
6748 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6749 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
6750
6751 /* BM */
6752 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
6753 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
6754
6755 /* Descriptors */
6756 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
6757 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
6758 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
6759 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
6760
6761 /* Buffer Data */
6762 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
6763 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
6764
6765 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
6766 << MVPP22_AXI_CODE_CACHE_OFFS;
6767 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
6768 << MVPP22_AXI_CODE_DOMAIN_OFFS;
6769 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
6770 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
6771
6772 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
6773 << MVPP22_AXI_CODE_CACHE_OFFS;
6774 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6775 << MVPP22_AXI_CODE_DOMAIN_OFFS;
6776
6777 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
6778
6779 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
6780 << MVPP22_AXI_CODE_CACHE_OFFS;
6781 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6782 << MVPP22_AXI_CODE_DOMAIN_OFFS;
6783
6784 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
6785 }
6786
6787 /* Initialize network controller common part HW */
6788 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
6789 {
6790 const struct mbus_dram_target_info *dram_target_info;
6791 int err, i;
6792 u32 val;
6793
6794 /* MBUS windows configuration */
6795 dram_target_info = mv_mbus_dram_info();
6796 if (dram_target_info)
6797 mvpp2_conf_mbus_windows(dram_target_info, priv);
6798
6799 if (priv->hw_version == MVPP22)
6800 mvpp2_axi_init(priv);
6801
6802 /* Disable HW PHY polling */
6803 if (priv->hw_version == MVPP21) {
6804 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6805 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
6806 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6807 } else {
6808 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
6809 val &= ~MVPP22_SMI_POLLING_EN;
6810 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
6811 }
6812
6813 /* Allocate and initialize aggregated TXQs */
6814 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
6815 sizeof(*priv->aggr_txqs),
6816 GFP_KERNEL);
6817 if (!priv->aggr_txqs)
6818 return -ENOMEM;
6819
6820 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6821 priv->aggr_txqs[i].id = i;
6822 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
6823 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
6824 if (err < 0)
6825 return err;
6826 }
6827
6828 /* Fifo Init */
6829 if (priv->hw_version == MVPP21) {
6830 mvpp2_rx_fifo_init(priv);
6831 } else {
6832 mvpp22_rx_fifo_init(priv);
6833 mvpp22_tx_fifo_init(priv);
6834 }
6835
6836 if (priv->hw_version == MVPP21)
6837 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
6838 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
6839
6840 /* Allow cache snoop when transmiting packets */
6841 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
6842
6843 /* Buffer Manager initialization */
6844 err = mvpp2_bm_init(&pdev->dev, priv);
6845 if (err < 0)
6846 return err;
6847
6848 /* Parser default initialization */
6849 err = mvpp2_prs_default_init(pdev, priv);
6850 if (err < 0)
6851 return err;
6852
6853 /* Classifier default initialization */
6854 mvpp2_cls_init(priv);
6855
6856 return 0;
6857 }
6858
6859 static int mvpp2_probe(struct platform_device *pdev)
6860 {
6861 const struct acpi_device_id *acpi_id;
6862 struct fwnode_handle *fwnode = pdev->dev.fwnode;
6863 struct fwnode_handle *port_fwnode;
6864 struct mvpp2 *priv;
6865 struct resource *res;
6866 void __iomem *base;
6867 int i, shared;
6868 int err;
6869
6870 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
6871 if (!priv)
6872 return -ENOMEM;
6873
6874 if (has_acpi_companion(&pdev->dev)) {
6875 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
6876 &pdev->dev);
6877 if (!acpi_id)
6878 return -EINVAL;
6879 priv->hw_version = (unsigned long)acpi_id->driver_data;
6880 } else {
6881 priv->hw_version =
6882 (unsigned long)of_device_get_match_data(&pdev->dev);
6883 }
6884
6885 /* multi queue mode isn't supported on PPV2.1, fallback to single
6886 * mode
6887 */
6888 if (priv->hw_version == MVPP21)
6889 queue_mode = MVPP2_QDIST_SINGLE_MODE;
6890
6891 base = devm_platform_ioremap_resource(pdev, 0);
6892 if (IS_ERR(base))
6893 return PTR_ERR(base);
6894
6895 if (priv->hw_version == MVPP21) {
6896 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
6897 if (IS_ERR(priv->lms_base))
6898 return PTR_ERR(priv->lms_base);
6899 } else {
6900 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
6901 if (has_acpi_companion(&pdev->dev)) {
6902 /* In case the MDIO memory region is declared in
6903 * the ACPI, it can already appear as 'in-use'
6904 * in the OS. Because it is overlapped by second
6905 * region of the network controller, make
6906 * sure it is released, before requesting it again.
6907 * The care is taken by mvpp2 driver to avoid
6908 * concurrent access to this memory region.
6909 */
6910 release_resource(res);
6911 }
6912 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
6913 if (IS_ERR(priv->iface_base))
6914 return PTR_ERR(priv->iface_base);
6915 }
6916
6917 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
6918 priv->sysctrl_base =
6919 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
6920 "marvell,system-controller");
6921 if (IS_ERR(priv->sysctrl_base))
6922 /* The system controller regmap is optional for dt
6923 * compatibility reasons. When not provided, the
6924 * configuration of the GoP relies on the
6925 * firmware/bootloader.
6926 */
6927 priv->sysctrl_base = NULL;
6928 }
6929
6930 if (priv->hw_version == MVPP22 &&
6931 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
6932 priv->percpu_pools = 1;
6933
6934 mvpp2_setup_bm_pool();
6935
6936
6937 priv->nthreads = min_t(unsigned int, num_present_cpus(),
6938 MVPP2_MAX_THREADS);
6939
6940 shared = num_present_cpus() - priv->nthreads;
6941 if (shared > 0)
6942 bitmap_fill(&priv->lock_map,
6943 min_t(int, shared, MVPP2_MAX_THREADS));
6944
6945 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6946 u32 addr_space_sz;
6947
6948 addr_space_sz = (priv->hw_version == MVPP21 ?
6949 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
6950 priv->swth_base[i] = base + i * addr_space_sz;
6951 }
6952
6953 if (priv->hw_version == MVPP21)
6954 priv->max_port_rxqs = 8;
6955 else
6956 priv->max_port_rxqs = 32;
6957
6958 if (dev_of_node(&pdev->dev)) {
6959 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
6960 if (IS_ERR(priv->pp_clk))
6961 return PTR_ERR(priv->pp_clk);
6962 err = clk_prepare_enable(priv->pp_clk);
6963 if (err < 0)
6964 return err;
6965
6966 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
6967 if (IS_ERR(priv->gop_clk)) {
6968 err = PTR_ERR(priv->gop_clk);
6969 goto err_pp_clk;
6970 }
6971 err = clk_prepare_enable(priv->gop_clk);
6972 if (err < 0)
6973 goto err_pp_clk;
6974
6975 if (priv->hw_version == MVPP22) {
6976 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
6977 if (IS_ERR(priv->mg_clk)) {
6978 err = PTR_ERR(priv->mg_clk);
6979 goto err_gop_clk;
6980 }
6981
6982 err = clk_prepare_enable(priv->mg_clk);
6983 if (err < 0)
6984 goto err_gop_clk;
6985
6986 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
6987 if (IS_ERR(priv->mg_core_clk)) {
6988 priv->mg_core_clk = NULL;
6989 } else {
6990 err = clk_prepare_enable(priv->mg_core_clk);
6991 if (err < 0)
6992 goto err_mg_clk;
6993 }
6994 }
6995
6996 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
6997 if (IS_ERR(priv->axi_clk)) {
6998 err = PTR_ERR(priv->axi_clk);
6999 if (err == -EPROBE_DEFER)
7000 goto err_mg_core_clk;
7001 priv->axi_clk = NULL;
7002 } else {
7003 err = clk_prepare_enable(priv->axi_clk);
7004 if (err < 0)
7005 goto err_mg_core_clk;
7006 }
7007
7008 /* Get system's tclk rate */
7009 priv->tclk = clk_get_rate(priv->pp_clk);
7010 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
7011 &priv->tclk)) {
7012 dev_err(&pdev->dev, "missing clock-frequency value\n");
7013 return -EINVAL;
7014 }
7015
7016 if (priv->hw_version == MVPP22) {
7017 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
7018 if (err)
7019 goto err_axi_clk;
7020 /* Sadly, the BM pools all share the same register to
7021 * store the high 32 bits of their address. So they
7022 * must all have the same high 32 bits, which forces
7023 * us to restrict coherent memory to DMA_BIT_MASK(32).
7024 */
7025 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7026 if (err)
7027 goto err_axi_clk;
7028 }
7029
7030 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */
7031 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7032 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i))
7033 priv->port_map |= BIT(i);
7034 }
7035
7036 /* Initialize network controller */
7037 err = mvpp2_init(pdev, priv);
7038 if (err < 0) {
7039 dev_err(&pdev->dev, "failed to initialize controller\n");
7040 goto err_axi_clk;
7041 }
7042
7043 err = mvpp22_tai_probe(&pdev->dev, priv);
7044 if (err < 0)
7045 goto err_axi_clk;
7046
7047 /* Initialize ports */
7048 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7049 err = mvpp2_port_probe(pdev, port_fwnode, priv);
7050 if (err < 0)
7051 goto err_port_probe;
7052 }
7053
7054 if (priv->port_count == 0) {
7055 dev_err(&pdev->dev, "no ports enabled\n");
7056 err = -ENODEV;
7057 goto err_axi_clk;
7058 }
7059
7060 /* Statistics must be gathered regularly because some of them (like
7061 * packets counters) are 32-bit registers and could overflow quite
7062 * quickly. For instance, a 10Gb link used at full bandwidth with the
7063 * smallest packets (64B) will overflow a 32-bit counter in less than
7064 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
7065 */
7066 snprintf(priv->queue_name, sizeof(priv->queue_name),
7067 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
7068 priv->port_count > 1 ? "+" : "");
7069 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
7070 if (!priv->stats_queue) {
7071 err = -ENOMEM;
7072 goto err_port_probe;
7073 }
7074
7075 mvpp2_dbgfs_init(priv, pdev->name);
7076
7077 platform_set_drvdata(pdev, priv);
7078 return 0;
7079
7080 err_port_probe:
7081 i = 0;
7082 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7083 if (priv->port_list[i])
7084 mvpp2_port_remove(priv->port_list[i]);
7085 i++;
7086 }
7087 err_axi_clk:
7088 clk_disable_unprepare(priv->axi_clk);
7089
7090 err_mg_core_clk:
7091 if (priv->hw_version == MVPP22)
7092 clk_disable_unprepare(priv->mg_core_clk);
7093 err_mg_clk:
7094 if (priv->hw_version == MVPP22)
7095 clk_disable_unprepare(priv->mg_clk);
7096 err_gop_clk:
7097 clk_disable_unprepare(priv->gop_clk);
7098 err_pp_clk:
7099 clk_disable_unprepare(priv->pp_clk);
7100 return err;
7101 }
7102
7103 static int mvpp2_remove(struct platform_device *pdev)
7104 {
7105 struct mvpp2 *priv = platform_get_drvdata(pdev);
7106 struct fwnode_handle *fwnode = pdev->dev.fwnode;
7107 int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
7108 struct fwnode_handle *port_fwnode;
7109
7110 mvpp2_dbgfs_cleanup(priv);
7111
7112 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7113 if (priv->port_list[i]) {
7114 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
7115 mvpp2_port_remove(priv->port_list[i]);
7116 }
7117 i++;
7118 }
7119
7120 destroy_workqueue(priv->stats_queue);
7121
7122 if (priv->percpu_pools)
7123 poolnum = mvpp2_get_nrxqs(priv) * 2;
7124
7125 for (i = 0; i < poolnum; i++) {
7126 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
7127
7128 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
7129 }
7130
7131 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7132 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
7133
7134 dma_free_coherent(&pdev->dev,
7135 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
7136 aggr_txq->descs,
7137 aggr_txq->descs_dma);
7138 }
7139
7140 if (is_acpi_node(port_fwnode))
7141 return 0;
7142
7143 clk_disable_unprepare(priv->axi_clk);
7144 clk_disable_unprepare(priv->mg_core_clk);
7145 clk_disable_unprepare(priv->mg_clk);
7146 clk_disable_unprepare(priv->pp_clk);
7147 clk_disable_unprepare(priv->gop_clk);
7148
7149 return 0;
7150 }
7151
7152 static const struct of_device_id mvpp2_match[] = {
7153 {
7154 .compatible = "marvell,armada-375-pp2",
7155 .data = (void *)MVPP21,
7156 },
7157 {
7158 .compatible = "marvell,armada-7k-pp22",
7159 .data = (void *)MVPP22,
7160 },
7161 { }
7162 };
7163 MODULE_DEVICE_TABLE(of, mvpp2_match);
7164
7165 #ifdef CONFIG_ACPI
7166 static const struct acpi_device_id mvpp2_acpi_match[] = {
7167 { "MRVL0110", MVPP22 },
7168 { },
7169 };
7170 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
7171 #endif
7172
7173 static struct platform_driver mvpp2_driver = {
7174 .probe = mvpp2_probe,
7175 .remove = mvpp2_remove,
7176 .driver = {
7177 .name = MVPP2_DRIVER_NAME,
7178 .of_match_table = mvpp2_match,
7179 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
7180 },
7181 };
7182
7183 module_platform_driver(mvpp2_driver);
7184
7185 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
7186 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
7187 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support