drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/spinlock.h>
  48 #include <net/devlink.h>
  49 #include <linux/rwsem.h>
  50
  51 #include <linux/mlx4/device.h>
  52 #include <linux/mlx4/driver.h>
  53 #include <linux/mlx4/doorbell.h>
  54 #include <linux/mlx4/cmd.h>
  55 #include "fw_qos.h"
  56
  57 #define DRV_NAME        "mlx4_core"
  58 #define DRV_VERSION     "4.0-0"
  59 #define DRV_NAME_FOR_FW         "Linux," DRV_NAME "," DRV_VERSION
  60
  61 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  62 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  63 #define MLX4_FS_NUM_OF_L2_ADDR          8
  64 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  65 #define MLX4_FS_NUM_MCG                 (1 << 17)
  66
  67 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
  68
  69 #define MLX4_QUERY_IF_STAT_RESET        BIT(31)
  70
  71 enum {
  72         MLX4_HCR_BASE           = 0x80680,
  73         MLX4_HCR_SIZE           = 0x0001c,
  74         MLX4_CLR_INT_SIZE       = 0x00008,
  75         MLX4_SLAVE_COMM_BASE    = 0x0,
  76         MLX4_COMM_PAGESIZE      = 0x1000,
  77         MLX4_CLOCK_SIZE         = 0x00008,
  78         MLX4_COMM_CHAN_CAPS     = 0x8,
  79         MLX4_COMM_CHAN_FLAGS    = 0xc
  80 };
  81
  82 enum {
  83         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
  84         MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
  85         MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
  86         MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
  87 };
  88
  89 enum {
  90         MLX4_NUM_PDS            = 1 << 15
  91 };
  92
  93 enum {
  94         MLX4_CMPT_TYPE_QP       = 0,
  95         MLX4_CMPT_TYPE_SRQ      = 1,
  96         MLX4_CMPT_TYPE_CQ       = 2,
  97         MLX4_CMPT_TYPE_EQ       = 3,
  98         MLX4_CMPT_NUM_TYPE
  99 };
 100
 101 enum {
 102         MLX4_CMPT_SHIFT         = 24,
 103         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 104 };
 105
 106 enum mlx4_mpt_state {
 107         MLX4_MPT_DISABLED = 0,
 108         MLX4_MPT_EN_HW,
 109         MLX4_MPT_EN_SW
 110 };
 111
 112 #define MLX4_COMM_TIME          10000
 113 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
 114 #define MLX4_COMM_CMD_NA_OP    0x0
 115
 116
 117 enum {
 118         MLX4_COMM_CMD_RESET,
 119         MLX4_COMM_CMD_VHCR0,
 120         MLX4_COMM_CMD_VHCR1,
 121         MLX4_COMM_CMD_VHCR2,
 122         MLX4_COMM_CMD_VHCR_EN,
 123         MLX4_COMM_CMD_VHCR_POST,
 124         MLX4_COMM_CMD_FLR = 254
 125 };
 126
 127 enum {
 128         MLX4_VF_SMI_DISABLED,
 129         MLX4_VF_SMI_ENABLED
 130 };
 131
 132 /*The flag indicates that the slave should delay the RESET cmd*/
 133 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 134 /*indicates how many retries will be done if we are in the middle of FLR*/
 135 #define NUM_OF_RESET_RETRIES    10
 136 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 137 enum mlx4_resource {
 138         RES_QP,
 139         RES_CQ,
 140         RES_SRQ,
 141         RES_XRCD,
 142         RES_MPT,
 143         RES_MTT,
 144         RES_MAC,
 145         RES_VLAN,
 146         RES_NPORT_ID,
 147         RES_COUNTER,
 148         RES_FS_RULE,
 149         RES_EQ,
 150         MLX4_NUM_OF_RESOURCE_TYPE
 151 };
 152
 153 enum mlx4_alloc_mode {
 154         RES_OP_RESERVE,
 155         RES_OP_RESERVE_AND_MAP,
 156         RES_OP_MAP_ICM,
 157 };
 158
 159 enum mlx4_res_tracker_free_type {
 160         RES_TR_FREE_ALL,
 161         RES_TR_FREE_SLAVES_ONLY,
 162         RES_TR_FREE_STRUCTS_ONLY,
 163 };
 164
 165 /*
 166  *Virtual HCR structures.
 167  * mlx4_vhcr is the sw representation, in machine endianness
 168  *
 169  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 170  * to FW to go through communication channel.
 171  * It is big endian, and has the same structure as the physical HCR
 172  * used by command interface
 173  */
 174 struct mlx4_vhcr {
 175         u64     in_param;
 176         u64     out_param;
 177         u32     in_modifier;
 178         u32     errno;
 179         u16     op;
 180         u16     token;
 181         u8      op_modifier;
 182         u8      e_bit;
 183 };
 184
 185 struct mlx4_vhcr_cmd {
 186         __be64 in_param;
 187         __be32 in_modifier;
 188         u32 reserved1;
 189         __be64 out_param;
 190         __be16 token;
 191         u16 reserved;
 192         u8 status;
 193         u8 flags;
 194         __be16 opcode;
 195 };
 196
 197 struct mlx4_cmd_info {
 198         u16 opcode;
 199         bool has_inbox;
 200         bool has_outbox;
 201         bool out_is_imm;
 202         bool encode_slave_id;
 203         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 204                       struct mlx4_cmd_mailbox *inbox);
 205         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 206                        struct mlx4_cmd_mailbox *inbox,
 207                        struct mlx4_cmd_mailbox *outbox,
 208                        struct mlx4_cmd_info *cmd);
 209 };
 210
 211 #ifdef CONFIG_MLX4_DEBUG
 212 extern int mlx4_debug_level;
 213 #else /* CONFIG_MLX4_DEBUG */
 214 #define mlx4_debug_level        (0)
 215 #endif /* CONFIG_MLX4_DEBUG */
 216
 217 #define mlx4_dbg(mdev, format, ...)                                     \
 218 do {                                                                    \
 219         if (mlx4_debug_level)                                           \
 220                 dev_printk(KERN_DEBUG,                                  \
 221                            &(mdev)->persist->pdev->dev, format,         \
 222                            ##__VA_ARGS__);                              \
 223 } while (0)
 224
 225 #define mlx4_err(mdev, format, ...)                                     \
 226         dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 227 #define mlx4_info(mdev, format, ...)                                    \
 228         dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 229 #define mlx4_warn(mdev, format, ...)                                    \
 230         dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 231
 232 extern int log_mtts_per_seg;
 233 extern int mlx4_internal_err_reset;
 234
 235 #define MLX4_MAX_NUM_SLAVES     (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
 236                                      MLX4_MFUNC_MAX))
 237 #define ALL_SLAVES 0xff
 238
 239 struct mlx4_bitmap {
 240         u32                     last;
 241         u32                     top;
 242         u32                     max;
 243         u32                     reserved_top;
 244         u32                     mask;
 245         u32                     avail;
 246         u32                     effective_len;
 247         spinlock_t              lock;
 248         unsigned long          *table;
 249 };
 250
 251 struct mlx4_buddy {
 252         unsigned long         **bits;
 253         unsigned int           *num_free;
 254         u32                     max_order;
 255         spinlock_t              lock;
 256 };
 257
 258 struct mlx4_icm;
 259
 260 struct mlx4_icm_table {
 261         u64                     virt;
 262         int                     num_icm;
 263         u32                     num_obj;
 264         int                     obj_size;
 265         int                     lowmem;
 266         int                     coherent;
 267         struct mutex            mutex;
 268         struct mlx4_icm       **icm;
 269 };
 270
 271 #define MLX4_MPT_FLAG_SW_OWNS       (0xfUL << 28)
 272 #define MLX4_MPT_FLAG_FREE          (0x3UL << 28)
 273 #define MLX4_MPT_FLAG_MIO           (1 << 17)
 274 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
 275 #define MLX4_MPT_FLAG_PHYSICAL      (1 <<  9)
 276 #define MLX4_MPT_FLAG_REGION        (1 <<  8)
 277
 278 #define MLX4_MPT_PD_MASK            (0x1FFFFUL)
 279 #define MLX4_MPT_PD_VF_MASK         (0xFE0000UL)
 280 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
 281 #define MLX4_MPT_PD_FLAG_RAE        (1 << 28)
 282 #define MLX4_MPT_PD_FLAG_EN_INV     (3 << 24)
 283
 284 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
 285
 286 #define MLX4_MPT_STATUS_SW              0xF0
 287 #define MLX4_MPT_STATUS_HW              0x00
 288
 289 #define MLX4_CQE_SIZE_MASK_STRIDE       0x3
 290 #define MLX4_EQE_SIZE_MASK_STRIDE       0x30
 291
 292 #define MLX4_EQ_ASYNC                   0
 293 #define MLX4_EQ_TO_CQ_VECTOR(vector)    ((vector) - \
 294                                          !!((int)(vector) >= MLX4_EQ_ASYNC))
 295 #define MLX4_CQ_TO_EQ_VECTOR(vector)    ((vector) + \
 296                                          !!((int)(vector) >= MLX4_EQ_ASYNC))
 297
 298 /*
 299  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 300  */
 301 struct mlx4_mpt_entry {
 302         __be32 flags;
 303         __be32 qpn;
 304         __be32 key;
 305         __be32 pd_flags;
 306         __be64 start;
 307         __be64 length;
 308         __be32 lkey;
 309         __be32 win_cnt;
 310         u8      reserved1[3];
 311         u8      mtt_rep;
 312         __be64 mtt_addr;
 313         __be32 mtt_sz;
 314         __be32 entity_size;
 315         __be32 first_byte_offset;
 316 } __packed;
 317
 318 /*
 319  * Must be packed because start is 64 bits but only aligned to 32 bits.
 320  */
 321 struct mlx4_eq_context {
 322         __be32                  flags;
 323         u16                     reserved1[3];
 324         __be16                  page_offset;
 325         u8                      log_eq_size;
 326         u8                      reserved2[4];
 327         u8                      eq_period;
 328         u8                      reserved3;
 329         u8                      eq_max_count;
 330         u8                      reserved4[3];
 331         u8                      intr;
 332         u8                      log_page_size;
 333         u8                      reserved5[2];
 334         u8                      mtt_base_addr_h;
 335         __be32                  mtt_base_addr_l;
 336         u32                     reserved6[2];
 337         __be32                  consumer_index;
 338         __be32                  producer_index;
 339         u32                     reserved7[4];
 340 };
 341
 342 struct mlx4_cq_context {
 343         __be32                  flags;
 344         u16                     reserved1[3];
 345         __be16                  page_offset;
 346         __be32                  logsize_usrpage;
 347         __be16                  cq_period;
 348         __be16                  cq_max_count;
 349         u8                      reserved2[3];
 350         u8                      comp_eqn;
 351         u8                      log_page_size;
 352         u8                      reserved3[2];
 353         u8                      mtt_base_addr_h;
 354         __be32                  mtt_base_addr_l;
 355         __be32                  last_notified_index;
 356         __be32                  solicit_producer_index;
 357         __be32                  consumer_index;
 358         __be32                  producer_index;
 359         u32                     reserved4[2];
 360         __be64                  db_rec_addr;
 361 };
 362
 363 struct mlx4_srq_context {
 364         __be32                  state_logsize_srqn;
 365         u8                      logstride;
 366         u8                      reserved1;
 367         __be16                  xrcd;
 368         __be32                  pg_offset_cqn;
 369         u32                     reserved2;
 370         u8                      log_page_size;
 371         u8                      reserved3[2];
 372         u8                      mtt_base_addr_h;
 373         __be32                  mtt_base_addr_l;
 374         __be32                  pd;
 375         __be16                  limit_watermark;
 376         __be16                  wqe_cnt;
 377         u16                     reserved4;
 378         __be16                  wqe_counter;
 379         u32                     reserved5;
 380         __be64                  db_rec_addr;
 381 };
 382
 383 struct mlx4_eq_tasklet {
 384         struct list_head list;
 385         struct list_head process_list;
 386         struct tasklet_struct task;
 387         /* lock on completion tasklet list */
 388         spinlock_t lock;
 389 };
 390
 391 struct mlx4_eq {
 392         struct mlx4_dev        *dev;
 393         void __iomem           *doorbell;
 394         int                     eqn;
 395         u32                     cons_index;
 396         u16                     irq;
 397         u16                     have_irq;
 398         int                     nent;
 399         struct mlx4_buf_list   *page_list;
 400         struct mlx4_mtt         mtt;
 401         struct mlx4_eq_tasklet  tasklet_ctx;
 402         struct mlx4_active_ports actv_ports;
 403         u32                     ref_count;
 404         cpumask_var_t           affinity_mask;
 405 };
 406
 407 struct mlx4_slave_eqe {
 408         u8 type;
 409         u8 port;
 410         u32 param;
 411 };
 412
 413 struct mlx4_slave_event_eq_info {
 414         int eqn;
 415         u16 token;
 416 };
 417
 418 struct mlx4_profile {
 419         int                     num_qp;
 420         int                     rdmarc_per_qp;
 421         int                     num_srq;
 422         int                     num_cq;
 423         int                     num_mcg;
 424         int                     num_mpt;
 425         unsigned                num_mtt;
 426 };
 427
 428 struct mlx4_fw {
 429         u64                     clr_int_base;
 430         u64                     catas_offset;
 431         u64                     comm_base;
 432         u64                     clock_offset;
 433         struct mlx4_icm        *fw_icm;
 434         struct mlx4_icm        *aux_icm;
 435         u32                     catas_size;
 436         u16                     fw_pages;
 437         u8                      clr_int_bar;
 438         u8                      catas_bar;
 439         u8                      comm_bar;
 440         u8                      clock_bar;
 441 };
 442
 443 struct mlx4_comm {
 444         u32                     slave_write;
 445         u32                     slave_read;
 446 };
 447
 448 enum {
 449         MLX4_MCAST_CONFIG       = 0,
 450         MLX4_MCAST_DISABLE      = 1,
 451         MLX4_MCAST_ENABLE       = 2,
 452 };
 453
 454 #define VLAN_FLTR_SIZE  128
 455
 456 struct mlx4_vlan_fltr {
 457         __be32 entry[VLAN_FLTR_SIZE];
 458 };
 459
 460 struct mlx4_mcast_entry {
 461         struct list_head list;
 462         u64 addr;
 463 };
 464
 465 struct mlx4_promisc_qp {
 466         struct list_head list;
 467         u32 qpn;
 468 };
 469
 470 struct mlx4_steer_index {
 471         struct list_head list;
 472         unsigned int index;
 473         struct list_head duplicates;
 474 };
 475
 476 #define MLX4_EVENT_TYPES_NUM 64
 477
 478 struct mlx4_slave_state {
 479         u8 comm_toggle;
 480         u8 last_cmd;
 481         u8 init_port_mask;
 482         bool active;
 483         bool old_vlan_api;
 484         bool vst_qinq_supported;
 485         u8 function;
 486         dma_addr_t vhcr_dma;
 487         u16 user_mtu[MLX4_MAX_PORTS + 1];
 488         u16 mtu[MLX4_MAX_PORTS + 1];
 489         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 490         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 491         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 492         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 493         /* event type to eq number lookup */
 494         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 495         u16 eq_pi;
 496         u16 eq_ci;
 497         spinlock_t lock;
 498         /*initialized via the kzalloc*/
 499         u8 is_slave_going_down;
 500         u32 cookie;
 501         enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
 502 };
 503
 504 #define MLX4_VGT 4095
 505 #define NO_INDX  (-1)
 506
 507 struct mlx4_vport_state {
 508         u64 mac;
 509         u16 default_vlan;
 510         u8  default_qos;
 511         __be16 vlan_proto;
 512         u32 tx_rate;
 513         bool spoofchk;
 514         u32 link_state;
 515         u8 qos_vport;
 516         __be64 guid;
 517 };
 518
 519 struct mlx4_vf_admin_state {
 520         struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
 521         u8 enable_smi[MLX4_MAX_PORTS + 1];
 522 };
 523
 524 struct mlx4_vport_oper_state {
 525         struct mlx4_vport_state state;
 526         int mac_idx;
 527         int vlan_idx;
 528 };
 529
 530 struct mlx4_vf_oper_state {
 531         struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
 532         u8 smi_enabled[MLX4_MAX_PORTS + 1];
 533 };
 534
 535 struct slave_list {
 536         struct mutex mutex;
 537         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 538 };
 539
 540 struct resource_allocator {
 541         spinlock_t alloc_lock; /* protect quotas */
 542         union {
 543                 unsigned int res_reserved;
 544                 unsigned int res_port_rsvd[MLX4_MAX_PORTS];
 545         };
 546         union {
 547                 int res_free;
 548                 int res_port_free[MLX4_MAX_PORTS];
 549         };
 550         int *quota;
 551         int *allocated;
 552         int *guaranteed;
 553 };
 554
 555 struct mlx4_resource_tracker {
 556         spinlock_t lock;
 557         /* tree for each resources */
 558         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 559         /* num_of_slave's lists, one per slave */
 560         struct slave_list *slave_list;
 561         struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
 562 };
 563
 564 #define SLAVE_EVENT_EQ_SIZE     128
 565 struct mlx4_slave_event_eq {
 566         u32 eqn;
 567         u32 cons;
 568         u32 prod;
 569         spinlock_t event_lock;
 570         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 571 };
 572
 573 struct mlx4_qos_manager {
 574         int num_of_qos_vfs;
 575         DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
 576 };
 577
 578 struct mlx4_master_qp0_state {
 579         int proxy_qp0_active;
 580         int qp0_active;
 581         int port_active;
 582 };
 583
 584 struct mlx4_mfunc_master_ctx {
 585         struct mlx4_slave_state *slave_state;
 586         struct mlx4_vf_admin_state *vf_admin;
 587         struct mlx4_vf_oper_state *vf_oper;
 588         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 589         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 590         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 591         u16                     max_user_mtu[MLX4_MAX_PORTS + 1];
 592         u8                      pptx;
 593         u8                      pprx;
 594         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 595         struct mlx4_resource_tracker res_tracker;
 596         struct workqueue_struct *comm_wq;
 597         struct work_struct      comm_work;
 598         struct work_struct      slave_event_work;
 599         struct work_struct      slave_flr_event_work;
 600         spinlock_t              slave_state_lock;
 601         __be32                  comm_arm_bit_vector[4];
 602         struct mlx4_eqe         cmd_eqe;
 603         struct mlx4_slave_event_eq slave_eq;
 604         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 605         struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
 606 };
 607
 608 struct mlx4_mfunc {
 609         struct mlx4_comm __iomem       *comm;
 610         struct mlx4_vhcr_cmd           *vhcr;
 611         dma_addr_t                      vhcr_dma;
 612
 613         struct mlx4_mfunc_master_ctx    master;
 614 };
 615
 616 #define MGM_QPN_MASK       0x00FFFFFF
 617 #define MGM_BLCK_LB_BIT    30
 618
 619 struct mlx4_mgm {
 620         __be32                  next_gid_index;
 621         __be32                  members_count;
 622         u32                     reserved[2];
 623         u8                      gid[16];
 624         __be32                  qp[MLX4_MAX_QP_PER_MGM];
 625 };
 626
 627 struct mlx4_cmd {
 628         struct dma_pool        *pool;
 629         void __iomem           *hcr;
 630         struct mutex            slave_cmd_mutex;
 631         struct semaphore        poll_sem;
 632         struct semaphore        event_sem;
 633         struct rw_semaphore     switch_sem;
 634         int                     max_cmds;
 635         spinlock_t              context_lock;
 636         int                     free_head;
 637         struct mlx4_cmd_context *context;
 638         u16                     token_mask;
 639         u8                      use_events;
 640         u8                      toggle;
 641         u8                      comm_toggle;
 642         u8                      initialized;
 643 };
 644
 645 enum {
 646         MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
 647         MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
 648         MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
 649 };
 650 struct mlx4_vf_immed_vlan_work {
 651         struct work_struct      work;
 652         struct mlx4_priv        *priv;
 653         int                     flags;
 654         int                     slave;
 655         int                     vlan_ix;
 656         int                     orig_vlan_ix;
 657         u8                      port;
 658         u8                      qos;
 659         u8                      qos_vport;
 660         u16                     vlan_id;
 661         u16                     orig_vlan_id;
 662         __be16                  vlan_proto;
 663 };
 664
 665
 666 struct mlx4_uar_table {
 667         struct mlx4_bitmap      bitmap;
 668 };
 669
 670 struct mlx4_mr_table {
 671         struct mlx4_bitmap      mpt_bitmap;
 672         struct mlx4_buddy       mtt_buddy;
 673         u64                     mtt_base;
 674         u64                     mpt_base;
 675         struct mlx4_icm_table   mtt_table;
 676         struct mlx4_icm_table   dmpt_table;
 677 };
 678
 679 struct mlx4_cq_table {
 680         struct mlx4_bitmap      bitmap;
 681         spinlock_t              lock;
 682         struct radix_tree_root  tree;
 683         struct mlx4_icm_table   table;
 684         struct mlx4_icm_table   cmpt_table;
 685 };
 686
 687 struct mlx4_eq_table {
 688         struct mlx4_bitmap      bitmap;
 689         char                   *irq_names;
 690         void __iomem           *clr_int;
 691         void __iomem          **uar_map;
 692         u32                     clr_mask;
 693         struct mlx4_eq         *eq;
 694         struct mlx4_icm_table   table;
 695         struct mlx4_icm_table   cmpt_table;
 696         int                     have_irq;
 697         u8                      inta_pin;
 698 };
 699
 700 struct mlx4_srq_table {
 701         struct mlx4_bitmap      bitmap;
 702         spinlock_t              lock;
 703         struct radix_tree_root  tree;
 704         struct mlx4_icm_table   table;
 705         struct mlx4_icm_table   cmpt_table;
 706 };
 707
 708 enum mlx4_qp_table_zones {
 709         MLX4_QP_TABLE_ZONE_GENERAL,
 710         MLX4_QP_TABLE_ZONE_RSS,
 711         MLX4_QP_TABLE_ZONE_RAW_ETH,
 712         MLX4_QP_TABLE_ZONE_NUM
 713 };
 714
 715 struct mlx4_qp_table {
 716         struct mlx4_bitmap      *bitmap_gen;
 717         struct mlx4_zone_allocator *zones;
 718         u32                     zones_uids[MLX4_QP_TABLE_ZONE_NUM];
 719         u32                     rdmarc_base;
 720         int                     rdmarc_shift;
 721         spinlock_t              lock;
 722         struct mlx4_icm_table   qp_table;
 723         struct mlx4_icm_table   auxc_table;
 724         struct mlx4_icm_table   altc_table;
 725         struct mlx4_icm_table   rdmarc_table;
 726         struct mlx4_icm_table   cmpt_table;
 727 };
 728
 729 struct mlx4_mcg_table {
 730         struct mutex            mutex;
 731         struct mlx4_bitmap      bitmap;
 732         struct mlx4_icm_table   table;
 733 };
 734
 735 struct mlx4_catas_err {
 736         u32 __iomem            *map;
 737         struct timer_list       timer;
 738         struct list_head        list;
 739 };
 740
 741 #define MLX4_MAX_MAC_NUM        128
 742 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 743
 744 struct mlx4_mac_table {
 745         __be64                  entries[MLX4_MAX_MAC_NUM];
 746         int                     refs[MLX4_MAX_MAC_NUM];
 747         bool                    is_dup[MLX4_MAX_MAC_NUM];
 748         struct mutex            mutex;
 749         int                     total;
 750         int                     max;
 751 };
 752
 753 #define MLX4_ROCE_GID_ENTRY_SIZE        16
 754
 755 struct mlx4_roce_gid_entry {
 756         u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
 757 };
 758
 759 struct mlx4_roce_gid_table {
 760         struct mlx4_roce_gid_entry      roce_gids[MLX4_ROCE_MAX_GIDS];
 761         struct mutex                    mutex;
 762 };
 763
 764 #define MLX4_MAX_VLAN_NUM       128
 765 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 766
 767 struct mlx4_vlan_table {
 768         __be32                  entries[MLX4_MAX_VLAN_NUM];
 769         int                     refs[MLX4_MAX_VLAN_NUM];
 770         int                     is_dup[MLX4_MAX_VLAN_NUM];
 771         struct mutex            mutex;
 772         int                     total;
 773         int                     max;
 774 };
 775
 776 #define SET_PORT_GEN_ALL_VALID  (MLX4_FLAG_V_MTU_MASK   | \
 777                                  MLX4_FLAG_V_PPRX_MASK  | \
 778                                  MLX4_FLAG_V_PPTX_MASK)
 779 #define SET_PORT_PROMISC_SHIFT          31
 780 #define SET_PORT_MC_PROMISC_SHIFT       30
 781
 782 enum {
 783         MCAST_DIRECT_ONLY       = 0,
 784         MCAST_DIRECT            = 1,
 785         MCAST_DEFAULT           = 2
 786 };
 787
 788
 789 struct mlx4_set_port_general_context {
 790         u16 reserved1;
 791         u8 flags2;
 792         u8 flags;
 793         union {
 794                 u8 ignore_fcs;
 795                 u8 roce_mode;
 796         };
 797         u8 reserved2;
 798         __be16 mtu;
 799         u8 pptx;
 800         u8 pfctx;
 801         u16 reserved3;
 802         u8 pprx;
 803         u8 pfcrx;
 804         u16 reserved4;
 805         u32 reserved5;
 806         u8 phv_en;
 807         u8 reserved6[5];
 808         __be16 user_mtu;
 809         u16 reserved7;
 810         u8 user_mac[6];
 811 };
 812
 813 struct mlx4_set_port_rqp_calc_context {
 814         __be32 base_qpn;
 815         u8 rererved;
 816         u8 n_mac;
 817         u8 n_vlan;
 818         u8 n_prio;
 819         u8 reserved2[3];
 820         u8 mac_miss;
 821         u8 intra_no_vlan;
 822         u8 no_vlan;
 823         u8 intra_vlan_miss;
 824         u8 vlan_miss;
 825         u8 reserved3[3];
 826         u8 no_vlan_prio;
 827         __be32 promisc;
 828         __be32 mcast;
 829 };
 830
 831 struct mlx4_port_info {
 832         struct mlx4_dev        *dev;
 833         int                     port;
 834         char                    dev_name[16];
 835         struct device_attribute port_attr;
 836         enum mlx4_port_type     tmp_type;
 837         char                    dev_mtu_name[16];
 838         struct device_attribute port_mtu_attr;
 839         struct mlx4_mac_table   mac_table;
 840         struct mlx4_vlan_table  vlan_table;
 841         struct mlx4_roce_gid_table gid_table;
 842         int                     base_qpn;
 843         struct cpu_rmap         *rmap;
 844         struct devlink_port     devlink_port;
 845 };
 846
 847 struct mlx4_sense {
 848         struct mlx4_dev         *dev;
 849         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 850         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 851         struct delayed_work     sense_poll;
 852 };
 853
 854 struct mlx4_msix_ctl {
 855         DECLARE_BITMAP(pool_bm, MAX_MSIX);
 856         struct mutex    pool_lock;
 857 };
 858
 859 struct mlx4_steer {
 860         struct list_head promisc_qps[MLX4_NUM_STEERS];
 861         struct list_head steer_entries[MLX4_NUM_STEERS];
 862 };
 863
 864 enum {
 865         MLX4_PCI_DEV_IS_VF              = 1 << 0,
 866         MLX4_PCI_DEV_FORCE_SENSE_PORT   = 1 << 1,
 867 };
 868
 869 enum {
 870         MLX4_NO_RR      = 0,
 871         MLX4_USE_RR     = 1,
 872 };
 873
 874 struct mlx4_priv {
 875         struct mlx4_dev         dev;
 876
 877         struct list_head        dev_list;
 878         struct list_head        ctx_list;
 879         spinlock_t              ctx_lock;
 880
 881         int                     pci_dev_data;
 882         int                     removed;
 883
 884         struct list_head        pgdir_list;
 885         struct mutex            pgdir_mutex;
 886
 887         struct mlx4_fw          fw;
 888         struct mlx4_cmd         cmd;
 889         struct mlx4_mfunc       mfunc;
 890
 891         struct mlx4_bitmap      pd_bitmap;
 892         struct mlx4_bitmap      xrcd_bitmap;
 893         struct mlx4_uar_table   uar_table;
 894         struct mlx4_mr_table    mr_table;
 895         struct mlx4_cq_table    cq_table;
 896         struct mlx4_eq_table    eq_table;
 897         struct mlx4_srq_table   srq_table;
 898         struct mlx4_qp_table    qp_table;
 899         struct mlx4_mcg_table   mcg_table;
 900         struct mlx4_bitmap      counters_bitmap;
 901         int                     def_counter[MLX4_MAX_PORTS];
 902
 903         struct mlx4_catas_err   catas_err;
 904
 905         void __iomem           *clr_base;
 906
 907         struct mlx4_uar         driver_uar;
 908         void __iomem           *kar;
 909         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 910         struct mlx4_sense       sense;
 911         struct mutex            port_mutex;
 912         struct mlx4_msix_ctl    msix_ctl;
 913         struct mlx4_steer       *steer;
 914         struct list_head        bf_list;
 915         struct mutex            bf_mutex;
 916         struct io_mapping       *bf_mapping;
 917         void __iomem            *clock_mapping;
 918         int                     reserved_mtts;
 919         int                     fs_hash_mode;
 920         u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
 921         struct mlx4_port_map    v2p; /* cached port mapping configuration */
 922         struct mutex            bond_mutex; /* for bond mode */
 923         __be64                  slave_node_guids[MLX4_MFUNC_MAX];
 924
 925         atomic_t                opreq_count;
 926         struct work_struct      opreq_task;
 927 };
 928
 929 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 930 {
 931         return container_of(dev, struct mlx4_priv, dev);
 932 }
 933
 934 #define MLX4_SENSE_RANGE        (HZ * 3)
 935
 936 extern struct workqueue_struct *mlx4_wq;
 937
 938 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 939 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
 940 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
 941                             int align, u32 skip_mask);
 942 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
 943                             int use_rr);
 944 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 945 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 946                      u32 reserved_bot, u32 resetrved_top);
 947 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 948
 949 int mlx4_reset(struct mlx4_dev *dev);
 950
 951 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 952 void mlx4_free_eq_table(struct mlx4_dev *dev);
 953
 954 int mlx4_init_pd_table(struct mlx4_dev *dev);
 955 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 956 int mlx4_init_uar_table(struct mlx4_dev *dev);
 957 int mlx4_init_mr_table(struct mlx4_dev *dev);
 958 int mlx4_init_eq_table(struct mlx4_dev *dev);
 959 int mlx4_init_cq_table(struct mlx4_dev *dev);
 960 int mlx4_init_qp_table(struct mlx4_dev *dev);
 961 int mlx4_init_srq_table(struct mlx4_dev *dev);
 962 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 963
 964 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 965 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 966 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 967 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 968 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 969 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 970 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 971 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 972 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 973 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
 974 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 975 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 976 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 977 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 978 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 979 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
 980 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
 981 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
 982 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
 983 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 984 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 985
 986 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 987                            struct mlx4_vhcr *vhcr,
 988                            struct mlx4_cmd_mailbox *inbox,
 989                            struct mlx4_cmd_mailbox *outbox,
 990                            struct mlx4_cmd_info *cmd);
 991 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 992                            struct mlx4_vhcr *vhcr,
 993                            struct mlx4_cmd_mailbox *inbox,
 994                            struct mlx4_cmd_mailbox *outbox,
 995                            struct mlx4_cmd_info *cmd);
 996 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 997                            struct mlx4_vhcr *vhcr,
 998                            struct mlx4_cmd_mailbox *inbox,
 999                            struct mlx4_cmd_mailbox *outbox,
1000                            struct mlx4_cmd_info *cmd);
1001 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
1002                            struct mlx4_vhcr *vhcr,
1003                            struct mlx4_cmd_mailbox *inbox,
1004                            struct mlx4_cmd_mailbox *outbox,
1005                            struct mlx4_cmd_info *cmd);
1006 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
1007                            struct mlx4_vhcr *vhcr,
1008                            struct mlx4_cmd_mailbox *inbox,
1009                            struct mlx4_cmd_mailbox *outbox,
1010                            struct mlx4_cmd_info *cmd);
1011 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1012                           struct mlx4_vhcr *vhcr,
1013                           struct mlx4_cmd_mailbox *inbox,
1014                           struct mlx4_cmd_mailbox *outbox,
1015                           struct mlx4_cmd_info *cmd);
1016 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
1017                             struct mlx4_vhcr *vhcr,
1018                             struct mlx4_cmd_mailbox *inbox,
1019                             struct mlx4_cmd_mailbox *outbox,
1020                             struct mlx4_cmd_info *cmd);
1021 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1022                      struct mlx4_vhcr *vhcr,
1023                      struct mlx4_cmd_mailbox *inbox,
1024                      struct mlx4_cmd_mailbox *outbox,
1025                      struct mlx4_cmd_info *cmd);
1026 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1027                             int *base, u8 flags);
1028 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1029 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1030 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1031 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1032                      int start_index, int npages, u64 *page_list);
1033 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1034 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1035 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1036                           struct mlx4_counter *data);
1037 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1038 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1039
1040 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1041 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1042 int mlx4_catas_init(struct mlx4_dev *dev);
1043 void mlx4_catas_end(struct mlx4_dev *dev);
1044 int mlx4_crdump_init(struct mlx4_dev *dev);
1045 void mlx4_crdump_end(struct mlx4_dev *dev);
1046 int mlx4_restart_one(struct pci_dev *pdev);
1047 int mlx4_register_device(struct mlx4_dev *dev);
1048 void mlx4_unregister_device(struct mlx4_dev *dev);
1049 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1050                          unsigned long param);
1051
1052 struct mlx4_dev_cap;
1053 struct mlx4_init_hca_param;
1054
1055 u64 mlx4_make_profile(struct mlx4_dev *dev,
1056                       struct mlx4_profile *request,
1057                       struct mlx4_dev_cap *dev_cap,
1058                       struct mlx4_init_hca_param *init_hca);
1059 void mlx4_master_comm_channel(struct work_struct *work);
1060 void mlx4_gen_slave_eqe(struct work_struct *work);
1061 void mlx4_master_handle_slave_flr(struct work_struct *work);
1062
1063 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1064                            struct mlx4_vhcr *vhcr,
1065                            struct mlx4_cmd_mailbox *inbox,
1066                            struct mlx4_cmd_mailbox *outbox,
1067                            struct mlx4_cmd_info *cmd);
1068 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1069                           struct mlx4_vhcr *vhcr,
1070                           struct mlx4_cmd_mailbox *inbox,
1071                           struct mlx4_cmd_mailbox *outbox,
1072                           struct mlx4_cmd_info *cmd);
1073 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1074                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1075                         struct mlx4_cmd_mailbox *outbox,
1076                         struct mlx4_cmd_info *cmd);
1077 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1078                           struct mlx4_vhcr *vhcr,
1079                           struct mlx4_cmd_mailbox *inbox,
1080                           struct mlx4_cmd_mailbox *outbox,
1081                           struct mlx4_cmd_info *cmd);
1082 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1083                             struct mlx4_vhcr *vhcr,
1084                             struct mlx4_cmd_mailbox *inbox,
1085                             struct mlx4_cmd_mailbox *outbox,
1086                           struct mlx4_cmd_info *cmd);
1087 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1088                           struct mlx4_vhcr *vhcr,
1089                           struct mlx4_cmd_mailbox *inbox,
1090                           struct mlx4_cmd_mailbox *outbox,
1091                           struct mlx4_cmd_info *cmd);
1092 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1093                           struct mlx4_vhcr *vhcr,
1094                           struct mlx4_cmd_mailbox *inbox,
1095                           struct mlx4_cmd_mailbox *outbox,
1096                           struct mlx4_cmd_info *cmd);
1097 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1098                           struct mlx4_vhcr *vhcr,
1099                           struct mlx4_cmd_mailbox *inbox,
1100                           struct mlx4_cmd_mailbox *outbox,
1101                           struct mlx4_cmd_info *cmd);
1102 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1103                           struct mlx4_vhcr *vhcr,
1104                           struct mlx4_cmd_mailbox *inbox,
1105                           struct mlx4_cmd_mailbox *outbox,
1106                           struct mlx4_cmd_info *cmd);
1107 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1108                           struct mlx4_vhcr *vhcr,
1109                           struct mlx4_cmd_mailbox *inbox,
1110                           struct mlx4_cmd_mailbox *outbox,
1111                            struct mlx4_cmd_info *cmd);
1112 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1113                            struct mlx4_vhcr *vhcr,
1114                            struct mlx4_cmd_mailbox *inbox,
1115                            struct mlx4_cmd_mailbox *outbox,
1116                            struct mlx4_cmd_info *cmd);
1117 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1118                            struct mlx4_vhcr *vhcr,
1119                            struct mlx4_cmd_mailbox *inbox,
1120                            struct mlx4_cmd_mailbox *outbox,
1121                            struct mlx4_cmd_info *cmd);
1122 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1123                            struct mlx4_vhcr *vhcr,
1124                            struct mlx4_cmd_mailbox *inbox,
1125                            struct mlx4_cmd_mailbox *outbox,
1126                            struct mlx4_cmd_info *cmd);
1127 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1128                          struct mlx4_vhcr *vhcr,
1129                          struct mlx4_cmd_mailbox *inbox,
1130                          struct mlx4_cmd_mailbox *outbox,
1131                          struct mlx4_cmd_info *cmd);
1132 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1133                         struct mlx4_vhcr *vhcr,
1134                         struct mlx4_cmd_mailbox *inbox,
1135                         struct mlx4_cmd_mailbox *outbox,
1136                         struct mlx4_cmd_info *cmd);
1137 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1138                              struct mlx4_vhcr *vhcr,
1139                              struct mlx4_cmd_mailbox *inbox,
1140                              struct mlx4_cmd_mailbox *outbox,
1141                              struct mlx4_cmd_info *cmd);
1142 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1143                               struct mlx4_vhcr *vhcr,
1144                               struct mlx4_cmd_mailbox *inbox,
1145                               struct mlx4_cmd_mailbox *outbox,
1146                               struct mlx4_cmd_info *cmd);
1147 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1148                              struct mlx4_vhcr *vhcr,
1149                              struct mlx4_cmd_mailbox *inbox,
1150                              struct mlx4_cmd_mailbox *outbox,
1151                              struct mlx4_cmd_info *cmd);
1152 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1153                             struct mlx4_vhcr *vhcr,
1154                             struct mlx4_cmd_mailbox *inbox,
1155                             struct mlx4_cmd_mailbox *outbox,
1156                             struct mlx4_cmd_info *cmd);
1157 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1158                             struct mlx4_vhcr *vhcr,
1159                             struct mlx4_cmd_mailbox *inbox,
1160                             struct mlx4_cmd_mailbox *outbox,
1161                             struct mlx4_cmd_info *cmd);
1162 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1163                               struct mlx4_vhcr *vhcr,
1164                               struct mlx4_cmd_mailbox *inbox,
1165                               struct mlx4_cmd_mailbox *outbox,
1166                               struct mlx4_cmd_info *cmd);
1167 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1168                          struct mlx4_vhcr *vhcr,
1169                          struct mlx4_cmd_mailbox *inbox,
1170                          struct mlx4_cmd_mailbox *outbox,
1171                          struct mlx4_cmd_info *cmd);
1172 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1173                             struct mlx4_vhcr *vhcr,
1174                             struct mlx4_cmd_mailbox *inbox,
1175                             struct mlx4_cmd_mailbox *outbox,
1176                             struct mlx4_cmd_info *cmd);
1177 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1178                             struct mlx4_vhcr *vhcr,
1179                             struct mlx4_cmd_mailbox *inbox,
1180                             struct mlx4_cmd_mailbox *outbox,
1181                             struct mlx4_cmd_info *cmd);
1182 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1183                             struct mlx4_vhcr *vhcr,
1184                             struct mlx4_cmd_mailbox *inbox,
1185                             struct mlx4_cmd_mailbox *outbox,
1186                             struct mlx4_cmd_info *cmd);
1187 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1188                          struct mlx4_vhcr *vhcr,
1189                          struct mlx4_cmd_mailbox *inbox,
1190                          struct mlx4_cmd_mailbox *outbox,
1191                          struct mlx4_cmd_info *cmd);
1192 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1193                           struct mlx4_vhcr *vhcr,
1194                           struct mlx4_cmd_mailbox *inbox,
1195                           struct mlx4_cmd_mailbox *outbox,
1196                           struct mlx4_cmd_info *cmd);
1197
1198 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1199
1200 enum {
1201         MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1202         MLX4_CMD_CLEANUP_POOL   = 1UL << 1,
1203         MLX4_CMD_CLEANUP_HCR    = 1UL << 2,
1204         MLX4_CMD_CLEANUP_VHCR   = 1UL << 3,
1205         MLX4_CMD_CLEANUP_ALL    = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1206 };
1207
1208 int mlx4_cmd_init(struct mlx4_dev *dev);
1209 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1210 int mlx4_multi_func_init(struct mlx4_dev *dev);
1211 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1212 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1213 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1214 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1215 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1216
1217 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1218                   u16 op, unsigned long timeout);
1219
1220 void mlx4_cq_tasklet_cb(struct tasklet_struct *t);
1221 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1222 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1223
1224 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1225
1226 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1227
1228 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1229 int mlx4_comm_internal_err(u32 slave_read);
1230
1231 int mlx4_crdump_collect(struct mlx4_dev *dev);
1232
1233 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1234                     enum mlx4_port_type *type);
1235 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1236                          enum mlx4_port_type *stype,
1237                          enum mlx4_port_type *defaults);
1238 void mlx4_start_sense(struct mlx4_dev *dev);
1239 void mlx4_stop_sense(struct mlx4_dev *dev);
1240 void mlx4_sense_init(struct mlx4_dev *dev);
1241 int mlx4_check_port_params(struct mlx4_dev *dev,
1242                            enum mlx4_port_type *port_type);
1243 int mlx4_change_port_types(struct mlx4_dev *dev,
1244                            enum mlx4_port_type *port_types);
1245
1246 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1247 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1248 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1249                               struct mlx4_roce_gid_table *table);
1250 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1251 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1252 int mlx4_bond_vlan_table(struct mlx4_dev *dev);
1253 int mlx4_unbond_vlan_table(struct mlx4_dev *dev);
1254 int mlx4_bond_mac_table(struct mlx4_dev *dev);
1255 int mlx4_unbond_mac_table(struct mlx4_dev *dev);
1256
1257 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1258 /* resource tracker functions*/
1259 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1260                                     enum mlx4_resource resource_type,
1261                                     u64 resource_id, int *slave);
1262 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1263 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1264 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1265
1266 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1267                                 enum mlx4_res_tracker_free_type type);
1268
1269 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1270                           struct mlx4_vhcr *vhcr,
1271                           struct mlx4_cmd_mailbox *inbox,
1272                           struct mlx4_cmd_mailbox *outbox,
1273                           struct mlx4_cmd_info *cmd);
1274 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1275                           struct mlx4_vhcr *vhcr,
1276                           struct mlx4_cmd_mailbox *inbox,
1277                           struct mlx4_cmd_mailbox *outbox,
1278                           struct mlx4_cmd_info *cmd);
1279 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1280                            struct mlx4_vhcr *vhcr,
1281                            struct mlx4_cmd_mailbox *inbox,
1282                            struct mlx4_cmd_mailbox *outbox,
1283                            struct mlx4_cmd_info *cmd);
1284 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1285                             struct mlx4_vhcr *vhcr,
1286                             struct mlx4_cmd_mailbox *inbox,
1287                             struct mlx4_cmd_mailbox *outbox,
1288                             struct mlx4_cmd_info *cmd);
1289 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1290                                struct mlx4_vhcr *vhcr,
1291                                struct mlx4_cmd_mailbox *inbox,
1292                                struct mlx4_cmd_mailbox *outbox,
1293                                struct mlx4_cmd_info *cmd);
1294 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1295                             struct mlx4_vhcr *vhcr,
1296                             struct mlx4_cmd_mailbox *inbox,
1297                             struct mlx4_cmd_mailbox *outbox,
1298                             struct mlx4_cmd_info *cmd);
1299 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1300
1301 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1302                                     int *gid_tbl_len, int *pkey_tbl_len);
1303
1304 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1305                            struct mlx4_vhcr *vhcr,
1306                            struct mlx4_cmd_mailbox *inbox,
1307                            struct mlx4_cmd_mailbox *outbox,
1308                            struct mlx4_cmd_info *cmd);
1309
1310 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1311                            struct mlx4_vhcr *vhcr,
1312                            struct mlx4_cmd_mailbox *inbox,
1313                            struct mlx4_cmd_mailbox *outbox,
1314                            struct mlx4_cmd_info *cmd);
1315
1316 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1317                          struct mlx4_vhcr *vhcr,
1318                          struct mlx4_cmd_mailbox *inbox,
1319                          struct mlx4_cmd_mailbox *outbox,
1320                          struct mlx4_cmd_info *cmd);
1321 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1322                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1323 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1324                           int block_mcast_loopback, enum mlx4_protocol prot,
1325                           enum mlx4_steer_type steer);
1326 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1327                               u8 gid[16], u8 port,
1328                               int block_mcast_loopback,
1329                               enum mlx4_protocol prot, u64 *reg_id);
1330 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1331                                 struct mlx4_vhcr *vhcr,
1332                                 struct mlx4_cmd_mailbox *inbox,
1333                                 struct mlx4_cmd_mailbox *outbox,
1334                                 struct mlx4_cmd_info *cmd);
1335 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1336                                struct mlx4_vhcr *vhcr,
1337                                struct mlx4_cmd_mailbox *inbox,
1338                                struct mlx4_cmd_mailbox *outbox,
1339                                struct mlx4_cmd_info *cmd);
1340 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1341                                      int port, void *buf);
1342 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1343                                    struct mlx4_vhcr *vhcr,
1344                                    struct mlx4_cmd_mailbox *inbox,
1345                                    struct mlx4_cmd_mailbox *outbox,
1346                                 struct mlx4_cmd_info *cmd);
1347 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1348                             struct mlx4_vhcr *vhcr,
1349                             struct mlx4_cmd_mailbox *inbox,
1350                             struct mlx4_cmd_mailbox *outbox,
1351                             struct mlx4_cmd_info *cmd);
1352 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1353                                struct mlx4_vhcr *vhcr,
1354                                struct mlx4_cmd_mailbox *inbox,
1355                                struct mlx4_cmd_mailbox *outbox,
1356                                struct mlx4_cmd_info *cmd);
1357 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1358                                          struct mlx4_vhcr *vhcr,
1359                                          struct mlx4_cmd_mailbox *inbox,
1360                                          struct mlx4_cmd_mailbox *outbox,
1361                                          struct mlx4_cmd_info *cmd);
1362 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1363                                          struct mlx4_vhcr *vhcr,
1364                                          struct mlx4_cmd_mailbox *inbox,
1365                                          struct mlx4_cmd_mailbox *outbox,
1366                                          struct mlx4_cmd_info *cmd);
1367 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1368                             struct mlx4_vhcr *vhcr,
1369                             struct mlx4_cmd_mailbox *inbox,
1370                             struct mlx4_cmd_mailbox *outbox,
1371                             struct mlx4_cmd_info *cmd);
1372
1373 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1374 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1375
1376 static inline void set_param_l(u64 *arg, u32 val)
1377 {
1378         *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1379 }
1380
1381 static inline void set_param_h(u64 *arg, u32 val)
1382 {
1383         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1384 }
1385
1386 static inline u32 get_param_l(u64 *arg)
1387 {
1388         return (u32) (*arg & 0xffffffff);
1389 }
1390
1391 static inline u32 get_param_h(u64 *arg)
1392 {
1393         return (u32)(*arg >> 32);
1394 }
1395
1396 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1397 {
1398         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1399 }
1400
1401 #define NOT_MASKED_PD_BITS 17
1402
1403 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1404
1405 void mlx4_init_quotas(struct mlx4_dev *dev);
1406
1407 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */
1408 void mlx4_replace_zero_macs(struct mlx4_dev *dev);
1409 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1410 /* Returns the VF index of slave */
1411 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1412 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1413 int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1414 int mlx4_bond_fs_rules(struct mlx4_dev *dev);
1415 int mlx4_unbond_fs_rules(struct mlx4_dev *dev);
1416
1417 enum mlx4_zone_flags {
1418         MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO   = 1UL << 0,
1419         MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO      = 1UL << 1,
1420         MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO       = 1UL << 2,
1421         MLX4_ZONE_USE_RR                        = 1UL << 3,
1422 };
1423
1424 enum mlx4_zone_alloc_flags {
1425         /* No two objects could overlap between zones. UID
1426          * could be left unused. If this flag is given and
1427          * two overlapped zones are used, an object will be free'd
1428          * from the smallest possible matching zone.
1429          */
1430         MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP        = 1UL << 0,
1431 };
1432
1433 struct mlx4_zone_allocator;
1434
1435 /* Create a new zone allocator */
1436 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1437
1438 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1439  * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1440  * Similarly, when searching for an object to free, this offset it taken into
1441  * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1442  * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1443  * When an allocation fails, <zone_alloc> tries to allocate from other zones
1444  * according to the policy set by <flags>. <puid> is the unique identifier
1445  * received to this zone.
1446  */
1447 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1448                       struct mlx4_bitmap *bitmap,
1449                       u32 flags,
1450                       int priority,
1451                       int offset,
1452                       u32 *puid);
1453
1454 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1455 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1456
1457 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1458  * the attached bitmaps.
1459  */
1460 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1461
1462 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1463  * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1464  * allocated from is returned in <puid>. If the allocation fails, a negative
1465  * number is returned. Otherwise, the offset of the first object is returned.
1466  */
1467 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1468                             int align, u32 skip_mask, u32 *puid);
1469
1470 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1471  * <zones>.
1472  */
1473 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1474                            u32 uid, u32 obj, u32 count);
1475
1476 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1477  * specifying the uid when freeing an object, zone allocator could figure it by
1478  * itself. Other parameters are similar to mlx4_zone_free.
1479  */
1480 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1481
1482 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1483 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1484
1485 #endif /* MLX4_H */