1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
9 #define MLXSW_CMD_MBOX_SIZE 4096
11 static inline char *mlxsw_cmd_mbox_alloc(void)
13 return kzalloc(MLXSW_CMD_MBOX_SIZE
, GFP_KERNEL
);
16 static inline void mlxsw_cmd_mbox_free(char *mbox
)
21 static inline void mlxsw_cmd_mbox_zero(char *mbox
)
23 memset(mbox
, 0, MLXSW_CMD_MBOX_SIZE
);
28 int mlxsw_cmd_exec(struct mlxsw_core
*mlxsw_core
, u16 opcode
, u8 opcode_mod
,
29 u32 in_mod
, bool out_mbox_direct
, bool reset_ok
,
30 char *in_mbox
, size_t in_mbox_size
,
31 char *out_mbox
, size_t out_mbox_size
);
33 static inline int mlxsw_cmd_exec_in(struct mlxsw_core
*mlxsw_core
, u16 opcode
,
34 u8 opcode_mod
, u32 in_mod
, char *in_mbox
,
37 return mlxsw_cmd_exec(mlxsw_core
, opcode
, opcode_mod
, in_mod
, false,
38 false, in_mbox
, in_mbox_size
, NULL
, 0);
41 static inline int mlxsw_cmd_exec_out(struct mlxsw_core
*mlxsw_core
, u16 opcode
,
42 u8 opcode_mod
, u32 in_mod
,
44 char *out_mbox
, size_t out_mbox_size
)
46 return mlxsw_cmd_exec(mlxsw_core
, opcode
, opcode_mod
, in_mod
,
47 out_mbox_direct
, false, NULL
, 0,
48 out_mbox
, out_mbox_size
);
51 static inline int mlxsw_cmd_exec_none(struct mlxsw_core
*mlxsw_core
, u16 opcode
,
52 u8 opcode_mod
, u32 in_mod
)
54 return mlxsw_cmd_exec(mlxsw_core
, opcode
, opcode_mod
, in_mod
, false,
55 false, NULL
, 0, NULL
, 0);
58 enum mlxsw_cmd_opcode
{
59 MLXSW_CMD_OPCODE_QUERY_FW
= 0x004,
60 MLXSW_CMD_OPCODE_QUERY_BOARDINFO
= 0x006,
61 MLXSW_CMD_OPCODE_QUERY_AQ_CAP
= 0x003,
62 MLXSW_CMD_OPCODE_MAP_FA
= 0xFFF,
63 MLXSW_CMD_OPCODE_UNMAP_FA
= 0xFFE,
64 MLXSW_CMD_OPCODE_CONFIG_PROFILE
= 0x100,
65 MLXSW_CMD_OPCODE_ACCESS_REG
= 0x040,
66 MLXSW_CMD_OPCODE_SW2HW_DQ
= 0x201,
67 MLXSW_CMD_OPCODE_HW2SW_DQ
= 0x202,
68 MLXSW_CMD_OPCODE_2ERR_DQ
= 0x01E,
69 MLXSW_CMD_OPCODE_QUERY_DQ
= 0x022,
70 MLXSW_CMD_OPCODE_SW2HW_CQ
= 0x016,
71 MLXSW_CMD_OPCODE_HW2SW_CQ
= 0x017,
72 MLXSW_CMD_OPCODE_QUERY_CQ
= 0x018,
73 MLXSW_CMD_OPCODE_SW2HW_EQ
= 0x013,
74 MLXSW_CMD_OPCODE_HW2SW_EQ
= 0x014,
75 MLXSW_CMD_OPCODE_QUERY_EQ
= 0x015,
76 MLXSW_CMD_OPCODE_QUERY_RESOURCES
= 0x101,
79 static inline const char *mlxsw_cmd_opcode_str(u16 opcode
)
82 case MLXSW_CMD_OPCODE_QUERY_FW
:
84 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO
:
85 return "QUERY_BOARDINFO";
86 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP
:
87 return "QUERY_AQ_CAP";
88 case MLXSW_CMD_OPCODE_MAP_FA
:
90 case MLXSW_CMD_OPCODE_UNMAP_FA
:
92 case MLXSW_CMD_OPCODE_CONFIG_PROFILE
:
93 return "CONFIG_PROFILE";
94 case MLXSW_CMD_OPCODE_ACCESS_REG
:
96 case MLXSW_CMD_OPCODE_SW2HW_DQ
:
98 case MLXSW_CMD_OPCODE_HW2SW_DQ
:
100 case MLXSW_CMD_OPCODE_2ERR_DQ
:
102 case MLXSW_CMD_OPCODE_QUERY_DQ
:
104 case MLXSW_CMD_OPCODE_SW2HW_CQ
:
106 case MLXSW_CMD_OPCODE_HW2SW_CQ
:
108 case MLXSW_CMD_OPCODE_QUERY_CQ
:
110 case MLXSW_CMD_OPCODE_SW2HW_EQ
:
112 case MLXSW_CMD_OPCODE_HW2SW_EQ
:
114 case MLXSW_CMD_OPCODE_QUERY_EQ
:
116 case MLXSW_CMD_OPCODE_QUERY_RESOURCES
:
117 return "QUERY_RESOURCES";
123 enum mlxsw_cmd_status
{
124 /* Command execution succeeded. */
125 MLXSW_CMD_STATUS_OK
= 0x00,
126 /* Internal error (e.g. bus error) occurred while processing command. */
127 MLXSW_CMD_STATUS_INTERNAL_ERR
= 0x01,
128 /* Operation/command not supported or opcode modifier not supported. */
129 MLXSW_CMD_STATUS_BAD_OP
= 0x02,
130 /* Parameter not supported, parameter out of range. */
131 MLXSW_CMD_STATUS_BAD_PARAM
= 0x03,
132 /* System was not enabled or bad system state. */
133 MLXSW_CMD_STATUS_BAD_SYS_STATE
= 0x04,
134 /* Attempt to access reserved or unallocated resource, or resource in
135 * inappropriate ownership.
137 MLXSW_CMD_STATUS_BAD_RESOURCE
= 0x05,
138 /* Requested resource is currently executing a command. */
139 MLXSW_CMD_STATUS_RESOURCE_BUSY
= 0x06,
140 /* Required capability exceeds device limits. */
141 MLXSW_CMD_STATUS_EXCEED_LIM
= 0x08,
142 /* Resource is not in the appropriate state or ownership. */
143 MLXSW_CMD_STATUS_BAD_RES_STATE
= 0x09,
144 /* Index out of range (might be beyond table size or attempt to
145 * access a reserved resource).
147 MLXSW_CMD_STATUS_BAD_INDEX
= 0x0A,
148 /* NVMEM checksum/CRC failed. */
149 MLXSW_CMD_STATUS_BAD_NVMEM
= 0x0B,
150 /* Device is currently running reset */
151 MLXSW_CMD_STATUS_RUNNING_RESET
= 0x26,
152 /* Bad management packet (silently discarded). */
153 MLXSW_CMD_STATUS_BAD_PKT
= 0x30,
156 static inline const char *mlxsw_cmd_status_str(u8 status
)
159 case MLXSW_CMD_STATUS_OK
:
161 case MLXSW_CMD_STATUS_INTERNAL_ERR
:
162 return "INTERNAL_ERR";
163 case MLXSW_CMD_STATUS_BAD_OP
:
165 case MLXSW_CMD_STATUS_BAD_PARAM
:
167 case MLXSW_CMD_STATUS_BAD_SYS_STATE
:
168 return "BAD_SYS_STATE";
169 case MLXSW_CMD_STATUS_BAD_RESOURCE
:
170 return "BAD_RESOURCE";
171 case MLXSW_CMD_STATUS_RESOURCE_BUSY
:
172 return "RESOURCE_BUSY";
173 case MLXSW_CMD_STATUS_EXCEED_LIM
:
175 case MLXSW_CMD_STATUS_BAD_RES_STATE
:
176 return "BAD_RES_STATE";
177 case MLXSW_CMD_STATUS_BAD_INDEX
:
179 case MLXSW_CMD_STATUS_BAD_NVMEM
:
181 case MLXSW_CMD_STATUS_RUNNING_RESET
:
182 return "RUNNING_RESET";
183 case MLXSW_CMD_STATUS_BAD_PKT
:
190 /* QUERY_FW - Query Firmware
191 * -------------------------
192 * OpMod == 0, INMmod == 0
193 * -----------------------
194 * The QUERY_FW command retrieves information related to firmware, command
195 * interface version and the amount of resources that should be allocated to
199 static inline int mlxsw_cmd_query_fw(struct mlxsw_core
*mlxsw_core
,
202 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_QUERY_FW
,
203 0, 0, false, out_mbox
, MLXSW_CMD_MBOX_SIZE
);
206 /* cmd_mbox_query_fw_fw_pages
207 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages.
209 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_pages
, 0x00, 16, 16);
211 /* cmd_mbox_query_fw_fw_rev_major
212 * Firmware Revision - Major
214 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_rev_major
, 0x00, 0, 16);
216 /* cmd_mbox_query_fw_fw_rev_subminor
217 * Firmware Sub-minor version (Patch level)
219 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_rev_subminor
, 0x04, 16, 16);
221 /* cmd_mbox_query_fw_fw_rev_minor
222 * Firmware Revision - Minor
224 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_rev_minor
, 0x04, 0, 16);
226 /* cmd_mbox_query_fw_core_clk
227 * Internal Clock Frequency (in MHz)
229 MLXSW_ITEM32(cmd_mbox
, query_fw
, core_clk
, 0x08, 16, 16);
231 /* cmd_mbox_query_fw_cmd_interface_rev
232 * Command Interface Interpreter Revision ID. This number is bumped up
233 * every time a non-backward-compatible change is done for the command
234 * interface. The current cmd_interface_rev is 1.
236 MLXSW_ITEM32(cmd_mbox
, query_fw
, cmd_interface_rev
, 0x08, 0, 16);
238 /* cmd_mbox_query_fw_dt
239 * If set, Debug Trace is supported
241 MLXSW_ITEM32(cmd_mbox
, query_fw
, dt
, 0x0C, 31, 1);
243 /* cmd_mbox_query_fw_api_version
244 * Indicates the version of the API, to enable software querying
245 * for compatibility. The current api_version is 1.
247 MLXSW_ITEM32(cmd_mbox
, query_fw
, api_version
, 0x0C, 0, 16);
249 /* cmd_mbox_query_fw_fw_hour
250 * Firmware timestamp - hour
252 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_hour
, 0x10, 24, 8);
254 /* cmd_mbox_query_fw_fw_minutes
255 * Firmware timestamp - minutes
257 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_minutes
, 0x10, 16, 8);
259 /* cmd_mbox_query_fw_fw_seconds
260 * Firmware timestamp - seconds
262 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_seconds
, 0x10, 8, 8);
264 /* cmd_mbox_query_fw_fw_year
265 * Firmware timestamp - year
267 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_year
, 0x14, 16, 16);
269 /* cmd_mbox_query_fw_fw_month
270 * Firmware timestamp - month
272 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_month
, 0x14, 8, 8);
274 /* cmd_mbox_query_fw_fw_day
275 * Firmware timestamp - day
277 MLXSW_ITEM32(cmd_mbox
, query_fw
, fw_day
, 0x14, 0, 8);
279 /* cmd_mbox_query_fw_clr_int_base_offset
280 * Clear Interrupt register's offset from clr_int_bar register
281 * in PCI address space.
283 MLXSW_ITEM64(cmd_mbox
, query_fw
, clr_int_base_offset
, 0x20, 0, 64);
285 /* cmd_mbox_query_fw_clr_int_bar
286 * PCI base address register (BAR) where clr_int register is located.
287 * 00 - BAR 0-1 (64 bit BAR)
289 MLXSW_ITEM32(cmd_mbox
, query_fw
, clr_int_bar
, 0x28, 30, 2);
291 /* cmd_mbox_query_fw_error_buf_offset
292 * Read Only buffer for internal error reports of offset
293 * from error_buf_bar register in PCI address space).
295 MLXSW_ITEM64(cmd_mbox
, query_fw
, error_buf_offset
, 0x30, 0, 64);
297 /* cmd_mbox_query_fw_error_buf_size
298 * Internal error buffer size in DWORDs
300 MLXSW_ITEM32(cmd_mbox
, query_fw
, error_buf_size
, 0x38, 0, 32);
302 /* cmd_mbox_query_fw_error_int_bar
303 * PCI base address register (BAR) where error buffer
304 * register is located.
305 * 00 - BAR 0-1 (64 bit BAR)
307 MLXSW_ITEM32(cmd_mbox
, query_fw
, error_int_bar
, 0x3C, 30, 2);
309 /* cmd_mbox_query_fw_doorbell_page_offset
310 * Offset of the doorbell page
312 MLXSW_ITEM64(cmd_mbox
, query_fw
, doorbell_page_offset
, 0x40, 0, 64);
314 /* cmd_mbox_query_fw_doorbell_page_bar
315 * PCI base address register (BAR) of the doorbell page
316 * 00 - BAR 0-1 (64 bit BAR)
318 MLXSW_ITEM32(cmd_mbox
, query_fw
, doorbell_page_bar
, 0x48, 30, 2);
320 /* cmd_mbox_query_fw_free_running_clock_offset
321 * The offset of the free running clock page
323 MLXSW_ITEM64(cmd_mbox
, query_fw
, free_running_clock_offset
, 0x50, 0, 64);
325 /* cmd_mbox_query_fw_fr_rn_clk_bar
326 * PCI base address register (BAR) of the free running clock page
330 MLXSW_ITEM32(cmd_mbox
, query_fw
, fr_rn_clk_bar
, 0x58, 30, 2);
332 /* QUERY_BOARDINFO - Query Board Information
333 * -----------------------------------------
334 * OpMod == 0 (N/A), INMmod == 0 (N/A)
335 * -----------------------------------
336 * The QUERY_BOARDINFO command retrieves adapter specific parameters.
339 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core
*mlxsw_core
,
342 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_QUERY_BOARDINFO
,
343 0, 0, false, out_mbox
, MLXSW_CMD_MBOX_SIZE
);
346 /* cmd_mbox_xm_num_local_ports
347 * Number of local_ports connected to the xm.
348 * Each local port is a 4x
352 MLXSW_ITEM32(cmd_mbox
, boardinfo
, xm_num_local_ports
, 0x00, 4, 3);
354 /* cmd_mbox_xm_exists
355 * An XM (eXtanded Mezanine, e.g. used for the XLT) is connected on the board.
357 MLXSW_ITEM32(cmd_mbox
, boardinfo
, xm_exists
, 0x00, 0, 1);
359 /* cmd_mbox_xm_local_port_entry
361 MLXSW_ITEM_BIT_ARRAY(cmd_mbox
, boardinfo
, xm_local_port_entry
, 0x04, 4, 8);
363 /* cmd_mbox_boardinfo_intapin
364 * When PCIe interrupt messages are being used, this value is used for clearing
365 * an interrupt. When using MSI-X, this register is not used.
367 MLXSW_ITEM32(cmd_mbox
, boardinfo
, intapin
, 0x10, 24, 8);
369 /* cmd_mbox_boardinfo_vsd_vendor_id
370 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor
371 * specifying/formatting the VSD. The vsd_vendor_id identifies the management
372 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID
373 * format and encoding as long as they use their assigned vsd_vendor_id.
375 MLXSW_ITEM32(cmd_mbox
, boardinfo
, vsd_vendor_id
, 0x1C, 0, 16);
377 /* cmd_mbox_boardinfo_vsd
378 * Vendor Specific Data. The VSD string that is burnt to the Flash
381 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208
382 MLXSW_ITEM_BUF(cmd_mbox
, boardinfo
, vsd
, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN
);
384 /* cmd_mbox_boardinfo_psid
385 * The PSID field is a 16-ascii (byte) character string which acts as
386 * the board ID. The PSID format is used in conjunction with
387 * Mellanox vsd_vendor_id (15B3h).
389 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16
390 MLXSW_ITEM_BUF(cmd_mbox
, boardinfo
, psid
, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN
);
392 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities
393 * -----------------------------------------------------
394 * OpMod == 0 (N/A), INMmod == 0 (N/A)
395 * -----------------------------------
396 * The QUERY_AQ_CAP command returns the device asynchronous queues
397 * capabilities supported.
400 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core
*mlxsw_core
,
403 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_QUERY_AQ_CAP
,
404 0, 0, false, out_mbox
, MLXSW_CMD_MBOX_SIZE
);
407 /* cmd_mbox_query_aq_cap_log_max_sdq_sz
408 * Log (base 2) of max WQEs allowed on SDQ.
410 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, log_max_sdq_sz
, 0x00, 24, 8);
412 /* cmd_mbox_query_aq_cap_max_num_sdqs
413 * Maximum number of SDQs.
415 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, max_num_sdqs
, 0x00, 0, 8);
417 /* cmd_mbox_query_aq_cap_log_max_rdq_sz
418 * Log (base 2) of max WQEs allowed on RDQ.
420 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, log_max_rdq_sz
, 0x04, 24, 8);
422 /* cmd_mbox_query_aq_cap_max_num_rdqs
423 * Maximum number of RDQs.
425 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, max_num_rdqs
, 0x04, 0, 8);
427 /* cmd_mbox_query_aq_cap_log_max_cq_sz
428 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1.
430 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, log_max_cq_sz
, 0x08, 24, 8);
432 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz
433 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2.
435 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, log_max_cqv2_sz
, 0x08, 16, 8);
437 /* cmd_mbox_query_aq_cap_max_num_cqs
438 * Maximum number of CQs.
440 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, max_num_cqs
, 0x08, 0, 8);
442 /* cmd_mbox_query_aq_cap_log_max_eq_sz
443 * Log (base 2) of max EQEs allowed on EQ.
445 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, log_max_eq_sz
, 0x0C, 24, 8);
447 /* cmd_mbox_query_aq_cap_max_num_eqs
448 * Maximum number of EQs.
450 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, max_num_eqs
, 0x0C, 0, 8);
452 /* cmd_mbox_query_aq_cap_max_sg_sq
453 * The maximum S/G list elements in an DSQ. DSQ must not contain
454 * more S/G entries than indicated here.
456 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, max_sg_sq
, 0x10, 8, 8);
458 /* cmd_mbox_query_aq_cap_
459 * The maximum S/G list elements in an DRQ. DRQ must not contain
460 * more S/G entries than indicated here.
462 MLXSW_ITEM32(cmd_mbox
, query_aq_cap
, max_sg_rq
, 0x10, 0, 8);
464 /* MAP_FA - Map Firmware Area
465 * --------------------------
466 * OpMod == 0 (N/A), INMmod == Number of VPM entries
467 * -------------------------------------------------
468 * The MAP_FA command passes physical pages to the switch. These pages
469 * are used to store the device firmware. MAP_FA can be executed multiple
470 * times until all the firmware area is mapped (the size that should be
471 * mapped is retrieved through the QUERY_FW command). All required pages
472 * must be mapped to finish the initialization phase. Physical memory
473 * passed in this command must be pinned.
476 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32
478 static inline int mlxsw_cmd_map_fa(struct mlxsw_core
*mlxsw_core
,
479 char *in_mbox
, u32 vpm_entries_count
)
481 return mlxsw_cmd_exec_in(mlxsw_core
, MLXSW_CMD_OPCODE_MAP_FA
,
482 0, vpm_entries_count
,
483 in_mbox
, MLXSW_CMD_MBOX_SIZE
);
486 /* cmd_mbox_map_fa_pa
489 MLXSW_ITEM64_INDEXED(cmd_mbox
, map_fa
, pa
, 0x00, 12, 52, 0x08, 0x00, true);
491 /* cmd_mbox_map_fa_log2size
492 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory
493 * that starts at PA_L/H.
495 MLXSW_ITEM32_INDEXED(cmd_mbox
, map_fa
, log2size
, 0x00, 0, 5, 0x08, 0x04, false);
497 /* UNMAP_FA - Unmap Firmware Area
498 * ------------------------------
499 * OpMod == 0 (N/A), INMmod == 0 (N/A)
500 * -----------------------------------
501 * The UNMAP_FA command unload the firmware and unmaps all the
502 * firmware area. After this command is completed the device will not access
503 * the pages that were mapped to the firmware area. After executing UNMAP_FA
504 * command, software reset must be done prior to execution of MAP_FW command.
507 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core
*mlxsw_core
)
509 return mlxsw_cmd_exec_none(mlxsw_core
, MLXSW_CMD_OPCODE_UNMAP_FA
, 0, 0);
512 /* QUERY_RESOURCES - Query chip resources
513 * --------------------------------------
514 * OpMod == 0 (N/A) , INMmod is index
515 * ----------------------------------
516 * The QUERY_RESOURCES command retrieves information related to chip resources
517 * by resource ID. Every command returns 32 entries. INmod is being use as base.
518 * for example, index 1 will return entries 32-63. When the tables end and there
519 * are no more sources in the table, will return resource id 0xFFF to indicate
523 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff
524 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100
525 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32
527 static inline int mlxsw_cmd_query_resources(struct mlxsw_core
*mlxsw_core
,
528 char *out_mbox
, int index
)
530 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_QUERY_RESOURCES
,
531 0, index
, false, out_mbox
,
532 MLXSW_CMD_MBOX_SIZE
);
535 /* cmd_mbox_query_resource_id
536 * The resource id. 0xFFFF indicates table's end.
538 MLXSW_ITEM32_INDEXED(cmd_mbox
, query_resource
, id
, 0x00, 16, 16, 0x8, 0, false);
540 /* cmd_mbox_query_resource_data
543 MLXSW_ITEM64_INDEXED(cmd_mbox
, query_resource
, data
,
544 0x00, 0, 40, 0x8, 0, false);
546 /* CONFIG_PROFILE (Set) - Configure Switch Profile
547 * ------------------------------
548 * OpMod == 1 (Set), INMmod == 0 (N/A)
549 * -----------------------------------
550 * The CONFIG_PROFILE command sets the switch profile. The command can be
551 * executed on the device only once at startup in order to allocate and
552 * configure all switch resources and prepare it for operational mode.
553 * It is not possible to change the device profile after the chip is
554 * in operational mode.
555 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate
556 * state therefore it is required to perform software reset to the device
557 * following an unsuccessful completion of the command. It is required
558 * to perform software reset to the device to change an existing profile.
561 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core
*mlxsw_core
,
564 return mlxsw_cmd_exec_in(mlxsw_core
, MLXSW_CMD_OPCODE_CONFIG_PROFILE
,
565 1, 0, in_mbox
, MLXSW_CMD_MBOX_SIZE
);
568 /* cmd_mbox_config_profile_set_max_vepa_channels
569 * Capability bit. Setting a bit to 1 configures the profile
570 * according to the mailbox contents.
572 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_vepa_channels
, 0x0C, 0, 1);
574 /* cmd_mbox_config_profile_set_max_lag
575 * Capability bit. Setting a bit to 1 configures the profile
576 * according to the mailbox contents.
578 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_lag
, 0x0C, 1, 1);
580 /* cmd_mbox_config_profile_set_max_port_per_lag
581 * Capability bit. Setting a bit to 1 configures the profile
582 * according to the mailbox contents.
584 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_port_per_lag
, 0x0C, 2, 1);
586 /* cmd_mbox_config_profile_set_max_mid
587 * Capability bit. Setting a bit to 1 configures the profile
588 * according to the mailbox contents.
590 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_mid
, 0x0C, 3, 1);
592 /* cmd_mbox_config_profile_set_max_pgt
593 * Capability bit. Setting a bit to 1 configures the profile
594 * according to the mailbox contents.
596 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_pgt
, 0x0C, 4, 1);
598 /* cmd_mbox_config_profile_set_max_system_port
599 * Capability bit. Setting a bit to 1 configures the profile
600 * according to the mailbox contents.
602 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_system_port
, 0x0C, 5, 1);
604 /* cmd_mbox_config_profile_set_max_vlan_groups
605 * Capability bit. Setting a bit to 1 configures the profile
606 * according to the mailbox contents.
608 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_vlan_groups
, 0x0C, 6, 1);
610 /* cmd_mbox_config_profile_set_max_regions
611 * Capability bit. Setting a bit to 1 configures the profile
612 * according to the mailbox contents.
614 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_regions
, 0x0C, 7, 1);
616 /* cmd_mbox_config_profile_set_flood_mode
617 * Capability bit. Setting a bit to 1 configures the profile
618 * according to the mailbox contents.
620 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_flood_mode
, 0x0C, 8, 1);
622 /* cmd_mbox_config_profile_set_max_flood_tables
623 * Capability bit. Setting a bit to 1 configures the profile
624 * according to the mailbox contents.
626 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_flood_tables
, 0x0C, 9, 1);
628 /* cmd_mbox_config_profile_set_max_ib_mc
629 * Capability bit. Setting a bit to 1 configures the profile
630 * according to the mailbox contents.
632 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_ib_mc
, 0x0C, 12, 1);
634 /* cmd_mbox_config_profile_set_max_pkey
635 * Capability bit. Setting a bit to 1 configures the profile
636 * according to the mailbox contents.
638 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_max_pkey
, 0x0C, 13, 1);
640 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap
641 * Capability bit. Setting a bit to 1 configures the profile
642 * according to the mailbox contents.
644 MLXSW_ITEM32(cmd_mbox
, config_profile
,
645 set_adaptive_routing_group_cap
, 0x0C, 14, 1);
647 /* cmd_mbox_config_profile_set_ar_sec
648 * Capability bit. Setting a bit to 1 configures the profile
649 * according to the mailbox contents.
651 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_ar_sec
, 0x0C, 15, 1);
653 /* cmd_mbox_config_set_kvd_linear_size
654 * Capability bit. Setting a bit to 1 configures the profile
655 * according to the mailbox contents.
657 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_kvd_linear_size
, 0x0C, 24, 1);
659 /* cmd_mbox_config_set_kvd_hash_single_size
660 * Capability bit. Setting a bit to 1 configures the profile
661 * according to the mailbox contents.
663 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_kvd_hash_single_size
, 0x0C, 25, 1);
665 /* cmd_mbox_config_set_kvd_hash_double_size
666 * Capability bit. Setting a bit to 1 configures the profile
667 * according to the mailbox contents.
669 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_kvd_hash_double_size
, 0x0C, 26, 1);
671 /* cmd_mbox_config_set_cqe_version
672 * Capability bit. Setting a bit to 1 configures the profile
673 * according to the mailbox contents.
675 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_cqe_version
, 0x08, 0, 1);
677 /* cmd_mbox_config_set_kvh_xlt_cache_mode
678 * Capability bit. Setting a bit to 1 configures the profile
679 * according to the mailbox contents.
681 MLXSW_ITEM32(cmd_mbox
, config_profile
, set_kvh_xlt_cache_mode
, 0x08, 3, 1);
683 /* cmd_mbox_config_profile_max_vepa_channels
684 * Maximum number of VEPA channels per port (0 through 16)
685 * 0 - multi-channel VEPA is disabled
687 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_vepa_channels
, 0x10, 0, 8);
689 /* cmd_mbox_config_profile_max_lag
690 * Maximum number of LAG IDs requested.
692 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_lag
, 0x14, 0, 16);
694 /* cmd_mbox_config_profile_max_port_per_lag
695 * Maximum number of ports per LAG requested.
697 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_port_per_lag
, 0x18, 0, 16);
699 /* cmd_mbox_config_profile_max_mid
700 * Maximum Multicast IDs.
701 * Multicast IDs are allocated from 0 to max_mid-1
703 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_mid
, 0x1C, 0, 16);
705 /* cmd_mbox_config_profile_max_pgt
706 * Maximum records in the Port Group Table per Switch Partition.
707 * Port Group Table indexes are from 0 to max_pgt-1
709 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_pgt
, 0x20, 0, 16);
711 /* cmd_mbox_config_profile_max_system_port
712 * The maximum number of system ports that can be allocated.
714 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_system_port
, 0x24, 0, 16);
716 /* cmd_mbox_config_profile_max_vlan_groups
717 * Maximum number VLAN Groups for VLAN binding.
719 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_vlan_groups
, 0x28, 0, 12);
721 /* cmd_mbox_config_profile_max_regions
722 * Maximum number of TCAM Regions.
724 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_regions
, 0x2C, 0, 16);
726 /* cmd_mbox_config_profile_max_flood_tables
727 * Maximum number of single-entry flooding tables. Different flooding tables
728 * can be associated with different packet types.
730 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_flood_tables
, 0x30, 16, 4);
732 /* cmd_mbox_config_profile_max_vid_flood_tables
733 * Maximum number of per-vid flooding tables. Flooding tables are associated
734 * to the different packet types for the different switch partitions.
735 * Table size is 4K entries covering all VID space.
737 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_vid_flood_tables
, 0x30, 8, 4);
739 /* cmd_mbox_config_profile_flood_mode
740 * Flooding mode to use.
741 * 0-2 - Backward compatible modes for SwitchX devices.
742 * 3 - Mixed mode, where:
743 * max_flood_tables indicates the number of single-entry tables.
744 * max_vid_flood_tables indicates the number of per-VID tables.
745 * max_fid_offset_flood_tables indicates the number of FID-offset tables.
746 * max_fid_flood_tables indicates the number of per-FID tables.
748 MLXSW_ITEM32(cmd_mbox
, config_profile
, flood_mode
, 0x30, 0, 2);
750 /* cmd_mbox_config_profile_max_fid_offset_flood_tables
751 * Maximum number of FID-offset flooding tables.
753 MLXSW_ITEM32(cmd_mbox
, config_profile
,
754 max_fid_offset_flood_tables
, 0x34, 24, 4);
756 /* cmd_mbox_config_profile_fid_offset_flood_table_size
757 * The size (number of entries) of each FID-offset flood table.
759 MLXSW_ITEM32(cmd_mbox
, config_profile
,
760 fid_offset_flood_table_size
, 0x34, 0, 16);
762 /* cmd_mbox_config_profile_max_fid_flood_tables
763 * Maximum number of per-FID flooding tables.
765 * Note: This flooding tables cover special FIDs only (vFIDs), starting at
766 * FID value 4K and higher.
768 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_fid_flood_tables
, 0x38, 24, 4);
770 /* cmd_mbox_config_profile_fid_flood_table_size
771 * The size (number of entries) of each per-FID table.
773 MLXSW_ITEM32(cmd_mbox
, config_profile
, fid_flood_table_size
, 0x38, 0, 16);
775 /* cmd_mbox_config_profile_max_ib_mc
776 * Maximum number of multicast FDB records for InfiniBand
777 * FDB (in 512 chunks) per InfiniBand switch partition.
779 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_ib_mc
, 0x40, 0, 15);
781 /* cmd_mbox_config_profile_max_pkey
782 * Maximum per port PKEY table size (for PKEY enforcement)
784 MLXSW_ITEM32(cmd_mbox
, config_profile
, max_pkey
, 0x44, 0, 15);
786 /* cmd_mbox_config_profile_ar_sec
787 * Primary/secondary capability
788 * Describes the number of adaptive routing sub-groups
789 * 0 - disable primary/secondary (single group)
790 * 1 - enable primary/secondary (2 sub-groups)
791 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2
792 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2
794 MLXSW_ITEM32(cmd_mbox
, config_profile
, ar_sec
, 0x4C, 24, 2);
796 /* cmd_mbox_config_profile_adaptive_routing_group_cap
797 * Adaptive Routing Group Capability. Indicates the number of AR groups
798 * supported. Note that when Primary/secondary is enabled, each
799 * primary/secondary couple consumes 2 adaptive routing entries.
801 MLXSW_ITEM32(cmd_mbox
, config_profile
, adaptive_routing_group_cap
, 0x4C, 0, 16);
803 /* cmd_mbox_config_profile_arn
804 * Adaptive Routing Notification Enable
805 * Not supported in SwitchX, SwitchX-2
807 MLXSW_ITEM32(cmd_mbox
, config_profile
, arn
, 0x50, 31, 1);
809 /* cmd_mbox_config_profile_kvh_xlt_cache_mode
810 * KVH XLT cache mode:
811 * 0 - XLT can use all KVH as best-effort
812 * 1 - XLT cache uses 1/2 KVH
814 MLXSW_ITEM32(cmd_mbox
, config_profile
, kvh_xlt_cache_mode
, 0x50, 8, 4);
816 /* cmd_mbox_config_kvd_linear_size
818 * Valid for Spectrum only
819 * Allowed values are 128*N where N=0 or higher
821 MLXSW_ITEM32(cmd_mbox
, config_profile
, kvd_linear_size
, 0x54, 0, 24);
823 /* cmd_mbox_config_kvd_hash_single_size
824 * KVD Hash single-entries size
825 * Valid for Spectrum only
826 * Allowed values are 128*N where N=0 or higher
827 * Must be greater or equal to cap_min_kvd_hash_single_size
828 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
830 MLXSW_ITEM32(cmd_mbox
, config_profile
, kvd_hash_single_size
, 0x58, 0, 24);
832 /* cmd_mbox_config_kvd_hash_double_size
833 * KVD Hash double-entries size (units of single-size entries)
834 * Valid for Spectrum only
835 * Allowed values are 128*N where N=0 or higher
836 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size
837 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
839 MLXSW_ITEM32(cmd_mbox
, config_profile
, kvd_hash_double_size
, 0x5C, 0, 24);
841 /* cmd_mbox_config_profile_swid_config_mask
842 * Modify Switch Partition Configuration mask. When set, the configu-
843 * ration value for the Switch Partition are taken from the mailbox.
844 * When clear, the current configuration values are used.
849 MLXSW_ITEM32_INDEXED(cmd_mbox
, config_profile
, swid_config_mask
,
850 0x60, 24, 8, 0x08, 0x00, false);
852 /* cmd_mbox_config_profile_swid_config_type
853 * Switch Partition type.
854 * 0000 - disabled (Switch Partition does not exist)
857 * 1000 - router port (SwitchX-2 only)
860 MLXSW_ITEM32_INDEXED(cmd_mbox
, config_profile
, swid_config_type
,
861 0x60, 20, 4, 0x08, 0x00, false);
863 /* cmd_mbox_config_profile_swid_config_properties
864 * Switch Partition properties.
866 MLXSW_ITEM32_INDEXED(cmd_mbox
, config_profile
, swid_config_properties
,
867 0x60, 0, 8, 0x08, 0x00, false);
869 /* cmd_mbox_config_profile_cqe_version
871 * 0: CQE version is 0
872 * 1: CQE version is either 1 or 2
873 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver.
875 MLXSW_ITEM32(cmd_mbox
, config_profile
, cqe_version
, 0xB0, 0, 8);
877 /* ACCESS_REG - Access EMAD Supported Register
878 * ----------------------------------
879 * OpMod == 0 (N/A), INMmod == 0 (N/A)
880 * -------------------------------------
881 * The ACCESS_REG command supports accessing device registers. This access
882 * is mainly used for bootstrapping.
885 static inline int mlxsw_cmd_access_reg(struct mlxsw_core
*mlxsw_core
,
887 char *in_mbox
, char *out_mbox
)
889 return mlxsw_cmd_exec(mlxsw_core
, MLXSW_CMD_OPCODE_ACCESS_REG
,
890 0, 0, false, reset_ok
,
891 in_mbox
, MLXSW_CMD_MBOX_SIZE
,
892 out_mbox
, MLXSW_CMD_MBOX_SIZE
);
895 /* SW2HW_DQ - Software to Hardware DQ
896 * ----------------------------------
897 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
898 * INMmod == DQ number
899 * ----------------------------------------------
900 * The SW2HW_DQ command transitions a descriptor queue from software to
901 * hardware ownership. The command enables posting WQEs and ringing DoorBells
902 * on the descriptor queue.
905 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core
*mlxsw_core
,
906 char *in_mbox
, u32 dq_number
,
909 return mlxsw_cmd_exec_in(mlxsw_core
, MLXSW_CMD_OPCODE_SW2HW_DQ
,
910 opcode_mod
, dq_number
,
911 in_mbox
, MLXSW_CMD_MBOX_SIZE
);
915 MLXSW_CMD_OPCODE_MOD_SDQ
= 0,
916 MLXSW_CMD_OPCODE_MOD_RDQ
= 1,
919 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core
*mlxsw_core
,
920 char *in_mbox
, u32 dq_number
)
922 return __mlxsw_cmd_sw2hw_dq(mlxsw_core
, in_mbox
, dq_number
,
923 MLXSW_CMD_OPCODE_MOD_SDQ
);
926 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core
*mlxsw_core
,
927 char *in_mbox
, u32 dq_number
)
929 return __mlxsw_cmd_sw2hw_dq(mlxsw_core
, in_mbox
, dq_number
,
930 MLXSW_CMD_OPCODE_MOD_RDQ
);
933 /* cmd_mbox_sw2hw_dq_cq
934 * Number of the CQ that this Descriptor Queue reports completions to.
936 MLXSW_ITEM32(cmd_mbox
, sw2hw_dq
, cq
, 0x00, 24, 8);
938 /* cmd_mbox_sw2hw_dq_sdq_tclass
939 * SDQ: CPU Egress TClass
942 MLXSW_ITEM32(cmd_mbox
, sw2hw_dq
, sdq_tclass
, 0x00, 16, 6);
944 /* cmd_mbox_sw2hw_dq_log2_dq_sz
945 * Log (base 2) of the Descriptor Queue size in 4KB pages.
947 MLXSW_ITEM32(cmd_mbox
, sw2hw_dq
, log2_dq_sz
, 0x00, 0, 6);
949 /* cmd_mbox_sw2hw_dq_pa
952 MLXSW_ITEM64_INDEXED(cmd_mbox
, sw2hw_dq
, pa
, 0x10, 12, 52, 0x08, 0x00, true);
954 /* HW2SW_DQ - Hardware to Software DQ
955 * ----------------------------------
956 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
957 * INMmod == DQ number
958 * ----------------------------------------------
959 * The HW2SW_DQ command transitions a descriptor queue from hardware to
960 * software ownership. Incoming packets on the DQ are silently discarded,
961 * SW should not post descriptors on nonoperational DQs.
964 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core
*mlxsw_core
,
965 u32 dq_number
, u8 opcode_mod
)
967 return mlxsw_cmd_exec_none(mlxsw_core
, MLXSW_CMD_OPCODE_HW2SW_DQ
,
968 opcode_mod
, dq_number
);
971 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core
*mlxsw_core
,
974 return __mlxsw_cmd_hw2sw_dq(mlxsw_core
, dq_number
,
975 MLXSW_CMD_OPCODE_MOD_SDQ
);
978 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core
*mlxsw_core
,
981 return __mlxsw_cmd_hw2sw_dq(mlxsw_core
, dq_number
,
982 MLXSW_CMD_OPCODE_MOD_RDQ
);
985 /* 2ERR_DQ - To Error DQ
986 * ---------------------
987 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
988 * INMmod == DQ number
989 * ----------------------------------------------
990 * The 2ERR_DQ command transitions the DQ into the error state from the state
991 * in which it has been. While the command is executed, some in-process
992 * descriptors may complete. Once the DQ transitions into the error state,
993 * if there are posted descriptors on the RDQ/SDQ, the hardware writes
994 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ.
995 * When the command is completed successfully, the DQ is already in
999 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core
*mlxsw_core
,
1000 u32 dq_number
, u8 opcode_mod
)
1002 return mlxsw_cmd_exec_none(mlxsw_core
, MLXSW_CMD_OPCODE_2ERR_DQ
,
1003 opcode_mod
, dq_number
);
1006 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core
*mlxsw_core
,
1009 return __mlxsw_cmd_2err_dq(mlxsw_core
, dq_number
,
1010 MLXSW_CMD_OPCODE_MOD_SDQ
);
1013 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core
*mlxsw_core
,
1016 return __mlxsw_cmd_2err_dq(mlxsw_core
, dq_number
,
1017 MLXSW_CMD_OPCODE_MOD_RDQ
);
1020 /* QUERY_DQ - Query DQ
1021 * ---------------------
1022 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
1023 * INMmod == DQ number
1024 * ----------------------------------------------
1025 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware.
1027 * Note: Output mailbox has the same format as SW2HW_DQ.
1030 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core
*mlxsw_core
,
1031 char *out_mbox
, u32 dq_number
,
1034 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_2ERR_DQ
,
1035 opcode_mod
, dq_number
, false,
1036 out_mbox
, MLXSW_CMD_MBOX_SIZE
);
1039 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core
*mlxsw_core
,
1040 char *out_mbox
, u32 dq_number
)
1042 return __mlxsw_cmd_query_dq(mlxsw_core
, out_mbox
, dq_number
,
1043 MLXSW_CMD_OPCODE_MOD_SDQ
);
1046 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core
*mlxsw_core
,
1047 char *out_mbox
, u32 dq_number
)
1049 return __mlxsw_cmd_query_dq(mlxsw_core
, out_mbox
, dq_number
,
1050 MLXSW_CMD_OPCODE_MOD_RDQ
);
1053 /* SW2HW_CQ - Software to Hardware CQ
1054 * ----------------------------------
1055 * OpMod == 0 (N/A), INMmod == CQ number
1056 * -------------------------------------
1057 * The SW2HW_CQ command transfers ownership of a CQ context entry from software
1058 * to hardware. The command takes the CQ context entry from the input mailbox
1059 * and stores it in the CQC in the ownership of the hardware. The command fails
1060 * if the requested CQC entry is already in the ownership of the hardware.
1063 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core
*mlxsw_core
,
1064 char *in_mbox
, u32 cq_number
)
1066 return mlxsw_cmd_exec_in(mlxsw_core
, MLXSW_CMD_OPCODE_SW2HW_CQ
,
1067 0, cq_number
, in_mbox
, MLXSW_CMD_MBOX_SIZE
);
1070 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver
{
1071 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1
,
1072 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2
,
1075 /* cmd_mbox_sw2hw_cq_cqe_ver
1078 MLXSW_ITEM32(cmd_mbox
, sw2hw_cq
, cqe_ver
, 0x00, 28, 4);
1080 /* cmd_mbox_sw2hw_cq_c_eqn
1081 * Event Queue this CQ reports completion events to.
1083 MLXSW_ITEM32(cmd_mbox
, sw2hw_cq
, c_eqn
, 0x00, 24, 1);
1085 /* cmd_mbox_sw2hw_cq_st
1086 * Event delivery state machine
1088 * 0x1 - ARMED (Request for Notification)
1090 MLXSW_ITEM32(cmd_mbox
, sw2hw_cq
, st
, 0x00, 8, 1);
1092 /* cmd_mbox_sw2hw_cq_log_cq_size
1093 * Log (base 2) of the CQ size (in entries).
1095 MLXSW_ITEM32(cmd_mbox
, sw2hw_cq
, log_cq_size
, 0x00, 0, 4);
1097 /* cmd_mbox_sw2hw_cq_producer_counter
1098 * Producer Counter. The counter is incremented for each CQE that is
1099 * written by the HW to the CQ.
1100 * Maintained by HW (valid for the QUERY_CQ command only)
1102 MLXSW_ITEM32(cmd_mbox
, sw2hw_cq
, producer_counter
, 0x04, 0, 16);
1104 /* cmd_mbox_sw2hw_cq_pa
1107 MLXSW_ITEM64_INDEXED(cmd_mbox
, sw2hw_cq
, pa
, 0x10, 11, 53, 0x08, 0x00, true);
1109 /* HW2SW_CQ - Hardware to Software CQ
1110 * ----------------------------------
1111 * OpMod == 0 (N/A), INMmod == CQ number
1112 * -------------------------------------
1113 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware
1114 * to software. The CQC entry is invalidated as a result of this command.
1117 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core
*mlxsw_core
,
1120 return mlxsw_cmd_exec_none(mlxsw_core
, MLXSW_CMD_OPCODE_HW2SW_CQ
,
1124 /* QUERY_CQ - Query CQ
1125 * ----------------------------------
1126 * OpMod == 0 (N/A), INMmod == CQ number
1127 * -------------------------------------
1128 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry.
1129 * The command stores the snapshot in the output mailbox in the software format.
1130 * Note that the CQ context state and values are not affected by the QUERY_CQ
1131 * command. The QUERY_CQ command is for debug purposes only.
1133 * Note: Output mailbox has the same format as SW2HW_CQ.
1136 static inline int mlxsw_cmd_query_cq(struct mlxsw_core
*mlxsw_core
,
1137 char *out_mbox
, u32 cq_number
)
1139 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_QUERY_CQ
,
1140 0, cq_number
, false,
1141 out_mbox
, MLXSW_CMD_MBOX_SIZE
);
1144 /* SW2HW_EQ - Software to Hardware EQ
1145 * ----------------------------------
1146 * OpMod == 0 (N/A), INMmod == EQ number
1147 * -------------------------------------
1148 * The SW2HW_EQ command transfers ownership of an EQ context entry from software
1149 * to hardware. The command takes the EQ context entry from the input mailbox
1150 * and stores it in the EQC in the ownership of the hardware. The command fails
1151 * if the requested EQC entry is already in the ownership of the hardware.
1154 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core
*mlxsw_core
,
1155 char *in_mbox
, u32 eq_number
)
1157 return mlxsw_cmd_exec_in(mlxsw_core
, MLXSW_CMD_OPCODE_SW2HW_EQ
,
1158 0, eq_number
, in_mbox
, MLXSW_CMD_MBOX_SIZE
);
1161 /* cmd_mbox_sw2hw_eq_int_msix
1162 * When set, MSI-X cycles will be generated by this EQ.
1163 * When cleared, an interrupt will be generated by this EQ.
1165 MLXSW_ITEM32(cmd_mbox
, sw2hw_eq
, int_msix
, 0x00, 24, 1);
1167 /* cmd_mbox_sw2hw_eq_st
1168 * Event delivery state machine
1170 * 0x1 - ARMED (Request for Notification)
1171 * 0x11 - Always ARMED
1174 MLXSW_ITEM32(cmd_mbox
, sw2hw_eq
, st
, 0x00, 8, 2);
1176 /* cmd_mbox_sw2hw_eq_log_eq_size
1177 * Log (base 2) of the EQ size (in entries).
1179 MLXSW_ITEM32(cmd_mbox
, sw2hw_eq
, log_eq_size
, 0x00, 0, 4);
1181 /* cmd_mbox_sw2hw_eq_producer_counter
1182 * Producer Counter. The counter is incremented for each EQE that is written
1183 * by the HW to the EQ.
1184 * Maintained by HW (valid for the QUERY_EQ command only)
1186 MLXSW_ITEM32(cmd_mbox
, sw2hw_eq
, producer_counter
, 0x04, 0, 16);
1188 /* cmd_mbox_sw2hw_eq_pa
1191 MLXSW_ITEM64_INDEXED(cmd_mbox
, sw2hw_eq
, pa
, 0x10, 11, 53, 0x08, 0x00, true);
1193 /* HW2SW_EQ - Hardware to Software EQ
1194 * ----------------------------------
1195 * OpMod == 0 (N/A), INMmod == EQ number
1196 * -------------------------------------
1199 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core
*mlxsw_core
,
1202 return mlxsw_cmd_exec_none(mlxsw_core
, MLXSW_CMD_OPCODE_HW2SW_EQ
,
1206 /* QUERY_EQ - Query EQ
1207 * ----------------------------------
1208 * OpMod == 0 (N/A), INMmod == EQ number
1209 * -------------------------------------
1211 * Note: Output mailbox has the same format as SW2HW_EQ.
1214 static inline int mlxsw_cmd_query_eq(struct mlxsw_core
*mlxsw_core
,
1215 char *out_mbox
, u32 eq_number
)
1217 return mlxsw_cmd_exec_out(mlxsw_core
, MLXSW_CMD_OPCODE_QUERY_EQ
,
1218 0, eq_number
, false,
1219 out_mbox
, MLXSW_CMD_MBOX_SIZE
);